SB_TMSG44V1_FPGA/src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiTb.v

`timescale 1ns / 1ns

module PacketAnalyzer4MosiTb (
);

//===============USER DEFINE===================
localparam [3:0] CNT_LMX_DATA = 1;
localparam [1:0] CNT_DDS_DATA = 1;
localparam [0:0] CNT_POT_DATA = 1;
localparam [0:0] CNT_DAC_DATA = 1;
localparam [0:0] CNT_ATT_DATA = 1;
localparam [1:0] CNT_SH_REG_DATA = 1;
localparam [2:0] CNT_MAX_DATA = 3;
localparam [1:0] CNT_GPIO_DATA = 1;
//===============USER DEFINE_END===============

localparam MODE_4MOSI = 1'b1;
localparam MODE_1MOSI = 1'b0;

//===============USER DEFINE===================
localparam MODE_SELECT = MODE_4MOSI;
//===============USER DEFINE_END===============

localparam CFG_REG = 	{MODE_SELECT, CNT_LMX_DATA, CNT_DDS_DATA, 
						CNT_POT_DATA, CNT_DAC_DATA, CNT_ATT_DATA,
						CNT_SH_REG_DATA, CNT_MAX_DATA, CNT_GPIO_DATA, 7'b0};

localparam CNT_DATA_WORDS = CNT_LMX_DATA + CNT_DDS_DATA + CNT_POT_DATA 
							+ CNT_DAC_DATA + CNT_ATT_DATA + CNT_SH_REG_DATA 
							+ CNT_MAX_DATA + CNT_GPIO_DATA;

reg clkMain_tb;
reg rstMain_tb;
reg busyMosi1_tb;

reg [23:0] dataFromSpi_tb;
reg valdataFromSpi_tb;

always #10 clkMain_tb = ~clkMain_tb;

initial begin
	clkMain_tb = 0;
	rstMain_tb = 1;
	busyMosi1_tb = 0;
	#100
	rstMain_tb = 0;
end

reg	[7:0]	state; 
reg	[63:0]	cnt;
reg	[63:0]	countState;

always @(posedge clkMain_tb) begin
	if (rstMain_tb) begin
		cnt <= 0;
		state <= 0;
		valdataFromSpi_tb <= 0;	
		dataFromSpi_tb <= 0;
		countState <= 0;
	end
	else begin
		case(state)
			0: begin
				dataFromSpi_tb <= CFG_REG;

				if (cnt == 6) begin
					cnt <= 0;
					valdataFromSpi_tb <= 1;
					state <= state + 1;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
			1: begin
				valdataFromSpi_tb <= 0;
				if (cnt == 1) begin
					cnt <= 0;
					state <= state + 1;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
			2: begin
				dataFromSpi_tb <= 24'hA; //DATA0

				if (cnt == 6) begin
					cnt <= 0;
					valdataFromSpi_tb <= 1;
					state <= state + 1;
					countState <= countState + 1;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
			3: begin
				valdataFromSpi_tb <= 0;
				if (countState == CNT_DATA_WORDS) begin
					state <= 5;
				end
				else if (cnt == 1) begin
					cnt <= 0;
					state <= state + 1;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
			4: begin
				dataFromSpi_tb <= 24'hF; //DATA1

				if (cnt == 6) begin
					cnt <= 0;
					valdataFromSpi_tb <= 1;
					state <= state + 1;
					countState <= countState + 1;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
			5: begin
				valdataFromSpi_tb <= 0;
				if (countState == CNT_DATA_WORDS) begin
					state <= state;
				end
				else if (cnt == 1) begin
					cnt <= 0;
					state <= 2;
				end
				else begin
					cnt <= cnt + 1;
					state <= state;
				end
			end
		endcase
	end
end

PacketAnalyzer4Mosi DUT (
	.Clk_i					(clkMain_tb),	
	.Rst_i					(rstMain_tb),	
	
	.DataFromSpi_i 			(dataFromSpi_tb),
	.ValDataFromSpi_i 		(valdataFromSpi_tb),
	
	.BusyMosi1_i			(busyMosi1_tb),

	.ValLmxDataToFifo_o		(),
	.ValDdsDataToFifo_o		(),
	.ValPotDataToFifo_o		(),
	.ValDacDataToFifo_o		(),
	.ValAttDataToFifo_o		(),
	.ValShRegDataToFifo_o	(),
	.ValMaxDataToFifo_o		(),
	.ValGpioDataToFifo_o	(),

	.Busy_o					()
);


endmodule