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zaytsev.mikhail
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SB_TMSG44V1_FPGA
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SB_TMSG44V1_...
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script
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recreate.tcl

recreate.tcl 5.8 KB
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  1. set DSN_ROOT [file normalize [file join [file dirname [info script]] "."]]
    2. 

  2. create_project -name SB_TMSG44V1_FPGA -dir $::DSN_ROOT/SB_TMSG44V1_FPGA_PROJ -pn GW1N-LV9PG256C6/I5 -device_version C -force 
    3. 

  3. 

  4. add_file -type cst "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/SbTmsg.cst"
    5. 

  5. add_file -type sdc "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/SbTmsg.sdc"
    6. 

  6. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Top/TopSbTmsg.v"
    7. 

  7. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v"
    8. 

  8. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv4/GowinClkDiv4.v"
    9. 

  9. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv5/GowinClkDiv5.v"
    10. 

  10. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.v"
    11. 

  11. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPLLFirst/GowinPLLFirst.v"
    12. 

  12. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPLLSecond/GowinPLLSecond.v"
    13. 

  13. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/ClkGen.v"
    14. 

  14. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/FifoCtrl/FifoCtrl.v"
    15. 

  15. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Gpio1Ctrl/Gpio1Ctrl.v"
    16. 

  16. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Gpio2Read/Gpio2Read.v"
    17. 

  17. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/InterfaceArbiter/InterfaceArbiter.v"
    18. 

  18. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v"
    19. 

  19. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v"
    20. 

  20. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/SpiM/SpiM.v"
    21. 

  21. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/SpiReadback/SpiReadback.v"
    22. 

  22. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/TempRead/TempI2cMaster.v"
    23. 

  23. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/TempRead/TempRead.v"
    24. 

  24. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Fifo16x3/Fifo16x3.v"
    25. 

  25. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/FifoDDS.v"
    26. 

  26. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoLMX/FifoLMX.v"
    27. 

  27. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoMax2870/FifoMax2870.v"
    28. 

  28. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.v"
    29. 

  29. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/AttenuatorWrapper.v"
    30. 

  30. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/DDSWrapper.v"
    31. 

  31. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/LmxWrapper.v"
    32. 

  32. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Max2870Wrapper.v"
    33. 

  33. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/ShifRegWrapper.v"
    34. 

  34. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/DacWrapper.v"
    35. 

  35. add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/PotWrapper.v"
    36. 

  36. 

  37. 

  38. 

  39. set_option -synthesis_tool gowinsynthesis
    40. 

  40. set_option -output_base_name SB_TMSG44V1_FPGA
    41. 

  41. set_option -top_module TopSbTmsg
    42. 

  42. set_option -gen_verilog_sim_netlist 1
    43. 

  43. 

  44. set_option -print_all_synthesis_warning 0
    45. 

  45. set_option -allow_duplicate_modules 0
    46. 

  46. set_option -multi_file_compilation_unit 1
    47. 

  47. set_option -auto_constraint_io 0
    48. 

  48. set_option -default_enum_encoding default
    49. 

  49. set_option -compiler_compatible 1
    50. 

  50. set_option -disable_io_insertion 0
    51. 

  51. set_option -fix_gated_and_generated_clocks 1
    52. 

  52. set_option -frequency Auto
    53. 

  53. set_option -looplimit 2000
    54. 

  54. set_option -maxfan 10000
    55. 

  55. set_option -pipe 1
    56. 

  56. set_option -resolve_multiple_driver 0
    57. 

  57. set_option -resource_sharing 1
    58. 

  58. set_option -retiming 0
    59. 

  59. set_option -run_prop_extract 1
    60. 

  60. set_option -rw_check_on_ram 0
    61. 

  61. set_option -supporttypedflt 0
    62. 

  62. set_option -symbolic_fsm_compiler 1
    63. 

  63. set_option -synthesis_onoff_pragma 0
    64. 

  64. set_option -update_models_cp 0
    65. 

  65. set_option -write_apr_constraint 1
    66. 

  66. set_option -gen_sdf 0
    67. 

  67. set_option -gen_io_cst 0
    68. 

  68. set_option -vccaux 3.3
    69. 

  69. set_option -gen_ibis 0
    70. 

  70. set_option -gen_posp 0
    71. 

  71. set_option -gen_text_timing_rpt 0
    72. 

  72. set_option -gen_verilog_sim_netlist 1
    73. 

  73. set_option -gen_vhdl_sim_netlist 0
    74. 

  74. set_option -show_init_in_vo 0
    75. 

  75. set_option -show_all_warn 0
    76. 

  76. set_option -timing_driven 1
    77. 

  77. set_option -ireg_in_iob 1
    78. 

  78. set_option -oreg_in_iob 1
    79. 

  79. set_option -ioreg_in_iob 1
    80. 

  80. set_option -replicate_resources 0
    81. 

  81. set_option -cst_warn_to_error 1
    82. 

  82. set_option -rpt_auto_place_io_info 0
    83. 

  83. set_option -correct_hold_violation 1
    84. 

  84. set_option -place_option 0
    85. 

  85. set_option -route_option 0
    86. 

  86. set_option -clock_route_order 0
    87. 

  87. set_option -route_maxfan 23
    88. 

  88. set_option -use_jtag_as_gpio 0
    89. 

  89. set_option -use_sspi_as_gpio 1
    90. 

  90. set_option -use_mspi_as_gpio 0
    91. 

  91. set_option -use_ready_as_gpio 1
    92. 

  92. set_option -use_done_as_gpio 0
    93. 

  93. set_option -use_reconfign_as_gpio 0
    94. 

  94. set_option -use_mode_as_gpio 0
    95. 

  95. set_option -use_i2c_as_gpio 0
    96. 

  96. set_option -use_cpu_as_gpio 0
    97. 

  97. set_option -power_on_reset_monitor 1
    98. 

  98. set_option -bit_format bin
    99. 

  99. set_option -bit_crc_check 1
    100. 

  100. set_option -bit_compress 0
    101. 

  101. set_option -bit_encrypt 0
    102. 

  102. set_option -bit_encrypt_key 00000000000000000000000000000000
    103. 

  103. set_option -bit_security 1
    104. 

  104. set_option -bit_incl_bsram_init 1
    105. 

  105. set_option -bg_programming off
    106. 

  106. set_option -hotboot 0
    107. 

  107. set_option -i2c_slave_addr 00
    108. 

  108. set_option -secure_mode 0
    109. 

  109. set_option -loading_rate default
    110. 

  110. set_option -program_done_bypass 0
    111. 

  111. set_option -wakeup_mode 0
    112. 

  112. set_option -user_code default
    113. 

  113. set_option -unused_pin default
    114. 

  114. set_option -multi_boot 1
    115. 

  115. set_option -multiboot_address_width 24
    116. 

  116. set_option -multiboot_mode normal
    117. 

  117. set_option -multiboot_spi_flash_address 00000000
    118. 

  118. set_option -mspi_jump 0
    119. 

  119. set_option -turn_off_bg 0
    120. 

  120. set_option -vccx 3.3
    121. 

  121. set_option -seu_handler 0
    122. 

  122. set_option -seu_handler_checksum 0
    123. 

  123. set_option -seu_handler_mode auto
    124. 

  124. set_option -error_detection false
    125. 

  125. set_option -error_detection_correction false
    126. 

  126. set_option -stop_seu_handler false
    127. 

  127. set_option -error_injection false
    128. 

  128. set_option -ext_cclk false
    129. 

  129. set_option -ext_cclk_div
    130.