Промежуточные изменения по использованию структуры для взаимодействия с адресами PCI

.vscode/settings.json

@@ -3,6 +3,11 @@
         "tmsgheaders.h": "c",
         "lmx2594regs.h": "c",
         "stdint.h": "c",
-        "lmx2594.h": "c"
+        "lmx2594.h": "c",
+        "pci.h": "c",
+        "lmk04821.h": "c",
+        "max2870.h": "c",
+        "ad9912.h": "c",
+        "command.h": "c"
     }
 }

Devices/ad9912.c

@@ -1,7 +1,7 @@
 #include "ad9912.h"
 #include <math.h>
 
- uint32_t ad9912regs[AD9912_COUNT] = {
+uint32_t ad9912regs[AD9912_COUNT] = {
         0x000018,
         0x000100,
         0x000202,
@@ -40,22 +40,21 @@
         0x050800,
         0x050900
 };
+
 uint32_t ad9912_ftw_regs_qspi[4];
+
 /*-------------------------AD9912 INIT FUNCTION-------------------------*/
-void ad9912_init(void *bar1) {
-    uint32_t *ptr_rst = bar1 + TMSG_BASE_ADDR;
-    *ptr_rst = GPIO_INIT_HEADER;
+void ad9912_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->sbtmsg_addr = GPIO_INIT_HEADER;
     //Rst on
-    *ptr_rst = AD9912_RST_ON;
+    pci_bar_1->sbtmsg_addr = AD9912_RST_ON;
     // Rst off
-    *ptr_rst = GPIO_REG;
+    pci_bar_1->sbtmsg_addr = GPIO_REG;
     //Init Header
-    uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
-    *ptr = InitDDSHeader;
+    pci_bar_1->sbtmsg_addr = InitDDSHeader;
     //Init Data
     for (int k = 0; k < AD9912_COUNT; k++) {
-        uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
-        *ptr = ad9912regs[k];
+        pci_bar_1->sbtmsg_addr = ad9912regs[k];
     }
 }
 /*----------------------------------------------------------------------*/
@@ -183,9 +182,7 @@ double ad9912_set_out_of_band(double lmx_freq,double f_pd) {
     return f_pd;
 }
 
-
-
-double ad9912_set(void *bar1, double freq, double f_pd) {
+double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd) {
     double fs = 1e9;
 
     if (freq >= 7500e6 && freq <= 15000e6) {
@@ -251,5 +248,4 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     // }
 
     return f_pd;
-
 }

Devices/ad9912.h

@@ -1,70 +1,71 @@
 #ifndef DMADRIVER_AD9912_H
 #define DMADRIVER_AD9912_H
 
+#include "pci.h"
 #include "tmsgheaders.h"
 
 #define     AD9912_COUNT        37
 #define     AD9912_BASE_ADDR    0x04
 
 #define AD9912_RST_ON ((DDS_SAW1_FPGA << 21) | \
-                  (GPIO_ADRF_V2 << 20) | \
-                  (GPIO_ADRF_V1 << 19) | \
-                  (REF_OFFSET_CTRL_FPGA << 18) | \
-                  (DDS_SAW2_FPGA << 17) | \
-                  (DDS_X2_FPGA << 16) | \
-                  (PLL_LOOP_CTRL << 15) | \
-                  (PLL_SYNC << 14) | \
-                  (PLL_SYNC_CTRL << 13) | \
-                  (PLL_VTUNE_CTRL << 12) | \
-                  (AM_ALC_1_FIX << 11) | \
-                  (SW_CAP1 << 10) | \
-                  (SW_CAP2 << 9) | \
-                  (SW_CAP3 << 8) | \
-                  (AM_ALC_SW << 7) | \
-                  (SW_CAP4 << 6) | \
-                  (DDS_SYNC_FPGA << 5) | \
-                  (0x1 << 4) | \
-                  (DDS_SYNC_CTRL_FPGA << 3) | \
-                  (CTRL_AM_SW3 << 2) | \
-                  (RF_SW2 << 1) | \
-                  (RF_SW1 << 0))
+				  (GPIO_ADRF_V2 << 20) | \
+				  (GPIO_ADRF_V1 << 19) | \
+				  (REF_OFFSET_CTRL_FPGA << 18) | \
+				  (DDS_SAW2_FPGA << 17) | \
+				  (DDS_X2_FPGA << 16) | \
+				  (PLL_LOOP_CTRL << 15) | \
+				  (PLL_SYNC << 14) | \
+				  (PLL_SYNC_CTRL << 13) | \
+				  (PLL_VTUNE_CTRL << 12) | \
+				  (AM_ALC_1_FIX << 11) | \
+				  (SW_CAP1 << 10) | \
+				  (SW_CAP2 << 9) | \
+				  (SW_CAP3 << 8) | \
+				  (AM_ALC_SW << 7) | \
+				  (SW_CAP4 << 6) | \
+				  (DDS_SYNC_FPGA << 5) | \
+				  (0x1 << 4) | \
+				  (DDS_SYNC_CTRL_FPGA << 3) | \
+				  (CTRL_AM_SW3 << 2) | \
+				  (RF_SW2 << 1) | \
+				  (RF_SW1 << 0))
 
 /**********************************************************************************
  * 										FTW0[7:0]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_7_0                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_7_0                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
-#define REGP_AD9912_FTW0_FREQ_WORD_7_0                         0xE
+#define BITP_AD9912_FTW0_FREQ_WORD_7_0							0
+#define BITM_AD9912_FTW0_FREQ_WORD_7_0							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
+#define REGP_AD9912_FTW0_FREQ_WORD_7_0							0xE
 /**********************************************************************************
  * 										FTW0[15:8]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_15_8                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_15_8                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
-#define REGP_AD9912_FTW0_FREQ_WORD_15_8                         0xF
+#define BITP_AD9912_FTW0_FREQ_WORD_15_8							0
+#define BITM_AD9912_FTW0_FREQ_WORD_15_8							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
+#define REGP_AD9912_FTW0_FREQ_WORD_15_8							0xF
 /**********************************************************************************
  * 										FTW0[23:16]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_23_16                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_23_16                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
-#define REGP_AD9912_FTW0_FREQ_WORD_23_16                         0x10
+#define BITP_AD9912_FTW0_FREQ_WORD_23_16						0
+#define BITM_AD9912_FTW0_FREQ_WORD_23_16						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
+#define REGP_AD9912_FTW0_FREQ_WORD_23_16						0x10
 /**********************************************************************************
  * 										FTW0[31:24]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_31_24                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_31_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
-#define REGP_AD9912_FTW0_FREQ_WORD_31_24                         0x11
+#define BITP_AD9912_FTW0_FREQ_WORD_31_24						0
+#define BITM_AD9912_FTW0_FREQ_WORD_31_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
+#define REGP_AD9912_FTW0_FREQ_WORD_31_24						0x11
 /**********************************************************************************
  * 										FTW0[39:32]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_39_24                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_39_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
-#define REGP_AD9912_FTW0_FREQ_WORD_39_24                         0x12
+#define BITP_AD9912_FTW0_FREQ_WORD_39_24						0
+#define BITM_AD9912_FTW0_FREQ_WORD_39_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
+#define REGP_AD9912_FTW0_FREQ_WORD_39_24						0x12
 /**********************************************************************************
  * 										FTW0[47:40]
 *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_47_40                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_47_40                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
-#define REGP_AD9912_FTW0_FREQ_WORD_47_40                         0x13
+#define BITP_AD9912_FTW0_FREQ_WORD_47_40						0
+#define BITM_AD9912_FTW0_FREQ_WORD_47_40						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
+#define REGP_AD9912_FTW0_FREQ_WORD_47_40						0x13
 
 /**********************************************************************************
  * 										INSTRUCTION WORD[15:0]
@@ -76,22 +77,22 @@
 #define ENUM_AD9912_INSTRUCTION_WORD_WRITE                          (0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 #define ENUM_AD9912_INSTRUCTION_WORD_READ                           (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 
-#define BITP_AD9912_INSTRUCTION_WORD_LENGTH                         5
-#define BITM_AD9912_INSTRUCTION_WORD_LENGTH                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1                       (0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2                       (0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3                       (0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_STREAM                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define BITP_AD9912_INSTRUCTION_WORD_LENGTH							5
+#define BITM_AD9912_INSTRUCTION_WORD_LENGTH							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1						(0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2						(0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3						(0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_STREAM							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 
-#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        16
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        (0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
-#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       0
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       (0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					16
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					(0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					0
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					(0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 //Addr[12:0]
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS                        (0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
-#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR                      (0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
-#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8                 (0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
-#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12                (0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS						(0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR						(0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8					(0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12				(0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 /**********************************************************************************
  * 										QSPI_FTW[7:0][15:8]
 *********************************************************************************/
@@ -134,8 +135,8 @@
 #define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)
 
 extern uint32_t ad9912_ftw_regs_qspi[4];
-void ad9912_init(void *bar1);
-double ad9912_set(void *bar1, double freq, double f_pd);
+void ad9912_init(reg_addr_pci* pci_bar_1);
+double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd);
 double ad9912_set_out_of_band(double freq,double f_pd); 
 double ad9912_set_main_band(double freq,double f_pd);
 #endif //DMADRIVER_AD9912_H

Devices/dac8811.c

@@ -1,37 +1,29 @@
 #include "dac8811.h"
 
-
-void dac8811_set(void *bar1, uint16_t dac_data) {
-    //Header for DAC8811
-    uint32_t *ptr_header = bar1 + DAC8811_BASE_ADDR;
-    *ptr_header = DAC8811_HEADER;
-    //Data for DAC8811
-    uint32_t *ptr = bar1 + DAC8811_BASE_ADDR;
-    *ptr = dac_data;
+void dac8811_set(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	//Header for DAC8811
+	pci_bar_1->sbtmsg_addr = DAC8811_HEADER;
+	//Data for DAC8811
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_set_qspi(void *bar1, uint16_t dac_data) {
-    uint32_t *data = bar1 + DAC8811_BASE_ADDR;
-    //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_DAC_4MOSI_HEADER)| TERM_BIT_1);
-    // Send the data 
-    *data = dac_data;
+void dac8811_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	// Create a header
+	pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) | (0x1 << BITP_DAC_4MOSI_HEADER) | TERM_BIT_1);
+	// Send the data 
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_att_set_qspi(void *bar1, uint16_t dac_data) {
-    uint32_t *data = bar1 + DAC8811_BASE_ADDR;
-    //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_ATT_4MOSI_HEADER)| TERM_BIT_1);
-    // Send the data 
-    *data = dac_data;
+void dac8811_att_set(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	//Header for DAC8811
+	pci_bar_1->sbtmsg_addr = DAC8811_ATT_HEADER;
+	//Data for DAC8811
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_att_set(void *bar1, uint16_t dac_data) {
-    //Header for DAC8811
-    uint32_t *ptr_header = bar1 + DAC8811_BASE_ADDR;
-    *ptr_header = DAC8811_ATT_HEADER;
-    //Data for DAC8811
-    uint32_t *ptr = bar1 + DAC8811_BASE_ADDR;
-    *ptr = dac_data;
+void dac8811_att_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	// Create a header
+	pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) | (0x1 << BITP_ATT_4MOSI_HEADER) | TERM_BIT_1);
+	// Send the data 
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
-

Devices/dac8811.h

@@ -1,13 +1,18 @@
+#ifndef DAC8811_H
+#define DAC8811_H
+
+#include "pci.h"
 #include "tmsgheaders.h"
 
+#define DAC8811_BASE_ADDR		0x04
 
-#define     DAC8811_BASE_ADDR       0x04
+#define DAC8811_HEADER			((0 << 23) | (DeviceIdDac << 18) | (DACWordNum << 1) | 1)
+#define DAC8811_ATT_HEADER		((0 << 23) | (DeviceIdAtt << 18) | (ATTWordNum << 1) | 1)
 
-#define     DAC8811_HEADER          ((0 << 23) | (DeviceIdDac << 18) | (DACWordNum << 1) | 1)
-#define     DAC8811_ATT_HEADER      ((0 << 23) | (DeviceIdAtt << 18) | (ATTWordNum << 1) | 1)
 
+void dac8811_set(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_att_set(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_att_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data);
 
-void dac8811_set(void *bar1, uint16_t dac_data);
-void dac8811_att_set(void *bar1, uint16_t dac_data);
-void dac8811_att_set_qspi(void *bar1, uint16_t dac_data);
-void dac8811_set_qspi(void *bar1, uint16_t dac_data);
+#endif //DAC8811_H

Devices/lmk04821.c

@@ -1,5 +1,4 @@
 #include "lmk04821.h"
-#include "pci.h"
 
 const uint32_t lmk04821regs_b[LMK_COUNT] = {
         0x000090,
@@ -273,26 +272,24 @@ const uint32_t lmk04821_rst_b[] = {
         0x000010
 };
 
-void lmk04821_a_init(reg_addr_pci* pce_bar_1) {
+void lmk04821_a_init(reg_addr_pci* pci_bar_1) {
     //Rst for Lmk_a
     for (int i = 0; i < 2; i++) {
-        pce_bar_1->lmk_a_addr = lmk04821_rst_a[i];
+        pci_bar_1->lmk_a_addr = lmk04821_rst_a[i];
     }
     //Init for Lmk_a
     for (int j = 0; j < LMK_COUNT; j++) {
-        pce_bar_1->lmk_a_addr = lmk04821regs_a[j];
+        pci_bar_1->lmk_a_addr = lmk04821regs_a[j];
     }
 }
 
-void lmk04821_b_init(void *bar1) {
+void lmk04821_b_init(reg_addr_pci* pci_bar_1) {
     //Rst for Lmk_a
     for (int i = 0; i < 2; i++) {
-        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
-        *ptr = lmk04821_rst_b[i];
+        pci_bar_1->lmk_b_addr = lmk04821_rst_b[i];
     }
     //Init for Lmk_a
     for (int j = 0; j < LMK_COUNT; j++) {
-        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
-        *ptr = lmk04821regs_b[j];
+        pci_bar_1->lmk_b_addr = lmk04821regs_b[j];
     }
 }

Devices/lmk04821.h

@@ -5,15 +5,11 @@
 #include <stdint.h>
 #include <unistd.h>
 #include <stdio.h>
+#include "pci.h"
 
-#define     LMK_BASE_ADDR       0x10
-#define	    LMK_B_BASE_ADDR	    0x14
-#define     LMK_COUNT           129
+#define     LMK_COUNT   129
 
-
-
-void lmk04821_a_init(void *bar1);
-
-void lmk04821_b_init(void *bar1);
+void lmk04821_a_init(reg_addr_pci* pci_bar_1);
+void lmk04821_b_init(reg_addr_pci* pci_bar_1);
 
 #endif //DMADRIVER_LMK04821_H

Devices/pci.h

@@ -4,15 +4,15 @@
 #include <stdint.h>
 
 typedef struct {
-	uint32_t reserve_1;
-	uint32_t sbtmsg_addr;
-	uint32_t cfg_reg_addr;
-	uint32_t reserve_2;
-	uint32_t lmk_a_addr;
-	uint32_t lmk_b_addr;
-	uint32_t reserve_3;
-	uint32_t att_pe_1_addr;
-	uint32_t att_pe_2_addr;
+	uint32_t reserve_1;		//0x00
+	uint32_t sbtmsg_addr;	//0x04
+	uint32_t cfg_reg_addr;	//0x08
+	uint32_t reserve_2;		//0x0C
+	uint32_t lmk_a_addr;	//0x10
+	uint32_t lmk_b_addr;	//0x14
+	uint32_t reserve_3;		//0x18
+	uint32_t att_pe_1_addr;	//0x1C
+	uint32_t att_pe_2_addr;	//0x20
 } reg_addr_pci;
 
 #endif /* PCI_H */

Devices/pe43711.c

@@ -1,23 +1,19 @@
 #include "pe43711.h"
 
-void pe43711_att_1_init(void *bar1) {
-    uint32_t *ptr = bar1 + PE43711_1_ADDR;
-    *ptr = PE43711_ATTEN_0DB;
+void pe43711_att_1_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->att_pe_1_addr = PE43711_ATTEN_0DB;
 }
 
-void pe43711_att_2_init(void *bar1) {
-    uint32_t *ptr = bar1 + PE43711_2_ADDR;
-    *ptr = PE43711_ATTEN_0DB;
+void pe43711_att_2_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->att_pe_2_addr = PE43711_ATTEN_0DB;
 }
 
-void pe43711_att_1_set(void *bar1, uint8_t atten) {
-    uint32_t *ptr = bar1 + PE43711_1_ADDR;
-    *ptr = atten;
+void pe43711_att_1_set(reg_addr_pci* pci_bar_1, uint8_t atten) {
+    pci_bar_1->att_pe_1_addr = atten;
 }
 
-void pe43711_att_2_set(void *bar1, uint8_t atten) {
-    uint32_t *ptr = bar1 + PE43711_2_ADDR;
-    *ptr = atten;
+void pe43711_att_2_set(reg_addr_pci* pci_bar_1, uint8_t atten) {
+    pci_bar_1->att_pe_2_addr = atten;
 }
 
 

Devices/pe43711.h

@@ -1,8 +1,7 @@
-#include "tmsgheaders.h"
-
-#define PE43711_1_ADDR          0x1C
-#define PE43711_2_ADDR          0x20
+#ifndef PE43711_H
+#define PE43711_H
 
+#include "pci.h"
 
 #define PE43711_ATTEN_0DB           0
 #define PE43711_ATTEN_025DB         1
@@ -15,8 +14,10 @@
 #define PE43711_ATTEN_3175DB        127
 
 
-void pe43711_att_1_init(void *bar1);
-void pe43711_att_2_init(void *bar1);
+void pe43711_att_1_init(reg_addr_pci* pci_bar_1);
+void pe43711_att_2_init(reg_addr_pci* pci_bar_1);
+
+void pe43711_att_1_set(reg_addr_pci* pci_bar_1, uint8_t atten);
+void pe43711_att_2_set(reg_addr_pci* pci_bar_1, uint8_t atten);
 
-void pe43711_att_1_set(void *bar1, uint8_t atten);
-void pe43711_att_2_set(void *bar1, uint8_t atten);
+#endif /* PE43711_H */

Devices/potentiometer.c

@@ -1,54 +1,53 @@
 #include "potentiometer.h"
-
+#include "tmsgheaders.h"
 
 uint32_t pot_array [2] = {0,0};
 
-void potentiometer_set(void *bar1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b) {
+void potentiometer_set(reg_addr_pci* pci_bar_1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b) {
     usleep(1);
     uint32_t cfg_reg = get_cfg_reg();
     SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI);
-    uint32_t *spi_mode = bar1 + CFG_REG_ADDR;
-    *spi_mode = cfg_reg;
+    pci_bar_1->cfg_reg_addr = cfg_reg;
+    
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_a << TPL0202_DATA_BITP);
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_b << TPL0202_DATA_BITP);
     
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_a << TPL0202_DATA_BITP);
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_b << TPL0202_DATA_BITP);
     // Create a header for the Potentiometer 4MOSI
     uint32_t pot_header = (ENUM_SPIMODE_4MOSI | (0x2 << BITP_POT_4MOSI_HEADER) | SB_HEADER_TERM_BIT_1);
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-    *ptr = pot_header;
+    pci_bar_1->sbtmsg_addr = pot_header;
+    
     // Send the data
-    *ptr = pot_ch_a;
-    *ptr = pot_ch_b;
+    pci_bar_1->sbtmsg_addr = pot_ch_a;
+    pci_bar_1->sbtmsg_addr = pot_ch_b;
     usleep(1);
+
     SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_1MOSI);
-    *spi_mode = cfg_reg;
+    pci_bar_1->cfg_reg_addr = cfg_reg;
     set_cfg_reg(cfg_reg);
     usleep(1);
 }
 
-void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope ) {
+void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope) {
 
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
 
     pot_array[0] = pot_ch_a;
     pot_array[1] = pot_ch_b;
 }
 
-void potentiometer_set_offset (void *bar1, uint8_t pot_offset) {
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
-      uint32_t *data = bar1 + LMX_BASE_ADDR;
+void potentiometer_set_offset (reg_addr_pci* pci_bar_1, uint8_t pot_offset) {
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
     //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
-    *data = pot_ch_a;
+    pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
+    pci_bar_1->sbtmsg_addr = pot_ch_a;
 
 }
 
-void potentiometer_set_slope ( void *bar1, uint8_t pot_slope) {
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
-    uint32_t *data = bar1 + LMX_BASE_ADDR;
+void potentiometer_set_slope (reg_addr_pci* pci_bar_1, uint8_t pot_slope) {
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
     //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
-    *data = pot_ch_b;
+    pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
+    pci_bar_1->sbtmsg_addr = pot_ch_b;
 
 }

Devices/potentiometer.h

@@ -1,4 +1,7 @@
-#include "tmsgheaders.h"
+#ifndef POTENTIOMETER_H
+#define POTENTIOMETER_H
+
+#include "pci.h"
 
 #define     TPL0202_CMD_BITP                        12
 #define     TPL0202_CMD_BITM                        (0x3 << TPL0202_CMD_BITP)
@@ -19,7 +22,9 @@
 
 extern uint32_t pot_array [2];
 
-void potentiometer_set(void *bar1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b);
-void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope );
-void potentiometer_set_offset (void *bar1, uint8_t pot_offset);
-void potentiometer_set_slope ( void *bar1, uint8_t pot_slope);
+void potentiometer_set(reg_addr_pci* pci_bar_1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b);
+void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope);
+void potentiometer_set_offset(reg_addr_pci* pci_bar_1, uint8_t pot_offset);
+void potentiometer_set_slope(reg_addr_pci* pci_bar_1, uint8_t pot_slope);
+
+#endif //POTENTIOMETER_H

command.c

@@ -135,7 +135,7 @@ void handleArmCmd(const char* recvBuff)
 
 	splitLexeme(recvBuff, armCode, sizeof(armCode[0]), convertToUInt16);
 	printf("\n%u\n", armCode[0]);
-	dac8811_set_qspi(bar1,armCode[0]);
+	dac8811_set_qspi(pci_bar_1, armCode[0]);
 }
 
 void handleAttCmd(const char* recvBuff)
@@ -144,7 +144,7 @@ void handleAttCmd(const char* recvBuff)
 
 	splitLexeme(recvBuff, attCode, sizeof(attCode[0]), convertToUInt16);
 	printf("\n%u\n", attCode[0]);
-	dac8811_att_set_qspi(bar1, attCode[0]);
+	dac8811_att_set_qspi(pci_bar_1, attCode[0]);
 }
 
 void handleIdnCmd(const char* recvBuff)
@@ -161,7 +161,7 @@ void handleOffsetCmd(const char* recvBuff)
 
 	splitLexeme(recvBuff, offsetCode, sizeof(offsetCode[0]), convertToUInt16);
 	printf("\n%u\n", offsetCode[0]);
-	potentiometer_set_offset(bar1, offsetCode[0]);
+	potentiometer_set_offset(pci_bar_1, offsetCode[0]);
 }
 
 void handleSlopeCmd(const char* recvBuff)
@@ -169,7 +169,7 @@ void handleSlopeCmd(const char* recvBuff)
 	printf("\nHandle command \"TMSG44:SLOPE\"\n");
 	splitLexeme(recvBuff, slopeCode, sizeof(slopeCode[0]), convertToUInt16);
 	printf("\n%u\n", slopeCode[0]);
-	potentiometer_set_slope(bar1, slopeCode[0]);
+	potentiometer_set_slope(pci_bar_1, slopeCode[0]);
 }
 
 //Проходим по массиву команд и ищем команду, которая совпадает с началом строки recvBuff. 

command.h

@@ -4,6 +4,7 @@
 // Включение необходимых стандартных библиотек
 #include <stdint.h>
 #include <stddef.h>
+#include "Devices//pci.h"
 
 // Определение констант
 
@@ -16,6 +17,7 @@ extern volatile int conn_fd;
 extern volatile int pci_fd;
 
 extern  void *bar1;
+extern reg_addr_pci* pci_bar_1;
 
 // extern uint16_t armCode[1];
 // extern uint16_t attCode[1];

main.c

@@ -11,6 +11,8 @@
 #include <fcntl.h>
 #include <sys/time.h>
 
+#include "Devices//pci.h"
+
 #include "Devices//tmsgheaders.h"
 #include "Devices//lmx2594.h"
 #include "Devices//max2870.h"
@@ -20,7 +22,7 @@
 #include "Devices//potentiometer.h"
 
 #include "command.h"
-#include "Devices//pci.h"
+
 
 #define REQUESTED_MEMORY_SIZE  0x1000
 #define SERVER_PORT 5025
@@ -31,7 +33,7 @@ volatile int pci_fd = 0;
 int listen_fd = 0;
 
 void *bar1;
-reg_addr_pci* pce_bar_1;
+reg_addr_pci* pci_bar_1;
 
 //Обработчик ошибок
 void error(const char *msg)
@@ -108,19 +110,19 @@ int main(int argc, char *argv[])
         return 1;
     }
 
-	pce_bar_1 = (reg_addr_pci*)bar1;
+	pci_bar_1 = (reg_addr_pci*)bar1;
 
-    lmk04821_a_init(pce_bar_1);
+    lmk04821_a_init(pci_bar_1);
     usleep(500);
-    lmk04821_b_init(bar1);
-	pe43711_att_1_init(bar1);
+    lmk04821_b_init(pci_bar_1);
+	pe43711_att_1_init(pci_bar_1);
 	usleep(1);
-	pe43711_att_2_init(bar1);
+	pe43711_att_2_init(pci_bar_1);
     rst_for_fpga(bar1);
     shift_reg(bar1);
-	potentiometer_set(bar1, 0, 0);
+	potentiometer_set(pci_bar_1, 0, 0);
 	max2870_init(bar1);
-    ad9912_init(bar1);
+    ad9912_init(pci_bar_1);
     lmx2594_init(bar1);
 
 	usleep(1000);