Исправления в порядке отправки регистров

Devices/ad9912.c

@@ -231,10 +231,10 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40]
     // };
     // First 16 bits is the instruction word
-    ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
-    ad9912_ftw_regs_qspi[1] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24);
-    ad9912_ftw_regs_qspi[2] = (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0);
-    ad9912_ftw_regs_qspi[3] = (0x00 << BITP_AD9912_QSPI_PHASE_13_8);
+    ad9912_ftw_regs_qspi[0] = (0x00 << BITP_AD9912_QSPI_PHASE_13_8);
+    ad9912_ftw_regs_qspi[1] = (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0);
+    ad9912_ftw_regs_qspi[2] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24);
+    ad9912_ftw_regs_qspi[3] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
     // // Create the appropriate header
     // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
     // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);