Merge branch 'Mikhail/feature_StructForPciTrasfer' into dev

.vscode/settings.json

@@ -1,6 +1,13 @@
 {
     "files.associations": {
         "tmsgheaders.h": "c",
-        "lmx2594regs.h": "c"
+        "lmx2594regs.h": "c",
+        "stdint.h": "c",
+        "lmx2594.h": "c",
+        "pci.h": "c",
+        "lmk04821.h": "c",
+        "max2870.h": "c",
+        "ad9912.h": "c",
+        "command.h": "c"
     }
 }

Devices/ad9912.c

@@ -1,7 +1,7 @@
 #include "ad9912.h"
 #include <math.h>
 
- uint32_t ad9912regs[AD9912_COUNT] = {
+uint32_t ad9912regs[AD9912_COUNT] = {
         0x000018,
         0x000100,
         0x000202,
@@ -40,22 +40,21 @@
         0x050800,
         0x050900
 };
+
 uint32_t ad9912_ftw_regs_qspi[4];
+
 /*-------------------------AD9912 INIT FUNCTION-------------------------*/
-void ad9912_init(void *bar1) {
-    uint32_t *ptr_rst = bar1 + TMSG_BASE_ADDR;
-    *ptr_rst = GPIO_INIT_HEADER;
+void ad9912_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->sbtmsg_addr = INIT_GPIO1_HEADER;
     //Rst on
-    *ptr_rst = AD9912_RST_ON;
+    pci_bar_1->sbtmsg_addr = AD9912_RST_ON;
     // Rst off
-    *ptr_rst = GPIO_REG;
+    pci_bar_1->sbtmsg_addr = GPIO_REG;
     //Init Header
-    uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
-    *ptr = InitDDSHeader;
+    pci_bar_1->sbtmsg_addr = INIT_DDS_HEADER;
     //Init Data
     for (int k = 0; k < AD9912_COUNT; k++) {
-        uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
-        *ptr = ad9912regs[k];
+        pci_bar_1->sbtmsg_addr = ad9912regs[k];
     }
 }
 /*----------------------------------------------------------------------*/
@@ -63,16 +62,13 @@ void ad9912_init(void *bar1) {
 double ad9912_set_main_band(double lmx_freq,double f_pd) {
     // Divide the frequncy by the old value of the phase detector frequency and only left with the integer part
     uint32_t N = (uint32_t) (lmx_freq/f_pd);
-     if (f_pd >= 300e6) {
-        N = N+10;
-    }
     if (lmx_freq <= 12500e6) {
         if (N < 28){
-            N= 28;
+            N = 28;
         };
     }
     else if (lmx_freq > 12500e6) {
-        if (N <32) {
+        if (N < 32) {
             N = 32;
         }
     };
@@ -164,16 +160,13 @@ double ad9912_set_out_of_band(double lmx_freq,double f_pd) {
 
     // Divide the frequncy by the old value of the phase detector frequency and only left with the integer part
     uint32_t N = (uint32_t) (f_vco/f_pd);
-    if (f_pd >= 300e6) {
-        N = N+10;
-    }
     if (f_vco <= 12500e6) {
         if (N < 28){
-            N= 28;
+            N = 28;
         };
     }
     else if (f_vco > 12500e6) {
-        if (N <32) {
+        if (N < 32) {
             N = 32;
         }
     };
@@ -183,16 +176,14 @@ double ad9912_set_out_of_band(double lmx_freq,double f_pd) {
     return f_pd;
 }
 
-
-
-double ad9912_set(void *bar1, double freq, double f_pd) {
+double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd) {
     double fs = 1e9;
 
     if (freq >= 7500e6 && freq <= 15000e6) {
-        f_pd = ad9912_set_main_band(freq,f_pd);
+        f_pd = ad9912_set_main_band(freq, f_pd);
     }
     else if (freq >= 10e6 && freq < 7500e6) {
-        f_pd = ad9912_set_out_of_band(freq,f_pd);
+        f_pd = ad9912_set_out_of_band(freq, f_pd);
     }
     else {
         return -1;
@@ -251,5 +242,4 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     // }
 
     return f_pd;
-
 }

Devices/ad9912.h

@@ -1,97 +1,98 @@
-#ifndef DMADRIVER_AD9912_H
-#define DMADRIVER_AD9912_H
+#ifndef AD9912_H
+#define AD9912_H
 
+#include "pci.h"
 #include "tmsgheaders.h"
 
 #define     AD9912_COUNT        37
 #define     AD9912_BASE_ADDR    0x04
 
 #define AD9912_RST_ON ((DDS_SAW1_FPGA << 21) | \
-                  (GPIO_ADRF_V2 << 20) | \
-                  (GPIO_ADRF_V1 << 19) | \
-                  (REF_OFFSET_CTRL_FPGA << 18) | \
-                  (DDS_SAW2_FPGA << 17) | \
-                  (DDS_X2_FPGA << 16) | \
-                  (PLL_LOOP_CTRL << 15) | \
-                  (PLL_SYNC << 14) | \
-                  (PLL_SYNC_CTRL << 13) | \
-                  (PLL_VTUNE_CTRL << 12) | \
-                  (AM_ALC_1_FIX << 11) | \
-                  (SW_CAP1 << 10) | \
-                  (SW_CAP2 << 9) | \
-                  (SW_CAP3 << 8) | \
-                  (AM_ALC_SW << 7) | \
-                  (SW_CAP4 << 6) | \
-                  (DDS_SYNC_FPGA << 5) | \
-                  (0x1 << 4) | \
-                  (DDS_SYNC_CTRL_FPGA << 3) | \
-                  (CTRL_AM_SW3 << 2) | \
-                  (RF_SW2 << 1) | \
-                  (RF_SW1 << 0))
+						(GPIO_ADRF_V2 << 20) | \
+						(GPIO_ADRF_V1 << 19) | \
+						(REF_OFFSET_CTRL_FPGA << 18) | \
+						(DDS_SAW2_FPGA << 17) | \
+						(DDS_X2_FPGA << 16) | \
+						(PLL_LOOP_CTRL << 15) | \
+						(PLL_SYNC << 14) | \
+						(PLL_SYNC_CTRL << 13) | \
+						(PLL_VTUNE_CTRL << 12) | \
+						(AM_ALC_1_FIX << 11) | \
+						(SW_CAP1 << 10) | \
+						(SW_CAP2 << 9) | \
+						(SW_CAP3 << 8) | \
+						(AM_ALC_SW << 7) | \
+						(SW_CAP4 << 6) | \
+						(DDS_SYNC_FPGA << 5) | \
+						(0x1 << 4) | \
+						(DDS_SYNC_CTRL_FPGA << 3) | \
+						(CTRL_AM_SW3 << 2) | \
+						(RF_SW2 << 1) | \
+						(RF_SW1 << 0))
 
 /**********************************************************************************
  * 										FTW0[7:0]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_7_0                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_7_0                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
-#define REGP_AD9912_FTW0_FREQ_WORD_7_0                         0xE
+#define BITP_AD9912_FTW0_FREQ_WORD_7_0							0
+#define BITM_AD9912_FTW0_FREQ_WORD_7_0							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
+#define REGP_AD9912_FTW0_FREQ_WORD_7_0							0xE
 /**********************************************************************************
  * 										FTW0[15:8]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_15_8                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_15_8                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
-#define REGP_AD9912_FTW0_FREQ_WORD_15_8                         0xF
+#define BITP_AD9912_FTW0_FREQ_WORD_15_8							0
+#define BITM_AD9912_FTW0_FREQ_WORD_15_8							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
+#define REGP_AD9912_FTW0_FREQ_WORD_15_8							0xF
 /**********************************************************************************
  * 										FTW0[23:16]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_23_16                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_23_16                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
-#define REGP_AD9912_FTW0_FREQ_WORD_23_16                         0x10
+#define BITP_AD9912_FTW0_FREQ_WORD_23_16						0
+#define BITM_AD9912_FTW0_FREQ_WORD_23_16						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
+#define REGP_AD9912_FTW0_FREQ_WORD_23_16						0x10
 /**********************************************************************************
  * 										FTW0[31:24]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_31_24                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_31_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
-#define REGP_AD9912_FTW0_FREQ_WORD_31_24                         0x11
+#define BITP_AD9912_FTW0_FREQ_WORD_31_24						0
+#define BITM_AD9912_FTW0_FREQ_WORD_31_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
+#define REGP_AD9912_FTW0_FREQ_WORD_31_24						0x11
 /**********************************************************************************
  * 										FTW0[39:32]
  *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_39_24                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_39_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
-#define REGP_AD9912_FTW0_FREQ_WORD_39_24                         0x12
+#define BITP_AD9912_FTW0_FREQ_WORD_39_24						0
+#define BITM_AD9912_FTW0_FREQ_WORD_39_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
+#define REGP_AD9912_FTW0_FREQ_WORD_39_24						0x12
 /**********************************************************************************
  * 										FTW0[47:40]
 *********************************************************************************/
-#define BITP_AD9912_FTW0_FREQ_WORD_47_40                        0
-#define BITM_AD9912_FTW0_FREQ_WORD_47_40                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
-#define REGP_AD9912_FTW0_FREQ_WORD_47_40                         0x13
+#define BITP_AD9912_FTW0_FREQ_WORD_47_40						0
+#define BITM_AD9912_FTW0_FREQ_WORD_47_40						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
+#define REGP_AD9912_FTW0_FREQ_WORD_47_40						0x13
 
 /**********************************************************************************
  * 										INSTRUCTION WORD[15:0]
 *********************************************************************************/
-#define BITP_AD9912_INSTRUCTION_WORD_15_0                           0
-#define BITM_AD9912_INSTRUCTION_WORD_15_0                           (0xFFFF << BITP_AD9912_INSTRUCTION_WORD_15_0)
-#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE                     7
-#define BITM_AD9912_INSTRUCTION_WORD_READ_WRITE                     (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
-#define ENUM_AD9912_INSTRUCTION_WORD_WRITE                          (0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
-#define ENUM_AD9912_INSTRUCTION_WORD_READ                           (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+#define BITP_AD9912_INSTRUCTION_WORD_15_0							0
+#define BITM_AD9912_INSTRUCTION_WORD_15_0							(0xFFFF << BITP_AD9912_INSTRUCTION_WORD_15_0)
+#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE						7
+#define BITM_AD9912_INSTRUCTION_WORD_READ_WRITE						(0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+#define ENUM_AD9912_INSTRUCTION_WORD_WRITE							(0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+#define ENUM_AD9912_INSTRUCTION_WORD_READ							(0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 
-#define BITP_AD9912_INSTRUCTION_WORD_LENGTH                         5
-#define BITM_AD9912_INSTRUCTION_WORD_LENGTH                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1                       (0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2                       (0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3                       (0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
-#define ENUM_AD9912_INSTRUCTION_WORD_STREAM                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define BITP_AD9912_INSTRUCTION_WORD_LENGTH							5
+#define BITM_AD9912_INSTRUCTION_WORD_LENGTH							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1						(0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2						(0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3						(0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_STREAM							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 
-#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        16
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        (0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
-#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       0
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       (0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					16
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					(0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					0
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					(0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 //Addr[12:0]
-#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS                        (0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
-#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR                      (0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
-#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8                 (0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
-#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12                (0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS						(0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR						(0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8					(0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12				(0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 /**********************************************************************************
  * 										QSPI_FTW[7:0][15:8]
 *********************************************************************************/
@@ -134,8 +135,8 @@
 #define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)
 
 extern uint32_t ad9912_ftw_regs_qspi[4];
-void ad9912_init(void *bar1);
-double ad9912_set(void *bar1, double freq, double f_pd);
+void ad9912_init(reg_addr_pci* pci_bar_1);
+double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd);
 double ad9912_set_out_of_band(double freq,double f_pd); 
 double ad9912_set_main_band(double freq,double f_pd);
-#endif //DMADRIVER_AD9912_H
+#endif //AD9912_H

Devices/dac8811.c

@@ -1,37 +1,29 @@
 #include "dac8811.h"
 
-
-void dac8811_set(void *bar1, uint16_t dac_data) {
-    //Header for DAC8811
-    uint32_t *ptr_header = bar1 + DAC8811_BASE_ADDR;
-    *ptr_header = DAC8811_HEADER;
-    //Data for DAC8811
-    uint32_t *ptr = bar1 + DAC8811_BASE_ADDR;
-    *ptr = dac_data;
+void dac8811_set(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	//Header for DAC8811
+	pci_bar_1->sbtmsg_addr = DAC8811_HEADER;
+	//Data for DAC8811
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_set_qspi(void *bar1, uint16_t dac_data) {
-    uint32_t *data = bar1 + DAC8811_BASE_ADDR;
-    //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_DAC_4MOSI_HEADER)| TERM_BIT_1);
-    // Send the data 
-    *data = dac_data;
+void dac8811_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	// Create a header
+	pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) | (0x1 << BITP_DAC_4MOSI_HEADER) | TERM_BIT_1);
+	// Send the data 
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_att_set_qspi(void *bar1, uint16_t dac_data) {
-    uint32_t *data = bar1 + DAC8811_BASE_ADDR;
-    //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_ATT_4MOSI_HEADER)| TERM_BIT_1);
-    // Send the data 
-    *data = dac_data;
+void dac8811_att_set(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	//Header for DAC8811
+	pci_bar_1->sbtmsg_addr = DAC8811_ATT_HEADER;
+	//Data for DAC8811
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
 
-void dac8811_att_set(void *bar1, uint16_t dac_data) {
-    //Header for DAC8811
-    uint32_t *ptr_header = bar1 + DAC8811_BASE_ADDR;
-    *ptr_header = DAC8811_ATT_HEADER;
-    //Data for DAC8811
-    uint32_t *ptr = bar1 + DAC8811_BASE_ADDR;
-    *ptr = dac_data;
+void dac8811_att_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data) {
+	// Create a header
+	pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) | (0x1 << BITP_ATT_4MOSI_HEADER) | TERM_BIT_1);
+	// Send the data 
+	pci_bar_1->sbtmsg_addr = dac_data;
 }
-

Devices/dac8811.h

@@ -1,13 +1,18 @@
+#ifndef DAC8811_H
+#define DAC8811_H
+
+#include "pci.h"
 #include "tmsgheaders.h"
 
+#define DAC8811_BASE_ADDR		0x04
 
-#define     DAC8811_BASE_ADDR       0x04
+#define DAC8811_HEADER			((0 << 23) | (DeviceIdDac << 18) | (DACWordNum << 1) | 1)
+#define DAC8811_ATT_HEADER		((0 << 23) | (DeviceIdAtt << 18) | (ATTWordNum << 1) | 1)
 
-#define     DAC8811_HEADER          ((0 << 23) | (DeviceIdDac << 18) | (DACWordNum << 1) | 1)
-#define     DAC8811_ATT_HEADER      ((0 << 23) | (DeviceIdAtt << 18) | (ATTWordNum << 1) | 1)
 
+void dac8811_set(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_att_set(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_att_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data);
+void dac8811_set_qspi(reg_addr_pci* pci_bar_1, uint16_t dac_data);
 
-void dac8811_set(void *bar1, uint16_t dac_data);
-void dac8811_att_set(void *bar1, uint16_t dac_data);
-void dac8811_att_set_qspi(void *bar1, uint16_t dac_data);
-void dac8811_set_qspi(void *bar1, uint16_t dac_data);
+#endif //DAC8811_H

Devices/lmk04821.c

@@ -272,28 +272,24 @@ const uint32_t lmk04821_rst_b[] = {
         0x000010
 };
 
-void lmk04821_a_init(void *bar1) {
+void lmk04821_a_init(reg_addr_pci* pci_bar_1) {
     //Rst for Lmk_a
     for (int i = 0; i < 2; i++) {
-        uint32_t *ptr = bar1 + LMK_BASE_ADDR;
-        *ptr = lmk04821_rst_a[i];
+        pci_bar_1->lmk_a_addr = lmk04821_rst_a[i];
     }
     //Init for Lmk_a
     for (int j = 0; j < LMK_COUNT; j++) {
-        uint32_t *ptr = bar1 + LMK_BASE_ADDR;
-        *ptr = lmk04821regs_a[j];
+        pci_bar_1->lmk_a_addr = lmk04821regs_a[j];
     }
 }
 
-void lmk04821_b_init(void *bar1) {
+void lmk04821_b_init(reg_addr_pci* pci_bar_1) {
     //Rst for Lmk_a
     for (int i = 0; i < 2; i++) {
-        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
-        *ptr = lmk04821_rst_b[i];
+        pci_bar_1->lmk_b_addr = lmk04821_rst_b[i];
     }
     //Init for Lmk_a
     for (int j = 0; j < LMK_COUNT; j++) {
-        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
-        *ptr = lmk04821regs_b[j];
+        pci_bar_1->lmk_b_addr = lmk04821regs_b[j];
     }
 }

Devices/lmk04821.h

@@ -1,19 +1,15 @@
-#ifndef DMADRIVER_LMK04821_H
-#define DMADRIVER_LMK04821_H
+#ifndef LMK04821_H
+#define LMK04821_H
 
 //#include "tmsgheaders.h"
 #include <stdint.h>
 #include <unistd.h>
 #include <stdio.h>
+#include "pci.h"
 
-#define     LMK_BASE_ADDR       0x10
-#define	    LMK_B_BASE_ADDR	    0x14
-#define     LMK_COUNT           129
+#define     LMK_COUNT   129
 
+void lmk04821_a_init(reg_addr_pci* pci_bar_1);
+void lmk04821_b_init(reg_addr_pci* pci_bar_1);
 
-
-void lmk04821_a_init(void *bar1);
-
-void lmk04821_b_init(void *bar1);
-
-#endif //DMADRIVER_LMK04821_H
+#endif //LMK04821_H

Devices/lmx2594.h

@@ -1,55 +1,53 @@
-#ifndef DMADRIVER_LMX2594_H
-#define DMADRIVER_LMX2594_H
+#ifndef LMX2594_H
+#define LMX2594_H
+
+#include "pci.h"
 #include "tmsgheaders.h"
 #include "lmx2594regs.h"
 
-#define     LMX_COUNT           113
-#define     LMX_BASE_ADDR       0x04
-#define     LMX_LD_STATUS_ADDR  0x18
-
+#define LMX_COUNT			113
+#define LMX_BASE_ADDR		0x04
+#define LMX_LD_STATUS_ADDR	0x18
 
 struct vco_params {
-    int vco_core;
-    double f_coremin;
-    double f_coremax;
-    int c_core_min;
-    int c_core_max;
-    int a_core_min;
-    int a_core_max;
-    uint16_t vco_cap_ctrl_strt;
-    uint16_t vco_daciset_strt;
-    uint16_t acal_cmp_dly;
-    uint16_t cal_clk_div;
-    uint16_t pfd_dly_sel;
-    uint16_t fcal_hpfd_adj;
-    // LMX parameters
-    double N_div;
-    uint32_t N;
-    int chan_div;
-    uint8_t ch_div_reg;
-    double f_vco;
-
-
-
+	int vco_core;
+	double f_coremin;
+	double f_coremax;
+	int c_core_min;
+	int c_core_max;
+	int a_core_min;
+	int a_core_max;
+	uint16_t vco_cap_ctrl_strt;
+	uint16_t vco_daciset_strt;
+	uint16_t acal_cmp_dly;
+	uint16_t cal_clk_div;
+	uint16_t pfd_dly_sel;
+	uint16_t fcal_hpfd_adj;
+	// LMX parameters
+	double N_div;
+	uint32_t N;
+	int chan_div;
+	uint8_t ch_div_reg;
+	double f_vco;
 };
 
 extern uint32_t lmx_change_freq_regs[12];
 
-void set_vco_params (struct vco_params *params);
-void send_vco_params(void *bar1, struct vco_params *params);
-struct vco_params calculate_vco_params (double lmx_freq, double f_pd);
+void set_vco_params(struct vco_params *params);
+void send_vco_params(reg_addr_pci* pci_bar_1, struct vco_params *params);
+struct vco_params calculate_vco_params(double lmx_freq, double f_pd);
 
-void lmx2594_init(void *bar1);
-void auto_cal(void *bar1);
+void lmx2594_init(reg_addr_pci* pci_bar_1);
+void auto_cal(reg_addr_pci* pci_bar_1);
 
-int lmx_freq_set_main_band(void *bar1, double freq, double f_pd);
-int lmx_freq_set_main_band_int_mode(void *bar1, double freq, double f_pd);
-int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd);
-int lmx_freq_set_out_of_band_int_mode(void *bar1, double freq, double f_pd);
+int lmx_freq_set_main_band(reg_addr_pci* pci_bar_1, double freq, double f_pd);
+int lmx_freq_set_main_band_int_mode(double freq, double f_pd);
+int lmx_freq_set_out_of_band(reg_addr_pci* pci_bar_1, double freq, double f_pd);
+int lmx_freq_set_out_of_band_int_mode(double freq, double f_pd);
 
 double lmx_lower_bond_set (double freq, double f_pd);
 double lmx_get_freq(double freq);
-int lmx_freq_set(void *bar1, double freq,double f_pd);
-uint32_t lmx_ld_status(void *bar1);
+int lmx_freq_set(reg_addr_pci* pci_bar_1, double freq,double f_pd);
+uint32_t lmx_ld_status(reg_addr_pci* pci_bar_1);
 
-#endif //DMADRIVER_LMX2594_H
+#endif //LMX2594_H

Devices/max2870.c

@@ -1,35 +1,34 @@
 #include "max2870.h"
 #include "tmsgheaders.h"
 
-
 const uint32_t max2870_regs[] ={
-    0x80280000,
-    0x800303E9,
-    0x94005E42,
-    0x00000133,
-    0x638E80FC,
-    0x01400005
+	0x80280000,
+	0x800303E9,
+	0x94005E42,
+	0x00000133,
+	0x638E80FC,
+	0x01400005
 };
 
-void max2870_init(void *bar1) {
-    uint32_t cfg_reg = get_cfg_reg();
-    // Set the command to enter the 32-bit mode
-    SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_32_BIT);
-    uint32_t *ptr_cmd = bar1 + CFG_REG_ADDR;
-    *ptr_cmd = cfg_reg;
-    //Init Header
-    uint32_t *ptr = bar1 + MAX2870_BASE_ADDR;
-    *ptr = InitMAX2870Header;
-    //Init Data
-    for (int k = 0; k < sizeof(max2870_regs)/4; k++) {
-        uint32_t *ptr = bar1 + MAX2870_BASE_ADDR;
-        *ptr = max2870_regs[k];
-    }
-    usleep(1);
-    // Return to 24-bit mode
-    SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_24_BIT);
-    uint32_t *ptr_cmd_2 = bar1 + CFG_REG_ADDR;
-    *ptr_cmd_2 = cfg_reg;
-    usleep(1);
-    set_cfg_reg(cfg_reg);
+void max2870_init(reg_addr_pci* pci_bar_1) {
+	uint32_t cfg_reg = get_cfg_reg();
+
+	// Set the command to enter the 32-bit mode
+	SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_32_BIT);
+	pci_bar_1->cfg_reg_addr = cfg_reg;
+	
+	//Init Header
+	pci_bar_1->sbtmsg_addr = INIT_MAX2870_HEADER;
+	//Init Data
+	for (int k = 0; k < sizeof(max2870_regs) / 4; k++) {
+		pci_bar_1->sbtmsg_addr = max2870_regs[k];
+	}
+	usleep(1);
+
+	// Return to 24-bit mode
+	SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_24_BIT);
+	pci_bar_1->cfg_reg_addr = cfg_reg;
+	usleep(1);
+
+	set_cfg_reg(cfg_reg);
 }

Devices/max2870.h

@@ -1,6 +1,11 @@
+#ifndef MAX2870_H
+#define MAX2870_H
+
+#include "pci.h"
 #include "tmsgheaders.h"
 
+#define 	MAX2870_BASE_ADDR	0x04
 
-#define     MAX2870_BASE_ADDR       0x04
+void max2870_init(reg_addr_pci* pci_bar_1);
 
-void max2870_init(void *bar1);
+#endif //MAX2870_H

Devices/pci.h

@@ -0,0 +1,18 @@
+#ifndef PCI_H
+#define PCI_H
+
+#include <stdint.h>
+
+typedef struct {
+	uint32_t reserve_1;					//0x00
+	uint32_t sbtmsg_addr;				//0x04
+	uint32_t cfg_reg_addr;				//0x08
+	uint32_t reserve_2;					//0x0C
+	uint32_t lmk_a_addr;				//0x10
+	uint32_t lmk_b_addr;				//0x14
+	uint32_t sbtmsg_ld_status_addr;		//0x18
+	uint32_t att_pe_1_addr;				//0x1C
+	uint32_t att_pe_2_addr;				//0x20
+} reg_addr_pci;
+
+#endif /* PCI_H */

Devices/pe43711.c

@@ -1,23 +1,19 @@
 #include "pe43711.h"
 
-void pe43711_att_1_init(void *bar1) {
-    uint32_t *ptr = bar1 + PE43711_1_ADDR;
-    *ptr = PE43711_ATTEN_0DB;
+void pe43711_att_1_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->att_pe_1_addr = PE43711_ATTEN_0DB;
 }
 
-void pe43711_att_2_init(void *bar1) {
-    uint32_t *ptr = bar1 + PE43711_2_ADDR;
-    *ptr = PE43711_ATTEN_0DB;
+void pe43711_att_2_init(reg_addr_pci* pci_bar_1) {
+    pci_bar_1->att_pe_2_addr = PE43711_ATTEN_0DB;
 }
 
-void pe43711_att_1_set(void *bar1, uint8_t atten) {
-    uint32_t *ptr = bar1 + PE43711_1_ADDR;
-    *ptr = atten;
+void pe43711_att_1_set(reg_addr_pci* pci_bar_1, uint8_t atten) {
+    pci_bar_1->att_pe_1_addr = atten;
 }
 
-void pe43711_att_2_set(void *bar1, uint8_t atten) {
-    uint32_t *ptr = bar1 + PE43711_2_ADDR;
-    *ptr = atten;
+void pe43711_att_2_set(reg_addr_pci* pci_bar_1, uint8_t atten) {
+    pci_bar_1->att_pe_2_addr = atten;
 }
 
 

Devices/pe43711.h

@@ -1,8 +1,7 @@
-#include "tmsgheaders.h"
-
-#define PE43711_1_ADDR          0x1C
-#define PE43711_2_ADDR          0x20
+#ifndef PE43711_H
+#define PE43711_H
 
+#include "pci.h"
 
 #define PE43711_ATTEN_0DB           0
 #define PE43711_ATTEN_025DB         1
@@ -15,8 +14,10 @@
 #define PE43711_ATTEN_3175DB        127
 
 
-void pe43711_att_1_init(void *bar1);
-void pe43711_att_2_init(void *bar1);
+void pe43711_att_1_init(reg_addr_pci* pci_bar_1);
+void pe43711_att_2_init(reg_addr_pci* pci_bar_1);
+
+void pe43711_att_1_set(reg_addr_pci* pci_bar_1, uint8_t atten);
+void pe43711_att_2_set(reg_addr_pci* pci_bar_1, uint8_t atten);
 
-void pe43711_att_1_set(void *bar1, uint8_t atten);
-void pe43711_att_2_set(void *bar1, uint8_t atten);
+#endif /* PE43711_H */

Devices/potentiometer.c

@@ -1,54 +1,53 @@
 #include "potentiometer.h"
-
+#include "tmsgheaders.h"
 
 uint32_t pot_array [2] = {0,0};
 
-void potentiometer_set(void *bar1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b) {
+void potentiometer_set(reg_addr_pci* pci_bar_1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b) {
     usleep(1);
     uint32_t cfg_reg = get_cfg_reg();
     SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI);
-    uint32_t *spi_mode = bar1 + CFG_REG_ADDR;
-    *spi_mode = cfg_reg;
+    pci_bar_1->cfg_reg_addr = cfg_reg;
+    
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_a << TPL0202_DATA_BITP);
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_b << TPL0202_DATA_BITP);
     
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_a << TPL0202_DATA_BITP);
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_val_ch_b << TPL0202_DATA_BITP);
     // Create a header for the Potentiometer 4MOSI
     uint32_t pot_header = (ENUM_SPIMODE_4MOSI | (0x2 << BITP_POT_4MOSI_HEADER) | SB_HEADER_TERM_BIT_1);
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-    *ptr = pot_header;
+    pci_bar_1->sbtmsg_addr = pot_header;
+    
     // Send the data
-    *ptr = pot_ch_a;
-    *ptr = pot_ch_b;
+    pci_bar_1->sbtmsg_addr = pot_ch_a;
+    pci_bar_1->sbtmsg_addr = pot_ch_b;
     usleep(1);
+
     SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_1MOSI);
-    *spi_mode = cfg_reg;
+    pci_bar_1->cfg_reg_addr = cfg_reg;
     set_cfg_reg(cfg_reg);
     usleep(1);
 }
 
-void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope ) {
+void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope) {
 
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
 
     pot_array[0] = pot_ch_a;
     pot_array[1] = pot_ch_b;
 }
 
-void potentiometer_set_offset (void *bar1, uint8_t pot_offset) {
-    uint32_t pot_ch_a      =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
-      uint32_t *data = bar1 + LMX_BASE_ADDR;
+void potentiometer_set_offset (reg_addr_pci* pci_bar_1, uint8_t pot_offset) {
+    uint32_t pot_ch_a	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_A_ENUM << TPL0202_ADR_BITP)|(pot_offset << TPL0202_DATA_BITP);
     //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
-    *data = pot_ch_a;
+    pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
+    pci_bar_1->sbtmsg_addr = pot_ch_a;
 
 }
 
-void potentiometer_set_slope ( void *bar1, uint8_t pot_slope) {
-    uint32_t pot_ch_b     =    (TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
-    uint32_t *data = bar1 + LMX_BASE_ADDR;
+void potentiometer_set_slope (reg_addr_pci* pci_bar_1, uint8_t pot_slope) {
+    uint32_t pot_ch_b	=	(TPL0202_CMD_WR_WIPER_REG_ENUM << TPL0202_CMD_BITP)|(TPL0202_ADR_B_ENUM << TPL0202_ADR_BITP)|(pot_slope << TPL0202_DATA_BITP);
     //Create a header
-    *data = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
-    *data = pot_ch_b;
+    pci_bar_1->sbtmsg_addr = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_POT_4MOSI_HEADER)| TERM_BIT_1);
+    pci_bar_1->sbtmsg_addr = pot_ch_b;
 
 }

Devices/potentiometer.h

@@ -1,4 +1,7 @@
-#include "tmsgheaders.h"
+#ifndef POTENTIOMETER_H
+#define POTENTIOMETER_H
+
+#include "pci.h"
 
 #define     TPL0202_CMD_BITP                        12
 #define     TPL0202_CMD_BITM                        (0x3 << TPL0202_CMD_BITP)
@@ -19,7 +22,9 @@
 
 extern uint32_t pot_array [2];
 
-void potentiometer_set(void *bar1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b);
-void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope );
-void potentiometer_set_offset (void *bar1, uint8_t pot_offset);
-void potentiometer_set_slope ( void *bar1, uint8_t pot_slope);
+void potentiometer_set(reg_addr_pci* pci_bar_1, uint8_t pot_val_ch_a, uint8_t pot_val_ch_b);
+void potentiometer_set_qspi(uint8_t pot_offset, uint8_t pot_slope);
+void potentiometer_set_offset(reg_addr_pci* pci_bar_1, uint8_t pot_offset);
+void potentiometer_set_slope(reg_addr_pci* pci_bar_1, uint8_t pot_slope);
+
+#endif //POTENTIOMETER_H

Devices/tmsgheaders.c

@@ -1,20 +1,20 @@
 #include "tmsgheaders.h"
 
-uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF		|
-				  CFG_REG_WIDTH_SPI_TMSG_24_BIT	|
-				  CFG_REG_MOD_1					|  
-				  CFG_REG_LR_GPIO_0				|
-				  CFG_REG_HR_GPIO_0				|
-				  CFG_REG_SPI_MODE_1MOSI		|
-				  CFG_REG_SPI_CLK_10MHZ;
+uint32_t cfg_reg =	CFG_REG_RST_FOR_FPGA_OFF		|
+					CFG_REG_WIDTH_SPI_TMSG_24_BIT	|
+					CFG_REG_MOD_1					|
+					CFG_REG_LR_GPIO_0				|
+					CFG_REG_HR_GPIO_0				|
+					CFG_REG_SPI_MODE_1MOSI			|
+					CFG_REG_SPI_CLK_10MHZ;
 
 uint32_t tmsg_shift_reg = SHIFT_REG;
 
- uint32_t tmsgGpioReg = FPGA_AM_CTRL_0			| 
-						DDS_SAW1_FPGA_0			| 
+ uint32_t tmsg_gpio_reg = FPGA_AM_CTRL_0		|
+						DDS_SAW1_FPGA_0			|
 						GPIO_ADRF_V2_0			|
 						GPIO_ADRF_V1_0			|
-						REF_OFFSET_CTRL_FPGA_1	| 
+						REF_OFFSET_CTRL_FPGA_1	|
 						DDS_SAW2_FPGA_0			|
 						DDS_X2_FPGA_0			|
 						PLL_LOOP_CTRL_1			|
@@ -23,60 +23,57 @@ uint32_t tmsg_shift_reg = SHIFT_REG;
 						PLL_VTUNE_CTRL_1		|
 						AM_ALC_1_FIX_1			|
 						SW_CAP1_0				|
-						SW_CAP2_0				| 
-						SW_CAP3_0				| 
-						AM_ALC_SW_1				| 
-						SW_CAP4_0				| 
-						DDS_SYNC_FPGA_0			| 
-						DDS_RESET_FPGA_0		| 
-						DDS_SYNC_CTRL_FPGA_0	| 
-						CTRL_AM_SW3_0			| 
-						RF_SW2_0				| 
+						SW_CAP2_0				|
+						SW_CAP3_0				|
+						AM_ALC_SW_1				|
+						SW_CAP4_0				|
+						DDS_SYNC_FPGA_0			|
+						DDS_RESET_FPGA_0		|
+						DDS_SYNC_CTRL_FPGA_0	|
+						CTRL_AM_SW3_0			|
+						RF_SW2_0				|
 						RF_SW1_0;
 
 uint32_t get_cfg_reg(){
-	return cfgReg;
+	return cfg_reg;
 }
 
-void set_cfg_reg(uint32_t cfgRegToSet){
-	cfgReg = cfgRegToSet;
+void set_cfg_reg(uint32_t cfg_reg_to_set){
+	cfg_reg = cfg_reg_to_set;
 }
 
 uint32_t get_tmsg_gpio_reg(){
-	return tmsgGpioReg;
+	return tmsg_gpio_reg;
 }
 
-void set_tmsg_gpio_reg(uint32_t tmsgGpioRegToSet){
-	tmsgGpioReg = tmsgGpioRegToSet;
+void set_tmsg_gpio_reg(uint32_t tmsg_gpio_reg_to_set){
+	tmsg_gpio_reg = tmsg_gpio_reg_to_set;
 }
 
 uint32_t get_tmsg_shift_reg(){
 	return tmsg_shift_reg;
 }
 
-void set_tmsg_shift_reg(uint32_t tmsgShiftRegToSet){
-	tmsg_shift_reg = tmsgShiftRegToSet;
+void set_tmsg_shift_reg(uint32_t tmsg_shift_reg_to_set){
+	tmsg_shift_reg = tmsg_shift_reg_to_set;
 }
 
-void rst_for_fpga(void *bar1) {
-	SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
-	uint32_t *ptr = bar1 + CFG_REG_ADDR;
-	*ptr = cfgReg;
+void rst_for_fpga(reg_addr_pci* pci_bar_1) {
+	SET_REGISTER_PARAM(cfg_reg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
+	pci_bar_1->cfg_reg_addr = cfg_reg;
 	usleep(1);
-	SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_OFF);
-	*ptr = cfgReg;
+	SET_REGISTER_PARAM(cfg_reg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_OFF);
+	pci_bar_1->cfg_reg_addr = cfg_reg;
 }
 
-void shift_reg (void  *bar1) {
-	uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-	*ptr = InitShRegHeader;
-	uint32_t *data_ptr = bar1 + LMX_BASE_ADDR ;
-	*data_ptr = SHIFT_REG;
+void shift_reg (reg_addr_pci* pci_bar_1) {
+	pci_bar_1->sbtmsg_addr = INIT_SH_REG_HEADER;
+	pci_bar_1->sbtmsg_addr = SHIFT_REG;
 }
 
-void key_switch (void  *bar1, double freq, double lmx_freq) {
+void key_switch (reg_addr_pci* pci_bar_1, double freq, double lmx_freq) {
 	// uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-	// *ptr = InitShRegHeader;
+	// *ptr = INIT_SH_REG_HEADER;
 	
 	if (freq >= 100e3 && freq <= 6000e6) {
 		if (freq >= 100e3 && freq <= 1000e6) {
@@ -149,12 +146,12 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_1);
-		// *ptr = tmsgGpioReg;
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_1);
+		// *ptr = tmsg_gpio_reg;
 	}
 	else if (freq > 6000e6 && freq <= 27000e6) {
 		if (freq > 6000e6 && freq <= 7500e6){
@@ -165,8 +162,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 7500e6 && freq <= 9000e6){
 			// Data for Shift Reg
@@ -176,8 +173,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 9000e6 && freq <= 15000e6){
 			// Data for Shift Reg
@@ -187,8 +184,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 15000e6 && freq <= 18000e6){
 			// Data for Shift Reg
@@ -198,8 +195,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 18000e6 && freq <= 22000e6){
 			// Data for Shift Reg
@@ -209,8 +206,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 22000e6 && freq <= 27000e6){
 			// Data for Shift Regs
@@ -220,8 +217,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
 		}
 	
 		// // Header for GPIO_REG 1MOSI
@@ -231,19 +228,17 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		// *ptr = tmsgGpioReg;
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
+		// *ptr = tmsg_gpio_reg;
 
-		// Addr CFG_REG
-		uint32_t *ptr  = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_1);
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_0);
-		*ptr = cfgReg;
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_1);
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_0);
+		pci_bar_1->cfg_reg_addr = cfg_reg;
 	}
 	else if (freq > 27000e6 && freq <= 37000e6) {
 		double freq_div2 = freq / 2;
@@ -263,8 +258,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq_div2 > 18000e6 && freq_div2 <= 18500e6)
 		{
@@ -275,8 +270,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		
 		// // Header for GPIO_REG 1MOSI
@@ -286,19 +281,17 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		// *ptr = tmsgGpioReg;
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
+		// *ptr = tmsg_gpio_reg;
 
-		// Addr CFG_REG
-		uint32_t *ptr = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
-		*ptr = cfgReg;
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
+		pci_bar_1->cfg_reg_addr = cfg_reg;
 	}
 	else if (freq > 37000e6 && freq <= 45000e6) {
 		double freq_div2 = freq / 2;
@@ -310,8 +303,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if(freq_div2 > 22000e6 && freq_div2 <= 27500e6){
 			// Data for Shift Regs
@@ -321,8 +314,8 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
 			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
-			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+			SET_REGISTER_PARAM(tmsg_gpio_reg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
 		}
 
 		// Header for GPIO_REG 1MOSI
@@ -332,19 +325,17 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// 		SB_HEADER_TERM_BIT_1;
 		
 		// Data for GPIO_REG
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
-		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
-		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		// *ptr = tmsgGpioReg;
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		SET_REGISTER_PARAM(tmsg_gpio_reg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
+		// *ptr = tmsg_gpio_reg;
 
-		// Addr CFG_REG
-		uint32_t *ptr = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
-		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
-		*ptr = cfgReg;
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
+		SET_REGISTER_PARAM(cfg_reg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
+		pci_bar_1->cfg_reg_addr = cfg_reg;
 	}
 };
 	

Devices/tmsgheaders.h

@@ -3,6 +3,7 @@
 #include <stdint.h>
 #include <unistd.h>
 #include <stdio.h>
+#include "pci.h"
 
 // Device address 
 #define     TMSG_BASE_ADDR              0x04
@@ -67,17 +68,17 @@
 
 
 // Headers 1-MOSI
-#define LMX2594_RST_HEADER  ((0 << 23) | (DeviceIdLmx2594 << 18) | (2 << 1) | 1)
-#define GPIO_INIT_HEADER    ((0 << 23) | (DeviceIdGpio1 << 18) | (Gpio1InitWordNum << 1) | 1)
-#define InitGpio2Header    ((0 << 23) | (DeviceIdGpio2 << 18) | (Gpio2InitWordNum << 1) | 1)
-#define TempSensHeader     ((0 << 23) | (DeviceIdTemp << 18) | (TempSensWordNum << 1) | 1)
-#define InitLMX2594Header  ((0 << 23) | (DeviceIdLmx2594 << 18) | (Lmx2594InitWordNum << 1) | 1)
-#define InitDDSHeader      ((0 << 23) | (DeviceIdDDS << 18) | (DDSInitWordNum << 1) | 1)
-#define InitMAX2870Header  ((0 << 23) | (DeviceIdMax2870 << 18) | (MaxInitWordNum << 1) | 1)
-#define InitPotHeader      ((0 << 23) | (DeviceIdPot << 18) | (PotWordInitNum << 1) | 1)
-#define InitDacHeader      ((0 << 23) | (DeviceIdDac << 18) | (DacWordInitNum << 1) | 1)
-#define InitAttHeader      ((0 << 23) | (DeviceIdAtt << 18) | (AttWordInitNum << 1) | 1)
-#define InitShRegHeader    ((0 << 23) | (DeviceIdShReg << 18) | (ShRegWordInitNum << 1) | 1)
+#define LMX2594_RST_HEADER		((0 << 23) | (DeviceIdLmx2594 << 18) | (2 << 1) | 1)
+#define INIT_GPIO1_HEADER		((0 << 23) | (DeviceIdGpio1 << 18) | (Gpio1InitWordNum << 1) | 1)
+#define INIT_GPIO2_HEADER		((0 << 23) | (DeviceIdGpio2 << 18) | (Gpio2InitWordNum << 1) | 1)
+#define TEMP_SENS_HEADER		((0 << 23) | (DeviceIdTemp << 18) | (TempSensWordNum << 1) | 1)
+#define INIT_LMX2594_HEADER		((0 << 23) | (DeviceIdLmx2594 << 18) | (Lmx2594InitWordNum << 1) | 1)
+#define INIT_DDS_HEADER			((0 << 23) | (DeviceIdDDS << 18) | (DDSInitWordNum << 1) | 1)
+#define INIT_MAX2870_HEADER		((0 << 23) | (DeviceIdMax2870 << 18) | (MaxInitWordNum << 1) | 1)
+#define INIT_POT_HEADER			((0 << 23) | (DeviceIdPot << 18) | (PotWordInitNum << 1) | 1)
+#define INIT_DAC_HEADER			((0 << 23) | (DeviceIdDac << 18) | (DacWordInitNum << 1) | 1)
+#define INIT_ATT_HEADER			((0 << 23) | (DeviceIdAtt << 18) | (AttWordInitNum << 1) | 1)
+#define INIT_SH_REG_HEADER		((0 << 23) | (DeviceIdShReg << 18) | (ShRegWordInitNum << 1) | 1)
 
 // Headers 4-Mosi
 #define BITP_LMX2594_4MOSI_HEADER  12
@@ -302,35 +303,35 @@
 #define SHIFT_REG_SW3_RF_1				(0x1 << SHIFT_REG_SW3_RF_BITP)
 
 #define SHIFT_REG ((SHIFT_REG_SW_RF << 1) | \
-                    (SHIFT_REG_SW4_RF<<2) | \
-                    (SHIFT_REG_GPIO_SW_015_RF<<3) | \
-                    (SHIFT_REG_GPIO_SW_X2_RF<<0) | \
-                    (SHIFT_REG_SW1_RF <<5) | \
-                    (SHIFT_REG_SW_MIXER_RF <<4))
+					(SHIFT_REG_SW4_RF<<2) | \
+					(SHIFT_REG_GPIO_SW_015_RF<<3) | \
+					(SHIFT_REG_GPIO_SW_X2_RF<<0) | \
+					(SHIFT_REG_SW1_RF <<5) | \
+					(SHIFT_REG_SW_MIXER_RF <<4))
 
 #define GPIO_REG  ((FPGA_AM_CTRL << 22) | \
-                  (DDS_SAW1_FPGA << 21) | \
-                  (GPIO_ADRF_V2 << 20) | \
-                  (GPIO_ADRF_V1 << 19) | \
-                  (REF_OFFSET_CTRL_FPGA << 18) | \
-                  (DDS_SAW2_FPGA << 17) | \
-                  (DDS_X2_FPGA << 16) | \
-                  (PLL_LOOP_CTRL << 15) | \
-                  (PLL_SYNC << 14) | \
-                  (PLL_SYNC_CTRL << 13) | \
-                  (PLL_VTUNE_CTRL << 12) | \
-                  (AM_ALC_1_FIX << 11) | \
-                  (SW_CAP1 << 10) | \
-                  (SW_CAP2 << 9) | \
-                  (SW_CAP3 << 8) | \
-                  (AM_ALC_SW << 7) | \
-                  (SW_CAP4 << 6) | \
-                  (DDS_SYNC_FPGA << 5) | \
-                  (DDS_RESET_FPGA << 4) | \
-                  (DDS_SYNC_CTRL_FPGA << 3) | \
-                  (CTRL_AM_SW3 << 2) | \
-                  (RF_SW2 << 1) | \
-                  (RF_SW1 << 0))
+				  (DDS_SAW1_FPGA << 21) | \
+				  (GPIO_ADRF_V2 << 20) | \
+				  (GPIO_ADRF_V1 << 19) | \
+				  (REF_OFFSET_CTRL_FPGA << 18) | \
+				  (DDS_SAW2_FPGA << 17) | \
+				  (DDS_X2_FPGA << 16) | \
+				  (PLL_LOOP_CTRL << 15) | \
+				  (PLL_SYNC << 14) | \
+				  (PLL_SYNC_CTRL << 13) | \
+				  (PLL_VTUNE_CTRL << 12) | \
+				  (AM_ALC_1_FIX << 11) | \
+				  (SW_CAP1 << 10) | \
+				  (SW_CAP2 << 9) | \
+				  (SW_CAP3 << 8) | \
+				  (AM_ALC_SW << 7) | \
+				  (SW_CAP4 << 6) | \
+				  (DDS_SYNC_FPGA << 5) | \
+				  (DDS_RESET_FPGA << 4) | \
+				  (DDS_SYNC_CTRL_FPGA << 3) | \
+				  (CTRL_AM_SW3 << 2) | \
+				  (RF_SW2 << 1) | \
+				  (RF_SW1 << 0))
 
 // Macros to set register parameter
 #define SET_REGISTER_PARAM( REGISTER, BITM, BITP, PARAMETER )\
@@ -377,21 +378,19 @@
 #define    CFG_REG_SPI_CLK_10MHZ                (0x0 << CFG_REG_SPI_CLK_BITP)
 #define    CFG_REG_SPI_CLK_50MHZ                (0x1 << CFG_REG_SPI_CLK_BITP)
 
-#define    LMX_BASE_ADDR            0x04
+#define    LMX_BASE_ADDR                        0x04
 
-void rst_for_fpga(void *bar1);
-
-void shift_reg (void  *bar1);
-
-void key_switch (void  *bar1, double freq,double lmx_freq);
+void rst_for_fpga(reg_addr_pci* pci_bar_1);
+void shift_reg(reg_addr_pci* pci_bar_1);
+void key_switch(reg_addr_pci* pci_bar_1, double freq, double lmx_freq);
 
 uint32_t get_cfg_reg();
-void set_cfg_reg(uint32_t cfgRegToSet);
+void set_cfg_reg(uint32_t cfg_reg_to_set);
 
 uint32_t get_tmsg_gpio_reg();
-void set_tmsg_gpio_reg(uint32_t tmsgGpioRegToSet);
+void set_tmsg_gpio_reg(uint32_t tmsg_gpio_reg_to_set);
 
 uint32_t get_tmsg_shift_reg();
-void set_tmsg_shift_reg(uint32_t tmsgShiftRegToSet);
+void set_tmsg_shift_reg(uint32_t tmsg_shift_reg_to_set);
 
 #endif //DMADRIVER_TMSGHEADERS_H

command.c

@@ -23,38 +23,38 @@ uint16_t attCode[1] = {0};
 uint16_t offsetCode[1] = {0};
 uint16_t slopeCode[1] = {0};
 
-//Массив структур Command, который связывает строки команд с соответствующими функциями.
-Command commands[] = {
-	{"TMSG44:FREQ ", 	handleFreqCmd},
-	{"TMSG44:LD?", 		handleLdCmd},
-	{"TMSG44:POW ", 	handlePowCmd},
-	{"TMSG44:ARM ", 	handleArmCmd},
-	{"TMSG44:ATT ", 	handleAttCmd},
-	{"*IDN?", 			handleIdnCmd},
-	{"TMSG44:OFFSET ",	handleOffsetCmd},
-	{"TMSG44:SLOPE ",	handleSlopeCmd},
+//Массив структур command, который связывает строки команд с соответствующими функциями.
+command commands[] = {
+	{"TMSG44:FREQ ", 	handle_freq_cmd},
+	{"TMSG44:LD?", 		handle_ld_cmd},
+	{"TMSG44:POW ", 	handle_pow_cmd},
+	{"TMSG44:ARM ", 	handle_arm_cmd},
+	{"TMSG44:ATT ", 	handle_att_cmd},
+	{"*IDN?", 			handle_idn_cmd},
+	{"TMSG44:OFFSET ",	handle_offset_cmd},
+	{"TMSG44:SLOPE ",	handle_slope_cmd},
 	{NULL, NULL} // Завершающий элемент для обозначения конца массива
 };
 
 //handleXXXXCmd - обработчики команд
-void handleFreqCmd(const char* recvBuff)
+void handle_freq_cmd(const char* recv_buff)
 {
 	
 	printf("\nHandle command \"TMSG44:FREQ\"\n");
 	double freq[1] = {0};
 	double lmx_freq = 0;
 
-	splitLexeme(recvBuff, freq, sizeof(freq[0]), convertToDouble);
+	split_lexeme(recv_buff, freq, sizeof(freq[0]), convert_to_double);
 	
 	lmx_freq = lmx_get_freq(freq[0]);
-	f_pd = ad9912_set(bar1, lmx_freq, f_pd);
+	f_pd = ad9912_set(pci_bar_1, lmx_freq, f_pd);
 	printf("f_pd frequency is set to %.6f MHz\n", f_pd/1e6);
-    lmx_freq_set(bar1, lmx_freq, f_pd);
+    lmx_freq_set(pci_bar_1, lmx_freq, f_pd);
 	// Switch the keys 
-	key_switch(bar1, freq[0],lmx_freq);
+	key_switch(pci_bar_1, freq[0],lmx_freq);
     printf("The frequency is set to %.2f MHz\n", freq[0]/1e6);
 	// Send the data 
-	send_data_qspi(bar1);
+	send_data_qspi(pci_bar_1);
 	   // Return the 1 MOSI mode
     // usleep(1);
 	// cfg_reg = get_cfg_reg();
@@ -63,37 +63,46 @@ void handleFreqCmd(const char* recvBuff)
     // set_cfg_reg(cfg_reg);
 	
 }
-void send_data_qspi(void *bar1) {
+void send_data_qspi(reg_addr_pci* pci_bar_1) {
 	// get the gpio reg and shift reg data 
 	uint32_t gpio_reg = get_tmsg_gpio_reg();
 	uint32_t shift_reg = get_tmsg_shift_reg();
+	
 	// Create a header 4 Mosi mode
-	uint32_t qspi_header = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_GPIO_4MOSI_HEADER) |(0x1 << BITP_SHIFT_REG_4MOSI_HEADER )| ((sizeof(ad9912_ftw_regs_qspi) / 4) << BITP_DDS_4MOSI_HEADER) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | TERM_BIT_1);
-	uint32_t *data = bar1 + LMX_BASE_ADDR;
-	*data = qspi_header;
+	uint32_t qspi_header = ((ENUM_SPIMODE_4MOSI) | 
+							(0x1 << BITP_GPIO_4MOSI_HEADER) | 
+							(0x1 << BITP_SHIFT_REG_4MOSI_HEADER ) | 
+							((sizeof(ad9912_ftw_regs_qspi) / 4) << BITP_DDS_4MOSI_HEADER) | 
+							((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | 
+							(TERM_BIT_1));
+	
+	pci_bar_1->sbtmsg_addr = qspi_header;
+
 	// Initialize the registers
 	// Send the data for AD9912
 	for (int i = 0; i < sizeof(ad9912_ftw_regs_qspi) / 4; i++) {
-		*data = ad9912_ftw_regs_qspi[i];
+		pci_bar_1->sbtmsg_addr = ad9912_ftw_regs_qspi[i];
 	}
+
 	// Send the data for the GPIO
-	*data = gpio_reg;
+	pci_bar_1->sbtmsg_addr = gpio_reg;
+
 	// Send the data for LMX2594
 	for (int i = 0; i < sizeof(lmx_change_freq_regs) / 4; i++) {
-		*data = lmx_change_freq_regs[i];
+		pci_bar_1->sbtmsg_addr = lmx_change_freq_regs[i];
 	}
-	// Send the data for the shift register
-	*data = shift_reg;
 
+	// Send the data for the shift register
+	pci_bar_1->sbtmsg_addr = shift_reg;
 }
 
-void handleLdCmd(const char* recvBuff)
+void handle_ld_cmd(const char* recv_buff)
 {
 	char messageLd[] = "1\n";
 
 	printf("\nHandle command \"TMSG44:LD?\"\n");
 
-	uint32_t ld_status = lmx_ld_status(bar1);
+	uint32_t ld_status = lmx_ld_status(pci_bar_1);
 
 	clock_t before = clock();
 	clock_t difference;
@@ -111,7 +120,7 @@ void handleLdCmd(const char* recvBuff)
 			printf("LD timeout\n");
 			break;
 		}
-		ld_status = lmx_ld_status(bar1);
+		ld_status = lmx_ld_status(pci_bar_1);
 		// printf("WHILE LD status: %d\n", ld_status);
 	}
 
@@ -120,34 +129,34 @@ void handleLdCmd(const char* recvBuff)
 	printf("\nSend msg LD: %d!\n", ld_status);
 }
 
-void handlePowCmd(const char* recvBuff)
+void handle_pow_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"TMSG44:POW\"\n");
 	double pow[1] = {0};
 
-	splitLexeme(recvBuff, pow, sizeof(pow[0]), convertToDouble);
+	split_lexeme(recv_buff, pow, sizeof(pow[0]), convert_to_double);
 	printf("%f\n", pow[0]);
 }
 
-void handleArmCmd(const char* recvBuff)
+void handle_arm_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"TMSG44:ARM\"\n");
 
-	splitLexeme(recvBuff, armCode, sizeof(armCode[0]), convertToUInt16);
+	split_lexeme(recv_buff, armCode, sizeof(armCode[0]), convert_to_uint16);
 	printf("\n%u\n", armCode[0]);
-	dac8811_set_qspi(bar1,armCode[0]);
+	dac8811_set_qspi(pci_bar_1, armCode[0]);
 }
 
-void handleAttCmd(const char* recvBuff)
+void handle_att_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"TMSG44:ATT\"\n");
 
-	splitLexeme(recvBuff, attCode, sizeof(attCode[0]), convertToUInt16);
+	split_lexeme(recv_buff, attCode, sizeof(attCode[0]), convert_to_uint16);
 	printf("\n%u\n", attCode[0]);
-	dac8811_att_set_qspi(bar1, attCode[0]);
+	dac8811_att_set_qspi(pci_bar_1, attCode[0]);
 }
 
-void handleIdnCmd(const char* recvBuff)
+void handle_idn_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"*IDN?\"\n");
 
@@ -155,82 +164,82 @@ void handleIdnCmd(const char* recvBuff)
 	send(conn_fd, messageIdn, sizeof(messageIdn), 0);
 }
 
-void handleOffsetCmd(const char* recvBuff)
+void handle_offset_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"TMSG44:OFFSET\"\n");
 
-	splitLexeme(recvBuff, offsetCode, sizeof(offsetCode[0]), convertToUInt16);
+	split_lexeme(recv_buff, offsetCode, sizeof(offsetCode[0]), convert_to_uint16);
 	printf("\n%u\n", offsetCode[0]);
-	potentiometer_set_offset(bar1, offsetCode[0]);
+	potentiometer_set_offset(pci_bar_1, offsetCode[0]);
 }
 
-void handleSlopeCmd(const char* recvBuff)
+void handle_slope_cmd(const char* recv_buff)
 {
 	printf("\nHandle command \"TMSG44:SLOPE\"\n");
-	splitLexeme(recvBuff, slopeCode, sizeof(slopeCode[0]), convertToUInt16);
+	split_lexeme(recv_buff, slopeCode, sizeof(slopeCode[0]), convert_to_uint16);
 	printf("\n%u\n", slopeCode[0]);
-	potentiometer_set_slope(bar1, slopeCode[0]);
+	potentiometer_set_slope(pci_bar_1, slopeCode[0]);
 }
 
-//Проходим по массиву команд и ищем команду, которая совпадает с началом строки recvBuff. 
+//Проходим по массиву команд и ищем команду, которая совпадает с началом строки recv_buff. 
 //Если команда найдена, вызывается соответствующая функция-обработчик
-void processCommand(const char* recvBuff) 
+void process_command(const char* recv_buff) 
 {
 	for (int i = 0; commands[i].command != NULL; i++) 
 	{
-		if (!strncasecmp(recvBuff, commands[i].command, strlen(commands[i].command))) 
+		if (!strncasecmp(recv_buff, commands[i].command, strlen(commands[i].command))) 
 		{
-			commands[i].handler(recvBuff);
+			commands[i].handler(recv_buff);
 			return;
 		}
 	}
-	printf("\nUnknown command: %s\n", recvBuff);
+	printf("\nUnknown command: %s\n", recv_buff);
 }
 
 // Преобразование строки в uint16_t
-void convertToUInt16(const char *str, void *output) 
+void convert_to_uint16(const char *str, void *output) 
 {
 	*(uint16_t *)output = (uint16_t)strtoul(str, NULL, 10);
 }
 
 // Преобразование строки в unsigned long long int
-void convertToUint64(const char *str, void *output) 
+void convert_to_uint64(const char *str, void *output) 
 {
 	*(uint64_t *)output = (uint64_t)strtoull(str, NULL, 10);
 }
 
 // Преобразование строки в double
-void convertToDouble(const char *str, void *output) 
+void convert_to_double(const char *str, void *output) 
 {
 	*(double *)output = strtod(str, NULL);
 }
 
 // Универсальная функция для разделения строки на лексемы
-void splitLexeme(const char *ptrSCPI, void *numOutAndValue, size_t elementSize, ConvertFunc convertFunc) 
+void split_lexeme(const char *ptr_scpi, void *out_value, size_t element_size, convert_func_type convert_func) 
 {
 	uint8_t counter = 0;
 
 	// Разделители лексем
 	const char charSeparator[] = {" "};
-	char *ptrLexeme = NULL;
+	char *ptr_lexeme = NULL;
 	// Указатель для хранения контекста токенизации
 	char *savePtr;
 
 	// Инициализируем функцию
-	ptrLexeme = strtok_r((char *)ptrSCPI, charSeparator, &savePtr);
+	ptr_lexeme = strtok_r((char *)ptr_scpi, charSeparator, &savePtr);
 
 	// Ищем лексемы разделенные разделителем
-	ptrLexeme = strtok_r(NULL, charSeparator, &savePtr);
+	ptr_lexeme = strtok_r(NULL, charSeparator, &savePtr);
 
 	// Ищем лексемы строки
-	while (ptrLexeme) {
+	while (ptr_lexeme) {
 		// Проверяем, является ли первый символ лексемы числом
-		if(('0' <= ptrLexeme[0]) && (ptrLexeme[0] <= '9')) {
+		if(('0' <= ptr_lexeme[0]) && (ptr_lexeme[0] <= '9')) {
 			// Преобразуем строку с числом в число
-			convertFunc(ptrLexeme, (uint8_t *)numOutAndValue + counter * elementSize);
+			convert_func(ptr_lexeme, (uint8_t *)out_value + counter * element_size);
 			counter++;
 		}
 		// Ищем лексемы разделенные разделителем
-		ptrLexeme = strtok_r(NULL, charSeparator, &savePtr);
+		ptr_lexeme = strtok_r(NULL, charSeparator, &savePtr);
 	}
 }

command.h

@@ -4,6 +4,7 @@
 // Включение необходимых стандартных библиотек
 #include <stdint.h>
 #include <stddef.h>
+#include "Devices//pci.h"
 
 // Определение констант
 
@@ -16,36 +17,37 @@ extern volatile int conn_fd;
 extern volatile int pci_fd;
 
 extern  void *bar1;
+extern reg_addr_pci* pci_bar_1;
 
 // extern uint16_t armCode[1];
 // extern uint16_t attCode[1];
 
-typedef void (*CommandHandler)(const char*);
+typedef void (*command_handler)(const char*);
 
 // Объявление структур
 typedef struct {
 	const char* command;
-	CommandHandler handler;
-} Command;
+	command_handler handler;
+} command;
 
 // Определяем тип функции преобразования
-typedef void (*ConvertFunc)(const char *str, void *output);
+typedef void (*convert_func_type)(const char *str, void *output);
 
 // Прототипы функций
-void send_data_qspi(void *bar1);
-void handleCloseSignal(int signal);
-void handleFreqCmd(const char* recvBuff);
-void handleLdCmd(const char* recvBuff);
-void handlePowCmd(const char* recvBuff);
-void handleArmCmd(const char* recvBuff);
-void handleAttCmd(const char* recvBuff);
-void handleIdnCmd(const char* recvBuff);
-void handleOffsetCmd(const char* recvBuff);
-void handleSlopeCmd(const char* recvBuff);
-void processCommand(const char* recvBuff);
-void convertToUInt16(const char *str, void *output);
-void convertToUint64(const char *str, void *output);
-void convertToDouble(const char *str, void *output);
-void splitLexeme(const char *ptrSCPI, void *numOutAndValue, size_t elementSize, ConvertFunc convertFunc);
+void send_data_qspi(reg_addr_pci* pci_bar_1);
+void handle_close_signal(int signal);
+void handle_freq_cmd(const char* recv_buff);
+void handle_ld_cmd(const char* recv_buff);
+void handle_pow_cmd(const char* recv_buff);
+void handle_arm_cmd(const char* recv_buff);
+void handle_att_cmd(const char* recv_buff);
+void handle_idn_cmd(const char* recv_buff);
+void handle_offset_cmd(const char* recv_buff);
+void handle_slope_cmd(const char* recv_buff);
+void process_command(const char* recv_buff);
+void convert_to_uint16(const char *str, void *output);
+void convert_to_uint64(const char *str, void *output);
+void convert_to_double(const char *str, void *output);
+void split_lexeme(const char *ptr_scpi, void *out_value, size_t element_size, convert_func_type convert_func);
 
 #endif /* COMMAND_H */

main.c

@@ -11,6 +11,8 @@
 #include <fcntl.h>
 #include <sys/time.h>
 
+#include "Devices//pci.h"
+
 #include "Devices//tmsgheaders.h"
 #include "Devices//lmx2594.h"
 #include "Devices//max2870.h"
@@ -21,6 +23,7 @@
 
 #include "command.h"
 
+
 #define REQUESTED_MEMORY_SIZE  0x1000
 #define SERVER_PORT 5025
 #define BACKLOG 10
@@ -30,6 +33,7 @@ volatile int pci_fd = 0;
 int listen_fd = 0;
 
 void *bar1;
+reg_addr_pci* pci_bar_1;
 
 //Обработчик ошибок
 void error(const char *msg)
@@ -49,7 +53,7 @@ void error(const char *msg)
 } 
 
 //Обработчик сигнала SIGINT завершения программы при нажатии Ctrl+C
-void handleCloseSignal(int signal)
+void handle_close_signal(int signal)
 {
 	if (signal == SIGINT) 
 	{
@@ -84,11 +88,11 @@ int main(int argc, char *argv[])
 	struct sockaddr_in serv_addr, client_addr;
 	
 	// Приёмный буффер для сокета
-	char recvBuff[1024];
+	char recv_buff[1024];
 	// Разделители команд
 	const char charSeparator[] = {"\n"};
 	// Указатель команды
-	char *ptrLexeme = NULL;
+	char *ptr_lexeme = NULL;
 	// Указатель для хранения контекста токенизации
 	char *savePtr = NULL;
 
@@ -106,31 +110,32 @@ int main(int argc, char *argv[])
         return 1;
     }
 
-    lmk04821_a_init(bar1);
+	pci_bar_1 = (reg_addr_pci*)bar1;
+
+    lmk04821_a_init(pci_bar_1);
     usleep(500);
-    lmk04821_b_init(bar1);
-	pe43711_att_1_init(bar1);
+    lmk04821_b_init(pci_bar_1);
+	pe43711_att_1_init(pci_bar_1);
 	usleep(1);
-	pe43711_att_2_init(bar1);
-    rst_for_fpga(bar1);
-    shift_reg(bar1);
-	potentiometer_set(bar1, 0, 0);
-	max2870_init(bar1);
-    ad9912_init(bar1);
-    lmx2594_init(bar1);
+	pe43711_att_2_init(pci_bar_1);
+    rst_for_fpga(pci_bar_1);
+    shift_reg(pci_bar_1);
+	potentiometer_set(pci_bar_1, 0, 0);
+	max2870_init(pci_bar_1);
+    ad9912_init(pci_bar_1);
+    lmx2594_init(pci_bar_1);
 
 	usleep(1000);
+	
 	// Установка режима SPI
 	uint32_t cfg_reg = get_cfg_reg();
-    SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI);
+	SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI);
 	SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_CLK_BITM, CFG_REG_SPI_CLK_BITP, CFG_REG_SPI_CLK_50MHZ); 
-    uint32_t *spi_mode = bar1 +CFG_REG_ADDR;
-    *spi_mode = cfg_reg;
+	pci_bar_1->cfg_reg_addr = cfg_reg;
 	set_cfg_reg(cfg_reg);
 
-
 	// Установка обработчика сигналов
-	signal(SIGINT, handleCloseSignal);
+	signal(SIGINT, handle_close_signal);
 
 	listen_fd = socket(AF_INET, SOCK_STREAM, 0);
 	if (listen_fd < 0)
@@ -171,10 +176,10 @@ int main(int argc, char *argv[])
 		printf("Connection established with client\n");
 
 		//Очистка буфера
-		memset(recvBuff, 0, sizeof(recvBuff));
+		memset(recv_buff, 0, sizeof(recv_buff));
 		double time_begin =0;
 
-		while ((n = recv(conn_fd, recvBuff, sizeof(recvBuff) - 1, 0)) > 0)
+		while ((n = recv(conn_fd, recv_buff, sizeof(recv_buff) - 1, 0)) > 0)
 		{
 			gettimeofday(&tv, NULL);
 			double time_end = ((double)tv.tv_sec) * 1000 +
@@ -183,29 +188,29 @@ int main(int argc, char *argv[])
 			double total_time_ms = time_end - time_begin;
 
 			printf("TOTAL TIME (ms) = %f\n", total_time_ms);
-			recvBuff[n] = 0;
+			recv_buff[n] = 0;
 		
-			if(fputs(recvBuff, stdout) == EOF)
+			if(fputs(recv_buff, stdout) == EOF)
 			{
 				printf("\n Error : Fputs error\n");
 				break;
 			}
 		
 			// Указатель команды
-			ptrLexeme = NULL;
+			ptr_lexeme = NULL;
 			// Указатель для хранения контекста токенизации
 			savePtr = NULL;
 
 			// Инициализируем функцию и ищем команду в строке
-			ptrLexeme = strtok_r(recvBuff, charSeparator, &savePtr);
+			ptr_lexeme = strtok_r(recv_buff, charSeparator, &savePtr);
 			
 			// Выполняем команды, пока не дойдём до конца приёмного буффера
-			while (ptrLexeme) {
+			while (ptr_lexeme) {
 				// Запуск парсера команд
-				processCommand(ptrLexeme);
+				process_command(ptr_lexeme);
 
 				// Ищем команды разделенные разделителем
-				ptrLexeme = strtok_r(NULL, charSeparator, &savePtr);
+				ptr_lexeme = strtok_r(NULL, charSeparator, &savePtr);
 			}
 			gettimeofday(&tv, NULL);