Calibration assist

Devices/lmx2594.c

@@ -145,6 +145,16 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
     double N_div;
     N_div = freq / f_pd;
 
+    int vco_core;
+    double f_coremin;
+    double f_coremax;
+    int c_core_min;
+    int c_core_max;
+    int a_core_min;
+    int a_core_max;
+    uint16_t vco_cap_ctrl_strt;
+    uint16_t vco_daciset_strt;
+
     // divide whole part and fractional part
     uint32_t N = (uint32_t) N_div;
     // In frac part there is separate denominator and numerator
@@ -156,6 +166,90 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
         frac_n = 0;
         frac_d = 524287;
     }
+
+    // Partial assist for the calibration
+
+    //Determine a VCO core and other parameters
+
+    if (freq >= 7500e6 && freq <= 8600e6) {
+        vco_core = 1;
+        f_coremin = 7500e6;
+        f_coremax = 8600e6;
+        c_core_min = 164;
+        c_core_max = 12;
+        a_core_min = 299;
+        a_core_max = 240;
+    }
+    else if (freq > 8600e6 && freq < 9800e6) {
+        vco_core = 2;
+        f_coremin = 8600e6;
+        f_coremax = 9800e6;
+        c_core_min = 165;
+        c_core_max = 16;
+        a_core_min = 356;
+        a_core_max = 247;
+    }
+    else if (freq >= 9800e6 && freq <= 10800e6) {
+        vco_core = 3;
+        f_coremin = 9800e6;
+        f_coremax = 10800e6;
+        c_core_min = 158;
+        c_core_max = 19;
+        a_core_min = 324;
+        a_core_max = 224;
+    }
+    else if (freq > 10800e6 && freq <= 12000e6) {
+        vco_core = 4;
+        f_coremin = 10800e6;
+        f_coremax = 12000e6;
+        c_core_min = 140;
+        c_core_max = 0;
+        a_core_min = 383;
+        a_core_max = 244;
+    }
+    else if (freq > 12000e6 && freq <= 12900e6) {
+        vco_core = 5;
+        f_coremin = 12000e6;
+        f_coremax = 12900e6;
+        c_core_min = 183;
+        c_core_max = 36;
+        a_core_min = 205;
+        a_core_max = 146;
+    }
+    else if (freq > 12900e6 && freq <= 13900e6) {
+        vco_core = 6;
+        f_coremin = 12900e6;
+        f_coremax = 13900e6;
+        c_core_min = 155;
+        c_core_max = 6;
+        a_core_min = 242;
+        a_core_max = 163;
+    }
+    else if (freq > 13900e6 && freq <= 15000e6) {
+        vco_core = 7;
+        f_coremin = 13900e6;
+        f_coremax = 15000e6;
+        c_core_min = 175;
+        c_core_max = 19;
+        a_core_min = 323;
+        a_core_max = 244;
+    };
+    vco_cap_ctrl_strt = round(c_core_min - (c_core_min - c_core_max) * (freq - f_coremin) / (f_coremax - f_coremin));
+    printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
+    vco_daciset_strt = round(a_core_min + (a_core_min - a_core_max) * (freq - f_coremin) / (f_coremax - f_coremin));
+    printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
+
+    // Calibration assist 
+    //Set the VCO_CORE 
+    lmx2594regs[112 - VCO_SEL] = lmx2594regs[112 - VCO_SEL] & (~BITM_LMX2594_R20_VCO_SEL);
+    lmx2594regs[112 - VCO_SEL] = lmx2594regs[112 - VCO_SEL] | (vco_core << BITP_LMX2594_R20_VCO_SEL);
+    // Set the VCO_CAP_CTRL
+    lmx2594regs[112 - VCO_CAP_CTRL] = lmx2594regs[112 - VCO_CAP_CTRL] & (~BITM_LMX2594_R19_VCO_CAP_CTRL);
+    lmx2594regs[112 - VCO_CAP_CTRL] = lmx2594regs[112 - VCO_CAP_CTRL] | (vco_cap_ctrl_strt << BITP_LMX2594_R19_VCO_CAP_CTRL);
+    // Set the VCO_DACISET
+    lmx2594regs[112 - VCO_DACISET] = lmx2594regs[112 - VCO_DACISET] & (~BITM_LMX2594_R17_VCO_DACISET);
+    lmx2594regs[112 - VCO_DACISET] = lmx2594regs[112 - VCO_DACISET] | (vco_daciset_strt << BITP_LMX2594_R17_VCO_DACISET);
+
     // Recommended sequnce for changin freq
     // 1. Change the N-div value
     // 2. Change the PLL numerator and denominator
@@ -206,6 +300,9 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
     // Show the all the upper 16 bits of the register lmx2594regs[PLL_N_S]
     // Determine which regs are changed and send only those
     uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112 - VCO_SEL],
+            lmx2594regs[112 - VCO_CAP_CTRL],
+            lmx2594regs[112 - VCO_DACISET],
             lmx2594regs[112-MASH_ORDER],
             lmx2594regs[112-PFD_DLY_SEL],
             lmx2594regs[112-PLL_N_S],
@@ -244,6 +341,16 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
     double vco_div = 7.5e9 / freq;
     double N_div;
 
+    int vco_core;
+    double f_coremin;
+    double f_coremax;
+    int c_core_min;
+    int c_core_max;
+    int a_core_min;
+    int a_core_max;
+    uint16_t vco_cap_ctrl_strt;
+    uint16_t vco_daciset_strt;
+
     // minimum N_div value is 28 and Vco frequency can't be less than 7.5 GHz
     if (f_vco < 7.5e9) {
         if (vco_div > 2 && vco_div <= 4)
@@ -387,6 +494,87 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
     }
     // Partial assist for the calibration
 
+    //Determine a VCO core and other parameters
+
+    if (f_vco >= 7500e6 && f_vco <= 8600e6) {
+        vco_core = 1;
+        f_coremin = 7500e6;
+        f_coremax = 8600e6;
+        c_core_min = 164;
+        c_core_max = 12;
+        a_core_min = 299;
+        a_core_max = 240;
+    }
+    else if (f_vco > 8600e6 && f_vco < 9800e6) {
+        vco_core = 2;
+        f_coremin = 8600e6;
+        f_coremax = 9800e6;
+        c_core_min = 165;
+        c_core_max = 16;
+        a_core_min = 356;
+        a_core_max = 247;
+    }
+    else if (f_vco >= 9800e6 && f_vco <= 10800e6) {
+        vco_core = 3;
+        f_coremin = 9800e6;
+        f_coremax = 10800e6;
+        c_core_min = 158;
+        c_core_max = 19;
+        a_core_min = 324;
+        a_core_max = 224;
+    }
+    else if (f_vco > 10800e6 && f_vco <= 12000e6) {
+        vco_core = 4;
+        f_coremin = 10800e6;
+        f_coremax = 12000e6;
+        c_core_min = 140;
+        c_core_max = 0;
+        a_core_min = 383;
+        a_core_max = 244;
+    }
+    else if (f_vco > 12000e6 && f_vco <= 12900e6) {
+        vco_core = 5;
+        f_coremin = 12000e6;
+        f_coremax = 12900e6;
+        c_core_min = 183;
+        c_core_max = 36;
+        a_core_min = 205;
+        a_core_max = 146;
+    }
+    else if (f_vco > 12900e6 && f_vco <= 13900e6) {
+        vco_core = 6;
+        f_coremin = 12900e6;
+        f_coremax = 13900e6;
+        c_core_min = 155;
+        c_core_max = 6;
+        a_core_min = 242;
+        a_core_max = 163;
+    }
+    else if (f_vco > 13900e6 && f_vco <= 15000e6) {
+        vco_core = 7;
+        f_coremin = 13900e6;
+        f_coremax = 15000e6;
+        c_core_min = 175;
+        c_core_max = 19;
+        a_core_min = 323;
+        a_core_max = 244;
+    };
+    vco_cap_ctrl_strt = round(c_core_min - (c_core_min - c_core_max) * (f_vco - f_coremin) / (f_coremax - f_coremin));
+    printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
+    vco_daciset_strt = round(a_core_min + (a_core_min - a_core_max) * (f_vco - f_coremin) / (f_coremax - f_coremin));
+    printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
+
+    // Calibration assist 
+    //Set the VCO_CORE 
+    lmx2594regs[112 - VCO_SEL] = lmx2594regs[112 - VCO_SEL] & (~BITM_LMX2594_R20_VCO_SEL);
+    lmx2594regs[112 - VCO_SEL] = lmx2594regs[112 - VCO_SEL] | (vco_core << BITP_LMX2594_R20_VCO_SEL);
+    // Set the VCO_CAP_CTRL
+    lmx2594regs[112 - VCO_CAP_CTRL] = lmx2594regs[112 - VCO_CAP_CTRL] & (~BITM_LMX2594_R19_VCO_CAP_CTRL);
+    lmx2594regs[112 - VCO_CAP_CTRL] = lmx2594regs[112 - VCO_CAP_CTRL] | (vco_cap_ctrl_strt << BITP_LMX2594_R19_VCO_CAP_CTRL);
+    // Set the VCO_DACISET
+    lmx2594regs[112 - VCO_DACISET] = lmx2594regs[112 - VCO_DACISET] & (~BITM_LMX2594_R17_VCO_DACISET);
+    lmx2594regs[112 - VCO_DACISET] = lmx2594regs[112 - VCO_DACISET] | (vco_daciset_strt << BITP_LMX2594_R17_VCO_DACISET);
+
     lmx2594regs[112 - MASH_ORDER] = lmx2594regs[112 - MASH_ORDER] & (~BITM_LMX2594_R44_MASH_ORDER);
     // Set the MASH_ORDER to 3
     lmx2594regs[112 - MASH_ORDER] = lmx2594regs[112 - MASH_ORDER] | ENUM_LMX2594_R44_MASH_ORDER_3;
@@ -442,6 +630,9 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
     lmx2594regs[112 - FCAL_ADDR] = lmx2594regs[112 - FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
 
     uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112 - VCO_SEL],
+            lmx2594regs[112 - VCO_CAP_CTRL],
+            lmx2594regs[112 - VCO_DACISET],
             lmx2594regs[112-MASH_ORDER],
             lmx2594regs[112-PFD_DLY_SEL],
             lmx2594regs[112 - PLL_N_S],

Devices/lmx2594regs.h

@@ -19,11 +19,37 @@
 // R37
 #define     PFD_DLY_SEL                                 0x25
 
+//R20
+#define     VCO_SEL                                     0x14
+//R19
+#define     VCO_CAP_CTRL                                0x13
+//R17
+#define     VCO_DACISET                                 0x11
+
+//R0
 #define     FCAL_ADDR                                   0x00
 
 
 
 //BIT POSITIONS AND MASKS
+/**********************************************************************************
+ * 										R20
+ *********************************************************************************/
+// VCO_SEL [13:11]
+#define BITP_LMX2594_R20_VCO_SEL                        11
+#define BITM_LMX2594_R20_VCO_SEL                        (0x07 << BITP_LMX2594_R20_VCO_SEL)
+/**********************************************************************************
+ * 										R19
+ *********************************************************************************/
+// VCO_CAP_CTRL [7:0]
+#define BITP_LMX2594_R19_VCO_CAP_CTRL                   0
+#define BITM_LMX2594_R19_VCO_CAP_CTRL                   (0xFF << BITP_LMX2594_R19_VCO_CAP_CTRL)
+/**********************************************************************************
+ * 										R17
+ *********************************************************************************/
+// VCO_DACISET [8:0]
+#define BITP_LMX2594_R17_VCO_DACISET                    0
+#define BITM_LMX2594_R17_VCO_DACISET                    (0x1FF << BITP_LMX2594_R17_VCO_DACISET)
 /**********************************************************************************
  * 										R37
  *********************************************************************************/