Изменены названия в конфигурационном регистре. Добавлен макрос для работы с конфигурационным регистром

Devices/max2870.c

@@ -1,4 +1,5 @@
 #include "max2870.h"
+#include "tmsgheaders.h"
 
 
 const uint32_t max2870_regs[] ={
@@ -11,10 +12,11 @@ const uint32_t max2870_regs[] ={
 };
 
 void max2870_init(void *bar1) {
-
+    uint32_t cfg_reg = get_cfg_reg();
     // Set the command to enter the 32-bit mode
-    uint32_t *ptr_cmd = bar1 + RST_ADDR;
-    *ptr_cmd = CURR_WIDTH_32_BIT;
+    SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_32_BIT);
+    uint32_t *ptr_cmd = bar1 + CFG_REG_ADDR;
+    *ptr_cmd = cfg_reg;
     //Init Header
     uint32_t *ptr = bar1 + MAX2870_BASE_ADDR;
     *ptr = InitMAX2870Header;
@@ -25,7 +27,8 @@ void max2870_init(void *bar1) {
     }
     usleep(1);
     // Return to 24-bit mode
-    uint32_t *ptr_cmd_2 = bar1 + RST_ADDR;
-    *ptr_cmd_2 = CURR_WIDTH_24_BIT;
-
+    SET_REGISTER_PARAM(cfg_reg, CFG_REG_WIDTH_SPI_TMSG_BITM, CFG_REG_WIDTH_SPI_TMSG_BITP, CFG_REG_WIDTH_SPI_TMSG_24_BIT);
+    uint32_t *ptr_cmd_2 = bar1 + CFG_REG_ADDR;
+    *ptr_cmd_2 = cfg_reg;
+    set_cfg_reg(cfg_reg);
 }

Devices/tmsgheaders.c

@@ -1,10 +1,26 @@
 #include "tmsgheaders.h"
 
+uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF |
+                  CFG_REG_WIDTH_SPI_TMSG_24_BIT |
+                  CFG_REG_MOD_1 |  
+                  CFG_REG_LR_GPIO_0 |
+                  CFG_REG_HR_GPIO_0;
+
+uint32_t get_cfg_reg(){
+    return cfgReg;
+}
+
+void set_cfg_reg(uint32_t cfgRegToSet){
+    cfgReg = cfgRegToSet;
+}
+
 void rst_for_fpga(void *bar1) {
-    uint32_t *ptr = bar1 + RST_ADDR;
-    *ptr = RST_FOR_FPGA_ON;
+    SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
+    uint32_t *ptr = bar1 + CFG_REG_ADDR;
+    *ptr = cfgReg;
     usleep(1);
-    *ptr = RST_FOR_FPGA_OFF;
+    SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_OFF);
+    *ptr = cfgReg;
 }
 
 void shift_reg (void  *bar1) {

Devices/tmsgheaders.h

@@ -150,24 +150,41 @@
                   (RF_SW2 << 1) | \
                   (RF_SW1 << 0))
 
+#define SET_REGISTER_PARAM( REGISTER, BITM, BITP, PARAMETER )\
+			REGISTER &= ~BITM;\
+			REGISTER |= (PARAMETER << BITP);
 
-#define     RST_ADDR            0x08
-
-#define     RST_FOR_FPGA_ON     0x1
-#define     RST_FOR_FPGA_OFF    0x0
+#define     CFG_REG_ADDR            0x08
 
 // Command Register 
-#define    TMSG_RST_CMD_REG_BITP        0
-#define    CURR_WIDTH_CMD_REG_BITP      1
-#define    MOD_CMD_REG_BITP             2
+#define    CFG_REG_RST_FOR_FPGA_BITP            0
+#define    CFG_REG_WIDTH_SPI_TMSG_BITP          1
+#define    CFG_REG_MOD_CMD_REG_BITP             2
+#define    CFG_REG_LR_GPIO_BITP                 3
+#define    CFG_REG_HR_GPIO_BITP                 4
+
+#define    CFG_REG_RST_FOR_FPGA_BITM            (0x1 << CFG_REG_RST_FOR_FPGA_BITP)
+#define    CFG_REG_WIDTH_SPI_TMSG_BITM          (0x1 << CFG_REG_WIDTH_SPI_TMSG_BITP)
+#define    CFG_REG_MOD_CMD_REG_BITM             (0x1 << CFG_REG_MOD_CMD_REG_BITP)
+#define    CFG_REG_LR_GPIO_BITM                 (0x1 << CFG_REG_LR_GPIO_BITP)
+#define    CFG_REG_HR_GPIO_BITM                 (0x1 << CFG_REG_HR_GPIO_BITP)
+
+#define    CFG_REG_RST_FOR_FPGA_ON              0x1
+#define    CFG_REG_RST_FOR_FPGA_OFF             0x0
 
-#define    CURR_WIDTH_24_BIT            (0x0 << CURR_WIDTH_CMD_REG_BITP)
-#define    CURR_WIDTH_32_BIT            (0x1 << CURR_WIDTH_CMD_REG_BITP)
-#define    MOD_0                        (0x0 << MOD_CMD_REG_BITP)
-#define    MOD_1                        (0x1 << MOD_CMD_REG_BITP)
+#define    CFG_REG_WIDTH_SPI_TMSG_24_BIT        (0x0 << CFG_REG_WIDTH_SPI_TMSG_BITP)
+#define    CFG_REG_WIDTH_SPI_TMSG_32_BIT        (0x1 << CFG_REG_WIDTH_SPI_TMSG_BITP)
 
+#define    CFG_REG_MOD_0                        (0x0 << CFG_REG_MOD_CMD_REG_BITP)
+#define    CFG_REG_MOD_1                        (0x1 << CFG_REG_MOD_CMD_REG_BITP)
 
-#define     LMX_BASE_ADDR       0x04
+#define    CFG_REG_LR_GPIO_0                    (0x0 << CFG_REG_LR_GPIO_BITP)
+#define    CFG_REG_LR_GPIO_1                    (0x1 << CFG_REG_LR_GPIO_BITP)
+
+#define    CFG_REG_HR_GPIO_0                    (0x0 << CFG_REG_HR_GPIO_BITP)
+#define    CFG_REG_HR_GPIO_1                    (0x1 << CFG_REG_HR_GPIO_BITP)
+
+#define    LMX_BASE_ADDR            0x04
 
 void rst_for_fpga(void *bar1);
 
@@ -175,4 +192,7 @@ void shift_reg (void  *bar1);
 
 void key_switch (void  *bar1, double freq,double lmx_freq);
 
+uint32_t get_cfg_reg();
+void set_cfg_reg(uint32_t cfgRegToSet);
+
 #endif //DMADRIVER_TMSGHEADERS_H