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@@ -75,14 +75,14 @@ uint32_t lmx2594regs[LMX_COUNT] = {
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0x2F0300,
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0x2F0300,
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0x2E07FC,
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0x2E07FC,
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0x2DC8DF,
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0x2DC8DF,
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- 0x2C1FA3,
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+ 0x2C1FA0,
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0x2B0000,
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0x2B0000,
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0x2A0000,
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0x2A0000,
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0x290000,
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0x290000,
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0x280000,
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0x280000,
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0x2703E8,
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0x2703E8,
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0x260000,
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0x260000,
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- 0x250204,
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+ 0x250104,
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0x240032,
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0x240032,
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0x230004,
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0x230004,
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0x220000,
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0x220000,
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@@ -115,7 +115,7 @@ uint32_t lmx2594regs[LMX_COUNT] = {
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0x0740B2,
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0x0740B2,
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0x06C802,
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0x06C802,
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0x0500C8,
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0x0500C8,
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- 0x041443,
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+ 0x041243,
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0x030642,
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0x030642,
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0x020500,
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0x020500,
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0x010808,
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0x010808,
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@@ -479,6 +479,8 @@ int lmx_freq_set_main_band_int_mode(void *bar1, double freq, double f_pd) {
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lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
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lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
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// Next 16 bits of the register
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// Next 16 bits of the register
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lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (N_div & 0xFFFF);
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lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (N_div & 0xFFFF);
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+ // Clear the SEG1_EN bit
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+ lmx2594regs[112-CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
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// Set the OUTA_MUX to channel divider R45[12:11]; 0 - Channel divider, 1 - VCO;
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// Set the OUTA_MUX to channel divider R45[12:11]; 0 - Channel divider, 1 - VCO;
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lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] & (~BITM_LMX2594_R45_OUTA_MUX);
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lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] & (~BITM_LMX2594_R45_OUTA_MUX);
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lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] | ENUM_LMX2594_R45_OUTA_MUX_VCO;
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lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] | ENUM_LMX2594_R45_OUTA_MUX_VCO;
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@@ -487,13 +489,16 @@ int lmx_freq_set_main_band_int_mode(void *bar1, double freq, double f_pd) {
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lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
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lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
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uint32_t lmx_change_freq_regs[] = {
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uint32_t lmx_change_freq_regs[] = {
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+ lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_TRISTATE,
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lmx2594regs[112 - VCO_SEL],
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lmx2594regs[112 - VCO_SEL],
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lmx2594regs[112 - CAP_CTRL_START],
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lmx2594regs[112 - CAP_CTRL_START],
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lmx2594regs[112 - VCO_DACISET],
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lmx2594regs[112 - VCO_DACISET],
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lmx2594regs[112-PFD_DLY_SEL],
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lmx2594regs[112-PFD_DLY_SEL],
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+ lmx2594regs[112-CHDIV_DIV2],
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lmx2594regs[112-PLL_N_S],
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lmx2594regs[112-PLL_N_S],
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lmx2594regs[112-PLL_N_M],
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lmx2594regs[112-PLL_N_M],
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lmx2594regs[112 - OUTA_MUX],
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lmx2594regs[112 - OUTA_MUX],
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+ lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_15ma,
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lmx2594regs[112-FCAL_ADDR]
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lmx2594regs[112-FCAL_ADDR]
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};
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};
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// Create a header for the LMX2594 with the appropriate number of words
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// Create a header for the LMX2594 with the appropriate number of words
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