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Devices/ad9912.c

@@ -0,0 +1,60 @@
+#include "ad9912.h"
+
+const uint32_t ad9912regs[AD9912_COUNT] = {
+        0x000018,
+        0x000100,
+        0x000202,
+        0x000309,
+        0x000400,
+        0x000500,
+        0x001010,
+        0x001200,
+        0x001300,
+        0x002012,
+        0x002204,
+        0x010400,
+        0x010500,
+        0x010600,
+        0x01A633,
+        0x01A733,
+        0x01A833,
+        0x01A933,
+        0x01AA33,
+        0x01AB33,
+        0x01AC00,
+        0x01AD00,
+        0x020005,
+        0x020100,
+        0x040BFF,
+        0x040C01,
+        0x040E10,
+        0x050000,
+        0x050100,
+        0x050200,
+        0x050300,
+        0x050400,
+        0x050500,
+        0x050600,
+        0x050700,
+        0x050800,
+        0x050900
+};
+
+/*-------------------------AD9912 INIT FUNCTION-------------------------*/
+void ad9912_init(void *bar1) {
+    uint32_t *ptr_rst = bar1 + AD9912_BASE_ADDR;
+    *ptr_rst = GPIO_INIT_HEADER;
+    //Rst on
+    *ptr_rst = AD9912_RST_ON;
+    // Rst off
+    *ptr_rst = GPIO_REG;
+    //Init Header
+    uint32_t *ptr = bar1 + AD9912_BASE_ADDR;
+    *ptr = InitDDSHeader;
+    //Init Data
+    for (int k = 0; k < AD9912_COUNT; k++) {
+        uint32_t *ptr = bar1 + AD9912_BASE_ADDR;
+        *ptr = ad9912regs[k];
+    }
+}
+/*----------------------------------------------------------------------*/

Devices/ad9912.h

@@ -0,0 +1,36 @@
+#ifndef DMADRIVER_AD9912_H
+#define DMADRIVER_AD9912_H
+
+#include "tmsgheaders.h"
+
+#define     AD9912_COUNT        37
+#define     AD9912_BASE_ADDR    0x04
+
+#define AD9912_RST_ON ((DDS_SAW1_FPGA << 21) | \
+                  (GPIO_ADRF_V2 << 20) | \
+                  (GPIO_ADRF_V1 << 19) | \
+                  (REF_OFFSET_CTRL_FPGA << 18) | \
+                  (DDS_SAW2_FPGA << 17) | \
+                  (DDS_X2_FPGA << 16) | \
+                  (PLL_LOOP_CTRL << 15) | \
+                  (PLL_SYNC << 14) | \
+                  (PLL_SYNC_CTRL << 13) | \
+                  (PLL_VTUNE_CTRL << 12) | \
+                  (AM_ALC_1_FIX << 11) | \
+                  (SW_CAP1 << 10) | \
+                  (SW_CAP2 << 9) | \
+                  (SW_CAP3 << 8) | \
+                  (AM_ALC_SW << 7) | \
+                  (SW_CAP4 << 6) | \
+                  (DDS_SYNC_FPGA << 5) | \
+                  (0x1 << 4) | \
+                  (DDS_SYNC_CTRL_FPGA << 3) | \
+                  (CTRL_AM_SW3 << 2) | \
+                  (RF_SW2 << 1) | \
+                  (RF_SW1 << 0))
+
+/*-------------------------AD9912 INIT DATA-------------------------*/
+
+/*----------------------------------------------------------------------*/
+void ad9912_init(void *bar1);
+#endif //DMADRIVER_AD9912_H

Devices/lmk04821.c

@@ -0,0 +1,299 @@
+#include "lmk04821.h"
+
+const uint32_t lmk04821regs_b[LMK_COUNT] = {
+        0x000090,
+        0x000010,
+        0x000200,
+        0x000306,
+        0x0004D0,
+        0x00055B,
+        0x000600,
+        0x000C51,
+        0x000D04,
+        0x010001,
+        0x010197,
+        0x010255,
+        0x010302,
+        0x010402,
+        0x010500,
+        0x0106F1,
+        0x010790,
+        0x010801,
+        0x010955,
+        0x010A55,
+        0x010B02,
+        0x010C02,
+        0x010D00,
+        0x010EB1,
+        0x010F15,
+        0x011001,
+        0x011155,
+        0x011255,
+        0x011302,
+        0x011402,
+        0x011500,
+        0x0116F1,
+        0x011705,
+        0x011801,
+        0x011955,
+        0x011A55,
+        0x011B02,
+        0x011C02,
+        0x011D00,
+        0x011EF1,
+        0x011F05,
+        0x012001,
+        0x012155,
+        0x012255,
+        0x012302,
+        0x012402,
+        0x012500,
+        0x0126F1,
+        0x012715,
+        0x012801,
+        0x012955,
+        0x012A55,
+        0x012B02,
+        0x012C02,
+        0x012D00,
+        0x012EF1,
+        0x012F95,
+        0x013001,
+        0x013155,
+        0x013255,
+        0x013302,
+        0x013402,
+        0x013500,
+        0x013671,
+        0x013710,
+        0x013840,
+        0x013900,
+        0x013A00,
+        0x013B01,
+        0x013C00,
+        0x013D01,
+        0x013E00,
+        0x013F06,
+        0x0140E3,
+        0x014100,
+        0x014200,
+        0x014310,
+        0x0144FF,
+        0x01457F,
+        0x014611,
+        0x014713,
+        0x014802,
+        0x014942,
+        0x014A02,
+        0x014B16,
+        0x014C00,
+        0x014D00,
+        0x014EC0,
+        0x014F7F,
+        0x015003,
+        0x015102,
+        0x015200,
+        0x015300,
+        0x015464,
+        0x015500,
+        0x015678,
+        0x015700,
+        0x01580A,
+        0x015900,
+        0x015A78,
+        0x015BD4,
+        0x015C20,
+        0x015D00,
+        0x015E00,
+        0x015F0B,
+        0x016000,
+        0x016101,
+        0x016224,
+        0x016300,
+        0x016400,
+        0x016501,
+        0x0171AA,
+        0x017202,
+        0x017300,
+        0x017400,
+        0x017C15,
+        0x017D33,
+        0x016600,
+        0x016700,
+        0x01680A,
+        0x016959,
+        0x016A20,
+        0x016B00,
+        0x016C00,
+        0x016D20,
+        0x016E13,
+        0x1FFD00,
+        0x1FFE00,
+        0x1FFF53
+};
+
+const uint32_t lmk04821regs_a[LMK_COUNT] = {
+        0x000090,
+        0x000010,
+        0x000200,
+        0x000306,
+        0x0004D0,
+        0x00055B,
+        0x000600,
+        0x000C51,
+        0x000D04,
+        0x010001,
+        0x010197,
+        0x010255,
+        0x010302,
+        0x010402,
+        0x010500,
+        0x0106F1,
+        0x010707,
+        0x010801,
+        0x010955,
+        0x010A55,
+        0x010B02,
+        0x010C02,
+        0x010D00,
+        0x010EB1,
+        0x010F07,
+        0x011001,
+        0x011155,
+        0x011255,
+        0x011302,
+        0x011402,
+        0x011500,
+        0x0116F1,
+        0x011707,
+        0x011801,
+        0x011955,
+        0x011A55,
+        0x011B02,
+        0x011C02,
+        0x011D00,
+        0x011EF1,
+        0x011F07,
+        0x012001,
+        0x012155,
+        0x012255,
+        0x012302,
+        0x012402,
+        0x012500,
+        0x0126F1,
+        0x012707,
+        0x012801,
+        0x012955,
+        0x012A55,
+        0x012B02,
+        0x012C02,
+        0x012D00,
+        0x012EF1,
+        0x012F0F,
+        0x013001,
+        0x013155,
+        0x013255,
+        0x013302,
+        0x013402,
+        0x013500,
+        0x013679,
+        0x013783,
+        0x013840,
+        0x013901,
+        0x013A00,
+        0x013B01,
+        0x013C00,
+        0x013D01,
+        0x013E00,
+        0x013F06,
+        0x0140F2,
+        0x014100,
+        0x014200,
+        0x014311,
+        0x0144FF,
+        0x01457F,
+        0x014611,
+        0x014713,
+        0x014802,
+        0x014942,
+        0x014A02,
+        0x014B16,
+        0x014C00,
+        0x014D00,
+        0x014EC0,
+        0x014F7F,
+        0x015003,
+        0x015102,
+        0x015200,
+        0x015300,
+        0x015464,
+        0x015500,
+        0x015678,
+        0x015700,
+        0x01580A,
+        0x015900,
+        0x015A78,
+        0x015BD4,
+        0x015C20,
+        0x015D00,
+        0x015E00,
+        0x015F0B,
+        0x016000,
+        0x016101,
+        0x016224,
+        0x016300,
+        0x016400,
+        0x016501,
+        0x0171AA,
+        0x017202,
+        0x017360,
+        0x017400,
+        0x017C15,
+        0x017D33,
+        0x016600,
+        0x016700,
+        0x016801,
+        0x016959,
+        0x016A20,
+        0x016B00,
+        0x016C00,
+        0x016D20,
+        0x016E13,
+        0x1FFD00,
+        0x1FFE00,
+        0x1FFF53
+};
+const uint32_t lmk04821_rst_a[] = {
+        0x000090,
+        0x000010
+};
+const uint32_t lmk04821_rst_b[] = {
+        0x000090,
+        0x000010
+};
+
+void lmk04821_a_init(void *bar1) {
+    //Rst for Lmk_a
+    for (int i = 0; i < 2; i++) {
+        uint32_t *ptr = bar1 + LMK_BASE_ADDR;
+        *ptr = lmk04821_rst_a[i];
+    }
+    //Init for Lmk_a
+    for (int j = 0; j < LMK_COUNT; j++) {
+        uint32_t *ptr = bar1 + LMK_BASE_ADDR;
+        *ptr = lmk04821regs_a[j];
+    }
+}
+
+void lmk04821_b_init(void *bar1) {
+    //Rst for Lmk_a
+    for (int i = 0; i < 2; i++) {
+        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
+        *ptr = lmk04821_rst_b[i];
+    }
+    //Init for Lmk_a
+    for (int j = 0; j < LMK_COUNT; j++) {
+        uint32_t *ptr = bar1 + LMK_B_BASE_ADDR;
+        *ptr = lmk04821regs_b[j];
+    }
+}

Devices/lmk04821.h

@@ -0,0 +1,19 @@
+#ifndef DMADRIVER_LMK04821_H
+#define DMADRIVER_LMK04821_H
+
+//#include "tmsgheaders.h"
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+
+#define     LMK_BASE_ADDR       0x10
+#define	    LMK_B_BASE_ADDR	    0x14
+#define     LMK_COUNT           129
+
+
+
+void lmk04821_a_init(void *bar1);
+
+void lmk04821_b_init(void *bar1);
+
+#endif //DMADRIVER_LMK04821_H

Devices/lmx2594.c

@@ -0,0 +1,450 @@
+#include "lmx2594.h"
+
+
+const uint32_t lmx2594_rst[2] = {
+        0x00251e,
+        0x00251c
+};
+uint32_t lmx2594regs[LMX_COUNT] = {
+        0x700000,
+        0x6F0000,
+        0x6E0000,
+        0x6D0000,
+        0x6C0000,
+        0x6B0000,
+        0x6A0000,
+        0x690021,
+        0x680000,
+        0x670000,
+        0x660000,
+        0x650011,
+        0x640000,
+        0x630000,
+        0x620000,
+        0x610888,
+        0x600000,
+        0x5F0000,
+        0x5E0000,
+        0x5D0000,
+        0x5C0000,
+        0x5B0000,
+        0x5A0000,
+        0x590000,
+        0x580000,
+        0x570000,
+        0x560000,
+        0x550000,
+        0x540000,
+        0x530000,
+        0x520000,
+        0x510000,
+        0x500000,
+        0x4F0000,
+        0x4E0105,
+        0x4D0000,
+        0x4C000C,
+        0x4B0C40,
+        0x4A0000,
+        0x49003F,
+        0x480001,
+        0x470081,
+        0x46C350,
+        0x450000,
+        0x4403E8,
+        0x430000,
+        0x4201F4,
+        0x410000,
+        0x401388,
+        0x3F0000,
+        0x3E0322,
+        0x3D00A8,
+        0x3C03E8,
+        0x3B0001,
+        0x3A9001,
+        0x390020,
+        0x380000,
+        0x370000,
+        0x360000,
+        0x350000,
+        0x340820,
+        0x330080,
+        0x320000,
+        0x314180,
+        0x300300,
+        0x2F0300,
+        0x2E07FD,
+        0x2DC8DF,
+        0x2C1F20,
+        0x2B0000,
+        0x2A0000,
+        0x290000,
+        0x280000,
+        0x2703E8,
+        0x260000,
+        0x250104,
+        0x240032,
+        0x230004,
+        0x220000,
+        0x211E21,
+        0x200393,
+        0x1F43EC,
+        0x1E318C,
+        0x1D318C,
+        0x1C0488,
+        0x1B0002,
+        0x1A0DB0,
+        0x190C2B,
+        0x18071A,
+        0x17007C,
+        0x160001,
+        0x150401,
+        0x14D848,
+        0x1327B7,
+        0x120064,
+        0x110130,
+        0x100080,
+        0x0F064F,
+        0x0E1E40,
+        0x0D4000,
+        0x0C5001,
+        0x0B0018,
+        0x0A10D8,
+        0x090604,
+        0x082000,
+        0x0740B2,
+        0x06C802,
+        0x0500C8,
+        0x041443,
+        0x030642,
+        0x020500,
+        0x01080B,
+        0x00251C
+};
+
+
+
+void lmx2594_init(void *bar1) {
+    // Header for LMX Reset
+    uint32_t *ptr_rst = bar1 + LMX_BASE_ADDR;
+    *ptr_rst = LMX2594_RST_HEADER;
+    // Reset Data
+    for (int m = 0; m < 2; m++) {
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = lmx2594_rst[m];
+    }
+    // Header for init data
+    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    *ptr = InitLMX2594Header;
+    // Init data
+    for (int i = 0; i < LMX_COUNT; i++) {
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = lmx2594regs[i];
+    }
+}
+
+/*-------------------------LMX2594 Frequency Set-------------------------*/
+int lmx_freq_set_main_band(void *bar1, uint64_t freq, double f_pd, double N_div) {
+    N_div = freq / f_pd;
+
+    // divide whole part and fractional part
+    uint32_t N = (uint32_t) N_div;
+    // In frac part there is separate denominator and numerator
+    // If frac part is 0 then the denominator is 1000 and numerator is 0
+    uint32_t frac_n = (uint32_t) ((N_div - N) * 524287);
+    uint32_t frac_d = 524287;
+    // If frac part is 0 then the denominator is 1000 and numerator is 0
+    if (frac_n == 0) {
+        frac_n = 0;
+        frac_d = 524287;
+    }
+    // Recommended sequnce for changin freq
+    // 1. Change the N-div value
+    // 2. Change the PLL numerator and denominator
+    // 3. Program FCAL_EN bit
+    // Clear the required parts of the register
+    lmx2594regs[112-MASH_ORDER] = lmx2594regs[112-MASH_ORDER] & (~BITM_LMX2594_R44_MASH_ORDER);
+    // Set the MASH_ORDER to 3
+    lmx2594regs[112-MASH_ORDER] = lmx2594regs[112-MASH_ORDER] | ENUM_LMX2594_R44_MASH_ORDER_3;
+    // Set PF_DLY_SEL to 3
+    lmx2594regs[112-PFD_DLY_SEL] = lmx2594regs[112-PFD_DLY_SEL] & (~BITM_LMX2594_R37_PFD_DLY_SEL);
+    lmx2594regs[112-PFD_DLY_SEL] = lmx2594regs[112-PFD_DLY_SEL] | (0x3 << BITP_LMX2594_R37_PFD_DLY_SEL);
+    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] &(~0xFFFF);
+    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] | (N >> 16);
+    //CLear the lower 16 bits of the register
+    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
+    // Next 16 bits of the register
+    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (N & 0xFFFF);
+    // Clear the upper 16 bits of the register lmx2594regs[PLL_NUM_S]
+    lmx2594regs[112-PLL_NUM_S] = lmx2594regs[112-PLL_NUM_S] & (~0xFFFF);
+    lmx2594regs[112-PLL_NUM_S] = lmx2594regs[112-PLL_NUM_S] | (frac_n >> 16);
+    // Clear the lower 16 bits of the register lmx2594regs[PLL_NUM_M]
+    lmx2594regs[112-PLL_NUM_M] = lmx2594regs[112-PLL_NUM_M] & (~0xFFFF);
+    // Next 16 bits of the numerator
+    lmx2594regs[112-PLL_NUM_M] = lmx2594regs[112-PLL_NUM_M] | (frac_n & 0xFFFF);
+    // Clear the upper 16 bits of the register lmx2594regs[PLL_DEN_S]
+    lmx2594regs[112-PLL_DEN_S] = lmx2594regs[112-PLL_DEN_S] & (~0xFFFF);
+    // most significant 16 bits of the denominator
+    lmx2594regs[112-PLL_DEN_S] = lmx2594regs[112-PLL_DEN_S] | (frac_d >> 16);
+    // Clear the lower 16 bits of the register lmx2594regs[PLL_DEN_M]
+    lmx2594regs[112-PLL_DEN_M] = lmx2594regs[112-PLL_DEN_M] & (~0xFFFF);
+    // Next 16 bits of the denominator
+    lmx2594regs[112-PLL_DEN_M] = lmx2594regs[112-PLL_DEN_M] | (frac_d & 0xFFFF);
+    // Program the FCAL_EN bit
+    lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
+    // Show the all the upper 16 bits of the register lmx2594regs[PLL_N_S]
+    // Determine which regs are changed and send only those
+    uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112-MASH_ORDER],
+            lmx2594regs[112-PFD_DLY_SEL],
+            lmx2594regs[112-PLL_N_S],
+            lmx2594regs[112-PLL_N_M],
+            lmx2594regs[112-PLL_DEN_S],
+            lmx2594regs[112-PLL_DEN_M],
+            lmx2594regs[112-PLL_NUM_S],
+            lmx2594regs[112-PLL_NUM_M],
+            lmx2594regs[112-FCAL_ADDR]
+    };
+    // Create a header for the LMX2594 with the appropriate number of words
+    uint32_t LMX_HEADER = ((0 << 23) | (DeviceIdLmx2594 << 18) | ((sizeof(lmx_change_freq_regs)/4) << 1) | 1);
+    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    *ptr = LMX_HEADER;
+    for (int i = 0; i < sizeof(lmx_change_freq_regs)/4; i++) {
+        uint32_t *data_ptr = bar1 + LMX_BASE_ADDR;
+        *data_ptr = lmx_change_freq_regs[i];
+    }
+    usleep(1);
+    return 0;
+}
+
+int lmx_freq_set_out_of_band(void *bar1, uint64_t freq, double f_pd, double N_div) {
+    double f_vco = 2 * freq;
+    int chan_div = 2;
+    uint8_t ch_div_reg = 0; // 2
+    double vco_div = 7.5e9 / freq;
+
+    // minimum N_div value is 28 and Vco frequency can't be less than 7.5 GHz
+    if (f_vco < 7.5e9) {
+        if (vco_div > 2 && vco_div <= 4)
+            chan_div = 4;  // 4
+        f_vco = freq * chan_div;
+        if (vco_div > 4 && vco_div <= 6) {
+            chan_div = 6;  // 6
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 6 && vco_div <= 8) {
+            chan_div = 8;  // 8
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 8 && vco_div <= 12) {
+            chan_div = 12;  // 12
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 12 && vco_div <= 16) {
+            chan_div = 16;  // 16
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 16 && vco_div <= 24) {
+            chan_div = 24;  // 24
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 24 && vco_div <= 32) {
+            chan_div = 32;  // 32
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 32 && vco_div <= 48) {
+            chan_div = 48;  // 48
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 48 && vco_div <= 64) {
+            chan_div = 64;  // 64
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 64 && vco_div <= 72) {
+            chan_div = 72;  // 72
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 72 && vco_div <= 96) {
+            chan_div = 96;  // 96
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 96 && vco_div <= 128) {
+            chan_div = 128;  // 128
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 128 && vco_div <= 192) {
+            chan_div = 192;  // 192
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 192 && vco_div <= 256) {
+            chan_div = 256;  // 256
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 256 && vco_div <= 384) {
+            chan_div = 384;  // 384
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 384 && vco_div <= 512) {
+            chan_div = 512;  // 512
+            f_vco = freq * chan_div;
+        }
+        if (vco_div > 512 && vco_div <= 768) {
+            chan_div = 768;  // 768
+            f_vco = freq * chan_div;
+        }
+
+        switch (chan_div) {
+            case 2:
+                ch_div_reg = 0;
+                break;
+            case 4:
+                ch_div_reg = 1;
+                break;
+            case 6:
+                ch_div_reg = 2;
+                break;
+            case 8:
+                ch_div_reg = 3;
+                break;
+            case 12:
+                ch_div_reg = 4;
+                break;
+            case 16:
+                ch_div_reg = 5;
+                break;
+            case 24:
+                ch_div_reg = 6;
+                break;
+            case 32:
+                ch_div_reg = 7;
+                break;
+            case 48:
+                ch_div_reg = 8;
+                break;
+            case 64:
+                ch_div_reg = 9;
+                break;
+            case 72:
+                ch_div_reg = 10;
+                break;
+            case 96:
+                ch_div_reg = 11;
+                break;
+            case 128:
+                ch_div_reg = 12;
+                break;
+            case 192:
+                ch_div_reg = 13;
+                break;
+            case 256:
+                ch_div_reg = 14;
+                break;
+            case 384:
+                ch_div_reg = 15;
+                break;
+            case 512:
+                ch_div_reg = 16;
+                break;
+            case 768:
+                ch_div_reg = 17;
+                break;
+        }
+    } else {
+        ch_div_reg = 0;
+        f_vco = freq * 2;
+    }
+    N_div = f_vco / f_pd;
+
+    // divide whole part and fractional part
+    uint32_t N = (uint32_t) N_div;
+    uint32_t frac_n = (uint32_t) ((N_div - N) * 524287);
+    uint32_t frac_d = 524287;
+    // If frac part is 0 then the denominator is 1000 and numerator is 0
+    if (frac_n == 0) {
+        frac_n = 0;
+        frac_d = 524287;
+    }
+    lmx2594regs[112 - MASH_ORDER] = lmx2594regs[112 - MASH_ORDER] & (~BITM_LMX2594_R44_MASH_ORDER);
+    // Set the MASH_ORDER to 3
+    lmx2594regs[112 - MASH_ORDER] = lmx2594regs[112 - MASH_ORDER] | ENUM_LMX2594_R44_MASH_ORDER_3;
+    // Set PF_DLY_SEL to 3
+    lmx2594regs[112 - PFD_DLY_SEL] = lmx2594regs[112 - PFD_DLY_SEL] & (~BITM_LMX2594_R37_PFD_DLY_SEL);
+    lmx2594regs[112 - PFD_DLY_SEL] = lmx2594regs[112 - PFD_DLY_SEL] | (0x3 << BITP_LMX2594_R37_PFD_DLY_SEL);
+    lmx2594regs[112 - PLL_N_S] = lmx2594regs[112 - PLL_N_S] & (~0xFFFF);
+    lmx2594regs[112 - PLL_N_S] = lmx2594regs[112 - PLL_N_S] | (N >> 16);
+    //CLear the lower 16 bits of the register
+    lmx2594regs[112 - PLL_N_M] = lmx2594regs[112 - PLL_N_M] & (~0xFFFF);
+    // Next 16 bits of the register
+    lmx2594regs[112 - PLL_N_M] = lmx2594regs[112 - PLL_N_M] | (N & 0xFFFF);
+    // Clear the upper 16 bits of the register lmx2594regs[PLL_NUM_S]
+    lmx2594regs[112 - PLL_NUM_S] = lmx2594regs[112 - PLL_NUM_S] & (~0xFFFF);
+    lmx2594regs[112 - PLL_NUM_S] = lmx2594regs[112 - PLL_NUM_S] | (frac_n >> 16);
+    // Clear the lower 16 bits of the register lmx2594regs[PLL_NUM_M]
+    lmx2594regs[112 - PLL_NUM_M] = lmx2594regs[112 - PLL_NUM_M] & (~0xFFFF);
+    // Next 16 bits of the numerator
+    lmx2594regs[112 - PLL_NUM_M] = lmx2594regs[112 - PLL_NUM_M] | (frac_n & 0xFFFF);
+    // Clear the upper 16 bits of the register lmx2594regs[PLL_DEN_S]
+    lmx2594regs[112 - PLL_DEN_S] = lmx2594regs[112 - PLL_DEN_S] & (~0xFFFF);
+    // most significant 16 bits of the denominator
+    lmx2594regs[112 - PLL_DEN_S] = lmx2594regs[112 - PLL_DEN_S] | (frac_d >> 16);
+    // Clear the lower 16 bits of the register lmx2594regs[PLL_DEN_M]
+    lmx2594regs[112 - PLL_DEN_M] = lmx2594regs[112 - PLL_DEN_M] & (~0xFFFF);
+    // Next 16 bits of the denominator
+    lmx2594regs[112 - PLL_DEN_M] = lmx2594regs[112 - PLL_DEN_M] | (frac_d & 0xFFFF);
+    // Program the CHDIV value
+    lmx2594regs[112 - CHDIV] = lmx2594regs[112 - CHDIV] & (~BITM_LMX2594_R75_CHDIV);
+    // Set the CHDIV value with the starting position BITP_LMX2594_R75_CHDIV
+    lmx2594regs[112 - CHDIV] = lmx2594regs[112 - CHDIV] | (ch_div_reg << BITP_LMX2594_R75_CHDIV);
+    // If the ch_div > 2 then set the SEG1_EN bit
+    if (chan_div > 2) {
+        lmx2594regs[112 - CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
+        lmx2594regs[112 - CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] | (ENUM_LMX2594_R31_CHDIV_DIV2_EN);
+    }
+    // Set the OUTA_MUX to channel divider R45[12:11]; 0 - Channel divider, 1 - VCO;
+    lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] & (~BITM_LMX2594_R45_OUTA_MUX);
+    lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] | ENUM_LMX2594_R45_OUTA_MUX_CH_DIV;
+
+    // Program the FCAL_EN bit
+    lmx2594regs[112 - FCAL_ADDR] = lmx2594regs[112 - FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
+
+    uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112 - PLL_N_S],
+            lmx2594regs[112 - PLL_N_M],
+            lmx2594regs[112 - PLL_DEN_S],
+            lmx2594regs[112 - PLL_DEN_M],
+            lmx2594regs[112 - PLL_NUM_S],
+            lmx2594regs[112 - PLL_NUM_M],
+            lmx2594regs[112 - FCAL_ADDR],
+            lmx2594regs[112 - CHDIV_DIV2],
+            lmx2594regs[112 - CHDIV],
+            lmx2594regs[112 - OUTA_MUX]
+    };
+    // Create a header for the LMX2594 with the appropriate number of words
+    uint32_t LMX_HEADER = ((0 << 23) | (DeviceIdLmx2594 << 18) | ((sizeof(lmx_change_freq_regs) / 4) << 1) | 1);
+    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    *ptr = LMX_HEADER;
+    // Send the data
+    for (int i = 0; i < sizeof(lmx_change_freq_regs) / 4; i++) {
+        uint32_t *data_ptr = bar1 + LMX_BASE_ADDR;
+        *data_ptr = lmx_change_freq_regs[i];
+    }
+    usleep(1);
+    return 0;
+}
+
+int lmx_freq_set(void *bar1, uint64_t freq) {
+
+    double f_pd = 200e6;
+    double N_div = 0;
+    if (freq < 10e6 || freq > 15e9) {
+        printf("Frequency range is 10 MHz to 15 GHz\n");
+        return -1;
+    }
+    // if the frequency is in the main band - 7.5 GHz to 15 GHz
+    if (freq >= 7.5e9 && freq <= 15e9) {
+        lmx_freq_set_main_band(bar1, freq, f_pd, N_div);
+    }
+    else if (freq < 7.5e9) {
+        lmx_freq_set_out_of_band(bar1, freq, f_pd, N_div);
+    }
+    return 0;
+}

Devices/lmx2594.h

@@ -0,0 +1,17 @@
+#ifndef DMADRIVER_LMX2594_H
+#define DMADRIVER_LMX2594_H
+#include "tmsgheaders.h"
+#include "lmx2594regs.h"
+
+#define     LMX_COUNT           113
+#define     LMX_BASE_ADDR       0x04
+
+void lmx2594_init( void *bar1);
+
+
+int lmx_freq_set(void *bar1, uint64_t freq);
+
+
+
+
+#endif //DMADRIVER_LMX2594_H

Devices/lmx2594regs.h

@@ -0,0 +1,80 @@
+#ifndef DMADRIVER_LMK2594REGS_H
+#define DMADRIVER_LMK2594REGS_H
+
+#define     PLL_N_S                                     0x22
+#define     PLL_N_M                                     0x24
+#define     PLL_DEN_S                                   0x26
+#define     PLL_DEN_M                                   0x27
+#define     PLL_NUM_S                                   0x2A
+#define     PLL_NUM_M                                   0x2B
+#define     OUTA_MUX                                    0x2D
+
+// R75
+#define     CHDIV                                       0x4B
+// R31
+#define     CHDIV_DIV2                                  0x1F
+
+// R44
+#define     MASH_ORDER                                  0x2C
+// R37
+#define     PFD_DLY_SEL                                 0x25
+
+#define     FCAL_ADDR                                   0x00
+
+
+
+//BIT POSITIONS AND MASKS
+/**********************************************************************************
+ * 										R37
+ *********************************************************************************/
+#define BITP_LMX2594_R37_PFD_DLY_SEL                    8
+// Length 6 bits
+#define BITM_LMX2594_R37_PFD_DLY_SEL                    (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL)
+/**********************************************************************************
+ * 										R44
+ *********************************************************************************/
+#define BITP_LMX2594_R44_MASH_ORDER                      0
+#define BITM_LMX2594_R44_MASH_ORDER                      (0x07 << BITP_LMX2594_R44_MASH_ORDER)
+#define ENUM_LMX2594_R44_MASH_ORDER_INTEGER              (0x00 << BITP_LMX2594_R44_MASH_ORDER)
+#define ENUM_LMX2594_R44_MASH_ORDER_1                    (0x01 << BITP_LMX2594_R44_MASH_ORDER)
+#define ENUM_LMX2594_R44_MASH_ORDER_2                    (0x02 << BITP_LMX2594_R44_MASH_ORDER)
+#define ENUM_LMX2594_R44_MASH_ORDER_3                    (0x03 << BITP_LMX2594_R44_MASH_ORDER)
+#define ENUM_LMX2594_R44_MASH_ORDER_4                    (0x04 << BITP_LMX2594_R44_MASH_ORDER)
+/**********************************************************************************
+ * 										R45
+ *********************************************************************************/
+#define BITP_LMX2594_R45_OUTA_MUX                       11
+#define BITM_LMX2594_R45_OUTA_MUX                       (0x03 << BITP_LMX2594_R45_OUTA_MUX)
+#define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV                (0x00 << BITP_LMX2594_R45_OUTA_MUX)
+#define ENUM_LMX2594_R45_OUTA_MUX_VCO                   (0x01 << BITP_LMX2594_R45_OUTA_MUX)
+
+#define ENUM_LMX2594_R45_DEFAULT_VAL                    0x01
+
+/*********************************************************************************/
+
+
+/**********************************************************************************
+ * 										R75
+ *********************************************************************************/
+#define BITP_LMX2594_R75_CHDIV                          6
+#define BITM_LMX2594_R75_CHDIV                          (0x3F << BITP_LMX2594_R75_CHDIV)
+/*********************************************************************************/
+
+/**********************************************************************************
+ * 										R31
+ *********************************************************************************/
+#define BITP_LMX2594_R31_CHDIV_DIV2                     14
+#define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
+#define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
+#define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
+
+/**********************************************************************************
+ * 										R0
+ *********************************************************************************/
+
+#define BITP_LMX2594_R0_FCAL                            4
+#define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
+/*********************************************************************************/
+
+
+#endif //DMADRIVER_LMK2594REGS_H

Devices/tmsgheaders.c

@@ -0,0 +1,15 @@
+#include "tmsgheaders.h"
+
+void rst_for_fpga(void *bar1) {
+    uint32_t *ptr = bar1 + RST_ADDR;
+    *ptr = RST_FOR_FPGA_ON;
+    usleep(1);
+    *ptr = RST_FOR_FPGA_OFF;
+}
+
+void shift_reg (void  *bar1) {
+    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    *ptr = InitShRegHeader;
+    uint32_t *data_ptr = bar1 + LMX_BASE_ADDR ;
+    *data_ptr = SHIFT_REG;
+}

Devices/tmsgheaders.h

@@ -0,0 +1,128 @@
+#ifndef DMADRIVER_TMSGHEADERS_H
+#define DMADRIVER_TMSGHEADERS_H
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+// Device IDs
+#define DeviceIdLmx2594    0x0
+#define DeviceIdDDS        0x1
+#define DeviceIdPot        0x2
+#define DeviceIdDac        0x3
+#define DeviceIdAtt        0x4
+#define DeviceIdShReg      0x5
+#define DeviceIdMax2870    0x6
+#define DeviceIdGpio1      0x7
+#define DeviceIdTemp       0x8
+#define DeviceIdGpio2      0x9
+
+// Init Word Numbers 1 MOSI
+#define Gpio1InitWordNum   2
+#define Gpio2InitWordNum   1
+#define PotWordInitNum     1
+#define DacWordInitNum     1
+#define AttWordInitNum     1
+#define ShRegWordInitNum   1
+#define Lmx2594InitWordNum 113
+#define DDSInitWordNum     37
+#define MaxInitWordNum     6
+#define TempSensWordNum    1
+
+// Headers 1-MOSI
+#define LMX2594_RST_HEADER  ((0 << 23) | (DeviceIdLmx2594 << 18) | (2 << 1) | 1)
+#define GPIO_INIT_HEADER    ((0 << 23) | (DeviceIdGpio1 << 18) | (Gpio1InitWordNum << 1) | 1)
+#define InitGpio2Header    ((0 << 23) | (DeviceIdGpio2 << 18) | (Gpio2InitWordNum << 1) | 1)
+#define TempSensHeader     ((0 << 23) | (DeviceIdTemp << 18) | (TempSensWordNum << 1) | 1)
+#define InitLMX2594Header  ((0 << 23) | (DeviceIdLmx2594 << 18) | (Lmx2594InitWordNum << 1) | 1)
+#define InitDDSHeader      ((0 << 23) | (DeviceIdDDS << 18) | (DDSInitWordNum << 1) | 1)
+#define InitMAX2870Header  ((0 << 23) | (DeviceIdMax2870 << 18) | (MaxInitWordNum << 1) | 1)
+#define InitPotHeader      ((0 << 23) | (DeviceIdPot << 18) | (PotWordInitNum << 1) | 1)
+#define InitDacHeader      ((0 << 23) | (DeviceIdDac << 18) | (DacWordInitNum << 1) | 1)
+#define InitAttHeader      ((0 << 23) | (DeviceIdAtt << 18) | (AttWordInitNum << 1) | 1)
+#define InitShRegHeader    ((0 << 23) | (DeviceIdShReg << 18) | (ShRegWordInitNum << 1) | 1)
+
+
+// Word Numbers 4-MOSI
+#define LMXWordNum              14
+#define DDSWordNum              4
+#define POTWordNum              2
+#define DACWordNum              1
+#define ATTWordNum              1
+#define ShRegWordNum            1
+#define MaxWordNum              2
+#define GPIOWordNum             1
+
+// Define bit values for GPIO Reg
+#define RF_SW1                  0x0
+#define RF_SW2                  0x0
+#define CTRL_AM_SW3             0x0
+#define DDS_SYNC_CTRL_FPGA      0x0
+#define DDS_RESET_FPGA          0x0
+#define DDS_SYNC_FPGA           0x0
+#define SW_CAP4                 0x0
+#define AM_ALC_SW               0x0
+#define SW_CAP3                 0x0
+#define SW_CAP2                 0x0
+#define SW_CAP1                 0x0
+#define AM_ALC_1_FIX            0x0
+#define PLL_VTUNE_CTRL          0x1
+#define PLL_SYNC_CTRL           0x0
+#define PLL_SYNC                0x0
+#define PLL_LOOP_CTRL           0x1
+#define DDS_X2_FPGA             0x0
+#define DDS_SAW2_FPGA           0x0
+#define REF_OFFSET_CTRL_FPGA    0x1
+#define GPIO_ADRF_V1            0x2
+#define GPIO_ADRF_V2            0x0
+#define DDS_SAW1_FPGA           0x0
+
+// Define values for Shift Reg
+#define SHIFT_REG_RF_SW_RF      0x0
+#define SHIFT_REG_RF_SW4        0x0
+#define SHIFT_REG_RF_SW0        0x1
+#define SHIFT_REG_RF_SW_X2      0x0
+#define SHIFT_REG_RF_SWx_BANK   0x1
+#define SHIFT_REG_RF_SW_MIXER   0x0
+
+#define SHIFT_REG ((SHIFT_REG_RF_SW_RF << 1) | \
+                    (SHIFT_REG_RF_SW4<<2) | \
+                    (SHIFT_REG_RF_SW0<<3) | \
+                    (SHIFT_REG_RF_SW_X2<<0) | \
+                    (SHIFT_REG_RF_SWx_BANK <<5) | \
+                    (SHIFT_REG_RF_SW_MIXER <<4))
+
+#define GPIO_REG ((DDS_SAW1_FPGA << 21) | \
+                  (GPIO_ADRF_V2 << 20) | \
+                  (GPIO_ADRF_V1 << 19) | \
+                  (REF_OFFSET_CTRL_FPGA << 18) | \
+                  (DDS_SAW2_FPGA << 17) | \
+                  (DDS_X2_FPGA << 16) | \
+                  (PLL_LOOP_CTRL << 15) | \
+                  (PLL_SYNC << 14) | \
+                  (PLL_SYNC_CTRL << 13) | \
+                  (PLL_VTUNE_CTRL << 12) | \
+                  (AM_ALC_1_FIX << 11) | \
+                  (SW_CAP1 << 10) | \
+                  (SW_CAP2 << 9) | \
+                  (SW_CAP3 << 8) | \
+                  (AM_ALC_SW << 7) | \
+                  (SW_CAP4 << 6) | \
+                  (DDS_SYNC_FPGA << 5) | \
+                  (DDS_RESET_FPGA << 4) | \
+                  (DDS_SYNC_CTRL_FPGA << 3) | \
+                  (CTRL_AM_SW3 << 2) | \
+                  (RF_SW2 << 1) | \
+                  (RF_SW1 << 0))
+
+
+#define     RST_ADDR            0x08
+
+#define     RST_FOR_FPGA_ON     0x1
+#define     RST_FOR_FPGA_OFF    0x0
+
+#define     LMX_BASE_ADDR       0x04
+
+void rst_for_fpga(void *bar1);
+
+void shift_reg (void  *bar1);
+
+#endif //DMADRIVER_TMSGHEADERS_H

utils.c

@@ -0,0 +1,97 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <errno.h>
+
+#define RW_MAX_SIZE    0x7ffff000
+
+
+ssize_t read_from_buffer(char *fname, int fd, char *buffer, uint64_t size, uint64_t base) {
+    ssize_t rc;
+    char *buf = buffer;
+    off_t offset = base;
+    size_t count = 0;
+    int loop = 0;
+
+    while (count < size) {
+        uint64_t bytes = size - count;
+
+        if (bytes > RW_MAX_SIZE) {
+            bytes = RW_MAX_SIZE;
+        }
+        if (offset) {
+            rc = lseek(fd, offset, SEEK_SET);
+            if (rc != offset) {
+                fprintf(stderr, "%s, seek off 0x%lx != 0x%lx\n", fname, rc, offset);
+                perror("seek file");
+                return -EIO;
+            }
+        }
+        /* Read data from file into buffer */
+        rc = read(fd, buf, bytes);
+        if (rc < 0) {
+            fprintf(stderr, "%s, read failed\n", fname);
+            perror("read file");
+            return -EIO;
+        }
+        count += rc;
+        if (rc != bytes) {
+            fprintf(stderr, "%s, read failed, rc=%ld, bytes=%ld\n", fname, rc, bytes);
+            break;
+        }
+        buf += bytes;
+        offset += bytes;
+        loop++;
+    }
+    if (count != size && loop) {
+        fprintf(stderr, "%s, read failed, count=%ld, size=%ld\n", fname, count, size);
+        return -EIO;
+    }
+    return count;
+}
+
+ssize_t write_to_buffer(char *fname, int fd, char *buffer, uint64_t size, uint64_t base) {
+    ssize_t rc;
+    char *buf = buffer;
+    off_t offset = base;
+    size_t count = 0;
+    int loop = 0;
+
+    while (count < size) {
+        uint64_t bytes = size - count;
+
+        if (bytes > RW_MAX_SIZE) {
+            bytes = RW_MAX_SIZE;
+        }
+        if (offset) {
+            rc = lseek(fd, offset, SEEK_SET);
+            if (rc != offset) {
+                fprintf(stderr, "%s, seek off 0x%lx != 0x%lx\n", fname, rc, offset);
+                perror("seek file");
+                return -EIO;
+            }
+        }
+        /* Write data from buffer into file */
+        rc = write(fd, buf, bytes);
+        if (rc < 0) {
+            fprintf(stderr, "%s,write 0x%lx @ 0x%lx @ 0x%lx failed %ld.\n", fname, bytes, offset, rc);
+            perror("write file");
+            return -EIO;
+        }
+        count += rc;
+        printf("count = %ld, bytes = %ld\n", count, size);
+        if (rc != bytes) {
+            fprintf(stderr, "%s, write underflow 0x%lx/0x%lx @ 0x%lx.\n", fname, rc, bytes, offset);
+            break;
+        }
+        buf += bytes;
+        offset += bytes;
+        loop++;
+    }
+    if (count != size && loop) {
+        fprintf(stderr, "%s, write underflow, 0x%lx/0x%lx.\n", fname, count, size);
+        return -EIO;
+    }
+    return count;
+}