Добавил динамическое переключение ключей(0.1-9000 МГц).

Devices/lmx2594.c

@@ -235,10 +235,16 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
         a_core_min = 323;
         a_core_max = 244;
     };
-    printf("VCO_CORE = %d\n", vco_core);
+    if (freq >=11900e6 && freq <=12100e6) {
+        vco_daciset_strt = 300;
+        vco_core = 4;
+        vco_cap_ctrl_strt = 1;
+    }
     vco_cap_ctrl_strt = round(c_core_min - (c_core_min - c_core_max) * (freq - f_coremin) / (f_coremax - f_coremin));
-    printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
     vco_daciset_strt = round(a_core_min + (a_core_min - a_core_max) * (freq - f_coremin) / (f_coremax - f_coremin));
+    
+    printf("VCO_CORE = %d\n", vco_core);
+    printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
     printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
 
     // Calibration assist 
@@ -560,11 +566,18 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
         a_core_min = 323;
         a_core_max = 244;
     };
-    printf("VCO_CORE = %d\n", vco_core);
+
     vco_cap_ctrl_strt = round(c_core_min - (c_core_min - c_core_max) * (f_vco - f_coremin) / (f_coremax - f_coremin));
-    printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
     vco_daciset_strt = round(a_core_min + (a_core_min - a_core_max) * (f_vco - f_coremin) / (f_coremax - f_coremin));
-    printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
+   
+    if (f_vco >=11900e6 && f_vco <=12100e6) {
+        vco_daciset_strt = 300;
+        vco_core = 4;
+        vco_cap_ctrl_strt = 1;
+    }
+     printf("VCO_CORE = %d\n", vco_core);
+     printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
+     printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
 
     // Calibration assist 
     //Set the VCO_CORE 
@@ -683,6 +696,8 @@ int lmx_freq_set(void *bar1, double freq) {
     else if (freq < 7.5e9) {
         lmx_freq_set_out_of_band(bar1, freq, f_pd);
     }
+    // Switch the keys 
+    key_switch(bar1, freq);
     return 0;
 }
 

Devices/tmsgheaders.c

@@ -14,9 +14,48 @@ void shift_reg (void  *bar1) {
     *data_ptr = SHIFT_REG;
 }
 
-// void key_switch (void  *bar1, double freq){
-//     if (freq >= 2750e6 && freq <= 3600) {
-//         uint32_t *ptr_gpio = bar1 + LMX_BASE_ADDR;
-//         *ptr_gpio = GPIO_REG |;
-//     }
-// }
+void key_switch (void  *bar1, double freq){
+    if (freq >= 100e3 && freq <= 1000e6) {
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP|0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0<<SHIFT_REG_SW_MIXER_RF_BITP | 0x0<<SHIFT_REG_SW2_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
+    }
+    else if (freq > 1000e6 && freq <= 1300e6) {
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_SW3_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
+    }
+    else if (freq > 1300e6 && freq <= 2200e6) {
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x0<<SHIFT_REG_SW3_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
+    }
+    else if (freq > 2200e6 && freq <= 3600e6) {
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x0 <<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
+    }
+    else if (freq > 3600e6 && freq <= 5500e6) {
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x0<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
+    }
+    else if (freq >5500e6 && freq <= 9000e6){
+        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
+        *ptr_header = InitShRegHeader;
+        // Data for Shift Reg
+        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+        *ptr = 0x1<<SHIFT_REG_SW_MIXER_RF | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x0 << SHIFT_REG_SW_RF_BITP;
+    }
+};
+    

Devices/tmsgheaders.h

@@ -77,50 +77,53 @@
 #define GPIOWordNum             1
 
 // Define bit values for GPIO Reg
-#define RF_SW1                  0x0
-#define RF_SW2                  0x0
-#define CTRL_AM_SW3             0x0
-#define DDS_SYNC_CTRL_FPGA      0x0
-#define DDS_RESET_FPGA          0x0
-#define DDS_SYNC_FPGA           0x0
-#define SW_CAP4                 0x0
-#define AM_ALC_SW               0x1
-#define SW_CAP3                 0x0
-#define SW_CAP2                 0x0
-#define SW_CAP1                 0x0
-#define AM_ALC_1_FIX            0x1
-#define PLL_VTUNE_CTRL          0x1
-#define PLL_SYNC_CTRL           0x0
-#define PLL_SYNC                0x0
-#define PLL_LOOP_CTRL           0x1
-#define DDS_X2_FPGA             0x0
-#define DDS_SAW2_FPGA           0x0
-#define REF_OFFSET_CTRL_FPGA    0x1
-#define GPIO_ADRF_V1            0x2
-#define GPIO_ADRF_V2            0x0
-#define DDS_SAW1_FPGA           0x0
+#define RF_SW1                              0x0
+#define RF_SW2                              0x0
+#define CTRL_AM_SW3                         0x0
+#define DDS_SYNC_CTRL_FPGA                  0x0
+#define DDS_RESET_FPGA                      0x0
+#define DDS_SYNC_FPGA                       0x0
+#define SW_CAP4                             0x0
+#define AM_ALC_SW                           0x1
+#define SW_CAP3                             0x0
+#define SW_CAP2                             0x0
+#define SW_CAP1                             0x0
+#define AM_ALC_1_FIX                        0x1
+#define PLL_VTUNE_CTRL                      0x1
+#define PLL_SYNC_CTRL                       0x0
+#define PLL_SYNC                            0x0
+#define PLL_LOOP_CTRL                       0x1
+#define DDS_X2_FPGA                         0x0
+#define DDS_SAW2_FPGA                       0x0
+#define REF_OFFSET_CTRL_FPGA                0x1
+#define GPIO_ADRF_V1                        0x2
+#define GPIO_ADRF_V2                        0x0
+#define DDS_SAW1_FPGA                       0x0
 
 // Define values for Shift Reg
-#define SHIFT_REG_RF_SW_RF      0x0
-#define SHIFT_REG_RF_SW4        0x0
-#define SHIFT_REG_RF_SW0        0x1
-#define SHIFT_REG_RF_SW_X2      0x0
-#define SHIFT_REG_RF_SWx_BANK   0x1
-#define SHIFT_REG_RF_SW_MIXER   0x0
-
-#define SHIFT_REG_RF_SW_RF_BITP     1
-#define SHIFT_REG_RF_SW4_BITP       2
-#define SHIFT_REG_RF_SW0_BITP       3
-#define SHIFT_REG_RF_SW_X2_BITP     0
-#define SHIFT_REG_RF_SWx_BANK_BITP  5
-#define SHIFT_REG_RF_SW_MIXER_BITP  4
-
-#define SHIFT_REG ((SHIFT_REG_RF_SW_RF << 1) | \
-                    (SHIFT_REG_RF_SW4<<2) | \
-                    (SHIFT_REG_RF_SW0<<3) | \
-                    (SHIFT_REG_RF_SW_X2<<0) | \
-                    (SHIFT_REG_RF_SWx_BANK <<5) | \
-                    (SHIFT_REG_RF_SW_MIXER <<4))
+#define SHIFT_REG_SW_RF                     0x0
+#define SHIFT_REG_SW4_RF                    0x0
+#define SHIFT_REG_GPIO_SW_015_RF            0x1
+#define SHIFT_REG_GPIO_SW_X2_RF             0x0
+#define SHIFT_REG_SW1_RF                    0x1
+#define SHIFT_REG_SW_MIXER_RF               0x0
+
+
+#define SHIFT_REG_GPIO_SW_X2_RF_BITP        0
+#define SHIFT_REG_SW_RF_BITP                1
+#define SHIFT_REG_SW4_RF_BITP               2
+#define SHIFT_REG_GPIO_SW_015_RF_BITP       3
+#define SHIFT_REG_SW_MIXER_RF_BITP          4
+#define SHIFT_REG_SW1_RF_BITP               5
+#define SHIFT_REG_SW2_RF_BITP               6
+#define SHIFT_REG_SW3_RF_BITP               7
+
+#define SHIFT_REG ((SHIFT_REG_SW_RF << 1) | \
+                    (SHIFT_REG_SW4_RF<<2) | \
+                    (SHIFT_REG_GPIO_SW_015_RF<<3) | \
+                    (SHIFT_REG_GPIO_SW_X2_RF<<0) | \
+                    (SHIFT_REG_SW1_RF <<5) | \
+                    (SHIFT_REG_SW_MIXER_RF <<4))
 
 #define GPIO_REG ((DDS_SAW1_FPGA << 21) | \
                   (GPIO_ADRF_V2 << 20) | \
@@ -157,4 +160,6 @@ void rst_for_fpga(void *bar1);
 
 void shift_reg (void  *bar1);
 
+void key_switch (void  *bar1, double freq);
+
 #endif //DMADRIVER_TMSGHEADERS_H