Добавлен конфигурационный регистр. Изменение логики для нового частотного плана

Devices/tmsgheaders.c

@@ -1,11 +1,35 @@
 #include "tmsgheaders.h"
 
-uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF |
-                  CFG_REG_WIDTH_SPI_TMSG_24_BIT |
-                  CFG_REG_MOD_1 |  
-                  CFG_REG_LR_GPIO_0 |
+uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF		|
+                  CFG_REG_WIDTH_SPI_TMSG_24_BIT	|
+                  CFG_REG_MOD_1					|  
+                  CFG_REG_LR_GPIO_0				|
                   CFG_REG_HR_GPIO_0;
 
+ uint32_t tmsgGpioReg = FPGA_AM_CTRL_0			| 
+                        DDS_SAW1_FPGA_0			| 
+                        GPIO_ADRF_V2_0			|
+                        GPIO_ADRF_V1_0			|
+                        REF_OFFSET_CTRL_FPGA_1	| 
+                        DDS_SAW2_FPGA_0			|
+                        DDS_X2_FPGA_0			|
+                        PLL_LOOP_CTRL_1			|
+                        PLL_SYNC_0				|
+                        PLL_SYNC_CTRL_0			|
+                        PLL_VTUNE_CTRL_1		|
+                        AM_ALC_1_FIX_1			|
+                        SW_CAP1_0				|
+                        SW_CAP2_0				| 
+                        SW_CAP3_0				| 
+                        AM_ALC_SW_1				| 
+                        SW_CAP4_0				| 
+                        DDS_SYNC_FPGA_0			| 
+                        DDS_RESET_FPGA_0		| 
+                        DDS_SYNC_CTRL_FPGA_0	| 
+                        CTRL_AM_SW3_0			| 
+                        RF_SW2_0				| 
+                        RF_SW1_0;
+
 uint32_t get_cfg_reg(){
     return cfgReg;
 }
@@ -14,6 +38,14 @@ void set_cfg_reg(uint32_t cfgRegToSet){
     cfgReg = cfgRegToSet;
 }
 
+uint32_t get_tmsg_gpio_reg(){
+    return tmsgGpioReg;
+}
+
+void set_tmsg_gpio_reg(uint32_t tmsgGpioRegToSet){
+    tmsgGpioReg = tmsgGpioRegToSet;
+}
+
 void rst_for_fpga(void *bar1) {
     SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
     uint32_t *ptr = bar1 + CFG_REG_ADDR;
@@ -31,56 +63,163 @@ void shift_reg (void  *bar1) {
 }
 
 void key_switch (void  *bar1, double freq, double lmx_freq) {
+    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    *ptr = InitShRegHeader;
+
     if (freq >= 100e3 && freq <= 1000e6) {
         if (lmx_freq >= 2750e6 && lmx_freq <= 3600e6) {
-             uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-            *ptr_header = InitShRegHeader;
             // Data for Shift Reg
-            uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-            *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP|0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0<<SHIFT_REG_SW_MIXER_RF_BITP | 0x0<<SHIFT_REG_SW2_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
+            *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0<<SHIFT_REG_SW_MIXER_RF_BITP | 0x0<<SHIFT_REG_SW2_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
         }
         else if (lmx_freq > 3600e6 && lmx_freq <=3999.9e6) {
-            uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-            *ptr_header = InitShRegHeader;
             // Data for Shift Reg
-            uint32_t *ptr = bar1 + LMX_BASE_ADDR;
             *ptr = 0x0<<SHIFT_REG_SW1_RF_BITP | 0x0 <<SHIFT_REG_SW_MIXER_RF_BITP | 0x1 <<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
         }
     }
     else if (freq > 1000e6 && freq <= 1300e6) {
-        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-        *ptr_header = InitShRegHeader;
         // Data for Shift Reg
-        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
         *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_SW3_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
     }
     else if (freq > 1300e6 && freq <= 2200e6) {
-        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-        *ptr_header = InitShRegHeader;
         // Data for Shift Reg
-        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
         *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x0<<SHIFT_REG_SW3_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
     }
     else if (freq > 2200e6 && freq <= 3600e6) {
-        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-        *ptr_header = InitShRegHeader;
         // Data for Shift Reg
-        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
         *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x0 <<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
     }
     else if (freq > 3600e6 && freq <= 5500e6) {
-        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-        *ptr_header = InitShRegHeader;
         // Data for Shift Reg
-        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
         *ptr = 0x0<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
     }
-    else if (freq >5500e6 && freq <= 9000e6){
-        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
-        *ptr_header = InitShRegHeader;
+    else if (freq >5500e6 && freq <= 6000e6){
         // Data for Shift Reg
-        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
         *ptr = 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x0 << SHIFT_REG_SW_RF_BITP;
     }
+    else if (freq > 6000e6 && freq <= 7500e6){
+        // Data for Shift Reg
+        *ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x0 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+    }
+    else if (freq > 7500e6 && freq <= 9000e6){
+        // Data for Shift Reg
+        *ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x0 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+    }
+    else if (freq > 9000e6 && freq <= 15000e6){
+        // Data for Shift Reg
+        *ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x1 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+    }
+    else if (freq > 15000e6 && freq <= 18000e6){
+        // Data for Shift Reg
+        *ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x0 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+		*ptr = tmsgGpioReg;
+    }
+    else if (freq > 18000e6 && freq <= 22000e6){
+        // Data for Shift Reg
+        *ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x1 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
+		*ptr = tmsgGpioReg;
+    }
+    else if (freq > 22000e6 && freq <= 27000e6){
+		// Data for Shift Regs
+		*ptr = 0x0 << SHIFT_REG_SW_RF_BITP | 0x1 << SHIFT_REG_SW4_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0 << SHIFT_REG_GPIO_SW_X2_RF_BITP;
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
+		*ptr = tmsgGpioReg;
+    }
+
+	
+	if (freq >= 100e3 && freq <= 6000e6) {
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_0);
+		*ptr = tmsgGpioReg;
+	}
+	else if (freq > 6000e6 && freq <= 27000e6) {
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		*ptr = tmsgGpioReg;
+
+		// Addr CFG_REG
+		ptr = bar1 + CFG_REG_ADDR;
+		// Data CFG_REG
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_1);
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_0);
+		*ptr = cfgReg;
+
+        
+	}
+	else if (freq > 27000e6 && freq <= 37000e6) {
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		*ptr = tmsgGpioReg;
+
+		// Addr CFG_REG
+		ptr = bar1 + CFG_REG_ADDR;
+		// Data CFG_REG
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
+		*ptr = cfgReg;
+        if (freq / 2 > 13500e6 && freq / 2 <= 15000e6){
+            /* code */
+        }
+        else if(freq / 2 > 15000e6 && freq / 2 <= 18000e6){
+            /* code */
+        }
+        else if (freq / 2 > 18000e6 && freq / 2 <= 18500e6)
+        {
+            /* code */
+        }
+        
+	}
+	else if (freq > 37000e6 && freq <= 45000e6) {
+		// Header for GPIO_REG 1MOSI
+		*ptr = (0 << 23) | (DeviceIdGpio1 << 18) | (1 << 1) | 1;
+		// Data for GPIO_REG
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW2_BITM, RF_SW2_BITP, RF_SW2_0);
+		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
+		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
+		*ptr = tmsgGpioReg;
+
+		// Addr CFG_REG
+		ptr = bar1 + CFG_REG_ADDR;
+		// Data CFG_REG
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
+		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
+		*ptr = cfgReg;
+
+        if (freq / 2 > 18500e6 && freq / 2 <= 22000e6){
+            /* code */
+        }
+        else if(freq / 2 > 22000e6 && freq / 2 <= 27500e6){
+            /* code */
+        }
+	}
 };
     

Devices/tmsgheaders.h

@@ -96,11 +96,106 @@
 #define DDS_X2_FPGA                         0x0
 #define DDS_SAW2_FPGA                       0x0
 #define REF_OFFSET_CTRL_FPGA                0x1
-#define GPIO_ADRF_V1                        0x2
+#define GPIO_ADRF_V1                        0x0
 #define GPIO_ADRF_V2                        0x0
 #define DDS_SAW1_FPGA                       0x0
 #define FPGA_AM_CTRL                        0x0
 
+#define RF_SW1_BITP					0
+#define RF_SW2_BITP					1
+#define CTRL_AM_SW3_BITP			2
+#define DDS_SYNC_CTRL_FPGA_BITP		3
+#define DDS_RESET_FPGA_BITP			4
+#define DDS_SYNC_FPGA_BITP			5
+#define SW_CAP4_BITP				6
+#define AM_ALC_SW_BITP				7
+#define SW_CAP3_BITP				8
+#define SW_CAP2_BITP				9
+#define SW_CAP1_BITP				10
+#define AM_ALC_1_FIX_BITP			11
+#define PLL_VTUNE_CTRL_BITP			12
+#define PLL_SYNC_CTRL_BITP			13
+#define PLL_SYNC_BITP				14
+#define PLL_LOOP_CTRL_BITP			15
+#define DDS_X2_FPGA_BITP			16
+#define DDS_SAW2_FPGA_BITP			17
+#define REF_OFFSET_CTRL_FPGA_BITP	18
+#define GPIO_ADRF_V1_BITP			19
+#define GPIO_ADRF_V2_BITP			20
+#define DDS_SAW1_FPGA_BITP			21
+#define FPGA_AM_CTRL_BITP			22
+
+#define RF_SW1_BITM					(0x1 << RF_SW1_BITP					)
+#define RF_SW2_BITM					(0x1 << RF_SW2_BITP					)
+#define CTRL_AM_SW3_BITM			(0x1 << CTRL_AM_SW3_BITP			)
+#define DDS_SYNC_CTRL_FPGA_BITM		(0x1 << DDS_SYNC_CTRL_FPGA_BITP		)
+#define DDS_RESET_FPGA_BITM			(0x1 << DDS_RESET_FPGA_BITP			)
+#define DDS_SYNC_FPGA_BITM			(0x1 << DDS_SYNC_FPGA_BITP			)
+#define SW_CAP4_BITM				(0x1 << SW_CAP4_BITP				)
+#define AM_ALC_SW_BITM				(0x1 << AM_ALC_SW_BITP				)
+#define SW_CAP3_BITM				(0x1 << SW_CAP3_BITP				)
+#define SW_CAP2_BITM				(0x1 << SW_CAP2_BITP				)
+#define SW_CAP1_BITM				(0x1 << SW_CAP1_BITP				)
+#define AM_ALC_1_FIX_BITM			(0x1 << AM_ALC_1_FIX_BITP			)
+#define PLL_VTUNE_CTRL_BITM			(0x1 << PLL_VTUNE_CTRL_BITP			)
+#define PLL_SYNC_CTRL_BITM			(0x1 << PLL_SYNC_CTRL_BITP			)
+#define PLL_SYNC_BITM				(0x1 << PLL_SYNC_BITP				)
+#define PLL_LOOP_CTRL_BITM			(0x1 << PLL_LOOP_CTRL_BITP			)
+#define DDS_X2_FPGA_BITM			(0x1 << DDS_X2_FPGA_BITP			)
+#define DDS_SAW2_FPGA_BITM			(0x1 << DDS_SAW2_FPGA_BITP			)
+#define REF_OFFSET_CTRL_FPGA_BITM	(0x1 << REF_OFFSET_CTRL_FPGA_BITP	)
+#define GPIO_ADRF_V1_BITM			(0x1 << GPIO_ADRF_V1_BITP			)
+#define GPIO_ADRF_V2_BITM			(0x1 << GPIO_ADRF_V2_BITP			)
+#define DDS_SAW1_FPGA_BITM			(0x1 << DDS_SAW1_FPGA_BITP			)
+#define FPGA_AM_CTRL_BITM			(0x1 << FPGA_AM_CTRL_BITP			)
+
+#define RF_SW1_0					(0x0 << RF_SW1_BITP)
+#define RF_SW1_1					(0x1 << RF_SW1_BITP)
+#define RF_SW2_0					(0x0 << RF_SW2_BITP)
+#define RF_SW2_1					(0x1 << RF_SW2_BITP)
+#define CTRL_AM_SW3_0				(0x0 << CTRL_AM_SW3_BITP)
+#define CTRL_AM_SW3_1				(0x1 << CTRL_AM_SW3_BITP)
+#define DDS_SYNC_CTRL_FPGA_0		(0x0 << DDS_SYNC_CTRL_FPGA_BITP)
+#define DDS_SYNC_CTRL_FPGA_1		(0x1 << DDS_SYNC_CTRL_FPGA_BITP)
+#define DDS_RESET_FPGA_0			(0x0 << DDS_RESET_FPGA_BITP)
+#define DDS_RESET_FPGA_1			(0x1 << DDS_RESET_FPGA_BITP)
+#define DDS_SYNC_FPGA_0				(0x0 << DDS_SYNC_FPGA_BITP)
+#define DDS_SYNC_FPGA_1				(0x1 << DDS_SYNC_FPGA_BITP)
+#define SW_CAP4_0					(0x0 << SW_CAP4_BITP)
+#define SW_CAP4_1					(0x1 << SW_CAP4_BITP)
+#define AM_ALC_SW_0					(0x0 << AM_ALC_SW_BITP)
+#define AM_ALC_SW_1					(0x1 << AM_ALC_SW_BITP)
+#define SW_CAP3_0					(0x0 << SW_CAP3_BITP)
+#define SW_CAP3_1					(0x1 << SW_CAP3_BITP)
+#define SW_CAP2_0					(0x0 << SW_CAP2_BITP)
+#define SW_CAP2_1					(0x1 << SW_CAP2_BITP)
+#define SW_CAP1_0					(0x0 << SW_CAP1_BITP)
+#define SW_CAP1_1					(0x1 << SW_CAP1_BITP)
+#define AM_ALC_1_FIX_0				(0x0 << AM_ALC_1_FIX_BITP)
+#define AM_ALC_1_FIX_1				(0x1 << AM_ALC_1_FIX_BITP)
+#define PLL_VTUNE_CTRL_0			(0x0 << PLL_VTUNE_CTRL_BITP)
+#define PLL_VTUNE_CTRL_1			(0x1 << PLL_VTUNE_CTRL_BITP)
+#define PLL_SYNC_CTRL_0				(0x0 << PLL_SYNC_CTRL_BITP)
+#define PLL_SYNC_CTRL_1				(0x1 << PLL_SYNC_CTRL_BITP)
+#define PLL_SYNC_0					(0x0 << PLL_SYNC_BITP)
+#define PLL_SYNC_1					(0x1 << PLL_SYNC_BITP)
+#define PLL_LOOP_CTRL_0				(0x0 << PLL_LOOP_CTRL_BITP)
+#define PLL_LOOP_CTRL_1				(0x1 << PLL_LOOP_CTRL_BITP)
+#define DDS_X2_FPGA_0				(0x0 << DDS_X2_FPGA_BITP)
+#define DDS_X2_FPGA_1				(0x1 << DDS_X2_FPGA_BITP)
+#define DDS_SAW2_FPGA_0				(0x0 << DDS_SAW2_FPGA_BITP)
+#define DDS_SAW2_FPGA_1				(0x1 << DDS_SAW2_FPGA_BITP)
+#define REF_OFFSET_CTRL_FPGA_0		(0x0 << REF_OFFSET_CTRL_FPGA_BITP)
+#define REF_OFFSET_CTRL_FPGA_1		(0x1 << REF_OFFSET_CTRL_FPGA_BITP)
+#define GPIO_ADRF_V1_0				(0x0 << GPIO_ADRF_V1_BITP)
+#define GPIO_ADRF_V1_1				(0x1 << GPIO_ADRF_V1_BITP)
+#define GPIO_ADRF_V2_0				(0x0 << GPIO_ADRF_V2_BITP)
+#define GPIO_ADRF_V2_1				(0x1 << GPIO_ADRF_V2_BITP)
+#define DDS_SAW1_FPGA_0				(0x0 << DDS_SAW1_FPGA_BITP)
+#define DDS_SAW1_FPGA_1				(0x1 << DDS_SAW1_FPGA_BITP)
+#define FPGA_AM_CTRL_0				(0x0 << FPGA_AM_CTRL_BITP)
+#define FPGA_AM_CTRL_1				(0x1 << FPGA_AM_CTRL_BITP)
+
 // Define values for Shift Reg
 #define SHIFT_REG_SW_RF                     0x0
 #define SHIFT_REG_SW4_RF                    0x0