Заменен начальный адрес в отправке для ad9912

Devices/ad9912.c

@@ -232,9 +232,9 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     // };
     // First 16 bits is the instruction word
     ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12);
-    ad9912_ftw_regs_qspi[1] = (ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8 | (ftw0_7_0 << BITP_AD9912_QSPI_7_0) | (ftw0_15_8 << BITP_AD9912_QSPI_15_8));
-    ad9912_ftw_regs_qspi[2] = ((ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32));
-    ad9912_ftw_regs_qspi[3] = ((ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0) | (0x00 << BITP_AD9912_QSPI_PHASE_13_8));
+    ad9912_ftw_regs_qspi[1] = (ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8 | (0x00 << BITP_AD9912_QSPI_PHASE_13_8) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0));
+    ad9912_ftw_regs_qspi[2] = ((ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24));
+    ad9912_ftw_regs_qspi[3] = ((ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
     // // Create the appropriate header
     // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
     // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);

Devices/ad9912.h

@@ -90,17 +90,17 @@
 //Addr[12:0]
 #define BITM_AD9912_INSTRUCTION_WORD_ADDRESS                        (0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
 #define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR                      (0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
-#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8                 (0xA6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8                 (0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
 #define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12                (0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 /**********************************************************************************
  * 										QSPI_FTW[7:0][15:8]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_7_0                                        8
+#define BITP_AD9912_QSPI_7_0                                        0
 #define BITM_AD9912_QSPI_7_0                                        (0xFF << BITP_AD9912_QSPI_7_0)
 /**********************************************************************************
  * 										QSPI_FTW[15:8][7:0]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_15_8                                       0
+#define BITP_AD9912_QSPI_15_8                                       8
 #define BITM_AD9912_QSPI_15_8                                       (0xFF << BITP_AD9912_QSPI_15_8)
 /**********************************************************************************
  * 										QSPI_FTW[23:16]
@@ -110,12 +110,12 @@
 /**********************************************************************************
  * 										QSPI_FTW[31:24]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_31_24                                      8
+#define BITP_AD9912_QSPI_31_24                                      0
 #define BITM_AD9912_QSPI_31_24                                      (0xFF << BITP_AD9912_QSPI_31_24)
 /**********************************************************************************
  * 										QSPI_FTW[39:32]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_39_32                                      0
+#define BITP_AD9912_QSPI_39_32                                      8
 #define BITM_AD9912_QSPI_39_32                                      (0xFF << BITP_AD9912_QSPI_39_32)
 /**********************************************************************************
  * 										QSPI_FTW[47:40]
@@ -125,12 +125,12 @@
 /**********************************************************************************
  * 										QSPI_PHASE[7:0]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_PHASE_7_0                                  8
+#define BITP_AD9912_QSPI_PHASE_7_0                                  0
 #define BITM_AD9912_QSPI_PHASE_7_0                                  (0xFF << BITP_AD9912_QSPI_PHASE_7_0)
 /**********************************************************************************
  * 										QSPI_PHASE[13:8]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_PHASE_13_8                                 0
+#define BITP_AD9912_QSPI_PHASE_13_8                                 8
 #define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)
 
 extern uint32_t ad9912_ftw_regs_qspi[4];

Devices/tmsgheaders.c

@@ -74,7 +74,7 @@ void shift_reg (void  *bar1) {
 }
 
 void key_switch (void  *bar1, double freq, double lmx_freq) {
-	uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+	// uint32_t *ptr = bar1 + LMX_BASE_ADDR;
 	// *ptr = InitShRegHeader;
 	
 	if (freq >= 100e3 && freq <= 6000e6) {
@@ -238,7 +238,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
-		ptr = bar1 + CFG_REG_ADDR;
+		uint32_t *ptr  = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_1);
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_0);
@@ -293,7 +293,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
-		ptr = bar1 + CFG_REG_ADDR;
+		uint32_t *ptr = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);
@@ -339,7 +339,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
-		ptr = bar1 + CFG_REG_ADDR;
+		uint32_t *ptr = bar1 + CFG_REG_ADDR;
 		// Data CFG_REG
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_LR_GPIO_BITM, CFG_REG_LR_GPIO_BITP, CFG_REG_LR_GPIO_0);
 		SET_REGISTER_PARAM(cfgReg, CFG_REG_HR_GPIO_BITM, CFG_REG_HR_GPIO_BITP, CFG_REG_HR_GPIO_1);