Тестирование отправок qspi для ad9912 и ShiftReg

.vscode/settings.json

@@ -1,5 +1,6 @@
 {
     "files.associations": {
-        "tmsgheaders.h": "c"
+        "tmsgheaders.h": "c",
+        "lmx2594regs.h": "c"
     }
 }

Devices/ad9912.c

@@ -40,21 +40,21 @@
         0x050800,
         0x050900
 };
-
+uint32_t ad9912_ftw_regs_qspi[3];
 /*-------------------------AD9912 INIT FUNCTION-------------------------*/
 void ad9912_init(void *bar1) {
-    uint32_t *ptr_rst = bar1 + AD9912_BASE_ADDR;
+    uint32_t *ptr_rst = bar1 + TMSG_BASE_ADDR;
     *ptr_rst = GPIO_INIT_HEADER;
     //Rst on
     *ptr_rst = AD9912_RST_ON;
     // Rst off
     *ptr_rst = GPIO_REG;
     //Init Header
-    uint32_t *ptr = bar1 + AD9912_BASE_ADDR;
+    uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
     *ptr = InitDDSHeader;
     //Init Data
     for (int k = 0; k < AD9912_COUNT; k++) {
-        uint32_t *ptr = bar1 + AD9912_BASE_ADDR;
+        uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
         *ptr = ad9912regs[k];
     }
 }
@@ -181,7 +181,6 @@ double ad9912_set_out_of_band(double lmx_freq,double f_pd) {
 
 double ad9912_set(void *bar1, double freq, double f_pd) {
     double fs = 1e9;
-    int lmx_n = 50;
 
     if (freq >= 7500e6 && freq <= 15000e6) {
         f_pd = ad9912_set_main_band(freq,f_pd);
@@ -223,23 +222,26 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] | (ftw1_47_40 << BITP_AD9912_FTW0_FREQ_WORD_47_40);
     // Set the frequency
 
-    uint32_t ad9912_ftw_regs[] = {
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0],
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8],
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16],
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24],
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24],
-        ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40]
-    };
-
-    // Create the appropriate header
-    uint32_t *dds_header = bar1 + AD9912_BASE_ADDR;
-    *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);
-    uint32_t *dds_data = bar1 + AD9912_BASE_ADDR;
-    // Write the data
-    for (int i = 0; i < sizeof(ad9912_ftw_regs)/4; i++) {
-        *dds_data = ad9912_ftw_regs[i];
-    }
+    // uint32_t ad9912_ftw_regs[] = {
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0],
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8],
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16],
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24],
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24],
+    //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40]
+    // };
+    // First 16 bits is the instruction word
+    ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
+    ad9912_ftw_regs_qspi[1] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32);
+    ad9912_ftw_regs_qspi[2] = (ftw1_47_40 << BITP_AD9912_QSPI_47_40);
+    // // Create the appropriate header
+    // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
+    // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);
+    // uint32_t *dds_data = bar1 + TMSG_BASE_ADDR;
+    // // Write the data
+    // for (int i = 0; i < sizeof(ad9912_ftw_regs)/4; i++) {
+    //     *dds_data = ad9912_ftw_regs[i];
+    // }
 
     return f_pd;
 

Devices/ad9912.h

@@ -66,8 +66,60 @@
 #define BITM_AD9912_FTW0_FREQ_WORD_47_40                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
 #define REGP_AD9912_FTW0_FREQ_WORD_47_40                         0x13
 
+/**********************************************************************************
+ * 										INSTRUCTION WORD[15:0]
+*********************************************************************************/
+#define BITP_AD9912_INSTRUCTION_WORD_15_0                           0
+#define BITM_AD9912_INSTRUCTION_WORD_15_0                           (0xFFFF << BITP_AD9912_INSTRUCTION_WORD_15_0)
+#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE                     23
+#define BITM_AD9912_INSTRUCTION_WORD_READ_WRITE                     (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+#define ENUM_AD9912_INSTRUCTION_WORD_WRITE                          (0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+#define ENUM_AD9912_INSTRUCTION_WORD_READ                           (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
+
+#define BITP_AD9912_INSTRUCTION_WORD_LENGTH                         21
+#define BITM_AD9912_INSTRUCTION_WORD_LENGTH                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1                       (0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2                       (0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3                       (0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+#define ENUM_AD9912_INSTRUCTION_WORD_STREAM                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
+
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS                        8
+//Addr[12:0]
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS                        (0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR                      (0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+/**********************************************************************************
+ * 										QSPI_FTW[7:0]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_7_0                                        0
+#define BITM_AD9912_QSPI_7_0                                        (0xFF << BITP_AD9912_QSPI_7_0)
+/**********************************************************************************
+ * 										QSPI_FTW[15:8]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_15_8                                       0
+#define BITM_AD9912_QSPI_15_8                                       (0xFF << BITP_AD9912_QSPI_15_8)
+/**********************************************************************************
+ * 										QSPI_FTW[23:16]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_23_16                                      8
+#define BITM_AD9912_QSPI_23_16                                      (0xFF << BITP_AD9912_QSPI_23_16)
+/**********************************************************************************
+ * 										QSPI_FTW[31:24]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_31_24                                      16
+#define BITM_AD9912_QSPI_31_24                                      (0xFF << BITP_AD9912_QSPI_31_24)
+/**********************************************************************************
+ * 										QSPI_FTW[39:32]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_39_32                                      24
+#define BITM_AD9912_QSPI_39_32                                      (0xFF << BITP_AD9912_QSPI_39_32)
+/**********************************************************************************
+ * 										QSPI_FTW[47:40]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_47_40                                      0
+#define BITM_AD9912_QSPI_47_40                                      (0xFF << BITP_AD9912_QSPI_47_40)
+
 
-/*----------------------------------------------------------------------*/
+extern uint32_t ad9912_ftw_regs_qspi[3];
 void ad9912_init(void *bar1);
 double ad9912_set(void *bar1, double freq, double f_pd);
 double ad9912_set_out_of_band(double freq,double f_pd); 

Devices/lmx2594.c

@@ -121,10 +121,146 @@ uint32_t lmx2594regs[LMX_COUNT] = {
         0x00251C
 };
 
+uint32_t lmx_change_freq_regs[12];
+
 struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
     struct vco_params params;
 
-      if (lmx_freq >= 7500e6 && lmx_freq <= 8600e6) {
+    if (lmx_freq < 7500e6) {
+        params.f_vco = 2 * lmx_freq;
+        params.chan_div = 2;
+        params.ch_div_reg = 0;
+        double vco_div = 7.5e9 / lmx_freq;
+
+        if (params.f_vco < 7.5e9) {
+            if (vco_div > 2 && vco_div <= 4) {
+                params.chan_div = 4;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 4 && vco_div <= 6) {
+                params.chan_div = 6;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 6 && vco_div <= 8) {
+                params.chan_div = 8;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 8 && vco_div <= 12) {
+                params.chan_div = 12;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 12 && vco_div <= 16) {
+                params.chan_div = 16;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 16 && vco_div <= 24) {
+                params.chan_div = 24;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 24 && vco_div <= 32) {
+                params.chan_div = 32;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 32 && vco_div <= 48) {
+                params.chan_div = 48;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 48 && vco_div <= 64) {
+                params.chan_div = 64;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 64 && vco_div <= 96) {
+                params.chan_div = 96;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 96 && vco_div <= 128) {
+                params.chan_div = 128;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 128 && vco_div <= 192) {
+                params.chan_div = 192;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 192 && vco_div <= 256) {
+                params.chan_div = 256;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 256 && vco_div <= 384) {
+                params.chan_div = 384;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 384 && vco_div <= 512) {
+                params.chan_div = 512;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            else if (vco_div > 512 && vco_div <= 768) {
+                params.chan_div = 768;
+                params.f_vco = lmx_freq * params.chan_div;
+            }
+            switch(params.chan_div) {
+                case 2:
+                    params.ch_div_reg = 0;
+                    break;
+                case 4:
+                    params.ch_div_reg = 1;
+                    break;
+                case 6:
+                    params.ch_div_reg = 2;
+                    break;
+                case 8:
+                    params.ch_div_reg = 3;
+                    break;
+                case 12:
+                    params.ch_div_reg = 4;
+                    break;
+                case 16:
+                    params.ch_div_reg = 5;
+                    break;
+                case 24:
+                    params.ch_div_reg = 6;
+                    break;
+                case 32:
+                    params.ch_div_reg = 7;
+                    break;
+                case 48:
+                    params.ch_div_reg = 8;
+                    break;
+                case 64:
+                    params.ch_div_reg = 9;
+                    break;
+                case 96:
+                    params.ch_div_reg = 10;
+                    break;
+                case 128:
+                    params.ch_div_reg = 11;
+                    break;
+                case 192:
+                    params.ch_div_reg = 12;
+                    break;
+                case 256:
+                    params.ch_div_reg = 13;
+                    break;
+                case 384:
+                    params.ch_div_reg = 14;
+                    break;
+                case 512:
+                    params.ch_div_reg = 15;
+                    break;
+                case 768:
+                    params.ch_div_reg = 16;
+                    break;
+            }
+        }
+        else {
+            params.ch_div_reg = 0;
+            params.f_vco = lmx_freq*2;
+        }
+    }
+    else {
+        params.f_vco = lmx_freq; 
+    }
+
+      if (params.f_vco >= 7500e6 && params.f_vco <= 8600e6) {
         params.vco_core = 1;
         params.f_coremin = 7500e6;
         params.f_coremax = 8600e6;
@@ -133,7 +269,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 299;
         params.a_core_max = 240;
     }
-    else if (lmx_freq > 8600e6 && lmx_freq < 9800e6) {
+    else if (params.f_vco > 8600e6 && params.f_vco < 9800e6) {
         params.vco_core = 2;
         params.f_coremin = 8600e6;
         params.f_coremax = 9800e6;
@@ -142,7 +278,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 356;
         params.a_core_max = 247;
     }
-    else if (lmx_freq >= 9800e6 && lmx_freq <= 10800e6) {
+    else if (params.f_vco >= 9800e6 && params.f_vco <= 10800e6) {
         params.vco_core = 3;
         params.f_coremin = 9800e6;
         params.f_coremax = 10800e6;
@@ -151,7 +287,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 324;
         params.a_core_max = 224;
     }
-    else if (lmx_freq > 10800e6 && lmx_freq <= 12000e6) {
+    else if (params.f_vco > 10800e6 && params.f_vco <= 12000e6) {
         params.vco_core = 4;
         params.f_coremin = 10800e6;
         params.f_coremax = 12000e6;
@@ -160,7 +296,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 383;
         params.a_core_max = 244;
     }
-    else if (lmx_freq > 12000e6 && lmx_freq <= 12900e6) {
+    else if (params.f_vco > 12000e6 && params.f_vco <= 12900e6) {
         params.vco_core = 5;
         params.f_coremin = 12000e6;
         params.f_coremax = 12900e6;
@@ -169,7 +305,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 205;
         params.a_core_max = 146;
     }
-    else if (lmx_freq > 12900e6 && lmx_freq <= 13900e6) {
+    else if (params.f_vco > 12900e6 && params.f_vco <= 13900e6) {
         params.vco_core = 6;
         params.f_coremin = 12900e6;
         params.f_coremax = 13900e6;
@@ -178,7 +314,7 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_min = 242;
         params.a_core_max = 163;
     }
-    else if (lmx_freq > 13900e6 && lmx_freq <= 15000e6) {
+    else if (params.f_vco > 13900e6 && params.f_vco <= 15000e6) {
         params.vco_core = 7;
         params.f_coremin = 13900e6;
         params.f_coremax = 15000e6;
@@ -188,19 +324,19 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
         params.a_core_max = 244;
     }
 
-    if (lmx_freq >=11900e6 && lmx_freq <=12100e6) {
+    if (params.f_vco >=11900e6 && params.f_vco <=12100e6) {
         params.vco_daciset_strt = 300;
         params.vco_core = 4;
         params.vco_cap_ctrl_strt = 1;
     }
 
-    params.vco_cap_ctrl_strt = round(params.c_core_min - (params.c_core_min - params.c_core_max) * (lmx_freq - params.f_coremin) / (params.f_coremax - params.f_coremin));
-    params.vco_daciset_strt = round(params.a_core_min + (params.a_core_min - params.a_core_max) * (lmx_freq - params.f_coremin) / (params.f_coremax - params.f_coremin));
+    params.vco_cap_ctrl_strt = round(params.c_core_min - (params.c_core_min - params.c_core_max) * (params.f_vco - params.f_coremin) / (params.f_coremax - params.f_coremin));
+    params.vco_daciset_strt = round(params.a_core_min + (params.a_core_min - params.a_core_max) * (params.f_vco - params.f_coremin) / (params.f_coremax - params.f_coremin));
 
-    if (lmx_freq <= 12500e6) {
+    if (params.f_vco <= 12500e6) {
         params.pfd_dly_sel = 1;
     }
-    else if (lmx_freq > 12500e6) {
+    else if (params.f_vco > 12500e6) {
         params.pfd_dly_sel = 2;
     }
 
@@ -229,8 +365,23 @@ struct vco_params calculate_vco_params (double lmx_freq, double f_pd) {
     }
 
     // Calculate the ACAL_CMP_DLY
-    double Fsmclk = f_pd/(pow(2,params.cal_clk_div));
-    params.acal_cmp_dly = (uint8_t) ((uint64_t)round((Fsmclk)/10e6)); 
+    double fsm_clk = f_pd/(pow(2,params.cal_clk_div));
+    params.acal_cmp_dly = (uint8_t) ((uint64_t)round((fsm_clk)/10e6));
+
+    // Calculate the N_div
+    params.N_div = params.f_vco/f_pd;
+    params.N = (uint32_t) params.N_div;
+    if (params.f_vco <= 12500e6) {
+        if (params.N < 28) {
+            params.N = 28;
+        }
+    }
+    else if (params.f_vco > 12500e6) {
+        if (params.N < 32) {
+            params.N = 32;
+        }
+    }
+
     return params;
 }
 
@@ -261,22 +412,37 @@ void set_vco_params (struct vco_params *params) {
     lmx2594regs[112-R4_ADDR] = lmx2594regs[112-R4_ADDR] & (~BITM_LMX2594_R4_ACAL_CMP_DLY);
     lmx2594regs[112-R4_ADDR] = lmx2594regs[112-R4_ADDR] | (params->acal_cmp_dly << BITP_LMX2594_R4_ACAL_CMP_DLY);
 
-}
+    // Set the N Value
+    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] & (~0xFFFF);
+    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] | (params->N >> 16);
+    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
+    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (params->N & 0xFFFF);
 
+    // Set the CHDIV value
+    lmx2594regs[112-CHDIV] = lmx2594regs[112-CHDIV] & (~BITM_LMX2594_R75_CHDIV);
+    lmx2594regs[112-CHDIV] = lmx2594regs[112-CHDIV] | (params->ch_div_reg << BITP_LMX2594_R75_CHDIV);
+    if (params->chan_div > 2) {
+        lmx2594regs[112-CHDIV_DIV2] = lmx2594regs[112-CHDIV_DIV2] | BITM_LMX2594_R31_CHDIV_DIV2;
+    }
+    else {
+        lmx2594regs[112-CHDIV_DIV2] = lmx2594regs[112-CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
+    }
+
+}
 void auto_cal(void *bar1) {
     lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] & (~BITM_LMX2594_R0_FCAL);
     lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] | LMX2594_R0_FCAL_EN;
-    uint32_t *ptr_header = bar1+LMX_BASE_ADDR;
+    uint32_t *ptr_header = bar1+TMSG_BASE_ADDR;
     *ptr_header = ((0 << 23) | (DeviceIdLmx2594 << 18) | (0x1 << 1) | 1);
 
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
         *ptr = lmx2594regs[112-FCAL_ADDR];
 
 }
 
 void lmx2594_init(void *bar1) {
     // Header for LMX Reset
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
+    uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
     *ptr = LMX2594_RST_HEADER;
     // Reset Data
     for (int m = 0; m < (sizeof(lmx2594_rst))/4; m++) {
@@ -286,7 +452,7 @@ void lmx2594_init(void *bar1) {
     *ptr = InitLMX2594Header;
     // Init data
     for (int i = 0; i < LMX_COUNT; i++) {
-        uint32_t *data_ptr = bar1 + LMX_BASE_ADDR;
+        uint32_t *data_ptr = bar1 + TMSG_BASE_ADDR;
         *data_ptr = lmx2594regs[i];
     }
 }
@@ -294,34 +460,11 @@ void lmx2594_init(void *bar1) {
 /*-------------------------LMX2594 Frequency Set-------------------------*/
 int lmx_freq_set_main_band_int_mode(void *bar1, double lmx_freq, double f_pd) {
 
-    double N_div;
-    printf("f_pd before = %f\n",f_pd);
-    N_div = lmx_freq / f_pd;
-
-    uint32_t N = (uint32_t) N_div;
-     if (lmx_freq <= 12500e6) {
-        if (N < 28){
-            N= 28;
-        }
-    }
-    else if (lmx_freq > 12500e6) {
-        if (N <32) {
-            N = 32;
-        }
-    };
-
     // Partial assist for the calibration
     struct vco_params params = calculate_vco_params(lmx_freq, f_pd);
 
     // Set the vco params
     set_vco_params(&params);
-    // SET the N_DIV
-    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] &(~0xFFFF);
-    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] | (N >> 16);
-    //CLear the lower 16 bits of the register
-    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
-    // Next 16 bits of the register
-    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (N & 0xFFFF);
     // Clear the SEG1_EN bit
     lmx2594regs[112-CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
     // Set the OUTA_MUX to channel divider R45[12:11]; 0 - Channel divider, 1 - VCO;
@@ -330,204 +473,35 @@ int lmx_freq_set_main_band_int_mode(void *bar1, double lmx_freq, double f_pd) {
     lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] & (~BITM_LMX2594_R0_FCAL);   
     lmx2594regs[112-FCAL_ADDR] = lmx2594regs[112-FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
 
-    uint32_t lmx_change_freq_regs[] = {
-            lmx2594regs[112 - VCO_SEL],
-            lmx2594regs[112 - CAP_CTRL_START],
-            lmx2594regs[112 - VCO_DACISET],
-            lmx2594regs[112-PFD_DLY_SEL],
-            lmx2594regs[112-R4_ADDR],
-            lmx2594regs[112-R1_ADDR],
-            lmx2594regs[112-CHDIV_DIV2],
-            lmx2594regs[112-PLL_N_S],
-            lmx2594regs[112-PLL_N_M],
-            lmx2594regs[112 - OUTA_MUX],
-            lmx2594regs[112-FCAL_ADDR]
-    };
-     // Create a header for the LMX2594 with the appropriate number of words MOSI 4
-    uint32_t LMX_HEADER = ((0x1<< 23) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | 1);
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-    *ptr = LMX_HEADER;
-    uint32_t *data_ptr = bar1 + LMX_BASE_ADDR;
-    for (int i = 0; i < sizeof(lmx_change_freq_regs)/4; i++) {
-        *data_ptr = lmx_change_freq_regs[i];
-    }
+    lmx_change_freq_regs[0] = lmx2594regs[112 - VCO_SEL];
+    lmx_change_freq_regs[1] = lmx2594regs[112 - CAP_CTRL_START];
+    lmx_change_freq_regs[2] = lmx2594regs[112 - VCO_DACISET];
+    lmx_change_freq_regs[3] = lmx2594regs[112 - PFD_DLY_SEL];
+    lmx_change_freq_regs[4] = lmx2594regs[112 - R4_ADDR];
+    lmx_change_freq_regs[5] = lmx2594regs[112 - R1_ADDR];
+    lmx_change_freq_regs[6] = lmx2594regs[112 - PLL_N_S];
+    lmx_change_freq_regs[7] = lmx2594regs[112 - PLL_N_M];
+    lmx_change_freq_regs[8] = lmx2594regs[112 - CHDIV];
+    lmx_change_freq_regs[9] = lmx2594regs[112 - CHDIV_DIV2];
+    lmx_change_freq_regs[10] = lmx2594regs[112 - OUTA_MUX];
+    lmx_change_freq_regs[11] = lmx2594regs[112 - FCAL_ADDR];
+    //  // Create a header for the LMX2594 with the appropriate number of words MOSI 4
+    // uint32_t LMX_HEADER = ((ENUM_SPIMODE_4MOSI) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | TERM_BIT_1);
+    // uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
+    // *ptr = LMX_HEADER;
+    // uint32_t *data_ptr = bar1 + TMSG_BASE_ADDR;
+    // for (int i = 0; i < sizeof(lmx_change_freq_regs)/4; i++) {
+    //     *data_ptr = lmx_change_freq_regs[i];
+    // }
     return 0;
 }
 
 int lmx_freq_set_out_of_band_int_mode(void *bar1, double lmx_freq, double f_pd) {
-
-    double f_vco = 2 * lmx_freq;
-    int chan_div = 2;
-    uint8_t ch_div_reg = 0; // 2
-    double vco_div = 7.5e9 / lmx_freq;
-
-    // minimum N_div value is 28 and Vco frequency can't be less than 7.5 GHz
-    if (f_vco < 7.5e9) {
-        if (vco_div > 2 && vco_div <= 4) {
-            chan_div = 4;  // 4
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 4 && vco_div <= 6) {
-            chan_div = 6;  // 6
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 6 && vco_div <= 8) {
-            chan_div = 8;  // 8
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 8 && vco_div <= 12) {
-            chan_div = 12;  // 12
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 12 && vco_div <= 16) {
-            chan_div = 16;  // 16
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 16 && vco_div <= 24) {
-            chan_div = 24;  // 24
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 24 && vco_div <= 32) {
-            chan_div = 32;  // 32
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 32 && vco_div <= 48) {
-            chan_div = 48;  // 48
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 48 && vco_div <= 64) {
-            chan_div = 64;  // 64
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 64 && vco_div <= 72) {
-            chan_div = 72;  // 72
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 72 && vco_div <= 96) {
-            chan_div = 96;  // 96
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 96 && vco_div <= 128) {
-            chan_div = 128;  // 128
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 128 && vco_div <= 192) {
-            chan_div = 192;  // 192
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 192 && vco_div <= 256) {
-            chan_div = 256;  // 256
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 256 && vco_div <= 384) {
-            chan_div = 384;  // 384
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 384 && vco_div <= 512) {
-            chan_div = 512;  // 512
-            f_vco = lmx_freq * chan_div;
-        }
-        else if (vco_div > 512 && vco_div <= 768) {
-            chan_div = 768;  // 768
-            f_vco = lmx_freq * chan_div;
-        }
-        switch (chan_div) {
-            case 2:
-                ch_div_reg = 0;
-                break;
-            case 4:
-                ch_div_reg = 1;
-                break;
-            case 6:
-                ch_div_reg = 2;
-                break;
-            case 8:
-                ch_div_reg = 3;
-                break;
-            case 12:
-                ch_div_reg = 4;
-                break;
-            case 16:
-                ch_div_reg = 5;
-                break;
-            case 24:
-                ch_div_reg = 6;
-                break;
-            case 32:
-                ch_div_reg = 7;
-                break;
-            case 48:
-                ch_div_reg = 8;
-                break;
-            case 64:
-                ch_div_reg = 9;
-                break;
-            case 72:
-                ch_div_reg = 10;
-                break;
-            case 96:
-                ch_div_reg = 11;
-                break;
-            case 128:
-                ch_div_reg = 12;
-                break;
-            case 192:
-                ch_div_reg = 13;
-                break;
-            case 256:
-                ch_div_reg = 14;
-                break;
-            case 384:
-                ch_div_reg = 15;
-                break;
-            case 512:
-                ch_div_reg = 16;
-                break;
-            case 768:
-                ch_div_reg = 17;
-                break;
-        }
-    }
-    else {
-        ch_div_reg = 0;
-        f_vco = lmx_freq * 2;
-    }
-    double N_div = f_vco / f_pd;
-    uint32_t N = (uint32_t) N_div;
-     if (f_vco <= 12500e6) {
-        if (N < 28){
-            N= 28;
-        };
-    }
-    else if (f_vco > 12500e6) {
-        if (N <32) {
-            N = 32;
-        }
-    };
     // Partial assist for the calibration
 
-    struct vco_params params = calculate_vco_params(f_vco, f_pd);
+    struct vco_params params = calculate_vco_params(lmx_freq, f_pd);
     // Set the vco params
     set_vco_params(&params);
-    // Set the N value
-    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] &(~0xFFFF);
-    lmx2594regs[112-PLL_N_S] = lmx2594regs[112-PLL_N_S] | (N >> 16);
-    //CLear the lower 16 bits of the register
-    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] & (~0xFFFF);
-    // Next 16 bits of the register
-    lmx2594regs[112-PLL_N_M] = lmx2594regs[112-PLL_N_M] | (N & 0xFFFF);
-     // Program the CHDIV value
-    lmx2594regs[112 - CHDIV] = lmx2594regs[112 - CHDIV] & (~BITM_LMX2594_R75_CHDIV);
-    // Set the CHDIV value with the starting position BITP_LMX2594_R75_CHDIV
-    lmx2594regs[112 - CHDIV] = lmx2594regs[112 - CHDIV] | (ch_div_reg << BITP_LMX2594_R75_CHDIV);
-    // If the ch_div > 2 then set the SEG1_EN bit
-    if (chan_div > 2) {
-        lmx2594regs[112 - CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
-        lmx2594regs[112 - CHDIV_DIV2] = lmx2594regs[112 - CHDIV_DIV2] | (ENUM_LMX2594_R31_CHDIV_DIV2_EN);
-    }
-    else {
-        lmx2594regs[112-CHDIV_DIV2] =  lmx2594regs[112 - CHDIV_DIV2] & (~BITM_LMX2594_R31_CHDIV_DIV2);
-    }
     // Set the OUTA_MUX to channel divider R45[12:11]; 0 - Channel divider, 1 - VCO;
     lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] & (~BITM_LMX2594_R45_OUTA_MUX);
     lmx2594regs[112 - OUTA_MUX] = lmx2594regs[112 - OUTA_MUX] | ENUM_LMX2594_R45_OUTA_MUX_CH_DIV;
@@ -536,42 +510,28 @@ int lmx_freq_set_out_of_band_int_mode(void *bar1, double lmx_freq, double f_pd)
     lmx2594regs[112 - FCAL_ADDR] = lmx2594regs[112 - FCAL_ADDR] & (~LMX2594_R0_FCAL_EN);
     lmx2594regs[112 - FCAL_ADDR] = lmx2594regs[112 - FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
 
-    uint32_t lmx_change_freq_regs []={
-        lmx2594regs[112 - VCO_SEL],
-        lmx2594regs[112 - CAP_CTRL_START],
-        lmx2594regs[112 - VCO_DACISET],
-        lmx2594regs[112-PFD_DLY_SEL],
-        lmx2594regs[112-R4_ADDR],
-        lmx2594regs[112-R1_ADDR],
-        lmx2594regs[112 - PLL_N_S],
-        lmx2594regs[112 - PLL_N_M],
-        lmx2594regs[112 - CHDIV],
-        lmx2594regs[112 - CHDIV_DIV2],
-        lmx2594regs[112 - OUTA_MUX],
-        lmx2594regs[112 - FCAL_ADDR]
-    };
-
-    // Create a header for the LMX2594 with the appropriate number of words MOSI 4
-    uint32_t LMX_HEADER = ((0x1<< 23) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | 1);
-    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
-    *ptr = LMX_HEADER;
-    // Send the data
-    uint32_t *data_ptr = bar1 + LMX_BASE_ADDR;
-    for (int i = 0; i < sizeof(lmx_change_freq_regs) / 4; i++) {
-        *data_ptr = lmx_change_freq_regs[i];
-    }
-    // char filename[100];
-    // sprintf(filename, "%f.txt", lmx_freq);
-    // FILE * f = fopen(filename, "w");
-    // for (int i = 0; i < sizeof(lmx2594regs) / 4; i++) {
-    //     fprintf(f, "0x%08X\n", lmx2594regs[i]);
+    lmx_change_freq_regs[0] = lmx2594regs[112 - VCO_SEL];
+    lmx_change_freq_regs[1] = lmx2594regs[112 - CAP_CTRL_START];
+    lmx_change_freq_regs[2] = lmx2594regs[112 - VCO_DACISET];
+    lmx_change_freq_regs[3] = lmx2594regs[112 - PFD_DLY_SEL];
+    lmx_change_freq_regs[4] = lmx2594regs[112 - R4_ADDR];
+    lmx_change_freq_regs[5] = lmx2594regs[112 - R1_ADDR];
+    lmx_change_freq_regs[6] = lmx2594regs[112 - PLL_N_S];
+    lmx_change_freq_regs[7] = lmx2594regs[112 - PLL_N_M];
+    lmx_change_freq_regs[8] = lmx2594regs[112 - CHDIV];
+    lmx_change_freq_regs[9] = lmx2594regs[112 - CHDIV_DIV2];
+    lmx_change_freq_regs[10] = lmx2594regs[112 - OUTA_MUX];
+    lmx_change_freq_regs[11] = lmx2594regs[112 - FCAL_ADDR];
+
+    // // Create a header for the LMX2594 with the appropriate number of words MOSI 4
+    // uint32_t LMX_HEADER = ((0x1<< 23) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | 1);
+    // uint32_t *ptr = bar1 + TMSG_BASE_ADDR;
+    // *ptr = LMX_HEADER;
+    // // Send the data
+    // uint32_t *data_ptr = bar1 + TMSG_BASE_ADDR;
+    // for (int i = 0; i < sizeof(lmx_change_freq_regs) / 4; i++) {
+    //     *data_ptr = lmx_change_freq_regs[i];
     // }
-    // fclose(f);
-    // printf("N_div = %f\n", N_div);
-    // printf("f_vco = %f\n", f_vco);
-    // printf("N = %d\n", N);
-    // printf("chan_div = %d\n", chan_div);
-    // printf("chan_div_reg = %d\n", ch_div_reg);
     return 0;
 }
 
@@ -600,11 +560,6 @@ double lmx_get_freq(double freq) {
 
 int lmx_freq_set(void *bar1, double lmx_freq,double f_pd) {
     // Set the 4 Mosi mode
-    usleep(1);
-    uint32_t cfg_reg = get_cfg_reg();
-    SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI); 
-    uint32_t *spi_mode = bar1 +CFG_REG_ADDR;
-    *spi_mode = cfg_reg;
     // if the frequency is in the main band - 7.5 GHz to 15 GHz
     if (lmx_freq >= 7.5e9 && lmx_freq <= 15e9) {
         // lmx_freq_set_main_band(bar1, freq, f_pd);
@@ -614,11 +569,6 @@ int lmx_freq_set(void *bar1, double lmx_freq,double f_pd) {
         // lmx_freq_set_out_of_band(bar1, freq, f_pd);
         lmx_freq_set_out_of_band_int_mode(bar1, lmx_freq, f_pd);
     }
-    // Return the 1 MOSI mode
-    usleep(1);
-    SET_REGISTER_PARAM(cfg_reg,CFG_REG_SPI_MODE_BITM,CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_1MOSI);
-    *spi_mode = cfg_reg;
-    set_cfg_reg(cfg_reg);
     return 0;
 }
 

Devices/lmx2594.h

@@ -21,12 +21,22 @@ struct vco_params {
     uint16_t acal_cmp_dly;
     uint16_t cal_clk_div;
     uint16_t pfd_dly_sel;
-    uint16_t fcal_hpfd_adj; 
+    uint16_t fcal_hpfd_adj;
+    // LMX parameters
+    double N_div;
+    uint32_t N;
+    int chan_div;
+    uint8_t ch_div_reg;
+    double f_vco;
+
 
 
 };
 
+extern uint32_t lmx_change_freq_regs[12];
+
 void set_vco_params (struct vco_params *params);
+void send_vco_params(void *bar1, struct vco_params *params);
 struct vco_params calculate_vco_params (double lmx_freq, double f_pd);
 
 void lmx2594_init(void *bar1);

Devices/tmsgheaders.c

@@ -7,6 +7,8 @@ uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF		|
 				  CFG_REG_HR_GPIO_0				|
 				  CFG_REG_SPI_MODE_1MOSI;
 
+uint32_t tmsg_shift_reg = SHIFT_REG;
+
  uint32_t tmsgGpioReg = FPGA_AM_CTRL_0			| 
 						DDS_SAW1_FPGA_0			| 
 						GPIO_ADRF_V2_0			|
@@ -47,6 +49,14 @@ void set_tmsg_gpio_reg(uint32_t tmsgGpioRegToSet){
 	tmsgGpioReg = tmsgGpioRegToSet;
 }
 
+uint32_t get_tmsg_shift_reg(){
+	return tmsg_shift_reg;
+}
+
+void set_tmsg_shift_reg(uint32_t tmsgShiftRegToSet){
+	tmsg_shift_reg = tmsgShiftRegToSet;
+}
+
 void rst_for_fpga(void *bar1) {
 	SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
 	uint32_t *ptr = bar1 + CFG_REG_ADDR;
@@ -71,38 +81,71 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		if (freq >= 100e3 && freq <= 1000e6) {
 			if (lmx_freq >= 2750e6 && lmx_freq <= 3600e6) {
 				// Data for Shift Reg
-				*ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_0 | SHIFT_REG_SW2_RF_0 | SHIFT_REG_SW_RF_1;
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_0);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_0);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+				// *ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_0 | SHIFT_REG_SW2_RF_0 | SHIFT_REG_SW_RF_1;
 			}
 			else if (lmx_freq > 3600e6 && lmx_freq <=3999.9e6) {
 				// Data for Shift Reg
-				*ptr = SHIFT_REG_SW1_RF_0 | SHIFT_REG_SW_MIXER_RF_0 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_RF_1;
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_0);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_0);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+				SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+				// *ptr = SHIFT_REG_SW1_RF_0 | SHIFT_REG_SW_MIXER_RF_0 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_RF_1;
 			}
 		}
 		else if (freq > 1000e6 && freq <= 1300e6) {
 		// Data for Shift Reg
-		*ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_SW3_RF_1 | SHIFT_REG_SW_RF_1;
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_1);
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW2_RF_BITM, SHIFT_REG_SW2_RF_BITP, SHIFT_REG_SW2_RF_1);
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_1);
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW3_RF_BITM, SHIFT_REG_SW3_RF_BITP, SHIFT_REG_SW3_RF_1);
+		SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+		// *ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_SW3_RF_1 | SHIFT_REG_SW_RF_1;
 		}
 		else if (freq > 1300e6 && freq <= 2200e6) {
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_1 | SHIFT_REG_SW3_RF_0 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_SW_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW2_RF_BITM, SHIFT_REG_SW2_RF_BITP, SHIFT_REG_SW2_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW3_RF_BITM, SHIFT_REG_SW3_RF_BITP, SHIFT_REG_SW3_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+			// *ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_1 | SHIFT_REG_SW3_RF_0 | SHIFT_REG_GPIO_SW_015_RF_1 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_SW_RF_1;
 		}
 		else if (freq > 2200e6 && freq <= 3600e6) {
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_0 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW2_RF_BITM, SHIFT_REG_SW2_RF_BITP, SHIFT_REG_SW2_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+			// *ptr = SHIFT_REG_SW1_RF_1 | SHIFT_REG_SW2_RF_0 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_1;
 		}
 		else if (freq > 3600e6 && freq <= 5500e6) {
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW1_RF_0 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW1_RF_BITM, SHIFT_REG_SW1_RF_BITP, SHIFT_REG_SW1_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_1);
+			// *ptr = SHIFT_REG_SW1_RF_0 | SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_1;
 		}
 		else if (freq >5500e6 && freq <= 6000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_MIXER_RF_BITM, SHIFT_REG_SW_MIXER_RF_BITP, SHIFT_REG_SW_MIXER_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_1);
+			// *ptr = SHIFT_REG_SW_MIXER_RF_1 | SHIFT_REG_GPIO_SW_015_RF_1  | SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1;
 		}
-		// Header for GPIO_REG 1MOSI
-		*ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
-				(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
-				(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
-				SB_HEADER_TERM_BIT_1;
+		// // Header for GPIO_REG 1MOSI
+		// *ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
+		// 		(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
+		// 		(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
+		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
 		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
@@ -110,57 +153,81 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_0);
 		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_0);
 		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_1);
-		*ptr = tmsgGpioReg;
+		// *ptr = tmsgGpioReg;
 	}
 	else if (freq > 6000e6 && freq <= 27000e6) {
 		if (freq > 6000e6 && freq <= 7500e6){
 		// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 7500e6 && freq <= 9000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 9000e6 && freq <= 15000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 15000e6 && freq <= 18000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 18000e6 && freq <= 22000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if (freq > 22000e6 && freq <= 27000e6){
 			// Data for Shift Regs
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
 		}
 	
-		// Header for GPIO_REG 1MOSI
-		*ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
-				(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
-				(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
-				SB_HEADER_TERM_BIT_1;
+		// // Header for GPIO_REG 1MOSI
+		// *ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
+		// 		(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
+		// 		(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
+		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
 		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
@@ -168,7 +235,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		*ptr = tmsgGpioReg;
+		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
 		ptr = bar1 + CFG_REG_ADDR;
@@ -181,11 +248,19 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		double freq_div2 = freq / 2;
 		if (freq_div2 > 13500e6 && freq_div2 <= 15000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_1);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_1;
 		}
 		else if(freq_div2 > 15000e6 && freq_div2 <= 18000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_1);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_1 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);	// temporary solution. need GPIO_ADRF_V1_1
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
@@ -193,17 +268,21 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		else if (freq_div2 > 18000e6 && freq_div2 <= 18500e6)
 		{
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		
-		// Header for GPIO_REG 1MOSI
-		*ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
-				(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
-				(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
-				SB_HEADER_TERM_BIT_1;
+		// // Header for GPIO_REG 1MOSI
+		// *ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
+		// 		(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
+		// 		(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
+		// 		SB_HEADER_TERM_BIT_1;
 
 		// Data for GPIO_REG
 		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_0);
@@ -211,7 +290,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		*ptr = tmsgGpioReg;
+		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
 		ptr = bar1 + CFG_REG_ADDR;
@@ -224,24 +303,32 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		double freq_div2 = freq / 2;
 		if (freq_div2> 18500e6 && freq_div2 <= 22000e6){
 			// Data for Shift Reg
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_0);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_1);
 		}
 		else if(freq_div2 > 22000e6 && freq_div2 <= 27500e6){
 			// Data for Shift Regs
-			*ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW_RF_BITM, SHIFT_REG_SW_RF_BITP, SHIFT_REG_SW_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_SW4_RF_BITM, SHIFT_REG_SW4_RF_BITP, SHIFT_REG_SW4_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_015_RF_BITM, SHIFT_REG_GPIO_SW_015_RF_BITP, SHIFT_REG_GPIO_SW_015_RF_0);
+			SET_REGISTER_PARAM(tmsg_shift_reg, SHIFT_REG_GPIO_SW_X2_RF_BITM, SHIFT_REG_GPIO_SW_X2_RF_BITP, SHIFT_REG_GPIO_SW_X2_RF_0);
+			// *ptr = SHIFT_REG_SW_RF_0 | SHIFT_REG_SW4_RF_0 | SHIFT_REG_GPIO_SW_015_RF_0 | SHIFT_REG_GPIO_SW_X2_RF_0;
 			// Data for GPIO_REG
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V1_BITM, GPIO_ADRF_V1_BITP, GPIO_ADRF_V1_1);
 			SET_REGISTER_PARAM(tmsgGpioReg, GPIO_ADRF_V2_BITM, GPIO_ADRF_V2_BITP, GPIO_ADRF_V2_0);
 		}
 
 		// Header for GPIO_REG 1MOSI
-		*ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
-				(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
-				(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
-				SB_HEADER_TERM_BIT_1;
+		// *ptr = 	(SB_HEADER_SPI_MODE_1MOSI) | 
+		// 		(DeviceIdGpio1 << SB_HEADER_1MOSI_DEVICE_ID_BITP) | 
+		// 		(1 << SB_HEADER_1MOSI_WORD_NUM_BITP) | 
+		// 		SB_HEADER_TERM_BIT_1;
 		
 		// Data for GPIO_REG
 		SET_REGISTER_PARAM(tmsgGpioReg, RF_SW1_BITM, RF_SW1_BITP, RF_SW1_1);
@@ -249,7 +336,7 @@ void key_switch (void  *bar1, double freq, double lmx_freq) {
 		SET_REGISTER_PARAM(tmsgGpioReg, CTRL_AM_SW3_BITM, CTRL_AM_SW3_BITP, CTRL_AM_SW3_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, FPGA_AM_CTRL_BITM, FPGA_AM_CTRL_BITP, FPGA_AM_CTRL_1);
 		SET_REGISTER_PARAM(tmsgGpioReg, AM_ALC_SW_BITM, AM_ALC_SW_BITP, AM_ALC_SW_0);
-		*ptr = tmsgGpioReg;
+		// *ptr = tmsgGpioReg;
 
 		// Addr CFG_REG
 		ptr = bar1 + CFG_REG_ADDR;

Devices/tmsgheaders.h

@@ -3,6 +3,9 @@
 #include <stdint.h>
 #include <unistd.h>
 #include <stdio.h>
+
+// Device address 
+#define     TMSG_BASE_ADDR              0x04
 // Device IDs
 #define DeviceIdLmx2594                 0x0
 #define DeviceIdDDS                     0x1
@@ -117,6 +120,11 @@
 #define ENUM_SPIMODE_1MOSI          (0x0 << BITP_SPIMODE_4MOSI_HEADER)
 // SpiMode 4MOSI
 #define ENUM_SPIMODE_4MOSI          (0x1 << BITP_SPIMODE_4MOSI_HEADER)
+// Term Bit
+#define BITP_TERM_BIT               0
+#define BITM_TERM_BIT               (0x1 << BITP_TERM_BIT)
+#define TERM_BIT_0                  (0x0 << BITP_TERM_BIT)
+#define TERM_BIT_1                  (0x1 << BITP_TERM_BIT)
 
 // Word Numbers 4-MOSI
 #define LMXWordNum              14
@@ -265,6 +273,17 @@
 #define SHIFT_REG_SW2_RF_BITP               6
 #define SHIFT_REG_SW3_RF_BITP               7
 
+// Bit masks
+#define SHIFT_REG_SW_RF_BITM                (0x1 << SHIFT_REG_SW_RF_BITP)
+#define SHIFT_REG_SW4_RF_BITM               (0x1 << SHIFT_REG_SW4_RF_BITP)
+#define SHIFT_REG_GPIO_SW_015_RF_BITM       (0x1 << SHIFT_REG_GPIO_SW_015_RF_BITP)
+#define SHIFT_REG_GPIO_SW_X2_RF_BITM        (0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP)
+#define SHIFT_REG_SW_MIXER_RF_BITM          (0x1 << SHIFT_REG_SW_MIXER_RF_BITP)
+#define SHIFT_REG_SW1_RF_BITM               (0x1 << SHIFT_REG_SW1_RF_BITP)
+#define SHIFT_REG_SW2_RF_BITM               (0x1 << SHIFT_REG_SW2_RF_BITP)
+#define SHIFT_REG_SW3_RF_BITM               (0x1 << SHIFT_REG_SW3_RF_BITP)
+
+
 #define SHIFT_REG_GPIO_SW_X2_RF_0		(0x0 << SHIFT_REG_GPIO_SW_X2_RF_BITP)
 #define SHIFT_REG_GPIO_SW_X2_RF_1		(0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP)
 #define SHIFT_REG_SW_RF_0				(0x0 << SHIFT_REG_SW_RF_BITP)
@@ -364,4 +383,10 @@ void key_switch (void  *bar1, double freq,double lmx_freq);
 uint32_t get_cfg_reg();
 void set_cfg_reg(uint32_t cfgRegToSet);
 
+uint32_t get_tmsg_gpio_reg();
+void set_tmsg_gpio_reg(uint32_t tmsgGpioRegToSet);
+
+uint32_t get_tmsg_shift_reg();
+void set_tmsg_shift_reg(uint32_t tmsgShiftRegToSet);
+
 #endif //DMADRIVER_TMSGHEADERS_H

command.c

@@ -37,7 +37,10 @@ void handleFreqCmd(const char* recvBuff)
 	double lmx_freq = 0;
 
 	splitLexeme(recvBuff, freq, sizeof(freq[0]), convertToDouble);
-
+    uint32_t cfg_reg = get_cfg_reg();
+    SET_REGISTER_PARAM(cfg_reg, CFG_REG_SPI_MODE_BITM, CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_4MOSI); 
+    uint32_t *spi_mode = bar1 +CFG_REG_ADDR;
+    *spi_mode = cfg_reg;
 	lmx_freq = lmx_get_freq(freq[0]);
 	f_pd = ad9912_set(bar1, lmx_freq, f_pd);
 	printf("f_pd frequency is set to %.6f MHz\n", f_pd/1e6);
@@ -45,8 +48,37 @@ void handleFreqCmd(const char* recvBuff)
 	// Switch the keys 
 	key_switch(bar1, freq[0],lmx_freq);
     printf("The frequency is set to %.2f MHz\n", freq[0]/1e6);
+	// Send the data 
+	send_data_qspi(bar1);
+	   // Return the 1 MOSI mode
+    usleep(1);
+    SET_REGISTER_PARAM(cfg_reg,CFG_REG_SPI_MODE_BITM,CFG_REG_SPI_MODE_BITP, CFG_REG_SPI_MODE_1MOSI);
+    *spi_mode = cfg_reg;
+    set_cfg_reg(cfg_reg);
 	
 }
+void send_data_qspi(void *bar1) {
+	// get the gpio reg and shift reg data 
+	uint32_t gpio_reg = get_tmsg_gpio_reg();
+	uint32_t shift_reg = get_tmsg_shift_reg();
+	// Create a header 4 Mosi mode
+	uint32_t qspi_header = ((ENUM_SPIMODE_4MOSI) |(0x1 << BITP_GPIO_4MOSI_HEADER) |(0x1 << BITP_SHIFT_REG_4MOSI_HEADER )| ((sizeof(ad9912_ftw_regs_qspi) / 4) << BITP_DDS_4MOSI_HEADER) | ((sizeof(lmx_change_freq_regs) / 4) << BITP_LMX2594_4MOSI_HEADER) | TERM_BIT_1);
+	uint32_t *data = bar1 + LMX_BASE_ADDR;
+	*data = qspi_header;
+	// Initialize the registers
+	// Send the data for AD9912
+	for (int i = 0; i < sizeof(ad9912_ftw_regs_qspi) / 4; i++) {
+		*data = ad9912_ftw_regs_qspi[i];
+	}
+	// Send the data for the GPIO
+	*data = gpio_reg;
+	// Send the data for LMX2594
+	for (int i = 0; i < sizeof(lmx_change_freq_regs) / 4; i++) {
+		*data = lmx_change_freq_regs[i];
+	}
+	// Send the data for the shift register
+	*data = shift_reg;
+}
 
 void handleLdCmd(const char* recvBuff)
 {

command.h

@@ -29,6 +29,7 @@ typedef struct {
 typedef void (*ConvertFunc)(const char *str, void *output);
 
 // Прототипы функций
+void send_data_qspi(void *bar1);
 void handleCloseSignal(int signal);
 void handleFreqCmd(const char* recvBuff);
 void handleLdCmd(const char* recvBuff);