Исправлен порядок следования

Devices/ad9912.c

@@ -231,10 +231,10 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     //     ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40]
     // };
     // First 16 bits is the instruction word
-    ad9912_ftw_regs_qspi[0] = (0x00 << BITP_AD9912_QSPI_PHASE_13_8);
-    ad9912_ftw_regs_qspi[1] = (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0);
-    ad9912_ftw_regs_qspi[2] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24);
-    ad9912_ftw_regs_qspi[3] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
+    ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12);
+    ad9912_ftw_regs_qspi[1] = (ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8 | (ftw0_7_0 << BITP_AD9912_QSPI_7_0) | (ftw0_15_8 << BITP_AD9912_QSPI_15_8));
+    ad9912_ftw_regs_qspi[2] = ((ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32));
+    ad9912_ftw_regs_qspi[3] = ((ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0) | (0x00 << BITP_AD9912_QSPI_PHASE_13_8));
     // // Create the appropriate header
     // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
     // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);

Devices/ad9912.h

@@ -71,61 +71,66 @@
 *********************************************************************************/
 #define BITP_AD9912_INSTRUCTION_WORD_15_0                           0
 #define BITM_AD9912_INSTRUCTION_WORD_15_0                           (0xFFFF << BITP_AD9912_INSTRUCTION_WORD_15_0)
-#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE                     23
+#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE                     7
 #define BITM_AD9912_INSTRUCTION_WORD_READ_WRITE                     (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 #define ENUM_AD9912_INSTRUCTION_WORD_WRITE                          (0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 #define ENUM_AD9912_INSTRUCTION_WORD_READ                           (0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
 
-#define BITP_AD9912_INSTRUCTION_WORD_LENGTH                         21
+#define BITP_AD9912_INSTRUCTION_WORD_LENGTH                         5
 #define BITM_AD9912_INSTRUCTION_WORD_LENGTH                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 #define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1                       (0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 #define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2                       (0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 #define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3                       (0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 #define ENUM_AD9912_INSTRUCTION_WORD_STREAM                         (0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
 
-#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS                        8
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        16
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8                        (0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       0
+#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12                       (0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 //Addr[12:0]
 #define BITM_AD9912_INSTRUCTION_WORD_ADDRESS                        (0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
 #define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR                      (0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8                 (0xA6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
+#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12                (0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
 /**********************************************************************************
- * 										QSPI_FTW[7:0]
+ * 										QSPI_FTW[7:0][15:8]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_7_0                                        0
+#define BITP_AD9912_QSPI_7_0                                        8
 #define BITM_AD9912_QSPI_7_0                                        (0xFF << BITP_AD9912_QSPI_7_0)
 /**********************************************************************************
- * 										QSPI_FTW[15:8]
+ * 										QSPI_FTW[15:8][7:0]
 *********************************************************************************/
 #define BITP_AD9912_QSPI_15_8                                       0
 #define BITM_AD9912_QSPI_15_8                                       (0xFF << BITP_AD9912_QSPI_15_8)
 /**********************************************************************************
  * 										QSPI_FTW[23:16]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_23_16                                      8
+#define BITP_AD9912_QSPI_23_16                                      0
 #define BITM_AD9912_QSPI_23_16                                      (0xFF << BITP_AD9912_QSPI_23_16)
 /**********************************************************************************
  * 										QSPI_FTW[31:24]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_31_24                                      16
+#define BITP_AD9912_QSPI_31_24                                      8
 #define BITM_AD9912_QSPI_31_24                                      (0xFF << BITP_AD9912_QSPI_31_24)
 /**********************************************************************************
  * 										QSPI_FTW[39:32]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_39_32                                      0
+#define BITP_AD9912_QSPI_39_32                                      16
 #define BITM_AD9912_QSPI_39_32                                      (0xFF << BITP_AD9912_QSPI_39_32)
 /**********************************************************************************
  * 										QSPI_FTW[47:40]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_47_40                                      8
+#define BITP_AD9912_QSPI_47_40                                      0
 #define BITM_AD9912_QSPI_47_40                                      (0xFF << BITP_AD9912_QSPI_47_40)
 /**********************************************************************************
  * 										QSPI_PHASE[7:0]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_PHASE_7_0                                  16
+#define BITP_AD9912_QSPI_PHASE_7_0                                  8
 #define BITM_AD9912_QSPI_PHASE_7_0                                  (0xFF << BITP_AD9912_QSPI_PHASE_7_0)
 /**********************************************************************************
  * 										QSPI_PHASE[13:8]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_PHASE_13_8                                 0
+#define BITP_AD9912_QSPI_PHASE_13_8                                 16
 #define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)
 
 extern uint32_t ad9912_ftw_regs_qspi[4];