Добавлен перевод CPG в режим tri-state на период отгрузок

Devices/lmx2594.c

@@ -254,7 +254,6 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
     printf("VCO_CORE = %d\n", vco_core);
     printf("VCO_CAP_CTRL_STR = %d\n", vco_cap_ctrl_strt);
     printf("VCO_DACISET_STR = %d\n", vco_daciset_strt);
-
     // Calibration assist 
     //Set the VCO_CORE 
     lmx2594regs[112 - VCO_SEL] = lmx2594regs[112 - VCO_SEL] & (~BITM_LMX2594_R20_VCO_SEL);
@@ -316,6 +315,7 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
     // Show the all the upper 16 bits of the register lmx2594regs[PLL_N_S]
     // Determine which regs are changed and send only those
     uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_TRISTATE,
             lmx2594regs[112 - VCO_SEL],
             lmx2594regs[112 - CAP_CTRL_START],
             lmx2594regs[112 - VCO_DACISET],
@@ -330,6 +330,7 @@ int lmx_freq_set_main_band(void *bar1, double freq, double f_pd) {
             lmx2594regs[112 - CHDIV],
             lmx2594regs[112 - CHDIV_DIV2],
             lmx2594regs[112-OUTA_MUX],
+            lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_15ma,
             lmx2594regs[112-FCAL_ADDR]
     };
     // Create a header for the LMX2594 with the appropriate number of words
@@ -668,6 +669,7 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
     lmx2594regs[112 - FCAL_ADDR] = lmx2594regs[112 - FCAL_ADDR] | (LMX2594_R0_FCAL_EN);
 
     uint32_t lmx_change_freq_regs[] = {
+            lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_TRISTATE,
             lmx2594regs[112 - VCO_SEL],
             lmx2594regs[112 - CAP_CTRL_START],
             lmx2594regs[112 - VCO_DACISET],
@@ -682,6 +684,7 @@ int lmx_freq_set_out_of_band(void *bar1, double freq, double f_pd) {
             lmx2594regs[112 - CHDIV],
             lmx2594regs[112 - CHDIV_DIV2],
             lmx2594regs[112 - OUTA_MUX],
+            lmx2594regs[112-CPG_REG] = (lmx2594regs[112-CPG_REG] & (~BITM_LMX2594_R14_CPG)) | ENUM_LMX2594_R14_CPG_15ma,
             lmx2594regs[112 - FCAL_ADDR]
     };
     // Create a header for the LMX2594 with the appropriate number of words

Devices/lmx2594regs.h

@@ -9,26 +9,24 @@
 #define     PLL_NUM_M                                   0x2B
 #define     OUTA_MUX                                    0x2D
 
-
 //R78
 #define     CAP_CTRL_START                              0x4E
 // R75
 #define     CHDIV                                       0x4B
 // R31
 #define     CHDIV_DIV2                                  0x1F
-
 // R44
 #define     MASH_ORDER                                  0x2C
 // R37
 #define     PFD_DLY_SEL                                 0x25
-
 //R20
 #define     VCO_SEL                                     0x14
 //R19
 #define     VCO_CAP_CTRL                                0x13
 //R17
 #define     VCO_DACISET                                 0x11
-
+//R14
+#define     CPG_REG                                     0xD
 //R0
 #define     FCAL_ADDR                                   0x00
 
@@ -102,7 +100,13 @@
 #define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
 #define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
 #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
-
+/**********************************************************************************
+ * 										R14
+ *********************************************************************************/
+#define BITP_LMX2594_R14_CPG                            4
+#define BITM_LMX2594_R14_CPG                            (0x7 <<BITP_LMX2594_R14_CPG)
+#define ENUM_LMX2594_R14_CPG_TRISTATE                   (0x0<<BITP_LMX2594_R14_CPG)
+#define ENUM_LMX2594_R14_CPG_15ma                       (0x7<<BITP_LMX2594_R14_CPG)
 /**********************************************************************************
  * 										R1
  *********************************************************************************/
@@ -111,7 +115,7 @@
  * 										R0
  *********************************************************************************/
 
-#define BITP_LMX2594_R0_FCAL                            4
+#define BITP_LMX2594_R0_FCAL                            3
 #define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
 /*********************************************************************************/