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Devices/ad9912.c

@@ -40,7 +40,7 @@
         0x050800,
         0x050900
 };
-uint32_t ad9912_ftw_regs_qspi[3];
+uint32_t ad9912_ftw_regs_qspi[4];
 /*-------------------------AD9912 INIT FUNCTION-------------------------*/
 void ad9912_init(void *bar1) {
     uint32_t *ptr_rst = bar1 + TMSG_BASE_ADDR;
@@ -232,8 +232,9 @@ double ad9912_set(void *bar1, double freq, double f_pd) {
     // };
     // First 16 bits is the instruction word
     ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
-    ad9912_ftw_regs_qspi[1] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32);
-    ad9912_ftw_regs_qspi[2] = (ftw1_47_40 << BITP_AD9912_QSPI_47_40);
+    ad9912_ftw_regs_qspi[1] = (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24);
+    ad9912_ftw_regs_qspi[2] = (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0);
+    ad9912_ftw_regs_qspi[3] = (0x00 << BITP_AD9912_QSPI_PHASE_13_8);
     // // Create the appropriate header
     // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
     // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);

Devices/ad9912.h

@@ -110,16 +110,25 @@
 /**********************************************************************************
  * 										QSPI_FTW[39:32]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_39_32                                      24
+#define BITP_AD9912_QSPI_39_32                                      0
 #define BITM_AD9912_QSPI_39_32                                      (0xFF << BITP_AD9912_QSPI_39_32)
 /**********************************************************************************
  * 										QSPI_FTW[47:40]
 *********************************************************************************/
-#define BITP_AD9912_QSPI_47_40                                      0
+#define BITP_AD9912_QSPI_47_40                                      8
 #define BITM_AD9912_QSPI_47_40                                      (0xFF << BITP_AD9912_QSPI_47_40)
+/**********************************************************************************
+ * 										QSPI_PHASE[7:0]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_PHASE_7_0                                  16
+#define BITM_AD9912_QSPI_PHASE_7_0                                  (0xFF << BITP_AD9912_QSPI_PHASE_7_0)
+/**********************************************************************************
+ * 										QSPI_PHASE[13:8]
+*********************************************************************************/
+#define BITP_AD9912_QSPI_PHASE_13_8                                 0
+#define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)
 
-
-extern uint32_t ad9912_ftw_regs_qspi[3];
+extern uint32_t ad9912_ftw_regs_qspi[4];
 void ad9912_init(void *bar1);
 double ad9912_set(void *bar1, double freq, double f_pd);
 double ad9912_set_out_of_band(double freq,double f_pd);