#ifndef DMADRIVER_AD9912_H
#define DMADRIVER_AD9912_H

#include "tmsgheaders.h"

#define     AD9912_COUNT        37
#define     AD9912_BASE_ADDR    0x04

#define AD9912_RST_ON ((DDS_SAW1_FPGA << 21) | \
                  (GPIO_ADRF_V2 << 20) | \
                  (GPIO_ADRF_V1 << 19) | \
                  (REF_OFFSET_CTRL_FPGA << 18) | \
                  (DDS_SAW2_FPGA << 17) | \
                  (DDS_X2_FPGA << 16) | \
                  (PLL_LOOP_CTRL << 15) | \
                  (PLL_SYNC << 14) | \
                  (PLL_SYNC_CTRL << 13) | \
                  (PLL_VTUNE_CTRL << 12) | \
                  (AM_ALC_1_FIX << 11) | \
                  (SW_CAP1 << 10) | \
                  (SW_CAP2 << 9) | \
                  (SW_CAP3 << 8) | \
                  (AM_ALC_SW << 7) | \
                  (SW_CAP4 << 6) | \
                  (DDS_SYNC_FPGA << 5) | \
                  (0x1 << 4) | \
                  (DDS_SYNC_CTRL_FPGA << 3) | \
                  (CTRL_AM_SW3 << 2) | \
                  (RF_SW2 << 1) | \
                  (RF_SW1 << 0))

/**********************************************************************************
 * 										FTW0[7:0]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_7_0                        0
#define BITM_AD9912_FTW0_FREQ_WORD_7_0                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
#define REGP_AD9912_FTW0_FREQ_WORD_7_0                         0xE
/**********************************************************************************
 * 										FTW0[15:8]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_15_8                        0
#define BITM_AD9912_FTW0_FREQ_WORD_15_8                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
#define REGP_AD9912_FTW0_FREQ_WORD_15_8                         0xF
/**********************************************************************************
 * 										FTW0[23:16]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_23_16                        0
#define BITM_AD9912_FTW0_FREQ_WORD_23_16                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
#define REGP_AD9912_FTW0_FREQ_WORD_23_16                         0x10
/**********************************************************************************
 * 										FTW0[31:24]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_31_24                        0
#define BITM_AD9912_FTW0_FREQ_WORD_31_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
#define REGP_AD9912_FTW0_FREQ_WORD_31_24                         0x11
/**********************************************************************************
 * 										FTW0[39:32]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_39_24                        0
#define BITM_AD9912_FTW0_FREQ_WORD_39_24                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
#define REGP_AD9912_FTW0_FREQ_WORD_39_24                         0x12
/**********************************************************************************
 * 										FTW0[47:40]
*********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_47_40                        0
#define BITM_AD9912_FTW0_FREQ_WORD_47_40                        (0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
#define REGP_AD9912_FTW0_FREQ_WORD_47_40                         0x13


/*----------------------------------------------------------------------*/
void ad9912_init(void *bar1);
double ad9912_set(void *bar1, double freq, double f_pd);
double ad9912_set_out_of_band(double freq,double f_pd); 
double ad9912_set_main_band(double freq,double f_pd);
#endif //DMADRIVER_AD9912_H