#ifndef DMADRIVER_LMK2594REGS_H #define DMADRIVER_LMK2594REGS_H #define PLL_N_S 0x22 #define PLL_N_M 0x24 #define PLL_DEN_S 0x26 #define PLL_DEN_M 0x27 #define PLL_NUM_S 0x2A #define PLL_NUM_M 0x2B #define OUTA_MUX 0x2D // R75 #define CHDIV 0x4B // R31 #define CHDIV_DIV2 0x1F // R44 #define MASH_ORDER 0x2C // R37 #define PFD_DLY_SEL 0x25 #define FCAL_ADDR 0x00 //BIT POSITIONS AND MASKS /********************************************************************************** * R37 *********************************************************************************/ #define BITP_LMX2594_R37_PFD_DLY_SEL 8 // Length 6 bits #define BITM_LMX2594_R37_PFD_DLY_SEL (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL) /********************************************************************************** * R44 *********************************************************************************/ #define BITP_LMX2594_R44_MASH_ORDER 0 #define BITM_LMX2594_R44_MASH_ORDER (0x07 << BITP_LMX2594_R44_MASH_ORDER) #define ENUM_LMX2594_R44_MASH_ORDER_INTEGER (0x00 << BITP_LMX2594_R44_MASH_ORDER) #define ENUM_LMX2594_R44_MASH_ORDER_1 (0x01 << BITP_LMX2594_R44_MASH_ORDER) #define ENUM_LMX2594_R44_MASH_ORDER_2 (0x02 << BITP_LMX2594_R44_MASH_ORDER) #define ENUM_LMX2594_R44_MASH_ORDER_3 (0x03 << BITP_LMX2594_R44_MASH_ORDER) #define ENUM_LMX2594_R44_MASH_ORDER_4 (0x04 << BITP_LMX2594_R44_MASH_ORDER) /********************************************************************************** * R45 *********************************************************************************/ #define BITP_LMX2594_R45_OUTA_MUX 11 #define BITM_LMX2594_R45_OUTA_MUX (0x03 << BITP_LMX2594_R45_OUTA_MUX) #define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV (0x00 << BITP_LMX2594_R45_OUTA_MUX) #define ENUM_LMX2594_R45_OUTA_MUX_VCO (0x01 << BITP_LMX2594_R45_OUTA_MUX) #define ENUM_LMX2594_R45_DEFAULT_VAL 0x01 /*********************************************************************************/ /********************************************************************************** * R75 *********************************************************************************/ #define BITP_LMX2594_R75_CHDIV 6 #define BITM_LMX2594_R75_CHDIV (0x3F << BITP_LMX2594_R75_CHDIV) /*********************************************************************************/ /********************************************************************************** * R31 *********************************************************************************/ #define BITP_LMX2594_R31_CHDIV_DIV2 14 #define BITM_LMX2594_R31_CHDIV_DIV2 (0x01 << BITP_LMX2594_R31_CHDIV_DIV2) #define ENUM_LMX2594_R31_CHDIV_DIV2_EN (0x01 << BITP_LMX2594_R31_CHDIV_DIV2) #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS (0x00 << BITP_LMX2594_R31_CHDIV_DIV2) /********************************************************************************** * R0 *********************************************************************************/ #define BITP_LMX2594_R0_FCAL 4 #define LMX2594_R0_FCAL_EN (0x01 << BITP_LMX2594_R0_FCAL) /*********************************************************************************/ #endif //DMADRIVER_LMK2594REGS_H