#include "tmsgheaders.h"

uint32_t cfgReg = CFG_REG_RST_FOR_FPGA_OFF |
                  CFG_REG_WIDTH_SPI_TMSG_24_BIT |
                  CFG_REG_MOD_1 |  
                  CFG_REG_LR_GPIO_0 |
                  CFG_REG_HR_GPIO_0;

uint32_t get_cfg_reg(){
    return cfgReg;
}

void set_cfg_reg(uint32_t cfgRegToSet){
    cfgReg = cfgRegToSet;
}

void rst_for_fpga(void *bar1) {
    SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_ON);
    uint32_t *ptr = bar1 + CFG_REG_ADDR;
    *ptr = cfgReg;
    usleep(1);
    SET_REGISTER_PARAM(cfgReg, CFG_REG_RST_FOR_FPGA_BITM, CFG_REG_RST_FOR_FPGA_BITP, CFG_REG_RST_FOR_FPGA_OFF);
    *ptr = cfgReg;
}

void shift_reg (void  *bar1) {
    uint32_t *ptr = bar1 + LMX_BASE_ADDR;
    *ptr = InitShRegHeader;
    uint32_t *data_ptr = bar1 + LMX_BASE_ADDR ;
    *data_ptr = SHIFT_REG;
}

void key_switch (void  *bar1, double freq, double lmx_freq) {
    if (freq >= 100e3 && freq <= 1000e6) {
        if (lmx_freq >= 2750e6 && lmx_freq <= 3600e6) {
             uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
            *ptr_header = InitShRegHeader;
            // Data for Shift Reg
            uint32_t *ptr = bar1 + LMX_BASE_ADDR;
            *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP|0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x0<<SHIFT_REG_SW_MIXER_RF_BITP | 0x0<<SHIFT_REG_SW2_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
        }
        else if (lmx_freq > 3600e6 && lmx_freq <=3999.9e6) {
            uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
            *ptr_header = InitShRegHeader;
            // Data for Shift Reg
            uint32_t *ptr = bar1 + LMX_BASE_ADDR;
            *ptr = 0x0<<SHIFT_REG_SW1_RF_BITP | 0x0 <<SHIFT_REG_SW_MIXER_RF_BITP | 0x1 <<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
        }
    }
    else if (freq > 1000e6 && freq <= 1300e6) {
        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
        *ptr_header = InitShRegHeader;
        // Data for Shift Reg
        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_SW3_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
    }
    else if (freq > 1300e6 && freq <= 2200e6) {
        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
        *ptr_header = InitShRegHeader;
        // Data for Shift Reg
        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW2_RF_BITP | 0x0<<SHIFT_REG_SW3_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1 << SHIFT_REG_SW_RF_BITP;
    }
    else if (freq > 2200e6 && freq <= 3600e6) {
        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
        *ptr_header = InitShRegHeader;
        // Data for Shift Reg
        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
        *ptr = 0x1<<SHIFT_REG_SW1_RF_BITP | 0x0 <<SHIFT_REG_SW2_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
    }
    else if (freq > 3600e6 && freq <= 5500e6) {
        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
        *ptr_header = InitShRegHeader;
        // Data for Shift Reg
        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
        *ptr = 0x0<<SHIFT_REG_SW1_RF_BITP | 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x1 << SHIFT_REG_SW_RF_BITP;
    }
    else if (freq >5500e6 && freq <= 9000e6){
        uint32_t *ptr_header = bar1 + LMX_BASE_ADDR;
        *ptr_header = InitShRegHeader;
        // Data for Shift Reg
        uint32_t *ptr = bar1 + LMX_BASE_ADDR;
        *ptr = 0x1<<SHIFT_REG_SW_MIXER_RF_BITP | 0x1<<SHIFT_REG_GPIO_SW_015_RF_BITP  | 0x0 << SHIFT_REG_SW_RF_BITP;
    }
};