#ifndef DMADRIVER_TMSGHEADERS_H #define DMADRIVER_TMSGHEADERS_H #include #include #include #include "pci.h" // Device address #define TMSG_BASE_ADDR 0x04 // Device IDs #define DeviceIdLmx2594 0x0 #define DeviceIdDDS 0x1 #define DeviceIdPot 0x2 #define DeviceIdDac 0x3 #define DeviceIdAtt 0x4 #define DeviceIdShReg 0x5 #define DeviceIdMax2870 0x6 #define DeviceIdGpio1 0x7 #define DeviceIdTemp 0x8 #define DeviceIdGpio2 0x9 #define SB_HEADER_TERM_BIT_BITP 0 #define SB_HEADER_1MOSI_WORD_NUM_BITP 1 #define SB_HEADER_1MOSI_DEVICE_ID_BITP 18 #define SB_HEADER_SPI_MODE_BITP 23 #define SB_HEADER_TERM_BIT_0 (0x0 << SB_HEADER_TERM_BIT_BITP) #define SB_HEADER_TERM_BIT_1 (0x1 << SB_HEADER_TERM_BIT_BITP) #define SB_HEADER_SPI_MODE_1MOSI (0x0 << SB_HEADER_SPI_MODE_BITP) #define SB_HEADER_SPI_MODE_4MOSI (0x1 << SB_HEADER_SPI_MODE_BITP) // Init Word Numbers 1 MOSI #define Gpio1InitWordNum 2 #define Gpio2InitWordNum 1 #define PotWordInitNum 1 #define DacWordInitNum 1 #define AttWordInitNum 1 #define ShRegWordInitNum 1 #define Lmx2594InitWordNum 113 #define DDSInitWordNum 37 #define MaxInitWordNum 6 #define TempSensWordNum 1 // Bit Positions #define RF_SW1_BITP 0 #define RF_SW2_BITP 1 #define CTRL_AM_SW3_BITP 2 #define DDS_SYNC_CTRL_FPGA_BITP 3 #define DDS_RESET_FPGA_BITP 4 #define DDS_SYNC_FPGA_BITP 5 #define SW_CAP4_BITP 6 #define AM_ALC_SW_BITP 7 #define SW_CAP3_BITP 8 #define SW_CAP2_BITP 9 #define SW_CAP1_BITP 10 #define AM_ALC_1_FIX_BITP 11 #define PLL_VTUNE_CTRL_BITP 12 #define PLL_SYNC_CTRL_BITP 13 #define PLL_SYNC_BITP 14 #define PLL_LOOP_CTRL_BITP 15 #define DDS_X2_FPGA_BITP 16 #define DDS_SAW2_FPGA_BITP 17 #define REF_OFFSET_CTRL_FPGA_BITP 18 #define GPIO_ADRF_V1_BITP 19 #define GPIO_ADRF_V2_BITP 20 #define DDS_SAW1_FPGA_BITP 21 // Headers 1-MOSI #define LMX2594_RST_HEADER ((0 << 23) | (DeviceIdLmx2594 << 18) | (2 << 1) | 1) #define INIT_GPIO1_HEADER ((0 << 23) | (DeviceIdGpio1 << 18) | (Gpio1InitWordNum << 1) | 1) #define INIT_GPIO2_HEADER ((0 << 23) | (DeviceIdGpio2 << 18) | (Gpio2InitWordNum << 1) | 1) #define TEMP_SENS_HEADER ((0 << 23) | (DeviceIdTemp << 18) | (TempSensWordNum << 1) | 1) #define INIT_LMX2594_HEADER ((0 << 23) | (DeviceIdLmx2594 << 18) | (Lmx2594InitWordNum << 1) | 1) #define INIT_DDS_HEADER ((0 << 23) | (DeviceIdDDS << 18) | (DDSInitWordNum << 1) | 1) #define INIT_MAX2870_HEADER ((0 << 23) | (DeviceIdMax2870 << 18) | (MaxInitWordNum << 1) | 1) #define INIT_POT_HEADER ((0 << 23) | (DeviceIdPot << 18) | (PotWordInitNum << 1) | 1) #define INIT_DAC_HEADER ((0 << 23) | (DeviceIdDac << 18) | (DacWordInitNum << 1) | 1) #define INIT_ATT_HEADER ((0 << 23) | (DeviceIdAtt << 18) | (AttWordInitNum << 1) | 1) #define INIT_SH_REG_HEADER ((0 << 23) | (DeviceIdShReg << 18) | (ShRegWordInitNum << 1) | 1) // Headers 4-Mosi #define BITP_LMX2594_4MOSI_HEADER 12 //Bit mask [15:12] #define BITM_LMX2594_4MOSI_HEADER (0xF << BITP_LMX2594_4MOSI_HEADER) #define BITP_DDS_4MOSI_HEADER 19 //Bit mask [21:19] #define BITM_DDS_4MOSI_HEADER (0x7 << BITP_DDS_4MOSI_HEADER) // MAX2870 #define BITP_MAX2870_4MOSI_HEADER 9 //Bit mask [10:9] #define BITM_MAX2870_4MOSI_HEADER (0x3 << BITP_MAX2870_4MOSI_HEADER) //Shift Reg #define BITP_SHIFT_REG_4MOSI_HEADER 6 //Bit mask [7:6] #define BITM_SHIFT_REG_4MOSI_HEADER (0x3 << BITP_SHIFT_REG_4MOSI_HEADER) // GPIO #define BITP_GPIO_4MOSI_HEADER 16 //Bit mask [17:16] #define BITM_GPIO_4MOSI_HEADER (0x3 << BITP_GPIO_4MOSI_HEADER) // POT #define BITP_POT_4MOSI_HEADER 3 //Bit mask [4:3] #define BITM_POT_4MOSI_HEADER (0x3 << BITP_POT_4MOSI_HEADER) // DAC #define BITP_DAC_4MOSI_HEADER 2 //Bit mask [2:2] #define BITM_DAC_4MOSI_HEADER (0x1 << BITP_DAC_4MOSI_HEADER) // ATT #define BITP_ATT_4MOSI_HEADER 1 //Bit mask [1:1] #define BITM_ATT_4MOSI_HEADER (0x1 << BITP_ATT_4MOSI_HEADER) // SpiMode #define BITP_SPIMODE_4MOSI_HEADER 23 //Bit mask [23:23] #define BITM_SPIMODE_4MOSI_HEADER (0x1 << BITP_SPIMODE_4MOSI_HEADER) // SpiMode 1MOSI #define ENUM_SPIMODE_1MOSI (0x0 << BITP_SPIMODE_4MOSI_HEADER) // SpiMode 4MOSI #define ENUM_SPIMODE_4MOSI (0x1 << BITP_SPIMODE_4MOSI_HEADER) // Term Bit #define BITP_TERM_BIT 0 #define BITM_TERM_BIT (0x1 << BITP_TERM_BIT) #define TERM_BIT_0 (0x0 << BITP_TERM_BIT) #define TERM_BIT_1 (0x1 << BITP_TERM_BIT) // Word Numbers 4-MOSI #define LMXWordNum 14 #define DDSWordNum 4 #define POTWordNum 2 #define DACWordNum 1 #define ATTWordNum 1 #define ShRegWordNum 1 #define MaxWordNum 2 #define GPIOWordNum 1 // Define bit values for GPIO Reg #define RF_SW1 0x0 #define RF_SW2 0x0 #define CTRL_AM_SW3 0x0 #define DDS_SYNC_CTRL_FPGA 0x0 #define DDS_RESET_FPGA 0x0 #define DDS_SYNC_FPGA 0x0 #define SW_CAP4 0x0 #define AM_ALC_SW 0x1 #define SW_CAP3 0x0 #define SW_CAP2 0x0 #define SW_CAP1 0x0 #define AM_ALC_1_FIX 0x1 #define PLL_VTUNE_CTRL 0x1 #define PLL_SYNC_CTRL 0x0 #define PLL_SYNC 0x0 #define PLL_LOOP_CTRL 0x1 #define DDS_X2_FPGA 0x0 #define DDS_SAW2_FPGA 0x0 #define REF_OFFSET_CTRL_FPGA 0x1 #define GPIO_ADRF_V1 0x0 #define GPIO_ADRF_V2 0x0 #define DDS_SAW1_FPGA 0x0 #define FPGA_AM_CTRL 0x0 #define RF_SW1_BITP 0 #define RF_SW2_BITP 1 #define CTRL_AM_SW3_BITP 2 #define DDS_SYNC_CTRL_FPGA_BITP 3 #define DDS_RESET_FPGA_BITP 4 #define DDS_SYNC_FPGA_BITP 5 #define SW_CAP4_BITP 6 #define AM_ALC_SW_BITP 7 #define SW_CAP3_BITP 8 #define SW_CAP2_BITP 9 #define SW_CAP1_BITP 10 #define AM_ALC_1_FIX_BITP 11 #define PLL_VTUNE_CTRL_BITP 12 #define PLL_SYNC_CTRL_BITP 13 #define PLL_SYNC_BITP 14 #define PLL_LOOP_CTRL_BITP 15 #define DDS_X2_FPGA_BITP 16 #define DDS_SAW2_FPGA_BITP 17 #define REF_OFFSET_CTRL_FPGA_BITP 18 #define GPIO_ADRF_V1_BITP 19 #define GPIO_ADRF_V2_BITP 20 #define DDS_SAW1_FPGA_BITP 21 #define FPGA_AM_CTRL_BITP 22 #define RF_SW1_BITM (0x1 << RF_SW1_BITP ) #define RF_SW2_BITM (0x1 << RF_SW2_BITP ) #define CTRL_AM_SW3_BITM (0x1 << CTRL_AM_SW3_BITP ) #define DDS_SYNC_CTRL_FPGA_BITM (0x1 << DDS_SYNC_CTRL_FPGA_BITP ) #define DDS_RESET_FPGA_BITM (0x1 << DDS_RESET_FPGA_BITP ) #define DDS_SYNC_FPGA_BITM (0x1 << DDS_SYNC_FPGA_BITP ) #define SW_CAP4_BITM (0x1 << SW_CAP4_BITP ) #define AM_ALC_SW_BITM (0x1 << AM_ALC_SW_BITP ) #define SW_CAP3_BITM (0x1 << SW_CAP3_BITP ) #define SW_CAP2_BITM (0x1 << SW_CAP2_BITP ) #define SW_CAP1_BITM (0x1 << SW_CAP1_BITP ) #define AM_ALC_1_FIX_BITM (0x1 << AM_ALC_1_FIX_BITP ) #define PLL_VTUNE_CTRL_BITM (0x1 << PLL_VTUNE_CTRL_BITP ) #define PLL_SYNC_CTRL_BITM (0x1 << PLL_SYNC_CTRL_BITP ) #define PLL_SYNC_BITM (0x1 << PLL_SYNC_BITP ) #define PLL_LOOP_CTRL_BITM (0x1 << PLL_LOOP_CTRL_BITP ) #define DDS_X2_FPGA_BITM (0x1 << DDS_X2_FPGA_BITP ) #define DDS_SAW2_FPGA_BITM (0x1 << DDS_SAW2_FPGA_BITP ) #define REF_OFFSET_CTRL_FPGA_BITM (0x1 << REF_OFFSET_CTRL_FPGA_BITP ) #define GPIO_ADRF_V1_BITM (0x1 << GPIO_ADRF_V1_BITP ) #define GPIO_ADRF_V2_BITM (0x1 << GPIO_ADRF_V2_BITP ) #define DDS_SAW1_FPGA_BITM (0x1 << DDS_SAW1_FPGA_BITP ) #define FPGA_AM_CTRL_BITM (0x1 << FPGA_AM_CTRL_BITP ) #define RF_SW1_0 (0x0 << RF_SW1_BITP) #define RF_SW1_1 (0x1 << RF_SW1_BITP) #define RF_SW2_0 (0x0 << RF_SW2_BITP) #define RF_SW2_1 (0x1 << RF_SW2_BITP) #define CTRL_AM_SW3_0 (0x0 << CTRL_AM_SW3_BITP) #define CTRL_AM_SW3_1 (0x1 << CTRL_AM_SW3_BITP) #define DDS_SYNC_CTRL_FPGA_0 (0x0 << DDS_SYNC_CTRL_FPGA_BITP) #define DDS_SYNC_CTRL_FPGA_1 (0x1 << DDS_SYNC_CTRL_FPGA_BITP) #define DDS_RESET_FPGA_0 (0x0 << DDS_RESET_FPGA_BITP) #define DDS_RESET_FPGA_1 (0x1 << DDS_RESET_FPGA_BITP) #define DDS_SYNC_FPGA_0 (0x0 << DDS_SYNC_FPGA_BITP) #define DDS_SYNC_FPGA_1 (0x1 << DDS_SYNC_FPGA_BITP) #define SW_CAP4_0 (0x0 << SW_CAP4_BITP) #define SW_CAP4_1 (0x1 << SW_CAP4_BITP) #define AM_ALC_SW_0 (0x0 << AM_ALC_SW_BITP) #define AM_ALC_SW_1 (0x1 << AM_ALC_SW_BITP) #define SW_CAP3_0 (0x0 << SW_CAP3_BITP) #define SW_CAP3_1 (0x1 << SW_CAP3_BITP) #define SW_CAP2_0 (0x0 << SW_CAP2_BITP) #define SW_CAP2_1 (0x1 << SW_CAP2_BITP) #define SW_CAP1_0 (0x0 << SW_CAP1_BITP) #define SW_CAP1_1 (0x1 << SW_CAP1_BITP) #define AM_ALC_1_FIX_0 (0x0 << AM_ALC_1_FIX_BITP) #define AM_ALC_1_FIX_1 (0x1 << AM_ALC_1_FIX_BITP) #define PLL_VTUNE_CTRL_0 (0x0 << PLL_VTUNE_CTRL_BITP) #define PLL_VTUNE_CTRL_1 (0x1 << PLL_VTUNE_CTRL_BITP) #define PLL_SYNC_CTRL_0 (0x0 << PLL_SYNC_CTRL_BITP) #define PLL_SYNC_CTRL_1 (0x1 << PLL_SYNC_CTRL_BITP) #define PLL_SYNC_0 (0x0 << PLL_SYNC_BITP) #define PLL_SYNC_1 (0x1 << PLL_SYNC_BITP) #define PLL_LOOP_CTRL_0 (0x0 << PLL_LOOP_CTRL_BITP) #define PLL_LOOP_CTRL_1 (0x1 << PLL_LOOP_CTRL_BITP) #define DDS_X2_FPGA_0 (0x0 << DDS_X2_FPGA_BITP) #define DDS_X2_FPGA_1 (0x1 << DDS_X2_FPGA_BITP) #define DDS_SAW2_FPGA_0 (0x0 << DDS_SAW2_FPGA_BITP) #define DDS_SAW2_FPGA_1 (0x1 << DDS_SAW2_FPGA_BITP) #define REF_OFFSET_CTRL_FPGA_0 (0x0 << REF_OFFSET_CTRL_FPGA_BITP) #define REF_OFFSET_CTRL_FPGA_1 (0x1 << REF_OFFSET_CTRL_FPGA_BITP) #define GPIO_ADRF_V1_0 (0x0 << GPIO_ADRF_V1_BITP) #define GPIO_ADRF_V1_1 (0x1 << GPIO_ADRF_V1_BITP) #define GPIO_ADRF_V2_0 (0x0 << GPIO_ADRF_V2_BITP) #define GPIO_ADRF_V2_1 (0x1 << GPIO_ADRF_V2_BITP) #define DDS_SAW1_FPGA_0 (0x0 << DDS_SAW1_FPGA_BITP) #define DDS_SAW1_FPGA_1 (0x1 << DDS_SAW1_FPGA_BITP) #define FPGA_AM_CTRL_0 (0x0 << FPGA_AM_CTRL_BITP) #define FPGA_AM_CTRL_1 (0x1 << FPGA_AM_CTRL_BITP) // Define values for Shift Reg #define SHIFT_REG_SW_RF 0x0 #define SHIFT_REG_SW4_RF 0x0 #define SHIFT_REG_GPIO_SW_015_RF 0x1 #define SHIFT_REG_GPIO_SW_X2_RF 0x0 #define SHIFT_REG_SW1_RF 0x1 #define SHIFT_REG_SW_MIXER_RF 0x0 #define SHIFT_REG_GPIO_SW_X2_RF_BITP 0 #define SHIFT_REG_SW_RF_BITP 1 #define SHIFT_REG_SW4_RF_BITP 2 #define SHIFT_REG_GPIO_SW_015_RF_BITP 3 #define SHIFT_REG_SW_MIXER_RF_BITP 4 #define SHIFT_REG_SW1_RF_BITP 5 #define SHIFT_REG_SW2_RF_BITP 6 #define SHIFT_REG_SW3_RF_BITP 7 // Bit masks #define SHIFT_REG_SW_RF_BITM (0x1 << SHIFT_REG_SW_RF_BITP) #define SHIFT_REG_SW4_RF_BITM (0x1 << SHIFT_REG_SW4_RF_BITP) #define SHIFT_REG_GPIO_SW_015_RF_BITM (0x1 << SHIFT_REG_GPIO_SW_015_RF_BITP) #define SHIFT_REG_GPIO_SW_X2_RF_BITM (0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP) #define SHIFT_REG_SW_MIXER_RF_BITM (0x1 << SHIFT_REG_SW_MIXER_RF_BITP) #define SHIFT_REG_SW1_RF_BITM (0x1 << SHIFT_REG_SW1_RF_BITP) #define SHIFT_REG_SW2_RF_BITM (0x1 << SHIFT_REG_SW2_RF_BITP) #define SHIFT_REG_SW3_RF_BITM (0x1 << SHIFT_REG_SW3_RF_BITP) #define SHIFT_REG_GPIO_SW_X2_RF_0 (0x0 << SHIFT_REG_GPIO_SW_X2_RF_BITP) #define SHIFT_REG_GPIO_SW_X2_RF_1 (0x1 << SHIFT_REG_GPIO_SW_X2_RF_BITP) #define SHIFT_REG_SW_RF_0 (0x0 << SHIFT_REG_SW_RF_BITP) #define SHIFT_REG_SW_RF_1 (0x1 << SHIFT_REG_SW_RF_BITP) #define SHIFT_REG_SW4_RF_0 (0x0 << SHIFT_REG_SW4_RF_BITP) #define SHIFT_REG_SW4_RF_1 (0x1 << SHIFT_REG_SW4_RF_BITP) #define SHIFT_REG_GPIO_SW_015_RF_0 (0x0 << SHIFT_REG_GPIO_SW_015_RF_BITP) #define SHIFT_REG_GPIO_SW_015_RF_1 (0x1 << SHIFT_REG_GPIO_SW_015_RF_BITP) #define SHIFT_REG_SW_MIXER_RF_0 (0x0 << SHIFT_REG_SW_MIXER_RF_BITP) #define SHIFT_REG_SW_MIXER_RF_1 (0x1 << SHIFT_REG_SW_MIXER_RF_BITP) #define SHIFT_REG_SW1_RF_0 (0x0 << SHIFT_REG_SW1_RF_BITP) #define SHIFT_REG_SW1_RF_1 (0x1 << SHIFT_REG_SW1_RF_BITP) #define SHIFT_REG_SW2_RF_0 (0x0 << SHIFT_REG_SW2_RF_BITP) #define SHIFT_REG_SW2_RF_1 (0x1 << SHIFT_REG_SW2_RF_BITP) #define SHIFT_REG_SW3_RF_0 (0x0 << SHIFT_REG_SW3_RF_BITP) #define SHIFT_REG_SW3_RF_1 (0x1 << SHIFT_REG_SW3_RF_BITP) #define SHIFT_REG ((SHIFT_REG_SW_RF << 1) | \ (SHIFT_REG_SW4_RF<<2) | \ (SHIFT_REG_GPIO_SW_015_RF<<3) | \ (SHIFT_REG_GPIO_SW_X2_RF<<0) | \ (SHIFT_REG_SW1_RF <<5) | \ (SHIFT_REG_SW_MIXER_RF <<4)) #define GPIO_REG ((FPGA_AM_CTRL << 22) | \ (DDS_SAW1_FPGA << 21) | \ (GPIO_ADRF_V2 << 20) | \ (GPIO_ADRF_V1 << 19) | \ (REF_OFFSET_CTRL_FPGA << 18) | \ (DDS_SAW2_FPGA << 17) | \ (DDS_X2_FPGA << 16) | \ (PLL_LOOP_CTRL << 15) | \ (PLL_SYNC << 14) | \ (PLL_SYNC_CTRL << 13) | \ (PLL_VTUNE_CTRL << 12) | \ (AM_ALC_1_FIX << 11) | \ (SW_CAP1 << 10) | \ (SW_CAP2 << 9) | \ (SW_CAP3 << 8) | \ (AM_ALC_SW << 7) | \ (SW_CAP4 << 6) | \ (DDS_SYNC_FPGA << 5) | \ (DDS_RESET_FPGA << 4) | \ (DDS_SYNC_CTRL_FPGA << 3) | \ (CTRL_AM_SW3 << 2) | \ (RF_SW2 << 1) | \ (RF_SW1 << 0)) // Macros to set register parameter #define SET_REGISTER_PARAM( REGISTER, BITM, BITP, PARAMETER )\ REGISTER &= ~BITM;\ REGISTER |= PARAMETER; #define CFG_REG_ADDR 0x08 // Command Register #define CFG_REG_RST_FOR_FPGA_BITP 0 #define CFG_REG_WIDTH_SPI_TMSG_BITP 1 #define CFG_REG_MOD_CMD_REG_BITP 2 #define CFG_REG_LR_GPIO_BITP 3 #define CFG_REG_HR_GPIO_BITP 4 #define CFG_REG_SPI_MODE_BITP 5 #define CFG_REG_SPI_CLK_BITP 6 #define CFG_REG_RST_FOR_FPGA_BITM (0x1 << CFG_REG_RST_FOR_FPGA_BITP) #define CFG_REG_WIDTH_SPI_TMSG_BITM (0x1 << CFG_REG_WIDTH_SPI_TMSG_BITP) #define CFG_REG_MOD_CMD_REG_BITM (0x1 << CFG_REG_MOD_CMD_REG_BITP) #define CFG_REG_LR_GPIO_BITM (0x1 << CFG_REG_LR_GPIO_BITP) #define CFG_REG_HR_GPIO_BITM (0x1 << CFG_REG_HR_GPIO_BITP) #define CFG_REG_SPI_MODE_BITM (0x1 << CFG_REG_SPI_MODE_BITP) #define CFG_REG_SPI_CLK_BITM (0x1 << CFG_REG_SPI_CLK_BITP) #define CFG_REG_RST_FOR_FPGA_ON 0x1 #define CFG_REG_RST_FOR_FPGA_OFF 0x0 #define CFG_REG_WIDTH_SPI_TMSG_24_BIT (0x0 << CFG_REG_WIDTH_SPI_TMSG_BITP) #define CFG_REG_WIDTH_SPI_TMSG_32_BIT (0x1 << CFG_REG_WIDTH_SPI_TMSG_BITP) #define CFG_REG_MOD_0 (0x0 << CFG_REG_MOD_CMD_REG_BITP) #define CFG_REG_MOD_1 (0x1 << CFG_REG_MOD_CMD_REG_BITP) #define CFG_REG_LR_GPIO_0 (0x0 << CFG_REG_LR_GPIO_BITP) #define CFG_REG_LR_GPIO_1 (0x1 << CFG_REG_LR_GPIO_BITP) #define CFG_REG_HR_GPIO_0 (0x0 << CFG_REG_HR_GPIO_BITP) #define CFG_REG_HR_GPIO_1 (0x1 << CFG_REG_HR_GPIO_BITP) #define CFG_REG_SPI_MODE_1MOSI (0x0 << CFG_REG_SPI_MODE_BITP) #define CFG_REG_SPI_MODE_4MOSI (0x1 << CFG_REG_SPI_MODE_BITP) #define CFG_REG_SPI_CLK_10MHZ (0x0 << CFG_REG_SPI_CLK_BITP) #define CFG_REG_SPI_CLK_50MHZ (0x1 << CFG_REG_SPI_CLK_BITP) #define LMX_BASE_ADDR 0x04 void rst_for_fpga(reg_addr_pci* pci_bar_1); void shift_reg(reg_addr_pci* pci_bar_1); void key_switch(reg_addr_pci* pci_bar_1, double freq, double lmx_freq); uint32_t get_cfg_reg(); void set_cfg_reg(uint32_t cfg_reg_to_set); uint32_t get_tmsg_gpio_reg(); void set_tmsg_gpio_reg(uint32_t tmsg_gpio_reg_to_set); uint32_t get_tmsg_shift_reg(); void set_tmsg_shift_reg(uint32_t tmsg_shift_reg_to_set); #endif //DMADRIVER_TMSGHEADERS_H