ad9912.c 9.1 KB

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  1. #include "ad9912.h"
  2. #include <math.h>
  3. uint32_t ad9912regs[AD9912_COUNT] = {
  4. 0x000018,
  5. 0x000100,
  6. 0x000202,
  7. 0x000309,
  8. 0x000400,
  9. 0x000500,
  10. 0x001010,
  11. 0x001200,
  12. 0x001300,
  13. 0x002012,
  14. 0x002204,
  15. 0x010400,
  16. 0x010500,
  17. 0x010600,
  18. 0x01A633,
  19. 0x01A733,
  20. 0x01A833,
  21. 0x01A933,
  22. 0x01AA33,
  23. 0x01AB33,
  24. 0x01AC00,
  25. 0x01AD00,
  26. 0x020005,
  27. 0x020100,
  28. 0x040BFF,
  29. 0x040C01,
  30. 0x040E10,
  31. 0x050000,
  32. 0x050100,
  33. 0x050200,
  34. 0x050300,
  35. 0x050400,
  36. 0x050500,
  37. 0x050600,
  38. 0x050700,
  39. 0x050800,
  40. 0x050900
  41. };
  42. uint32_t ad9912_ftw_regs_qspi[4];
  43. /*-------------------------AD9912 INIT FUNCTION-------------------------*/
  44. void ad9912_init(reg_addr_pci* pci_bar_1) {
  45. pci_bar_1->sbtmsg_addr = GPIO_INIT_HEADER;
  46. //Rst on
  47. pci_bar_1->sbtmsg_addr = AD9912_RST_ON;
  48. // Rst off
  49. pci_bar_1->sbtmsg_addr = GPIO_REG;
  50. //Init Header
  51. pci_bar_1->sbtmsg_addr = InitDDSHeader;
  52. //Init Data
  53. for (int k = 0; k < AD9912_COUNT; k++) {
  54. pci_bar_1->sbtmsg_addr = ad9912regs[k];
  55. }
  56. }
  57. /*----------------------------------------------------------------------*/
  58. double ad9912_set_main_band(double lmx_freq,double f_pd) {
  59. // Divide the frequncy by the old value of the phase detector frequency and only left with the integer part
  60. uint32_t N = (uint32_t) (lmx_freq/f_pd);
  61. if (f_pd >= 300e6) {
  62. N = N+10;
  63. }
  64. if (lmx_freq <= 12500e6) {
  65. if (N < 28){
  66. N= 28;
  67. };
  68. }
  69. else if (lmx_freq > 12500e6) {
  70. if (N <32) {
  71. N = 32;
  72. }
  73. };
  74. printf("N = %d\n", N);
  75. // Calculate the new phase detector frequency by dividing the frequency by the new value of N
  76. f_pd = lmx_freq/N; // Phase detector frequency
  77. return f_pd;
  78. }
  79. double ad9912_set_out_of_band(double lmx_freq,double f_pd) {
  80. double f_vco = 2*lmx_freq; // VCO frequency
  81. double vco_div = 7.5e9/lmx_freq;
  82. int chan_div = 2;
  83. if (f_vco < 7.5e9) {
  84. if (vco_div > 2 && vco_div <= 4) {
  85. chan_div = 4; // 4
  86. f_vco = lmx_freq * chan_div;
  87. }
  88. else if (vco_div > 4 && vco_div <= 6) {
  89. chan_div = 6; // 6
  90. f_vco = lmx_freq * chan_div;
  91. }
  92. else if (vco_div > 6 && vco_div <= 8) {
  93. chan_div = 8; // 8
  94. f_vco = lmx_freq * chan_div;
  95. }
  96. else if (vco_div > 8 && vco_div <= 12) {
  97. chan_div = 12; // 12
  98. f_vco = lmx_freq * chan_div;
  99. }
  100. else if (vco_div > 12 && vco_div <= 16) {
  101. chan_div = 16; // 16
  102. f_vco = lmx_freq * chan_div;
  103. }
  104. else if (vco_div > 16 && vco_div <= 24) {
  105. chan_div = 24; // 24
  106. f_vco = lmx_freq * chan_div;
  107. }
  108. else if (vco_div > 24 && vco_div <= 32) {
  109. chan_div = 32; // 32
  110. f_vco = lmx_freq * chan_div;
  111. }
  112. else if (vco_div > 32 && vco_div <= 48) {
  113. chan_div = 48; // 48
  114. f_vco = lmx_freq * chan_div;
  115. }
  116. else if (vco_div > 48 && vco_div <= 64) {
  117. chan_div = 64; // 64
  118. f_vco = lmx_freq * chan_div;
  119. }
  120. else if (vco_div > 64 && vco_div <= 72) {
  121. chan_div = 72; // 72
  122. f_vco = lmx_freq * chan_div;
  123. }
  124. else if (vco_div > 72 && vco_div <= 96) {
  125. chan_div = 96; // 96
  126. f_vco = lmx_freq * chan_div;
  127. }
  128. else if (vco_div > 96 && vco_div <= 128) {
  129. chan_div = 128; // 128
  130. f_vco = lmx_freq * chan_div;
  131. }
  132. else if (vco_div > 128 && vco_div <= 192) {
  133. chan_div = 192; // 192
  134. f_vco = lmx_freq * chan_div;
  135. }
  136. else if (vco_div > 192 && vco_div <= 256) {
  137. chan_div = 256; // 256
  138. f_vco = lmx_freq * chan_div;
  139. }
  140. else if (vco_div > 256 && vco_div <= 384) {
  141. chan_div = 384; // 384
  142. f_vco = lmx_freq * chan_div;
  143. }
  144. else if (vco_div > 384 && vco_div <= 512) {
  145. chan_div = 512; // 512
  146. f_vco = lmx_freq * chan_div;
  147. }
  148. else if (vco_div > 512 && vco_div <= 768) {
  149. chan_div = 768; // 768
  150. f_vco = lmx_freq * chan_div;
  151. }
  152. }
  153. else {
  154. f_vco = lmx_freq * 2;
  155. }
  156. // Divide the frequncy by the old value of the phase detector frequency and only left with the integer part
  157. uint32_t N = (uint32_t) (f_vco/f_pd);
  158. if (f_pd >= 300e6) {
  159. N = N+10;
  160. }
  161. if (f_vco <= 12500e6) {
  162. if (N < 28){
  163. N= 28;
  164. };
  165. }
  166. else if (f_vco > 12500e6) {
  167. if (N <32) {
  168. N = 32;
  169. }
  170. };
  171. // Calculate the new phase detector frequency by dividing the frequency by the new value of N
  172. f_pd = f_vco/N; // Phase detector frequency
  173. return f_pd;
  174. }
  175. double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd) {
  176. double fs = 1e9;
  177. if (freq >= 7500e6 && freq <= 15000e6) {
  178. f_pd = ad9912_set_main_band(freq,f_pd);
  179. }
  180. else if (freq >= 10e6 && freq < 7500e6) {
  181. f_pd = ad9912_set_out_of_band(freq,f_pd);
  182. }
  183. else {
  184. return -1;
  185. printf("Frequency is out of range\n");
  186. }
  187. printf("f_pd = %f\n", f_pd);
  188. // FTW word
  189. double ftw_word = (f_pd*pow(2, 48))/fs;
  190. // Split the FTW word between 6 registers
  191. // First one is ftw_word[7:0]
  192. uint8_t ftw0_7_0 = (uint8_t) ftw_word;
  193. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0] & ~BITM_AD9912_FTW0_FREQ_WORD_7_0;
  194. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0] | (ftw0_7_0 << BITP_AD9912_FTW0_FREQ_WORD_7_0);
  195. // Second one is ftw_word[15:8]
  196. uint8_t ftw0_15_8 = (uint8_t) ((uint64_t)ftw_word >> 8);
  197. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8] & ~BITM_AD9912_FTW0_FREQ_WORD_15_8;
  198. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8] | (ftw0_15_8 << BITP_AD9912_FTW0_FREQ_WORD_15_8);
  199. // Third one is ftw_word[23:16]
  200. uint8_t ftw0_23_16 = (uint32_t) ((uint64_t)ftw_word >> 16);
  201. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16] & ~BITM_AD9912_FTW0_FREQ_WORD_23_16;
  202. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16] | (ftw0_23_16 << BITP_AD9912_FTW0_FREQ_WORD_23_16);
  203. // Fourth one is ftw_word[31:24]
  204. uint8_t ftw0_31_24 = (uint64_t) ((uint64_t)ftw_word >> 24);
  205. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24] & ~BITM_AD9912_FTW0_FREQ_WORD_31_24;
  206. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24] | (ftw0_31_24 << BITP_AD9912_FTW0_FREQ_WORD_31_24);
  207. // Fifth one is ftw_word[39:32]
  208. uint8_t ftw1_39_32 = (uint32_t) ((uint64_t)ftw_word >> 32);
  209. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24] & ~BITM_AD9912_FTW0_FREQ_WORD_39_24;
  210. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24] | (ftw1_39_32<< BITP_AD9912_FTW0_FREQ_WORD_39_24);
  211. // Sixth one is ftw_word[47:40]
  212. uint8_t ftw1_47_40 = (uint32_t) ((uint64_t)ftw_word >> 40);
  213. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] & ~BITM_AD9912_FTW0_FREQ_WORD_47_40;
  214. ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] = ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40] | (ftw1_47_40 << BITP_AD9912_FTW0_FREQ_WORD_47_40);
  215. // Set the frequency
  216. // uint32_t ad9912_ftw_regs[] = {
  217. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_7_0],
  218. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_15_8],
  219. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_23_16],
  220. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_31_24],
  221. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_39_24],
  222. // ad9912regs[REGP_AD9912_FTW0_FREQ_WORD_47_40]
  223. // };
  224. // First 16 bits is the instruction word
  225. ad9912_ftw_regs_qspi[0] = (ENUM_AD9912_INSTRUCTION_WORD_WRITE | ENUM_AD9912_INSTRUCTION_WORD_STREAM | ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12);
  226. ad9912_ftw_regs_qspi[1] = (ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8 | (0x00 << BITP_AD9912_QSPI_PHASE_13_8) | (0x00 << BITP_AD9912_QSPI_PHASE_7_0));
  227. ad9912_ftw_regs_qspi[2] = ((ftw1_47_40 << BITP_AD9912_QSPI_47_40) | (ftw1_39_32 << BITP_AD9912_QSPI_39_32) | (ftw0_31_24 << BITP_AD9912_QSPI_31_24));
  228. ad9912_ftw_regs_qspi[3] = ((ftw0_23_16 << BITP_AD9912_QSPI_23_16) | (ftw0_15_8 << BITP_AD9912_QSPI_15_8) | (ftw0_7_0 << BITP_AD9912_QSPI_7_0));
  229. // // Create the appropriate header
  230. // uint32_t *dds_header = bar1 + TMSG_BASE_ADDR;
  231. // *dds_header = ((0 << 23) | (DeviceIdDDS << 18) | ((sizeof(ad9912_ftw_regs)/4) << 1) | 1);
  232. // uint32_t *dds_data = bar1 + TMSG_BASE_ADDR;
  233. // // Write the data
  234. // for (int i = 0; i < sizeof(ad9912_ftw_regs)/4; i++) {
  235. // *dds_data = ad9912_ftw_regs[i];
  236. // }
  237. return f_pd;
  238. }