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TMSG44-CoolPi
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Devices
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lmx2594regs.h

lmx2594regs.h 5.8 KB
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  1. #ifndef DMADRIVER_LMK2594REGS_H
    2. 

  2. #define DMADRIVER_LMK2594REGS_H
    3. 

  3. 

  4. #define     PLL_N_S                                     0x22
    5. 

  5. #define     PLL_N_M                                     0x24
    6. 

  6. #define     PLL_DEN_S                                   0x26
    7. 

  7. #define     PLL_DEN_M                                   0x27
    8. 

  8. #define     PLL_NUM_S                                   0x2A
    9. 

  9. #define     PLL_NUM_M                                   0x2B
    10. 

  10. #define     OUTA_MUX                                    0x2D
    11. 

  11. 

  12. 

  13. //R78
    14. 

  14. #define     CAP_CTRL_START                              0x4E
    15. 

  15. // R75
    16. 

  16. #define     CHDIV                                       0x4B
    17. 

  17. // R31
    18. 

  18. #define     CHDIV_DIV2                                  0x1F
    19. 

  19. 

  20. // R44
    21. 

  21. #define     MASH_ORDER                                  0x2C
    22. 

  22. // R37
    23. 

  23. #define     PFD_DLY_SEL                                 0x25
    24. 

  24. 

  25. //R20
    26. 

  26. #define     VCO_SEL                                     0x14
    27. 

  27. //R19
    28. 

  28. #define     VCO_CAP_CTRL                                0x13
    29. 

  29. //R17
    30. 

  30. #define     VCO_DACISET                                 0x11
    31. 

  31. 

  32. //R0
    33. 

  33. #define     FCAL_ADDR                                   0x00
    34. 

  34. 

  35. 

  36. 

  37. //BIT POSITIONS AND MASKS
    38. 

  38. /**********************************************************************************
    39. 

  39.  * 										R20
    40. 

  40.  *********************************************************************************/
    41. 

  41. // VCO_SEL [13:11]
    42. 

  42. #define BITP_LMX2594_R20_VCO_SEL                        11
    43. 

  43. #define BITM_LMX2594_R20_VCO_SEL                        (0x07 << BITP_LMX2594_R20_VCO_SEL)
    44. 

  44. /**********************************************************************************
    45. 

  45.  * 										R19
    46. 

  46.  *********************************************************************************/
    47. 

  47. // VCO_CAP_CTRL [7:0]
    48. 

  48. #define BITP_LMX2594_R19_VCO_CAP_CTRL                   0
    49. 

  49. #define BITM_LMX2594_R19_VCO_CAP_CTRL                   (0xFF << BITP_LMX2594_R19_VCO_CAP_CTRL)
    50. 

  50. /**********************************************************************************
    51. 

  51.  * 										R17
    52. 

  52.  *********************************************************************************/
    53. 

  53. // VCO_DACISET [8:0]
    54. 

  54. #define BITP_LMX2594_R17_VCO_DACISET                    0
    55. 

  55. #define BITM_LMX2594_R17_VCO_DACISET                    (0x1FF << BITP_LMX2594_R17_VCO_DACISET)
    56. 

  56. /**********************************************************************************
    57. 

  57.  * 										R37
    58. 

  58.  *********************************************************************************/
    59. 

  59. #define BITP_LMX2594_R37_PFD_DLY_SEL                    8
    60. 

  60. // Length 6 bits
    61. 

  61. #define BITM_LMX2594_R37_PFD_DLY_SEL                    (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL)
    62. 

  62. /**********************************************************************************
    63. 

  63.  * 										R44
    64. 

  64.  *********************************************************************************/
    65. 

  65. #define BITP_LMX2594_R44_MASH_ORDER                      0
    66. 

  66. #define BITM_LMX2594_R44_MASH_ORDER                      (0x07 << BITP_LMX2594_R44_MASH_ORDER)
    67. 

  67. #define ENUM_LMX2594_R44_MASH_ORDER_INTEGER              (0x00 << BITP_LMX2594_R44_MASH_ORDER)
    68. 

  68. #define ENUM_LMX2594_R44_MASH_ORDER_1                    (0x01 << BITP_LMX2594_R44_MASH_ORDER)
    69. 

  69. #define ENUM_LMX2594_R44_MASH_ORDER_2                    (0x02 << BITP_LMX2594_R44_MASH_ORDER)
    70. 

  70. #define ENUM_LMX2594_R44_MASH_ORDER_3                    (0x03 << BITP_LMX2594_R44_MASH_ORDER)
    71. 

  71. #define ENUM_LMX2594_R44_MASH_ORDER_4                    (0x04 << BITP_LMX2594_R44_MASH_ORDER)
    72. 

  72. /**********************************************************************************
    73. 

  73.  * 										R45
    74. 

  74.  *********************************************************************************/
    75. 

  75. #define BITP_LMX2594_R45_OUTA_MUX                       11
    76. 

  76. #define BITM_LMX2594_R45_OUTA_MUX                       (0x03 << BITP_LMX2594_R45_OUTA_MUX)
    77. 

  77. #define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV                (0x00 << BITP_LMX2594_R45_OUTA_MUX)
    78. 

  78. #define ENUM_LMX2594_R45_OUTA_MUX_VCO                   (0x01 << BITP_LMX2594_R45_OUTA_MUX)
    79. 

  79. 

  80. #define ENUM_LMX2594_R45_DEFAULT_VAL                    0x01
    81. 

  81. 

  82. /*********************************************************************************/
    83. 

  83. 

  84. 

  85. /**********************************************************************************
    86. 

  86.  * 										R75
    87. 

  87.  *********************************************************************************/
    88. 

  88. #define BITP_LMX2594_R75_CHDIV                          6
    89. 

  89. #define BITM_LMX2594_R75_CHDIV                          (0x3F << BITP_LMX2594_R75_CHDIV)
    90. 

  90. 

  91. /**********************************************************************************
    92. 

  92.  * 										R78
    93. 

  93.  *********************************************************************************/
    94. 

  94. #define BITP_LMX2594_R78_VCO_CAP_CTRL_START             1
    95. 

  95. #define BITM_LMX2594_R78_VCO_CAP_CTRL_START             (0xFF<<BITP_LMX2594_R78_VCO_CAP_CTRL_START)
    96. 

  96. /*********************************************************************************/
    97. 

  97. 

  98. /**********************************************************************************
    99. 

  99.  * 										R31
    100. 

  100.  *********************************************************************************/
    101. 

  101. #define BITP_LMX2594_R31_CHDIV_DIV2                     14
    102. 

  102. #define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    103. 

  103. #define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    104. 

  104. #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
    105. 

  105. 

  106. /**********************************************************************************
    107. 

  107.  * 										R1
    108. 

  108.  *********************************************************************************/
    109. 

  109. 

  110. /**********************************************************************************
    111. 

  111.  * 										R0
    112. 

  112.  *********************************************************************************/
    113. 

  113. 

  114. #define BITP_LMX2594_R0_FCAL                            4
    115. 

  115. #define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
    116. 

  116. /*********************************************************************************/
    117. 

  117. 

  118. 

  119. #endif //DMADRIVER_LMK2594REGS_H
    120.