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TMSG44-CoolPi
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lmx2594regs.h

lmx2594regs.h 5.4 KB
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  1. #ifndef DMADRIVER_LMK2594REGS_H
    2. 

  2. #define DMADRIVER_LMK2594REGS_H
    3. 

  3. 

  4. #define     PLL_N_S                                     0x22
    5. 

  5. #define     PLL_N_M                                     0x24
    6. 

  6. #define     PLL_DEN_S                                   0x26
    7. 

  7. #define     PLL_DEN_M                                   0x27
    8. 

  8. #define     PLL_NUM_S                                   0x2A
    9. 

  9. #define     PLL_NUM_M                                   0x2B
    10. 

  10. #define     OUTA_MUX                                    0x2D
    11. 

  11. 

  12. // R75
    13. 

  13. #define     CHDIV                                       0x4B
    14. 

  14. // R31
    15. 

  15. #define     CHDIV_DIV2                                  0x1F
    16. 

  16. 

  17. // R44
    18. 

  18. #define     MASH_ORDER                                  0x2C
    19. 

  19. // R37
    20. 

  20. #define     PFD_DLY_SEL                                 0x25
    21. 

  21. 

  22. //R20
    23. 

  23. #define     VCO_SEL                                     0x14
    24. 

  24. //R19
    25. 

  25. #define     VCO_CAP_CTRL                                0x13
    26. 

  26. //R17
    27. 

  27. #define     VCO_DACISET                                 0x11
    28. 

  28. 

  29. //R0
    30. 

  30. #define     FCAL_ADDR                                   0x00
    31. 

  31. 

  32. 

  33. 

  34. //BIT POSITIONS AND MASKS
    35. 

  35. /**********************************************************************************
    36. 

  36.  * 										R20
    37. 

  37.  *********************************************************************************/
    38. 

  38. // VCO_SEL [13:11]
    39. 

  39. #define BITP_LMX2594_R20_VCO_SEL                        11
    40. 

  40. #define BITM_LMX2594_R20_VCO_SEL                        (0x07 << BITP_LMX2594_R20_VCO_SEL)
    41. 

  41. /**********************************************************************************
    42. 

  42.  * 										R19
    43. 

  43.  *********************************************************************************/
    44. 

  44. // VCO_CAP_CTRL [7:0]
    45. 

  45. #define BITP_LMX2594_R19_VCO_CAP_CTRL                   0
    46. 

  46. #define BITM_LMX2594_R19_VCO_CAP_CTRL                   (0xFF << BITP_LMX2594_R19_VCO_CAP_CTRL)
    47. 

  47. /**********************************************************************************
    48. 

  48.  * 										R17
    49. 

  49.  *********************************************************************************/
    50. 

  50. // VCO_DACISET [8:0]
    51. 

  51. #define BITP_LMX2594_R17_VCO_DACISET                    0
    52. 

  52. #define BITM_LMX2594_R17_VCO_DACISET                    (0x1FF << BITP_LMX2594_R17_VCO_DACISET)
    53. 

  53. /**********************************************************************************
    54. 

  54.  * 										R37
    55. 

  55.  *********************************************************************************/
    56. 

  56. #define BITP_LMX2594_R37_PFD_DLY_SEL                    8
    57. 

  57. // Length 6 bits
    58. 

  58. #define BITM_LMX2594_R37_PFD_DLY_SEL                    (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL)
    59. 

  59. /**********************************************************************************
    60. 

  60.  * 										R44
    61. 

  61.  *********************************************************************************/
    62. 

  62. #define BITP_LMX2594_R44_MASH_ORDER                      0
    63. 

  63. #define BITM_LMX2594_R44_MASH_ORDER                      (0x07 << BITP_LMX2594_R44_MASH_ORDER)
    64. 

  64. #define ENUM_LMX2594_R44_MASH_ORDER_INTEGER              (0x00 << BITP_LMX2594_R44_MASH_ORDER)
    65. 

  65. #define ENUM_LMX2594_R44_MASH_ORDER_1                    (0x01 << BITP_LMX2594_R44_MASH_ORDER)
    66. 

  66. #define ENUM_LMX2594_R44_MASH_ORDER_2                    (0x02 << BITP_LMX2594_R44_MASH_ORDER)
    67. 

  67. #define ENUM_LMX2594_R44_MASH_ORDER_3                    (0x03 << BITP_LMX2594_R44_MASH_ORDER)
    68. 

  68. #define ENUM_LMX2594_R44_MASH_ORDER_4                    (0x04 << BITP_LMX2594_R44_MASH_ORDER)
    69. 

  69. /**********************************************************************************
    70. 

  70.  * 										R45
    71. 

  71.  *********************************************************************************/
    72. 

  72. #define BITP_LMX2594_R45_OUTA_MUX                       11
    73. 

  73. #define BITM_LMX2594_R45_OUTA_MUX                       (0x03 << BITP_LMX2594_R45_OUTA_MUX)
    74. 

  74. #define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV                (0x00 << BITP_LMX2594_R45_OUTA_MUX)
    75. 

  75. #define ENUM_LMX2594_R45_OUTA_MUX_VCO                   (0x01 << BITP_LMX2594_R45_OUTA_MUX)
    76. 

  76. 

  77. #define ENUM_LMX2594_R45_DEFAULT_VAL                    0x01
    78. 

  78. 

  79. /*********************************************************************************/
    80. 

  80. 

  81. 

  82. /**********************************************************************************
    83. 

  83.  * 										R75
    84. 

  84.  *********************************************************************************/
    85. 

  85. #define BITP_LMX2594_R75_CHDIV                          6
    86. 

  86. #define BITM_LMX2594_R75_CHDIV                          (0x3F << BITP_LMX2594_R75_CHDIV)
    87. 

  87. /*********************************************************************************/
    88. 

  88. 

  89. /**********************************************************************************
    90. 

  90.  * 										R31
    91. 

  91.  *********************************************************************************/
    92. 

  92. #define BITP_LMX2594_R31_CHDIV_DIV2                     14
    93. 

  93. #define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    94. 

  94. #define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    95. 

  95. #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
    96. 

  96. 

  97. /**********************************************************************************
    98. 

  98.  * 										R1
    99. 

  99.  *********************************************************************************/
    100. 

  100. 

  101. /**********************************************************************************
    102. 

  102.  * 										R0
    103. 

  103.  *********************************************************************************/
    104. 

  104. 

  105. #define BITP_LMX2594_R0_FCAL                            4
    106. 

  106. #define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
    107. 

  107. /*********************************************************************************/
    108. 

  108. 

  109. 

  110. #endif //DMADRIVER_LMK2594REGS_H
    111.