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lmx2594regs.h

lmx2594regs.h 4.0 KB
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  1. #ifndef DMADRIVER_LMK2594REGS_H
    2. 

  2. #define DMADRIVER_LMK2594REGS_H
    3. 

  3. 

  4. #define     PLL_N_S                                     0x22
    5. 

  5. #define     PLL_N_M                                     0x24
    6. 

  6. #define     PLL_DEN_S                                   0x26
    7. 

  7. #define     PLL_DEN_M                                   0x27
    8. 

  8. #define     PLL_NUM_S                                   0x2A
    9. 

  9. #define     PLL_NUM_M                                   0x2B
    10. 

  10. #define     OUTA_MUX                                    0x2D
    11. 

  11. 

  12. // R75
    13. 

  13. #define     CHDIV                                       0x4B
    14. 

  14. // R31
    15. 

  15. #define     CHDIV_DIV2                                  0x1F
    16. 

  16. 

  17. // R44
    18. 

  18. #define     MASH_ORDER                                  0x2C
    19. 

  19. // R37
    20. 

  20. #define     PFD_DLY_SEL                                 0x25
    21. 

  21. 

  22. #define     FCAL_ADDR                                   0x00
    23. 

  23. 

  24. 

  25. 

  26. //BIT POSITIONS AND MASKS
    27. 

  27. /**********************************************************************************
    28. 

  28.  * 										R37
    29. 

  29.  *********************************************************************************/
    30. 

  30. #define BITP_LMX2594_R37_PFD_DLY_SEL                    8
    31. 

  31. // Length 6 bits
    32. 

  32. #define BITM_LMX2594_R37_PFD_DLY_SEL                    (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL)
    33. 

  33. /**********************************************************************************
    34. 

  34.  * 										R44
    35. 

  35.  *********************************************************************************/
    36. 

  36. #define BITP_LMX2594_R44_MASH_ORDER                      0
    37. 

  37. #define BITM_LMX2594_R44_MASH_ORDER                      (0x07 << BITP_LMX2594_R44_MASH_ORDER)
    38. 

  38. #define ENUM_LMX2594_R44_MASH_ORDER_INTEGER              (0x00 << BITP_LMX2594_R44_MASH_ORDER)
    39. 

  39. #define ENUM_LMX2594_R44_MASH_ORDER_1                    (0x01 << BITP_LMX2594_R44_MASH_ORDER)
    40. 

  40. #define ENUM_LMX2594_R44_MASH_ORDER_2                    (0x02 << BITP_LMX2594_R44_MASH_ORDER)
    41. 

  41. #define ENUM_LMX2594_R44_MASH_ORDER_3                    (0x03 << BITP_LMX2594_R44_MASH_ORDER)
    42. 

  42. #define ENUM_LMX2594_R44_MASH_ORDER_4                    (0x04 << BITP_LMX2594_R44_MASH_ORDER)
    43. 

  43. /**********************************************************************************
    44. 

  44.  * 										R45
    45. 

  45.  *********************************************************************************/
    46. 

  46. #define BITP_LMX2594_R45_OUTA_MUX                       11
    47. 

  47. #define BITM_LMX2594_R45_OUTA_MUX                       (0x03 << BITP_LMX2594_R45_OUTA_MUX)
    48. 

  48. #define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV                (0x00 << BITP_LMX2594_R45_OUTA_MUX)
    49. 

  49. #define ENUM_LMX2594_R45_OUTA_MUX_VCO                   (0x01 << BITP_LMX2594_R45_OUTA_MUX)
    50. 

  50. 

  51. #define ENUM_LMX2594_R45_DEFAULT_VAL                    0x01
    52. 

  52. 

  53. /*********************************************************************************/
    54. 

  54. 

  55. 

  56. /**********************************************************************************
    57. 

  57.  * 										R75
    58. 

  58.  *********************************************************************************/
    59. 

  59. #define BITP_LMX2594_R75_CHDIV                          6
    60. 

  60. #define BITM_LMX2594_R75_CHDIV                          (0x3F << BITP_LMX2594_R75_CHDIV)
    61. 

  61. /*********************************************************************************/
    62. 

  62. 

  63. /**********************************************************************************
    64. 

  64.  * 										R31
    65. 

  65.  *********************************************************************************/
    66. 

  66. #define BITP_LMX2594_R31_CHDIV_DIV2                     14
    67. 

  67. #define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    68. 

  68. #define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    69. 

  69. #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
    70. 

  70. 

  71. /**********************************************************************************
    72. 

  72.  * 										R0
    73. 

  73.  *********************************************************************************/
    74. 

  74. 

  75. #define BITP_LMX2594_R0_FCAL                            4
    76. 

  76. #define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
    77. 

  77. /*********************************************************************************/
    78. 

  78. 

  79. 

  80. #endif //DMADRIVER_LMK2594REGS_H
    81.