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TMSG44-CoolPi
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Devices
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lmx2594regs.h

lmx2594regs.h 8.6 KB
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  1. #ifndef DMADRIVER_LMK2594REGS_H
    2. 

  2. #define DMADRIVER_LMK2594REGS_H
    3. 

  3. 

  4. #define     PLL_N_S                                     0x22
    5. 

  5. #define     PLL_N_M                                     0x24
    6. 

  6. #define     PLL_DEN_S                                   0x26
    7. 

  7. #define     PLL_DEN_M                                   0x27
    8. 

  8. #define     PLL_NUM_S                                   0x2A
    9. 

  9. #define     PLL_NUM_M                                   0x2B
    10. 

  10. #define     OUTA_MUX                                    0x2D
    11. 

  11. 

  12. //R78
    13. 

  13. #define     CAP_CTRL_START                              0x4E
    14. 

  14. // R75
    15. 

  15. #define     CHDIV                                       0x4B
    16. 

  16. // R31
    17. 

  17. #define     CHDIV_DIV2                                  0x1F
    18. 

  18. // R44
    19. 

  19. #define     MASH_ORDER                                  0x2C
    20. 

  20. // R37
    21. 

  21. #define     PFD_DLY_SEL                                 0x25
    22. 

  22. //R20
    23. 

  23. #define     VCO_SEL                                     0x14
    24. 

  24. //R19
    25. 

  25. #define     VCO_CAP_CTRL                                0x13
    26. 

  26. //R17
    27. 

  27. #define     VCO_DACISET                                 0x11
    28. 

  28. //R14
    29. 

  29. #define     CPG_REG                                     0xE
    30. 

  30. //R4
    31. 

  31. #define     R4_ADDR                                     0x04
    32. 

  32. //R1
    33. 

  33. #define     R1_ADDR                                     0x01
    34. 

  34. //R0
    35. 

  35. #define     FCAL_ADDR                                   0x00
    36. 

  36. 

  37. 

  38. 

  39. //BIT POSITIONS AND MASKS
    40. 

  40. /**********************************************************************************
    41. 

  41.  * 										R20
    42. 

  42.  *********************************************************************************/
    43. 

  43. // VCO_SEL [13:11]
    44. 

  44. #define BITP_LMX2594_R20_VCO_SEL                        11
    45. 

  45. #define BITM_LMX2594_R20_VCO_SEL                        (0x07 << BITP_LMX2594_R20_VCO_SEL)
    46. 

  46. /**********************************************************************************
    47. 

  47.  * 										R19
    48. 

  48.  *********************************************************************************/
    49. 

  49. // VCO_CAP_CTRL [7:0]
    50. 

  50. #define BITP_LMX2594_R19_VCO_CAP_CTRL                   0
    51. 

  51. #define BITM_LMX2594_R19_VCO_CAP_CTRL                   (0xFF << BITP_LMX2594_R19_VCO_CAP_CTRL)
    52. 

  52. /**********************************************************************************
    53. 

  53.  * 										R17
    54. 

  54.  *********************************************************************************/
    55. 

  55. // VCO_DACISET [8:0]
    56. 

  56. #define BITP_LMX2594_R17_VCO_DACISET                    0
    57. 

  57. #define BITM_LMX2594_R17_VCO_DACISET                    (0x1FF << BITP_LMX2594_R17_VCO_DACISET)
    58. 

  58. /**********************************************************************************
    59. 

  59.  * 										R37
    60. 

  60.  *********************************************************************************/
    61. 

  61. #define BITP_LMX2594_R37_PFD_DLY_SEL                    8
    62. 

  62. // Length 6 bits
    63. 

  63. #define BITM_LMX2594_R37_PFD_DLY_SEL                    (0x3F << BITP_LMX2594_R37_PFD_DLY_SEL)
    64. 

  64. /**********************************************************************************
    65. 

  65.  * 										R44
    66. 

  66.  *********************************************************************************/
    67. 

  67. #define BITP_LMX2594_R44_MASH_ORDER                      0
    68. 

  68. #define BITM_LMX2594_R44_MASH_ORDER                      (0x07 << BITP_LMX2594_R44_MASH_ORDER)
    69. 

  69. #define ENUM_LMX2594_R44_MASH_ORDER_INTEGER              (0x00 << BITP_LMX2594_R44_MASH_ORDER)
    70. 

  70. #define ENUM_LMX2594_R44_MASH_ORDER_1                    (0x01 << BITP_LMX2594_R44_MASH_ORDER)
    71. 

  71. #define ENUM_LMX2594_R44_MASH_ORDER_2                    (0x02 << BITP_LMX2594_R44_MASH_ORDER)
    72. 

  72. #define ENUM_LMX2594_R44_MASH_ORDER_3                    (0x03 << BITP_LMX2594_R44_MASH_ORDER)
    73. 

  73. #define ENUM_LMX2594_R44_MASH_ORDER_4                    (0x04 << BITP_LMX2594_R44_MASH_ORDER)
    74. 

  74. /**********************************************************************************
    75. 

  75.  * 										R45
    76. 

  76.  *********************************************************************************/
    77. 

  77. #define BITP_LMX2594_R45_OUTA_MUX                       11
    78. 

  78. #define BITM_LMX2594_R45_OUTA_MUX                       (0x03 << BITP_LMX2594_R45_OUTA_MUX)
    79. 

  79. #define ENUM_LMX2594_R45_OUTA_MUX_CH_DIV                (0x00 << BITP_LMX2594_R45_OUTA_MUX)
    80. 

  80. #define ENUM_LMX2594_R45_OUTA_MUX_VCO                   (0x01 << BITP_LMX2594_R45_OUTA_MUX)
    81. 

  81. 

  82. #define ENUM_LMX2594_R45_DEFAULT_VAL                    0x01
    83. 

  83. 

  84. /*********************************************************************************/
    85. 

  85. 

  86. 

  87. /**********************************************************************************
    88. 

  88.  * 										R75
    89. 

  89.  *********************************************************************************/
    90. 

  90. #define BITP_LMX2594_R75_CHDIV                          6
    91. 

  91. #define BITM_LMX2594_R75_CHDIV                          (0x3F << BITP_LMX2594_R75_CHDIV)
    92. 

  92. 

  93. /**********************************************************************************
    94. 

  94.  * 										R78
    95. 

  95.  *********************************************************************************/
    96. 

  96. #define BITP_LMX2594_R78_VCO_CAP_CTRL_START             1
    97. 

  97. #define BITM_LMX2594_R78_VCO_CAP_CTRL_START             (0xFF<<BITP_LMX2594_R78_VCO_CAP_CTRL_START)
    98. 

  98. /*********************************************************************************/
    99. 

  99. 

  100. /**********************************************************************************
    101. 

  101.  * 										R31
    102. 

  102.  *********************************************************************************/
    103. 

  103. #define BITP_LMX2594_R31_CHDIV_DIV2                     14
    104. 

  104. #define BITM_LMX2594_R31_CHDIV_DIV2                     (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    105. 

  105. #define ENUM_LMX2594_R31_CHDIV_DIV2_EN                  (0x01 << BITP_LMX2594_R31_CHDIV_DIV2)
    106. 

  106. #define ENUM_LMX2594_R31_CHDIV_DIV2_DIS                 (0x00 << BITP_LMX2594_R31_CHDIV_DIV2)
    107. 

  107. /**********************************************************************************
    108. 

  108.  * 										R14
    109. 

  109.  *********************************************************************************/
    110. 

  110. #define BITP_LMX2594_R14_CPG                            4
    111. 

  111. #define BITM_LMX2594_R14_CPG                            (0x7 <<BITP_LMX2594_R14_CPG)
    112. 

  112. #define ENUM_LMX2594_R14_CPG_TRISTATE                   (0x0<<BITP_LMX2594_R14_CPG)
    113. 

  113. #define ENUM_LMX2594_R14_CPG_15ma                       (0x7<<BITP_LMX2594_R14_CPG)
    114. 

  114. /**********************************************************************************
    115. 

  115.  * 										R4
    116. 

  116.  *********************************************************************************/
    117. 

  117. #define BITP_LMX2594_R4_ACAL_CMP_DLY                       8
    118. 

  118. #define BITM_LMX2594_R4_ACAL_CMP_DLY                       (0xFF<<BITP_LMX2594_R4_ACAL_CMP_DLY)
    119. 

  119. /**********************************************************************************
    120. 

  120.  * 										R1
    121. 

  121.  *********************************************************************************/
    122. 

  122. #define BITP_LMX2594_R1_CAL_CLK_DIV                     0
    123. 

  123. #define BITM_LMX2594_R1_CAL_CLK_DIV                     (0x7 << BITP_LMX2594_R1_CAL_CLK_DIV)
    124. 

  124. #define ENUM_LMX2594_R1_CAL_CLK_DIV1                    (0x0 << BITP_LMX2594_R1_CAL_CLK_DIV)
    125. 

  125. #define ENUM_LMX2594_R1_CAL_CLK_DIV2                    (0x1 << BITP_LMX2594_R1_CAL_CLK_DIV)
    126. 

  126. #define ENUM_LMX2594_R1_CAL_CLK_DIV4                    (0x2 << BITP_LMX2594_R1_CAL_CLK_DIV)
    127. 

  127. #define ENUM_LMX2594_R1_CAL_CLK_DIV8                    (0x3 << BITP_LMX2594_R1_CAL_CLK_DIV)
    128. 

  128. /**********************************************************************************
    129. 

  129.  * 										R0
    130. 

  130.  *********************************************************************************/
    131. 

  131. 

  132. #define BITP_LMX2594_R0_FCAL_HPFD_ADJ                   7
    133. 

  133. #define BITM_LMX2594_RO_FCAL_HPFD_ADJ                   (0x3 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    134. 

  134. #define LMX2594_R0_FCAL_HPFD_ADJ                        (0x03 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    135. 

  135. #define ENUM_LMX2594_R0_FCAL_HPFD_ADJ_LESS100MHZ        (0x00 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    136. 

  136. #define ENUM_LMX2594_R0_FCAL_HPFD_ADJ_100_150MHZ        (0x01 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    137. 

  137. #define ENUM_LMX2594_R0_FCAL_HPFD_ADJ_150_200MHZ        (0x02 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    138. 

  138. #define ENUM_LMX2594_R0_FCAL_HPFD_ADJ_MORE200MHZ        (0x03 << BITP_LMX2594_R0_FCAL_HPFD_ADJ)
    139. 

  139. 

  140. #define BITP_LMX2594_R0_FCAL_LPFD_ADJ                   5
    141. 

  141. #define LMX2594_R0_FCAL_LPFD_ADJ                        (0x03 << BITP_LMX2594_R0_FCAL_LPFD_ADJ)
    142. 

  142. #define ENUM_LMX2594_R0_FCAL_LPFD_ADJ_MORE10MHZ         (0x00 << BITP_LMX2594_R0_FCAL_LPFD_ADJ)
    143. 

  143. #define ENUM_LMX2594_R0_FCAL_LPFD_ADJ_5_10MHZ           (0x01 << BITP_LMX2594_R0_FCAL_LPFD_ADJ)
    144. 

  144. #define ENUM_LMX2594_R0_FCAL_LPFD_ADJ_2_5_5MHZ          (0x02 << BITP_LMX2594_R0_FCAL_LPFD_ADJ)
    145. 

  145. #define ENUM_LMX2594_R0_FCAL_LPFD_AD_LESS_2_5_MHZ       (0x03 << BITP_LMX2594_R0_FCAL_LPFD_ADJ)
    146. 

  146. 

  147. #define BITP_LMX2594_R0_FCAL                            3
    148. 

  148. #define BITM_LMX2594_R0_FCAL                         (0x01 << BITP_LMX2594_R0_FCAL)
    149. 

  149. #define LMX2594_R0_FCAL_EN                              (0x01 << BITP_LMX2594_R0_FCAL)
    150. 

  150. /*********************************************************************************/
    151. 

  151. 

  152. 

  153. #endif //DMADRIVER_LMK2594REGS_H
    154.