zaytsev.mikhail
/
TMSG44-CoolPi


			
				
					
						
						
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							#ifndef AD9912_H
#define AD9912_H

#include "pci.h"
#include "tmsgheaders.h"

#define     AD9912_COUNT        37
#define     AD9912_BASE_ADDR    0x04

#define AD9912_RST_ON ((DDS_SAW1_FPGA << 21) | \
						(GPIO_ADRF_V2 << 20) | \
						(GPIO_ADRF_V1 << 19) | \
						(REF_OFFSET_CTRL_FPGA << 18) | \
						(DDS_SAW2_FPGA << 17) | \
						(DDS_X2_FPGA << 16) | \
						(PLL_LOOP_CTRL << 15) | \
						(PLL_SYNC << 14) | \
						(PLL_SYNC_CTRL << 13) | \
						(PLL_VTUNE_CTRL << 12) | \
						(AM_ALC_1_FIX << 11) | \
						(SW_CAP1 << 10) | \
						(SW_CAP2 << 9) | \
						(SW_CAP3 << 8) | \
						(AM_ALC_SW << 7) | \
						(SW_CAP4 << 6) | \
						(DDS_SYNC_FPGA << 5) | \
						(0x1 << 4) | \
						(DDS_SYNC_CTRL_FPGA << 3) | \
						(CTRL_AM_SW3 << 2) | \
						(RF_SW2 << 1) | \
						(RF_SW1 << 0))

/**********************************************************************************
 * 										FTW0[7:0]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_7_0							0
#define BITM_AD9912_FTW0_FREQ_WORD_7_0							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
#define REGP_AD9912_FTW0_FREQ_WORD_7_0							0xE
/**********************************************************************************
 * 										FTW0[15:8]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_15_8							0
#define BITM_AD9912_FTW0_FREQ_WORD_15_8							(0xFF << BITP_AD9912_FTW0_FREQ_WORD_15_8)
#define REGP_AD9912_FTW0_FREQ_WORD_15_8							0xF
/**********************************************************************************
 * 										FTW0[23:16]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_23_16						0
#define BITM_AD9912_FTW0_FREQ_WORD_23_16						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_23_16)
#define REGP_AD9912_FTW0_FREQ_WORD_23_16						0x10
/**********************************************************************************
 * 										FTW0[31:24]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_31_24						0
#define BITM_AD9912_FTW0_FREQ_WORD_31_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_31_24)
#define REGP_AD9912_FTW0_FREQ_WORD_31_24						0x11
/**********************************************************************************
 * 										FTW0[39:32]
 *********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_39_24						0
#define BITM_AD9912_FTW0_FREQ_WORD_39_24						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_7_0)
#define REGP_AD9912_FTW0_FREQ_WORD_39_24						0x12
/**********************************************************************************
 * 										FTW0[47:40]
*********************************************************************************/
#define BITP_AD9912_FTW0_FREQ_WORD_47_40						0
#define BITM_AD9912_FTW0_FREQ_WORD_47_40						(0xFF << BITP_AD9912_FTW0_FREQ_WORD_47_40)
#define REGP_AD9912_FTW0_FREQ_WORD_47_40						0x13

/**********************************************************************************
 * 										INSTRUCTION WORD[15:0]
*********************************************************************************/
#define BITP_AD9912_INSTRUCTION_WORD_15_0							0
#define BITM_AD9912_INSTRUCTION_WORD_15_0							(0xFFFF << BITP_AD9912_INSTRUCTION_WORD_15_0)
#define BITP_AD9912_INSTRUCTION_WORD_READ_WRITE						7
#define BITM_AD9912_INSTRUCTION_WORD_READ_WRITE						(0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
#define ENUM_AD9912_INSTRUCTION_WORD_WRITE							(0x0 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)
#define ENUM_AD9912_INSTRUCTION_WORD_READ							(0x1 << BITP_AD9912_INSTRUCTION_WORD_READ_WRITE)

#define BITP_AD9912_INSTRUCTION_WORD_LENGTH							5
#define BITM_AD9912_INSTRUCTION_WORD_LENGTH							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_1						(0x0 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_2						(0x1 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
#define ENUM_AD9912_INSTRUCTION_WORD_LENGTH_3						(0x2 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)
#define ENUM_AD9912_INSTRUCTION_WORD_STREAM							(0x3 << BITP_AD9912_INSTRUCTION_WORD_LENGTH)

#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					16
#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_0_8					(0xFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
#define BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					0
#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS_9_12					(0xF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
//Addr[12:0]
#define BITM_AD9912_INSTRUCTION_WORD_ADDRESS						(0x1FFF << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
#define ENUM_AD9912_INSTRUCTION_WORD_INIT_ADDR						(0x01A6 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS)
#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_0_8					(0xAD << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_0_8)
#define ENUM_ADD9912_INSTRUCTION_WORD_INIT_ADDR_9_12				(0x1 << BITP_AD9912_INSTRUCTION_WORD_ADDRESS_9_12)
/**********************************************************************************
 * 										QSPI_FTW[7:0][15:8]
*********************************************************************************/
#define BITP_AD9912_QSPI_7_0                                        0
#define BITM_AD9912_QSPI_7_0                                        (0xFF << BITP_AD9912_QSPI_7_0)
/**********************************************************************************
 * 										QSPI_FTW[15:8][7:0]
*********************************************************************************/
#define BITP_AD9912_QSPI_15_8                                       8
#define BITM_AD9912_QSPI_15_8                                       (0xFF << BITP_AD9912_QSPI_15_8)
/**********************************************************************************
 * 										QSPI_FTW[23:16]
*********************************************************************************/
#define BITP_AD9912_QSPI_23_16                                      16
#define BITM_AD9912_QSPI_23_16                                      (0xFF << BITP_AD9912_QSPI_23_16)
/**********************************************************************************
 * 										QSPI_FTW[31:24]
*********************************************************************************/
#define BITP_AD9912_QSPI_31_24                                      0
#define BITM_AD9912_QSPI_31_24                                      (0xFF << BITP_AD9912_QSPI_31_24)
/**********************************************************************************
 * 										QSPI_FTW[39:32]
*********************************************************************************/
#define BITP_AD9912_QSPI_39_32                                      8
#define BITM_AD9912_QSPI_39_32                                      (0xFF << BITP_AD9912_QSPI_39_32)
/**********************************************************************************
 * 										QSPI_FTW[47:40]
*********************************************************************************/
#define BITP_AD9912_QSPI_47_40                                      16
#define BITM_AD9912_QSPI_47_40                                      (0xFF << BITP_AD9912_QSPI_47_40)
/**********************************************************************************
 * 										QSPI_PHASE[7:0]
*********************************************************************************/
#define BITP_AD9912_QSPI_PHASE_7_0                                  0
#define BITM_AD9912_QSPI_PHASE_7_0                                  (0xFF << BITP_AD9912_QSPI_PHASE_7_0)
/**********************************************************************************
 * 										QSPI_PHASE[13:8]
*********************************************************************************/
#define BITP_AD9912_QSPI_PHASE_13_8                                 8
#define BITM_AD9912_QSPI_PHASE_13_8                                 (0x3F << BITP_AD9912_QSPI_PHASE_13_8)

extern uint32_t ad9912_ftw_regs_qspi[4];
void ad9912_init(reg_addr_pci* pci_bar_1);
double ad9912_set(reg_addr_pci* pci_bar_1, double freq, double f_pd);
double ad9912_set_out_of_band(double freq,double f_pd); 
double ad9912_set_main_band(double freq,double f_pd);
#endif //AD9912_H