// Company:         TAIR
// Engineer:        Chigrinskiy A.  
// 
// Create Date:     18/04/2024 
// Design Name: 
// Module Name:     LmxWrapper
// Project Name:    SB_TMSG44V1_FPGA
// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:    This module is a wrapper for the LMX Fifo, LMX Fifo Controller and SPI Master modules.
//
// Dependencies:  
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module LmkWrapperA #(
    parameter IN_WIDTH = 24,
    parameter WR_NUM = 1,
    parameter OUT_WIDTH = 24,
    parameter DATA_WIDTH = 24
)(
    input WrClk_i,
    input RdClk_i,
    input Rst_i,
    input [IN_WIDTH-1:0] Data_i,
    input Val_i,

    output LmkAFifoEmpty_o,
    output Ss_o,
    output Sck_o,
    output Mosi_o
);
//================================================================================
//	                                REG/WIRE
//================================================================================    
wire [OUT_WIDTH-1:0] dataFromLmkFifoCtrl;
wire [OUT_WIDTH-1:0] dataFromLmkFifo;
wire readEn;
wire writeEn;
wire valRdDataLmk;
wire busySpiMLmx;
wire lmkFifoFull;
wire lmkFifoEmpty;
//================================================================================
//	                                ASSIGNMENTS
//================================================================================ 
assign LmkAFifoEmpty_o = lmkFifoEmpty;  
//==========================================================================//
//									CODING									//
//==========================================================================//
FifoCtrl #(
	.IN_WIDTH		(IN_WIDTH),
	.WR_NUM			(WR_NUM),
	.OUT_WIDTH		(OUT_WIDTH)
) FifoCtrlLmx
(
	.WrClk_i		(WrClk_i),
	.RdClk_i		(RdClk_i),
	.Rst_i			(Rst_i),
	.Data_i			(Data_i),
	.Val_i			(Val_i),
	.BusySpiM_i		(busySpiMLmx),
	.FifoFull_i		(lmkFifoFull),
	.FifoEmpty_i	(lmkFifoEmpty),
	.Data_o			(dataFromLmkFifoCtrl),
	.ReadEn_o		(readEn),
	.WriteEn_o		(writeEn),
	.ValRdData_o	(valRdDataLmk)
);

//FifoLMK FifoLMK (
//	.rst		(Rst_i),				// input wire rst
//	.wr_clk		(WrClk_i),				// input wire wr_clk
//	.rd_clk		(rd_clk),				// input wire rd_clk
//	.din		(dataFromLmkFifoCtrl),	// input wire [23 : 0] din
//	.wr_en		(writeEn),				// input wire wr_en
//	.rd_en		(readEn),				// input wire rd_en
//	.dout		(dataFromLmkFifo),		// output wire [23 : 0] dout
//	.full		(lmkFifoFull),			// output wire full
//	.empty		(lmkFifoEmpty)			// output wire empty
//);

FifoLMK FifoLMK (
  .rst(Rst_i),        // input wire rst
  .wr_clk(WrClk_i),  // input wire wr_clk
  .rd_clk(RdClk_i),  // input wire rd_clk
  .din(dataFromLmkFifoCtrl),        // input wire [23 : 0] din
  .wr_en(writeEn),    // input wire wr_en
  .rd_en(readEn),    // input wire rd_en
  .dout(dataFromLmkFifo),      // output wire [23 : 0] dout
  .full(lmkFifoFull),      // output wire full
  .empty(lmkFifoEmpty)    // output wire empty
);

SpiM #(
	.DATA_WIDTH	(DATA_WIDTH)
)SpiMLmk(
	.Clk_i		(RdClk_i),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataLmk),
	.SpiData_i	(dataFromLmkFifo),
	.Busy_o		(busySpiMLmx),
	.Ss_o		(Ss_o),
	.Mosi_o		(Mosi_o),
	.Sck_o		(Sck_o)
);

endmodule
