-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-- Date        : Thu Aug 15 12:39:56 2024
-- Host        : DESKTOP-1TRD5RL running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/PCIe/AX7103/SRC/18_PCIe_test/FPGA/xdma_0_ex/xdma_0_ex.gen/sources_1/ip/xdma_0/xdma_0_sim_netlist.vhdl
-- Design      : xdma_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a100tfgg484-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 14) => B"00",
      DIADI(13 downto 8) => wdata(14 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 1) => B"000",
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52\,
      DOBDO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53\,
      DOBDO(13 downto 8) => rdata(14 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74\,
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_19 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_19 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_19;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_19 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_20 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_20 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_20;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_20 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
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      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_21 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_21 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_21;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_21 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_26 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_26 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_26;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_26 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_54\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 13) => B"000",
      DIADI(12 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(13 downto 9),
      DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 1) => B"000",
      DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52\,
      DOBDO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53\,
      DOBDO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_54\,
      DOBDO(12 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(13 downto 9),
      DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74\,
      DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_27 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_27 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_27;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_27 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17),
      DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17),
      DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_28 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_28 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_28;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_28 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17),
      DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17),
      DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_BRAM_TDP_MACRO_29 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_BRAM_TDP_MACRO_29 : entity is "BRAM_TDP_MACRO";
end xdma_0_BRAM_TDP_MACRO_29;

architecture STRUCTURE of xdma_0_BRAM_TDP_MACRO_29 is
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\ : STD_LOGIC;
  signal \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : label is "PRIMITIVE";
begin
\genblk5_0.bram36_tdp_bl.bram36_tdp_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED\(31 downto 16),
      DIADI(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(7 downto 0),
      DIBDI(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED\(31 downto 16),
      DIBDI(15 downto 0) => B"0000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17),
      DIPADIP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20\,
      DOADO(14) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21\,
      DOADO(13) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22\,
      DOADO(12) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23\,
      DOADO(11) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24\,
      DOADO(10) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25\,
      DOADO(9) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26\,
      DOADO(8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27\,
      DOADO(7) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28\,
      DOADO(6) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29\,
      DOADO(5) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30\,
      DOADO(4) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31\,
      DOADO(3) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32\,
      DOADO(2) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33\,
      DOADO(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34\,
      DOADO(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70\,
      DOPADOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17),
      DOPBDOP(0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_cfg_sideband is
  port (
    cfg_interrupt : out STD_LOGIC;
    cfg_interrupt_assert : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \pcie_dma_in\\.cfg_interrupt_sent\ : out STD_LOGIC;
    \pcie_dma_in\\.cfg_interrupt_msi_sent\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    user_reset_out : in STD_LOGIC;
    user_clk_out : in STD_LOGIC;
    cfg_command : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_rdy : in STD_LOGIC;
    \pcie_dma_out\\.cfg_interrupt_int\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_msienable : in STD_LOGIC;
    \pcie_dma_out\\.cfg_interrupt_msi_int\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_mmenable : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_cfg_sideband : entity is "xdma_0_cfg_sideband";
end xdma_0_xdma_0_cfg_sideband;

architecture STRUCTURE of xdma_0_xdma_0_cfg_sideband is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_10_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_11_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_7_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_9_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0\ : STD_LOGIC;
  signal \Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^cfg_interrupt\ : STD_LOGIC;
  signal \^cfg_interrupt_assert\ : STD_LOGIC;
  signal cfg_interrupt_reg : STD_LOGIC;
  signal g2ip_cfg_interrupt213_in : STD_LOGIC;
  signal g2ip_cfg_interrupt_di : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \i__carry_i_1__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__2_n_0\ : STD_LOGIC;
  signal interrupt_req_sent : STD_LOGIC;
  signal interrupt_req_sent0 : STD_LOGIC;
  signal \interrupt_req_sent0_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \interrupt_req_sent0_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \interrupt_req_sent0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \NLW_interrupt_req_sent0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1\ : label is "soft_lutpair2132";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1\ : label is "soft_lutpair2129";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3\ : label is "soft_lutpair2128";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_10\ : label is "soft_lutpair2128";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_11\ : label is "soft_lutpair2126";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5\ : label is "soft_lutpair2126";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9\ : label is "soft_lutpair2127";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5\ : label is "soft_lutpair2125";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6\ : label is "soft_lutpair2124";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7\ : label is "soft_lutpair2127";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_1\ : label is "soft_lutpair2130";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_2\ : label is "soft_lutpair2130";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3\ : label is "soft_lutpair2125";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6\ : label is "soft_lutpair2124";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2\ : label is "soft_lutpair2131";
  attribute SOFT_HLUTNM of \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3\ : label is "soft_lutpair2129";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \interrupt_req_sent0_inferred__0/i__carry\ : label is 11;
  attribute SOFT_HLUTNM of udma_wrapper_i_145 : label is "soft_lutpair2132";
  attribute SOFT_HLUTNM of udma_wrapper_i_146 : label is "soft_lutpair2131";
begin
  E(0) <= \^e\(0);
  Q(4 downto 0) <= \^q\(4 downto 0);
  cfg_interrupt <= \^cfg_interrupt\;
  cfg_interrupt_assert <= \^cfg_interrupt_assert\;
\Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => \^cfg_interrupt\,
      I1 => \pcie_dma_out\\.cfg_interrupt_int\(0),
      I2 => cfg_interrupt_msienable,
      O => \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0\
    );
\Legacy_MSI_Interrupt.cfg_interrupt_reg_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0\,
      Q => cfg_interrupt_reg,
      R => user_reset_out
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB02"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_int\(0),
      I1 => cfg_interrupt_reg,
      I2 => cfg_interrupt_msienable,
      I3 => \^cfg_interrupt_assert\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0\,
      Q => \^cfg_interrupt_assert\,
      R => user_reset_out
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFAEAEAEAEAE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(1),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(3),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(2),
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0\,
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0\,
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0\,
      O => g2ip_cfg_interrupt_di(0)
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(14),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFAEAEAEAEAE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(11),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0\,
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0\,
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEFEE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(9),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(5),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(13),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101011111011"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(4),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(2),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(5),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(8),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(6),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFAEAEAEAEAE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(17),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(21),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0\,
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(25),
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEFEEEE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(19),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(15),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(22),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(23),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010101011111011"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      I1 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0\,
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(15),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(18),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(17),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(16),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAEEFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(27),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(29),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(31),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(30),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(28),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(26),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(22),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(24),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0FFE0FFE0FFE0E0"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0\,
      I1 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0\,
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0\,
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(1),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(2),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(3),
      O => g2ip_cfg_interrupt_di(1)
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(13),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_10_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(18),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(19),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_11_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAEAAAEAAAE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(11),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(14),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(13),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0\,
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFFFEFEFEFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(6),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(13),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(15),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010100000001"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(1),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(4),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(5),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(8),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(9),
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0\,
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(22),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(19),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(18),
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100010001000101"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(16),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(17),
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_10_n_0\,
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_11_n_0\,
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(21),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(6),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001110"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(28),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(29),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(30),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(31),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(25),
      I5 => \pcie_dma_out\\.cfg_interrupt_msi_int\(24),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1110"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(24),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(25),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(26),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(27),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(23),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF0002"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0\,
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0\,
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0\,
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0\,
      O => g2ip_cfg_interrupt_di(2)
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFEFCFEFCFFFCFE"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0\,
      I1 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_7_n_0\,
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(14),
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_9_n_0\,
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8_n_0\,
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(9),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(8),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(11),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(3),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(2),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(1),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(5),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(4),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(6),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(21),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(23),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(22),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(27),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(26),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(25),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(24),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0\,
      I1 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0\,
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0\,
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0\,
      O => g2ip_cfg_interrupt_di(3)
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_msienable,
      I1 => user_reset_out,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1110"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0\,
      I1 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0\,
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0\,
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0\,
      O => g2ip_cfg_interrupt_di(4)
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(6),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(7),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(4),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(5),
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(14),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(10),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(9),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(8),
      I4 => \pcie_dma_out\\.cfg_interrupt_msi_int\(11),
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_7_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(24),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(25),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(26),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(27),
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(22),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(20),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(23),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(21),
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_9_n_0\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(13),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(12),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(15),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_7_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(29),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(28),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(31),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(30),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_msi_int\(17),
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(16),
      I2 => \pcie_dma_out\\.cfg_interrupt_msi_int\(19),
      I3 => \pcie_dma_out\\.cfg_interrupt_msi_int\(18),
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_9_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^e\(0),
      D => g2ip_cfg_interrupt_di(0),
      Q => \^q\(0),
      R => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^e\(0),
      D => g2ip_cfg_interrupt_di(1),
      Q => \^q\(1),
      R => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^e\(0),
      D => g2ip_cfg_interrupt_di(2),
      Q => \^q\(2),
      R => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^e\(0),
      D => g2ip_cfg_interrupt_di(3),
      Q => \^q\(3),
      R => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^e\(0),
      D => g2ip_cfg_interrupt_di(4),
      Q => \^q\(4),
      R => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F4FF0000F4F4"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0\,
      I1 => cfg_command(0),
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0\,
      I3 => cfg_interrupt_rdy,
      I4 => user_reset_out,
      I5 => \^cfg_interrupt\,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => g2ip_cfg_interrupt213_in,
      I1 => cfg_interrupt_reg,
      I2 => cfg_interrupt_msienable,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \pcie_dma_out\\.cfg_interrupt_int\(0),
      I1 => cfg_interrupt_reg,
      I2 => cfg_interrupt_msienable,
      O => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0\
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0\,
      I1 => \pcie_dma_out\\.cfg_interrupt_msi_int\(0),
      I2 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0\,
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_8_n_0\,
      I4 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0\,
      I5 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_7_n_0\,
      O => g2ip_cfg_interrupt213_in
    );
\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0\,
      Q => \^cfg_interrupt\,
      R => '0'
    );
\Legacy_MSI_Interrupt.interrupt_req_sent_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => user_reset_out,
      I1 => \Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0\,
      I2 => cfg_command(0),
      I3 => \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0\,
      O => \Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0\
    );
\Legacy_MSI_Interrupt.interrupt_req_sent_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA0082AA000082"
    )
        port map (
      I0 => cfg_interrupt_rdy,
      I1 => \pcie_dma_out\\.cfg_interrupt_int\(0),
      I2 => cfg_interrupt_reg,
      I3 => interrupt_req_sent,
      I4 => cfg_interrupt_msienable,
      I5 => interrupt_req_sent0,
      O => \Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0\
    );
\Legacy_MSI_Interrupt.interrupt_req_sent_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0\,
      Q => interrupt_req_sent,
      R => '0'
    );
dma_cpl_fifo_inst_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => user_reset_out,
      O => \^e\(0)
    );
\i__carry_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cfg_interrupt_mmenable(2),
      I1 => cfg_interrupt_mmenable(1),
      O => \i__carry_i_1__1_n_0\
    );
\i__carry_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => \^q\(4),
      I1 => cfg_interrupt_mmenable(0),
      I2 => cfg_interrupt_mmenable(2),
      I3 => cfg_interrupt_mmenable(1),
      O => \i__carry_i_2__2_n_0\
    );
\i__carry_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200022"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      I2 => cfg_interrupt_mmenable(0),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \i__carry_i_3__2_n_0\
    );
\i__carry_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100011"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      I2 => cfg_interrupt_mmenable(0),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \i__carry_i_4__2_n_0\
    );
\i__carry_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      O => \i__carry_i_5__1_n_0\
    );
\i__carry_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B4B"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      I2 => \^q\(4),
      I3 => cfg_interrupt_mmenable(0),
      O => \i__carry_i_6__2_n_0\
    );
\i__carry_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000220DD"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      I2 => cfg_interrupt_mmenable(0),
      I3 => \^q\(3),
      I4 => \^q\(2),
      O => \i__carry_i_7__2_n_0\
    );
\i__carry_i_8__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000110EE"
    )
        port map (
      I0 => cfg_interrupt_mmenable(1),
      I1 => cfg_interrupt_mmenable(2),
      I2 => cfg_interrupt_mmenable(0),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \i__carry_i_8__2_n_0\
    );
\interrupt_req_sent0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => interrupt_req_sent0,
      CO(2) => \interrupt_req_sent0_inferred__0/i__carry_n_1\,
      CO(1) => \interrupt_req_sent0_inferred__0/i__carry_n_2\,
      CO(0) => \interrupt_req_sent0_inferred__0/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1__1_n_0\,
      DI(2) => \i__carry_i_2__2_n_0\,
      DI(1) => \i__carry_i_3__2_n_0\,
      DI(0) => \i__carry_i_4__2_n_0\,
      O(3 downto 0) => \NLW_interrupt_req_sent0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5__1_n_0\,
      S(2) => \i__carry_i_6__2_n_0\,
      S(1) => \i__carry_i_7__2_n_0\,
      S(0) => \i__carry_i_8__2_n_0\
    );
udma_wrapper_i_145: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => cfg_interrupt_msienable,
      I1 => interrupt_req_sent,
      O => \pcie_dma_in\\.cfg_interrupt_msi_sent\
    );
udma_wrapper_i_146: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => interrupt_req_sent,
      I1 => cfg_interrupt_msienable,
      O => \pcie_dma_in\\.cfg_interrupt_sent\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_dma_cpl is
  port (
    in_packet_q : out STD_LOGIC;
    \s_axis_rc\\.tuser\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \s_axis_rc\\.tkeep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \s_axis_rc\\.tlast\ : out STD_LOGIC;
    \s_axis_rc\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    in_packet_q_reg_0 : in STD_LOGIC;
    user_clk_out : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_tvalid : in STD_LOGIC;
    \s_axis_rc\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \rc_64.wr_compl_status_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rc_64.wr_byte_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \rc_64.wr_cid_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \rc_64.wr_tc_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rc_64.wr_attr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_dma_cpl : entity is "xdma_0_dma_cpl";
end xdma_0_xdma_0_dma_cpl;

architecture STRUCTURE of xdma_0_xdma_0_dma_cpl is
  signal \FSM_onehot_rc_64.state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_rc_64.state_reg_n_0_[4]\ : STD_LOGIC;
  signal current_dw_count : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__1_n_0\ : STD_LOGIC;
  signal in16 : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal in22 : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal in23 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^in_packet_q\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \rc_64.current_dw_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[10]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[11]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[1]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[2]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[3]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[3]_i_3_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[4]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[5]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[6]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[7]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[8]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count[9]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[11]_i_3_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[11]_i_3_n_3\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \rc_64.current_dw_count_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \rc_64.wr_byte_reg_n_0_[0]\ : STD_LOGIC;
  signal \rc_64.wr_byte_reg_n_0_[1]\ : STD_LOGIC;
  signal \rc_64.wr_compl_status_reg_n_0_[0]\ : STD_LOGIC;
  signal \rc_64.wr_compl_status_reg_n_0_[1]\ : STD_LOGIC;
  signal \rc_64.wr_compl_status_reg_n_0_[2]\ : STD_LOGIC;
  signal \rc_64.wr_data[0]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[10]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[11]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[12]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[13]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[14]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[15]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[16]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[17]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[18]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[19]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[1]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[20]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[21]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[22]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[23]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[24]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[25]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[26]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[27]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[28]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[29]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[2]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[30]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[31]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[32]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[33]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[34]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[35]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[36]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[37]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[38]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[39]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[3]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[40]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[41]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[42]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[43]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[44]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[45]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[46]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[47]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[48]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[49]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[4]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[50]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[51]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[52]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[53]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[54]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[55]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[56]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[57]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[58]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[59]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[5]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[60]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[61]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[62]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[63]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[6]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[7]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[8]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data[9]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[32]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[33]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[34]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[35]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[36]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[37]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[38]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[39]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[40]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[41]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[42]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[43]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[44]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[45]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[46]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[47]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[48]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[49]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[50]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[51]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[52]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[53]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[54]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[55]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[56]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[57]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[58]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[59]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[60]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[61]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[62]\ : STD_LOGIC;
  signal \rc_64.wr_data_reg_n_0_[63]\ : STD_LOGIC;
  signal \rc_64.wr_ep_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_ep_reg_n_0\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[0]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[1]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[2]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[3]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[4]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[5]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[6]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[7]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[8]\ : STD_LOGIC;
  signal \rc_64.wr_len_reg_n_0_[9]\ : STD_LOGIC;
  signal \rc_64.wr_tag[0]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[1]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[2]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[3]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[4]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[5]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[6]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[7]_i_1_n_0\ : STD_LOGIC;
  signal \rc_64.wr_tag[7]_i_2_n_0\ : STD_LOGIC;
  signal \^s_axis_rc\\.tuser\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal s_axis_rc_tdata0 : STD_LOGIC;
  signal \s_axis_rc_tdata0_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \s_axis_rc_tdata0_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \s_axis_rc_tdata0_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \s_axis_rc_tdata0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal udma_wrapper_i_154_n_0 : STD_LOGIC;
  signal udma_wrapper_i_155_n_0 : STD_LOGIC;
  signal udma_wrapper_i_156_n_0 : STD_LOGIC;
  signal udma_wrapper_i_157_n_0 : STD_LOGIC;
  signal udma_wrapper_i_158_n_0 : STD_LOGIC;
  signal udma_wrapper_i_159_n_0 : STD_LOGIC;
  signal udma_wrapper_i_160_n_0 : STD_LOGIC;
  signal udma_wrapper_i_161_n_0 : STD_LOGIC;
  signal udma_wrapper_i_161_n_1 : STD_LOGIC;
  signal udma_wrapper_i_161_n_2 : STD_LOGIC;
  signal udma_wrapper_i_161_n_3 : STD_LOGIC;
  signal udma_wrapper_i_161_n_4 : STD_LOGIC;
  signal udma_wrapper_i_161_n_5 : STD_LOGIC;
  signal udma_wrapper_i_161_n_6 : STD_LOGIC;
  signal udma_wrapper_i_161_n_7 : STD_LOGIC;
  signal udma_wrapper_i_162_n_0 : STD_LOGIC;
  signal udma_wrapper_i_163_n_0 : STD_LOGIC;
  signal udma_wrapper_i_164_n_0 : STD_LOGIC;
  signal udma_wrapper_i_165_n_0 : STD_LOGIC;
  signal udma_wrapper_i_166_n_0 : STD_LOGIC;
  signal udma_wrapper_i_167_n_0 : STD_LOGIC;
  signal udma_wrapper_i_168_n_0 : STD_LOGIC;
  signal udma_wrapper_i_169_n_0 : STD_LOGIC;
  signal udma_wrapper_i_238_n_0 : STD_LOGIC;
  signal udma_wrapper_i_239_n_0 : STD_LOGIC;
  signal udma_wrapper_i_239_n_1 : STD_LOGIC;
  signal udma_wrapper_i_239_n_2 : STD_LOGIC;
  signal udma_wrapper_i_239_n_3 : STD_LOGIC;
  signal udma_wrapper_i_239_n_4 : STD_LOGIC;
  signal udma_wrapper_i_239_n_5 : STD_LOGIC;
  signal udma_wrapper_i_239_n_6 : STD_LOGIC;
  signal udma_wrapper_i_239_n_7 : STD_LOGIC;
  signal udma_wrapper_i_240_n_0 : STD_LOGIC;
  signal udma_wrapper_i_241_n_1 : STD_LOGIC;
  signal udma_wrapper_i_241_n_2 : STD_LOGIC;
  signal udma_wrapper_i_241_n_3 : STD_LOGIC;
  signal udma_wrapper_i_241_n_4 : STD_LOGIC;
  signal udma_wrapper_i_241_n_5 : STD_LOGIC;
  signal udma_wrapper_i_241_n_6 : STD_LOGIC;
  signal udma_wrapper_i_241_n_7 : STD_LOGIC;
  signal udma_wrapper_i_242_n_0 : STD_LOGIC;
  signal udma_wrapper_i_243_n_0 : STD_LOGIC;
  signal udma_wrapper_i_244_n_0 : STD_LOGIC;
  signal udma_wrapper_i_245_n_0 : STD_LOGIC;
  signal udma_wrapper_i_254_n_0 : STD_LOGIC;
  signal udma_wrapper_i_255_n_0 : STD_LOGIC;
  signal udma_wrapper_i_256_n_0 : STD_LOGIC;
  signal udma_wrapper_i_257_n_0 : STD_LOGIC;
  signal udma_wrapper_i_258_n_0 : STD_LOGIC;
  signal udma_wrapper_i_259_n_0 : STD_LOGIC;
  signal udma_wrapper_i_260_n_0 : STD_LOGIC;
  signal udma_wrapper_i_261_n_0 : STD_LOGIC;
  signal wr_tc : STD_LOGIC;
  signal \NLW_rc_64.current_dw_count_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_rc_64.current_dw_count_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_rc_64.current_dw_count_reg[11]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_s_axis_rc_tdata0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_s_axis_rc_tdata0_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_s_axis_rc_tdata0_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_i_241_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_rc_64.state[2]_i_2\ : label is "soft_lutpair1995";
  attribute SOFT_HLUTNM of \FSM_onehot_rc_64.state[3]_i_2\ : label is "soft_lutpair1996";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_rc_64.state_reg[0]\ : label is "RX_DATA:00100,RX_NEW:10000,RX_DATA_N:01000,RX_IDLE:00001,RX_DW0_DW1:00010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_rc_64.state_reg[1]\ : label is "RX_DATA:00100,RX_NEW:10000,RX_DATA_N:01000,RX_IDLE:00001,RX_DW0_DW1:00010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_rc_64.state_reg[2]\ : label is "RX_DATA:00100,RX_NEW:10000,RX_DATA_N:01000,RX_IDLE:00001,RX_DW0_DW1:00010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_rc_64.state_reg[3]\ : label is "RX_DATA:00100,RX_NEW:10000,RX_DATA_N:01000,RX_IDLE:00001,RX_DW0_DW1:00010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_rc_64.state_reg[4]\ : label is "RX_DATA:00100,RX_NEW:10000,RX_DATA_N:01000,RX_IDLE:00001,RX_DW0_DW1:00010";
  attribute SOFT_HLUTNM of \rc_64.current_dw_count[9]_i_1\ : label is "soft_lutpair1956";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[11]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[11]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[3]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[4]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[7]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rc_64.current_dw_count_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \rc_64.wr_data[0]_i_1\ : label is "soft_lutpair1961";
  attribute SOFT_HLUTNM of \rc_64.wr_data[10]_i_1\ : label is "soft_lutpair1971";
  attribute SOFT_HLUTNM of \rc_64.wr_data[11]_i_1\ : label is "soft_lutpair1972";
  attribute SOFT_HLUTNM of \rc_64.wr_data[12]_i_1\ : label is "soft_lutpair1973";
  attribute SOFT_HLUTNM of \rc_64.wr_data[13]_i_1\ : label is "soft_lutpair1974";
  attribute SOFT_HLUTNM of \rc_64.wr_data[14]_i_1\ : label is "soft_lutpair1975";
  attribute SOFT_HLUTNM of \rc_64.wr_data[15]_i_1\ : label is "soft_lutpair1976";
  attribute SOFT_HLUTNM of \rc_64.wr_data[16]_i_1\ : label is "soft_lutpair1977";
  attribute SOFT_HLUTNM of \rc_64.wr_data[17]_i_1\ : label is "soft_lutpair1978";
  attribute SOFT_HLUTNM of \rc_64.wr_data[18]_i_1\ : label is "soft_lutpair1979";
  attribute SOFT_HLUTNM of \rc_64.wr_data[19]_i_1\ : label is "soft_lutpair1980";
  attribute SOFT_HLUTNM of \rc_64.wr_data[1]_i_1\ : label is "soft_lutpair1962";
  attribute SOFT_HLUTNM of \rc_64.wr_data[20]_i_1\ : label is "soft_lutpair1981";
  attribute SOFT_HLUTNM of \rc_64.wr_data[21]_i_1\ : label is "soft_lutpair1982";
  attribute SOFT_HLUTNM of \rc_64.wr_data[22]_i_1\ : label is "soft_lutpair1983";
  attribute SOFT_HLUTNM of \rc_64.wr_data[23]_i_1\ : label is "soft_lutpair1984";
  attribute SOFT_HLUTNM of \rc_64.wr_data[24]_i_1\ : label is "soft_lutpair1985";
  attribute SOFT_HLUTNM of \rc_64.wr_data[25]_i_1\ : label is "soft_lutpair1986";
  attribute SOFT_HLUTNM of \rc_64.wr_data[26]_i_1\ : label is "soft_lutpair1987";
  attribute SOFT_HLUTNM of \rc_64.wr_data[27]_i_1\ : label is "soft_lutpair1988";
  attribute SOFT_HLUTNM of \rc_64.wr_data[28]_i_1\ : label is "soft_lutpair1989";
  attribute SOFT_HLUTNM of \rc_64.wr_data[29]_i_1\ : label is "soft_lutpair1990";
  attribute SOFT_HLUTNM of \rc_64.wr_data[2]_i_1\ : label is "soft_lutpair1963";
  attribute SOFT_HLUTNM of \rc_64.wr_data[30]_i_1\ : label is "soft_lutpair1991";
  attribute SOFT_HLUTNM of \rc_64.wr_data[31]_i_1\ : label is "soft_lutpair1992";
  attribute SOFT_HLUTNM of \rc_64.wr_data[32]_i_1\ : label is "soft_lutpair1961";
  attribute SOFT_HLUTNM of \rc_64.wr_data[33]_i_1\ : label is "soft_lutpair1962";
  attribute SOFT_HLUTNM of \rc_64.wr_data[34]_i_1\ : label is "soft_lutpair1963";
  attribute SOFT_HLUTNM of \rc_64.wr_data[35]_i_1\ : label is "soft_lutpair1964";
  attribute SOFT_HLUTNM of \rc_64.wr_data[36]_i_1\ : label is "soft_lutpair1965";
  attribute SOFT_HLUTNM of \rc_64.wr_data[37]_i_1\ : label is "soft_lutpair1966";
  attribute SOFT_HLUTNM of \rc_64.wr_data[38]_i_1\ : label is "soft_lutpair1967";
  attribute SOFT_HLUTNM of \rc_64.wr_data[39]_i_1\ : label is "soft_lutpair1968";
  attribute SOFT_HLUTNM of \rc_64.wr_data[3]_i_1\ : label is "soft_lutpair1964";
  attribute SOFT_HLUTNM of \rc_64.wr_data[40]_i_1\ : label is "soft_lutpair1969";
  attribute SOFT_HLUTNM of \rc_64.wr_data[41]_i_1\ : label is "soft_lutpair1970";
  attribute SOFT_HLUTNM of \rc_64.wr_data[42]_i_1\ : label is "soft_lutpair1971";
  attribute SOFT_HLUTNM of \rc_64.wr_data[43]_i_1\ : label is "soft_lutpair1972";
  attribute SOFT_HLUTNM of \rc_64.wr_data[44]_i_1\ : label is "soft_lutpair1973";
  attribute SOFT_HLUTNM of \rc_64.wr_data[45]_i_1\ : label is "soft_lutpair1974";
  attribute SOFT_HLUTNM of \rc_64.wr_data[46]_i_1\ : label is "soft_lutpair1975";
  attribute SOFT_HLUTNM of \rc_64.wr_data[47]_i_1\ : label is "soft_lutpair1976";
  attribute SOFT_HLUTNM of \rc_64.wr_data[48]_i_1\ : label is "soft_lutpair1977";
  attribute SOFT_HLUTNM of \rc_64.wr_data[49]_i_1\ : label is "soft_lutpair1978";
  attribute SOFT_HLUTNM of \rc_64.wr_data[4]_i_1\ : label is "soft_lutpair1965";
  attribute SOFT_HLUTNM of \rc_64.wr_data[50]_i_1\ : label is "soft_lutpair1979";
  attribute SOFT_HLUTNM of \rc_64.wr_data[51]_i_1\ : label is "soft_lutpair1980";
  attribute SOFT_HLUTNM of \rc_64.wr_data[52]_i_1\ : label is "soft_lutpair1981";
  attribute SOFT_HLUTNM of \rc_64.wr_data[53]_i_1\ : label is "soft_lutpair1982";
  attribute SOFT_HLUTNM of \rc_64.wr_data[54]_i_1\ : label is "soft_lutpair1983";
  attribute SOFT_HLUTNM of \rc_64.wr_data[55]_i_1\ : label is "soft_lutpair1984";
  attribute SOFT_HLUTNM of \rc_64.wr_data[56]_i_1\ : label is "soft_lutpair1985";
  attribute SOFT_HLUTNM of \rc_64.wr_data[57]_i_1\ : label is "soft_lutpair1986";
  attribute SOFT_HLUTNM of \rc_64.wr_data[58]_i_1\ : label is "soft_lutpair1987";
  attribute SOFT_HLUTNM of \rc_64.wr_data[59]_i_1\ : label is "soft_lutpair1988";
  attribute SOFT_HLUTNM of \rc_64.wr_data[5]_i_1\ : label is "soft_lutpair1966";
  attribute SOFT_HLUTNM of \rc_64.wr_data[60]_i_1\ : label is "soft_lutpair1989";
  attribute SOFT_HLUTNM of \rc_64.wr_data[61]_i_1\ : label is "soft_lutpair1990";
  attribute SOFT_HLUTNM of \rc_64.wr_data[62]_i_1\ : label is "soft_lutpair1991";
  attribute SOFT_HLUTNM of \rc_64.wr_data[63]_i_1\ : label is "soft_lutpair1992";
  attribute SOFT_HLUTNM of \rc_64.wr_data[6]_i_1\ : label is "soft_lutpair1967";
  attribute SOFT_HLUTNM of \rc_64.wr_data[7]_i_1\ : label is "soft_lutpair1968";
  attribute SOFT_HLUTNM of \rc_64.wr_data[8]_i_1\ : label is "soft_lutpair1969";
  attribute SOFT_HLUTNM of \rc_64.wr_data[9]_i_1\ : label is "soft_lutpair1970";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[0]_i_1\ : label is "soft_lutpair2000";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[1]_i_1\ : label is "soft_lutpair2000";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[2]_i_1\ : label is "soft_lutpair1999";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[3]_i_1\ : label is "soft_lutpair1999";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[4]_i_1\ : label is "soft_lutpair1998";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[5]_i_1\ : label is "soft_lutpair1998";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[6]_i_1\ : label is "soft_lutpair1997";
  attribute SOFT_HLUTNM of \rc_64.wr_tag[7]_i_2\ : label is "soft_lutpair1997";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \s_axis_rc_tdata0_inferred__0/i__carry\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \s_axis_rc_tdata0_inferred__0/i__carry__0\ : label is 11;
  attribute SOFT_HLUTNM of udma_wrapper_i_156 : label is "soft_lutpair1959";
  attribute SOFT_HLUTNM of udma_wrapper_i_157 : label is "soft_lutpair1995";
  attribute SOFT_HLUTNM of udma_wrapper_i_158 : label is "soft_lutpair1958";
  attribute SOFT_HLUTNM of udma_wrapper_i_160 : label is "soft_lutpair1956";
  attribute ADDER_THRESHOLD of udma_wrapper_i_161 : label is 35;
  attribute SOFT_HLUTNM of udma_wrapper_i_162 : label is "soft_lutpair1958";
  attribute SOFT_HLUTNM of udma_wrapper_i_165 : label is "soft_lutpair1955";
  attribute SOFT_HLUTNM of udma_wrapper_i_166 : label is "soft_lutpair1957";
  attribute SOFT_HLUTNM of udma_wrapper_i_167 : label is "soft_lutpair1957";
  attribute SOFT_HLUTNM of udma_wrapper_i_168 : label is "soft_lutpair1960";
  attribute SOFT_HLUTNM of udma_wrapper_i_169 : label is "soft_lutpair1955";
  attribute SOFT_HLUTNM of udma_wrapper_i_19 : label is "soft_lutpair1994";
  attribute SOFT_HLUTNM of udma_wrapper_i_238 : label is "soft_lutpair1996";
  attribute ADDER_THRESHOLD of udma_wrapper_i_239 : label is 35;
  attribute SOFT_HLUTNM of udma_wrapper_i_24 : label is "soft_lutpair1993";
  attribute ADDER_THRESHOLD of udma_wrapper_i_241 : label is 35;
  attribute SOFT_HLUTNM of udma_wrapper_i_35 : label is "soft_lutpair1959";
  attribute SOFT_HLUTNM of udma_wrapper_i_51 : label is "soft_lutpair1994";
  attribute SOFT_HLUTNM of udma_wrapper_i_56 : label is "soft_lutpair1993";
  attribute SOFT_HLUTNM of udma_wrapper_i_73 : label is "soft_lutpair1960";
begin
  in_packet_q <= \^in_packet_q\;
  \s_axis_rc\\.tuser\(3 downto 0) <= \^s_axis_rc\\.tuser\(3 downto 0);
\FSM_onehot_rc_64.state[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E0EE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      I2 => \^in_packet_q\,
      I3 => m_axis_tvalid,
      O => \FSM_onehot_rc_64.state[0]_i_1_n_0\
    );
\FSM_onehot_rc_64.state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F444F444F44444"
    )
        port map (
      I0 => \s_axis_rc\\.tready\(0),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I2 => m_axis_tvalid,
      I3 => \^in_packet_q\,
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      I5 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      O => \FSM_onehot_rc_64.state[1]_i_1_n_0\
    );
\FSM_onehot_rc_64.state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3A0A"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state[2]_i_2_n_0\,
      I2 => \s_axis_rc\\.tready\(0),
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \FSM_onehot_rc_64.state[2]_i_1_n_0\
    );
\FSM_onehot_rc_64.state[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \rc_64.wr_compl_status_reg_n_0_[1]\,
      I1 => \rc_64.wr_compl_status_reg_n_0_[0]\,
      I2 => \rc_64.wr_compl_status_reg_n_0_[2]\,
      I3 => udma_wrapper_i_155_n_0,
      O => \FSM_onehot_rc_64.state[2]_i_2_n_0\
    );
\FSM_onehot_rc_64.state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFA8AAAAA8A8AAAA"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I1 => udma_wrapper_i_165_n_0,
      I2 => \FSM_onehot_rc_64.state[3]_i_2_n_0\,
      I3 => \FSM_onehot_rc_64.state[4]_i_3_n_0\,
      I4 => \s_axis_rc\\.tready\(0),
      I5 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \FSM_onehot_rc_64.state[3]_i_1_n_0\
    );
\FSM_onehot_rc_64.state[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => udma_wrapper_i_161_n_4,
      I1 => udma_wrapper_i_161_n_5,
      I2 => udma_wrapper_i_239_n_7,
      O => \FSM_onehot_rc_64.state[3]_i_2_n_0\
    );
\FSM_onehot_rc_64.state[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      O => \FSM_onehot_rc_64.state[4]_i_1_n_0\
    );
\FSM_onehot_rc_64.state[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2FFF0F0F2F2F0F0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state[4]_i_3_n_0\,
      I2 => \FSM_onehot_rc_64.state[4]_i_4_n_0\,
      I3 => udma_wrapper_i_169_n_0,
      I4 => \s_axis_rc\\.tready\(0),
      I5 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      O => \FSM_onehot_rc_64.state[4]_i_2_n_0\
    );
\FSM_onehot_rc_64.state[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[8]\,
      I1 => \rc_64.wr_len_reg_n_0_[9]\,
      I2 => \rc_64.wr_len_reg_n_0_[3]\,
      I3 => \rc_64.wr_len_reg_n_0_[2]\,
      I4 => \FSM_onehot_rc_64.state[4]_i_5_n_0\,
      O => \FSM_onehot_rc_64.state[4]_i_3_n_0\
    );
\FSM_onehot_rc_64.state[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888808"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => \s_axis_rc\\.tready\(0),
      I2 => udma_wrapper_i_155_n_0,
      I3 => \rc_64.wr_compl_status_reg_n_0_[2]\,
      I4 => \rc_64.wr_compl_status_reg_n_0_[0]\,
      I5 => \rc_64.wr_compl_status_reg_n_0_[1]\,
      O => \FSM_onehot_rc_64.state[4]_i_4_n_0\
    );
\FSM_onehot_rc_64.state[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[4]\,
      I1 => \rc_64.wr_len_reg_n_0_[5]\,
      I2 => \rc_64.wr_len_reg_n_0_[6]\,
      I3 => \rc_64.wr_len_reg_n_0_[7]\,
      O => \FSM_onehot_rc_64.state[4]_i_5_n_0\
    );
\FSM_onehot_rc_64.state_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \FSM_onehot_rc_64.state[0]_i_1_n_0\,
      Q => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      S => SR(0)
    );
\FSM_onehot_rc_64.state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \FSM_onehot_rc_64.state[1]_i_1_n_0\,
      Q => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      R => SR(0)
    );
\FSM_onehot_rc_64.state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \FSM_onehot_rc_64.state[2]_i_1_n_0\,
      Q => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      R => SR(0)
    );
\FSM_onehot_rc_64.state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \FSM_onehot_rc_64.state[3]_i_1_n_0\,
      Q => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      R => SR(0)
    );
\FSM_onehot_rc_64.state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \FSM_onehot_rc_64.state[4]_i_2_n_0\,
      Q => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      R => SR(0)
    );
\i__carry__0_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[9]\,
      I1 => p_1_in(9),
      I2 => \rc_64.wr_len_reg_n_0_[8]\,
      I3 => p_1_in(8),
      O => \i__carry__0_i_1__0_n_0\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => p_1_in(9),
      I1 => \rc_64.wr_len_reg_n_0_[9]\,
      I2 => p_1_in(8),
      I3 => \rc_64.wr_len_reg_n_0_[8]\,
      O => \i__carry__0_i_2_n_0\
    );
\i__carry_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[7]\,
      I1 => p_1_in(7),
      I2 => \rc_64.wr_len_reg_n_0_[6]\,
      I3 => p_1_in(6),
      O => \i__carry_i_1__0_n_0\
    );
\i__carry_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[5]\,
      I1 => p_1_in(5),
      I2 => \rc_64.wr_len_reg_n_0_[4]\,
      I3 => p_1_in(4),
      O => \i__carry_i_2__1_n_0\
    );
\i__carry_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[3]\,
      I1 => p_1_in(3),
      I2 => \rc_64.wr_len_reg_n_0_[2]\,
      I3 => p_1_in(2),
      O => \i__carry_i_3__1_n_0\
    );
\i__carry_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[1]\,
      I1 => p_1_in(1),
      I2 => \rc_64.wr_len_reg_n_0_[0]\,
      I3 => p_1_in(0),
      O => \i__carry_i_4__1_n_0\
    );
\i__carry_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => p_1_in(6),
      I1 => \rc_64.wr_len_reg_n_0_[6]\,
      I2 => p_1_in(7),
      I3 => \rc_64.wr_len_reg_n_0_[7]\,
      O => \i__carry_i_5__0_n_0\
    );
\i__carry_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => p_1_in(4),
      I1 => \rc_64.wr_len_reg_n_0_[4]\,
      I2 => p_1_in(5),
      I3 => \rc_64.wr_len_reg_n_0_[5]\,
      O => \i__carry_i_6__1_n_0\
    );
\i__carry_i_7__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => p_1_in(2),
      I1 => \rc_64.wr_len_reg_n_0_[2]\,
      I2 => p_1_in(3),
      I3 => \rc_64.wr_len_reg_n_0_[3]\,
      O => \i__carry_i_7__1_n_0\
    );
\i__carry_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \rc_64.wr_len_reg_n_0_[0]\,
      I2 => p_1_in(1),
      I3 => \rc_64.wr_len_reg_n_0_[1]\,
      O => \i__carry_i_8__1_n_0\
    );
in_packet_q_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => in_packet_q_reg_0,
      Q => \^in_packet_q\,
      R => '0'
    );
\rc_64.current_dw_count[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA8A8"
    )
        port map (
      I0 => in23(0),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => current_dw_count(0),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.current_dw_count[0]_i_1_n_0\
    );
\rc_64.current_dw_count[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(10),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(10),
      O => \rc_64.current_dw_count[10]_i_1_n_0\
    );
\rc_64.current_dw_count[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(11),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(11),
      O => \rc_64.current_dw_count[11]_i_1_n_0\
    );
\rc_64.current_dw_count[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(1),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(1),
      O => \rc_64.current_dw_count[1]_i_1_n_0\
    );
\rc_64.current_dw_count[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(2),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(2),
      O => \rc_64.current_dw_count[2]_i_1_n_0\
    );
\rc_64.current_dw_count[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(3),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(3),
      O => \rc_64.current_dw_count[3]_i_1_n_0\
    );
\rc_64.current_dw_count[3]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => current_dw_count(1),
      O => \rc_64.current_dw_count[3]_i_3_n_0\
    );
\rc_64.current_dw_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(4),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(4),
      O => \rc_64.current_dw_count[4]_i_1_n_0\
    );
\rc_64.current_dw_count[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(5),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(5),
      O => \rc_64.current_dw_count[5]_i_1_n_0\
    );
\rc_64.current_dw_count[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(6),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(6),
      O => \rc_64.current_dw_count[6]_i_1_n_0\
    );
\rc_64.current_dw_count[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(7),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(7),
      O => \rc_64.current_dw_count[7]_i_1_n_0\
    );
\rc_64.current_dw_count[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(8),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(8),
      O => \rc_64.current_dw_count[8]_i_1_n_0\
    );
\rc_64.current_dw_count[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => in23(9),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I4 => in22(9),
      O => \rc_64.current_dw_count[9]_i_1_n_0\
    );
\rc_64.current_dw_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[0]_i_1_n_0\,
      Q => current_dw_count(0),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[10]_i_1_n_0\,
      Q => current_dw_count(10),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[11]_i_1_n_0\,
      Q => current_dw_count(11),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rc_64.current_dw_count_reg[7]_i_2_n_0\,
      CO(3) => \NLW_rc_64.current_dw_count_reg[11]_i_2_CO_UNCONNECTED\(3),
      CO(2) => \rc_64.current_dw_count_reg[11]_i_2_n_1\,
      CO(1) => \rc_64.current_dw_count_reg[11]_i_2_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in23(11 downto 8),
      S(3 downto 0) => current_dw_count(11 downto 8)
    );
\rc_64.current_dw_count_reg[11]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \rc_64.current_dw_count_reg[8]_i_2_n_0\,
      CO(3 downto 2) => \NLW_rc_64.current_dw_count_reg[11]_i_3_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \rc_64.current_dw_count_reg[11]_i_3_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[11]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_rc_64.current_dw_count_reg[11]_i_3_O_UNCONNECTED\(3),
      O(2 downto 0) => in22(11 downto 9),
      S(3) => '0',
      S(2 downto 0) => current_dw_count(11 downto 9)
    );
\rc_64.current_dw_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[1]_i_1_n_0\,
      Q => current_dw_count(1),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[2]_i_1_n_0\,
      Q => current_dw_count(2),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[3]_i_1_n_0\,
      Q => current_dw_count(3),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rc_64.current_dw_count_reg[3]_i_2_n_0\,
      CO(2) => \rc_64.current_dw_count_reg[3]_i_2_n_1\,
      CO(1) => \rc_64.current_dw_count_reg[3]_i_2_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => current_dw_count(1),
      DI(0) => '0',
      O(3 downto 0) => in23(3 downto 0),
      S(3 downto 2) => current_dw_count(3 downto 2),
      S(1) => \rc_64.current_dw_count[3]_i_3_n_0\,
      S(0) => current_dw_count(0)
    );
\rc_64.current_dw_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[4]_i_1_n_0\,
      Q => current_dw_count(4),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rc_64.current_dw_count_reg[4]_i_2_n_0\,
      CO(2) => \rc_64.current_dw_count_reg[4]_i_2_n_1\,
      CO(1) => \rc_64.current_dw_count_reg[4]_i_2_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[4]_i_2_n_3\,
      CYINIT => current_dw_count(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in22(4 downto 1),
      S(3 downto 0) => current_dw_count(4 downto 1)
    );
\rc_64.current_dw_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[5]_i_1_n_0\,
      Q => current_dw_count(5),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[6]_i_1_n_0\,
      Q => current_dw_count(6),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[7]_i_1_n_0\,
      Q => current_dw_count(7),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rc_64.current_dw_count_reg[3]_i_2_n_0\,
      CO(3) => \rc_64.current_dw_count_reg[7]_i_2_n_0\,
      CO(2) => \rc_64.current_dw_count_reg[7]_i_2_n_1\,
      CO(1) => \rc_64.current_dw_count_reg[7]_i_2_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in23(7 downto 4),
      S(3 downto 0) => current_dw_count(7 downto 4)
    );
\rc_64.current_dw_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[8]_i_1_n_0\,
      Q => current_dw_count(8),
      R => SR(0)
    );
\rc_64.current_dw_count_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rc_64.current_dw_count_reg[4]_i_2_n_0\,
      CO(3) => \rc_64.current_dw_count_reg[8]_i_2_n_0\,
      CO(2) => \rc_64.current_dw_count_reg[8]_i_2_n_1\,
      CO(1) => \rc_64.current_dw_count_reg[8]_i_2_n_2\,
      CO(0) => \rc_64.current_dw_count_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in22(8 downto 5),
      S(3 downto 0) => current_dw_count(8 downto 5)
    );
\rc_64.current_dw_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.current_dw_count[9]_i_1_n_0\,
      Q => current_dw_count(9),
      R => SR(0)
    );
\rc_64.wr_attr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_attr_reg[2]_0\(0),
      Q => in16(28),
      R => SR(0)
    );
\rc_64.wr_attr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_attr_reg[2]_0\(1),
      Q => in16(29),
      R => SR(0)
    );
\rc_64.wr_attr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_attr_reg[2]_0\(2),
      Q => in16(30),
      R => SR(0)
    );
\rc_64.wr_byte_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(0),
      Q => \rc_64.wr_byte_reg_n_0_[0]\,
      R => SR(0)
    );
\rc_64.wr_byte_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(10),
      Q => p_1_in(8),
      R => SR(0)
    );
\rc_64.wr_byte_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(11),
      Q => p_1_in(9),
      R => SR(0)
    );
\rc_64.wr_byte_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(1),
      Q => \rc_64.wr_byte_reg_n_0_[1]\,
      R => SR(0)
    );
\rc_64.wr_byte_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(2),
      Q => p_1_in(0),
      R => SR(0)
    );
\rc_64.wr_byte_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(3),
      Q => p_1_in(1),
      R => SR(0)
    );
\rc_64.wr_byte_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(4),
      Q => p_1_in(2),
      R => SR(0)
    );
\rc_64.wr_byte_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(5),
      Q => p_1_in(3),
      R => SR(0)
    );
\rc_64.wr_byte_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(6),
      Q => p_1_in(4),
      R => SR(0)
    );
\rc_64.wr_byte_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(7),
      Q => p_1_in(5),
      R => SR(0)
    );
\rc_64.wr_byte_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(8),
      Q => p_1_in(6),
      R => SR(0)
    );
\rc_64.wr_byte_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_byte_reg[11]_0\(9),
      Q => p_1_in(7),
      R => SR(0)
    );
\rc_64.wr_cid_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(0),
      Q => in16(8),
      R => SR(0)
    );
\rc_64.wr_cid_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(10),
      Q => in16(18),
      R => SR(0)
    );
\rc_64.wr_cid_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(11),
      Q => in16(19),
      R => SR(0)
    );
\rc_64.wr_cid_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(12),
      Q => in16(20),
      R => SR(0)
    );
\rc_64.wr_cid_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(13),
      Q => in16(21),
      R => SR(0)
    );
\rc_64.wr_cid_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(14),
      Q => in16(22),
      R => SR(0)
    );
\rc_64.wr_cid_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(15),
      Q => in16(23),
      R => SR(0)
    );
\rc_64.wr_cid_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(1),
      Q => in16(9),
      R => SR(0)
    );
\rc_64.wr_cid_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(2),
      Q => in16(10),
      R => SR(0)
    );
\rc_64.wr_cid_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(3),
      Q => in16(11),
      R => SR(0)
    );
\rc_64.wr_cid_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(4),
      Q => in16(12),
      R => SR(0)
    );
\rc_64.wr_cid_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(5),
      Q => in16(13),
      R => SR(0)
    );
\rc_64.wr_cid_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(6),
      Q => in16(14),
      R => SR(0)
    );
\rc_64.wr_cid_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(7),
      Q => in16(15),
      R => SR(0)
    );
\rc_64.wr_cid_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(8),
      Q => in16(16),
      R => SR(0)
    );
\rc_64.wr_cid_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_cid_reg[15]_0\(9),
      Q => in16(17),
      R => SR(0)
    );
\rc_64.wr_compl_status_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_compl_status_reg[2]_0\(0),
      Q => \rc_64.wr_compl_status_reg_n_0_[0]\,
      R => SR(0)
    );
\rc_64.wr_compl_status_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_compl_status_reg[2]_0\(1),
      Q => \rc_64.wr_compl_status_reg_n_0_[1]\,
      R => SR(0)
    );
\rc_64.wr_compl_status_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_compl_status_reg[2]_0\(2),
      Q => \rc_64.wr_compl_status_reg_n_0_[2]\,
      R => SR(0)
    );
\rc_64.wr_data[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(24),
      I3 => m_axis_tdata(56),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[0]_i_1_n_0\
    );
\rc_64.wr_data[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(18),
      I3 => m_axis_tdata(50),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[10]_i_1_n_0\
    );
\rc_64.wr_data[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(19),
      I3 => m_axis_tdata(51),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[11]_i_1_n_0\
    );
\rc_64.wr_data[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(20),
      I3 => m_axis_tdata(52),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[12]_i_1_n_0\
    );
\rc_64.wr_data[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(21),
      I3 => m_axis_tdata(53),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[13]_i_1_n_0\
    );
\rc_64.wr_data[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(22),
      I3 => m_axis_tdata(54),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[14]_i_1_n_0\
    );
\rc_64.wr_data[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(23),
      I3 => m_axis_tdata(55),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[15]_i_1_n_0\
    );
\rc_64.wr_data[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(8),
      I3 => m_axis_tdata(40),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[16]_i_1_n_0\
    );
\rc_64.wr_data[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(9),
      I3 => m_axis_tdata(41),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[17]_i_1_n_0\
    );
\rc_64.wr_data[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(10),
      I3 => m_axis_tdata(42),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[18]_i_1_n_0\
    );
\rc_64.wr_data[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(11),
      I3 => m_axis_tdata(43),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[19]_i_1_n_0\
    );
\rc_64.wr_data[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(25),
      I3 => m_axis_tdata(57),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[1]_i_1_n_0\
    );
\rc_64.wr_data[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(12),
      I3 => m_axis_tdata(44),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[20]_i_1_n_0\
    );
\rc_64.wr_data[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(13),
      I3 => m_axis_tdata(45),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[21]_i_1_n_0\
    );
\rc_64.wr_data[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(14),
      I3 => m_axis_tdata(46),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[22]_i_1_n_0\
    );
\rc_64.wr_data[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(15),
      I3 => m_axis_tdata(47),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[23]_i_1_n_0\
    );
\rc_64.wr_data[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(0),
      I3 => m_axis_tdata(32),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[24]_i_1_n_0\
    );
\rc_64.wr_data[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(1),
      I3 => m_axis_tdata(33),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[25]_i_1_n_0\
    );
\rc_64.wr_data[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(2),
      I3 => m_axis_tdata(34),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[26]_i_1_n_0\
    );
\rc_64.wr_data[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(3),
      I3 => m_axis_tdata(35),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[27]_i_1_n_0\
    );
\rc_64.wr_data[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(4),
      I3 => m_axis_tdata(36),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[28]_i_1_n_0\
    );
\rc_64.wr_data[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(5),
      I3 => m_axis_tdata(37),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[29]_i_1_n_0\
    );
\rc_64.wr_data[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(26),
      I3 => m_axis_tdata(58),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[2]_i_1_n_0\
    );
\rc_64.wr_data[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(6),
      I3 => m_axis_tdata(38),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[30]_i_1_n_0\
    );
\rc_64.wr_data[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(7),
      I3 => m_axis_tdata(39),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[31]_i_1_n_0\
    );
\rc_64.wr_data[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(56),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[32]_i_1_n_0\
    );
\rc_64.wr_data[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(57),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[33]_i_1_n_0\
    );
\rc_64.wr_data[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(58),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[34]_i_1_n_0\
    );
\rc_64.wr_data[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(59),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[35]_i_1_n_0\
    );
\rc_64.wr_data[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(60),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[36]_i_1_n_0\
    );
\rc_64.wr_data[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(61),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[37]_i_1_n_0\
    );
\rc_64.wr_data[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(62),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[38]_i_1_n_0\
    );
\rc_64.wr_data[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(63),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[39]_i_1_n_0\
    );
\rc_64.wr_data[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(27),
      I3 => m_axis_tdata(59),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[3]_i_1_n_0\
    );
\rc_64.wr_data[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(48),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[40]_i_1_n_0\
    );
\rc_64.wr_data[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(49),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[41]_i_1_n_0\
    );
\rc_64.wr_data[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(50),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[42]_i_1_n_0\
    );
\rc_64.wr_data[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(51),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[43]_i_1_n_0\
    );
\rc_64.wr_data[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(52),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[44]_i_1_n_0\
    );
\rc_64.wr_data[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(53),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[45]_i_1_n_0\
    );
\rc_64.wr_data[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(54),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[46]_i_1_n_0\
    );
\rc_64.wr_data[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(55),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[47]_i_1_n_0\
    );
\rc_64.wr_data[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(40),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[48]_i_1_n_0\
    );
\rc_64.wr_data[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(41),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[49]_i_1_n_0\
    );
\rc_64.wr_data[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(28),
      I3 => m_axis_tdata(60),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[4]_i_1_n_0\
    );
\rc_64.wr_data[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(42),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[50]_i_1_n_0\
    );
\rc_64.wr_data[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(43),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[51]_i_1_n_0\
    );
\rc_64.wr_data[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(44),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[52]_i_1_n_0\
    );
\rc_64.wr_data[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(45),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[53]_i_1_n_0\
    );
\rc_64.wr_data[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(46),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[54]_i_1_n_0\
    );
\rc_64.wr_data[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(47),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[55]_i_1_n_0\
    );
\rc_64.wr_data[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(32),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[56]_i_1_n_0\
    );
\rc_64.wr_data[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(33),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[57]_i_1_n_0\
    );
\rc_64.wr_data[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(34),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[58]_i_1_n_0\
    );
\rc_64.wr_data[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(35),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[59]_i_1_n_0\
    );
\rc_64.wr_data[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(29),
      I3 => m_axis_tdata(61),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[5]_i_1_n_0\
    );
\rc_64.wr_data[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(36),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[60]_i_1_n_0\
    );
\rc_64.wr_data[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(37),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[61]_i_1_n_0\
    );
\rc_64.wr_data[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(38),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[62]_i_1_n_0\
    );
\rc_64.wr_data[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => m_axis_tdata(39),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \rc_64.wr_data[63]_i_1_n_0\
    );
\rc_64.wr_data[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(30),
      I3 => m_axis_tdata(62),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[6]_i_1_n_0\
    );
\rc_64.wr_data[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(31),
      I3 => m_axis_tdata(63),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[7]_i_1_n_0\
    );
\rc_64.wr_data[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(16),
      I3 => m_axis_tdata(48),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[8]_i_1_n_0\
    );
\rc_64.wr_data[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE0E0E0"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => m_axis_tdata(17),
      I3 => m_axis_tdata(49),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_data[9]_i_1_n_0\
    );
\rc_64.wr_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[0]_i_1_n_0\,
      Q => in16(32),
      R => SR(0)
    );
\rc_64.wr_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[10]_i_1_n_0\,
      Q => in16(42),
      R => SR(0)
    );
\rc_64.wr_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[11]_i_1_n_0\,
      Q => in16(43),
      R => SR(0)
    );
\rc_64.wr_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[12]_i_1_n_0\,
      Q => in16(44),
      R => SR(0)
    );
\rc_64.wr_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[13]_i_1_n_0\,
      Q => in16(45),
      R => SR(0)
    );
\rc_64.wr_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[14]_i_1_n_0\,
      Q => in16(46),
      R => SR(0)
    );
\rc_64.wr_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[15]_i_1_n_0\,
      Q => in16(47),
      R => SR(0)
    );
\rc_64.wr_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[16]_i_1_n_0\,
      Q => in16(48),
      R => SR(0)
    );
\rc_64.wr_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[17]_i_1_n_0\,
      Q => in16(49),
      R => SR(0)
    );
\rc_64.wr_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[18]_i_1_n_0\,
      Q => in16(50),
      R => SR(0)
    );
\rc_64.wr_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[19]_i_1_n_0\,
      Q => in16(51),
      R => SR(0)
    );
\rc_64.wr_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[1]_i_1_n_0\,
      Q => in16(33),
      R => SR(0)
    );
\rc_64.wr_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[20]_i_1_n_0\,
      Q => in16(52),
      R => SR(0)
    );
\rc_64.wr_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[21]_i_1_n_0\,
      Q => in16(53),
      R => SR(0)
    );
\rc_64.wr_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[22]_i_1_n_0\,
      Q => in16(54),
      R => SR(0)
    );
\rc_64.wr_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[23]_i_1_n_0\,
      Q => in16(55),
      R => SR(0)
    );
\rc_64.wr_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[24]_i_1_n_0\,
      Q => in16(56),
      R => SR(0)
    );
\rc_64.wr_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[25]_i_1_n_0\,
      Q => in16(57),
      R => SR(0)
    );
\rc_64.wr_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[26]_i_1_n_0\,
      Q => in16(58),
      R => SR(0)
    );
\rc_64.wr_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[27]_i_1_n_0\,
      Q => in16(59),
      R => SR(0)
    );
\rc_64.wr_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[28]_i_1_n_0\,
      Q => in16(60),
      R => SR(0)
    );
\rc_64.wr_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[29]_i_1_n_0\,
      Q => in16(61),
      R => SR(0)
    );
\rc_64.wr_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[2]_i_1_n_0\,
      Q => in16(34),
      R => SR(0)
    );
\rc_64.wr_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[30]_i_1_n_0\,
      Q => in16(62),
      R => SR(0)
    );
\rc_64.wr_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[31]_i_1_n_0\,
      Q => in16(63),
      R => SR(0)
    );
\rc_64.wr_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[32]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[32]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[33]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[33]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[34]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[34]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[35]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[35]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[36]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[36]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[37]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[37]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[38]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[38]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[39]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[39]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[3]_i_1_n_0\,
      Q => in16(35),
      R => SR(0)
    );
\rc_64.wr_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[40]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[40]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[41]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[41]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[42]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[42]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[43]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[43]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[44]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[44]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[45]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[45]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[46]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[46]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[47]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[47]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[48]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[48]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[49]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[49]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[4]_i_1_n_0\,
      Q => in16(36),
      R => SR(0)
    );
\rc_64.wr_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[50]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[50]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[51]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[51]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[52]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[52]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[53]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[53]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[54]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[54]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[55]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[55]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[56]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[56]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[57]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[57]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[58]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[58]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[59]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[59]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[5]_i_1_n_0\,
      Q => in16(37),
      R => SR(0)
    );
\rc_64.wr_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[60]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[60]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[61]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[61]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[62]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[62]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[63]_i_1_n_0\,
      Q => \rc_64.wr_data_reg_n_0_[63]\,
      R => SR(0)
    );
\rc_64.wr_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[6]_i_1_n_0\,
      Q => in16(38),
      R => SR(0)
    );
\rc_64.wr_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[7]_i_1_n_0\,
      Q => in16(39),
      R => SR(0)
    );
\rc_64.wr_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[8]_i_1_n_0\,
      Q => in16(40),
      R => SR(0)
    );
\rc_64.wr_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \FSM_onehot_rc_64.state[4]_i_1_n_0\,
      D => \rc_64.wr_data[9]_i_1_n_0\,
      Q => in16(41),
      R => SR(0)
    );
\rc_64.wr_ep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFABFFFF00A80000"
    )
        port map (
      I0 => m_axis_tdata(14),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      I3 => \^in_packet_q\,
      I4 => m_axis_tvalid,
      I5 => \rc_64.wr_ep_reg_n_0\,
      O => \rc_64.wr_ep_i_1_n_0\
    );
\rc_64.wr_ep_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \rc_64.wr_ep_i_1_n_0\,
      Q => \rc_64.wr_ep_reg_n_0\,
      R => SR(0)
    );
\rc_64.wr_len[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      O => wr_tc
    );
\rc_64.wr_len_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(0),
      Q => \rc_64.wr_len_reg_n_0_[0]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(1),
      Q => \rc_64.wr_len_reg_n_0_[1]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(2),
      Q => \rc_64.wr_len_reg_n_0_[2]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(3),
      Q => \rc_64.wr_len_reg_n_0_[3]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(4),
      Q => \rc_64.wr_len_reg_n_0_[4]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(5),
      Q => \rc_64.wr_len_reg_n_0_[5]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(6),
      Q => \rc_64.wr_len_reg_n_0_[6]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(7),
      Q => \rc_64.wr_len_reg_n_0_[7]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(8),
      Q => \rc_64.wr_len_reg_n_0_[8]\,
      R => SR(0)
    );
\rc_64.wr_len_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => D(9),
      Q => \rc_64.wr_len_reg_n_0_[9]\,
      R => SR(0)
    );
\rc_64.wr_tag[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(8),
      O => \rc_64.wr_tag[0]_i_1_n_0\
    );
\rc_64.wr_tag[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(9),
      O => \rc_64.wr_tag[1]_i_1_n_0\
    );
\rc_64.wr_tag[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(10),
      O => \rc_64.wr_tag[2]_i_1_n_0\
    );
\rc_64.wr_tag[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(11),
      O => \rc_64.wr_tag[3]_i_1_n_0\
    );
\rc_64.wr_tag[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(12),
      O => \rc_64.wr_tag[4]_i_1_n_0\
    );
\rc_64.wr_tag[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(13),
      O => \rc_64.wr_tag[5]_i_1_n_0\
    );
\rc_64.wr_tag[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(14),
      O => \rc_64.wr_tag[6]_i_1_n_0\
    );
\rc_64.wr_tag[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[0]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      O => \rc_64.wr_tag[7]_i_1_n_0\
    );
\rc_64.wr_tag[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => m_axis_tdata(15),
      O => \rc_64.wr_tag[7]_i_2_n_0\
    );
\rc_64.wr_tag_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[0]_i_1_n_0\,
      Q => in16(0),
      R => SR(0)
    );
\rc_64.wr_tag_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[1]_i_1_n_0\,
      Q => in16(1),
      R => SR(0)
    );
\rc_64.wr_tag_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[2]_i_1_n_0\,
      Q => in16(2),
      R => SR(0)
    );
\rc_64.wr_tag_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[3]_i_1_n_0\,
      Q => in16(3),
      R => SR(0)
    );
\rc_64.wr_tag_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[4]_i_1_n_0\,
      Q => in16(4),
      R => SR(0)
    );
\rc_64.wr_tag_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[5]_i_1_n_0\,
      Q => in16(5),
      R => SR(0)
    );
\rc_64.wr_tag_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[6]_i_1_n_0\,
      Q => in16(6),
      R => SR(0)
    );
\rc_64.wr_tag_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \rc_64.wr_tag[7]_i_1_n_0\,
      D => \rc_64.wr_tag[7]_i_2_n_0\,
      Q => in16(7),
      R => SR(0)
    );
\rc_64.wr_tc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_tc_reg[2]_0\(0),
      Q => in16(25),
      R => SR(0)
    );
\rc_64.wr_tc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_tc_reg[2]_0\(1),
      Q => in16(26),
      R => SR(0)
    );
\rc_64.wr_tc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_tc,
      D => \rc_64.wr_tc_reg[2]_0\(2),
      Q => in16(27),
      R => SR(0)
    );
\s_axis_rc_tdata0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \s_axis_rc_tdata0_inferred__0/i__carry_n_0\,
      CO(2) => \s_axis_rc_tdata0_inferred__0/i__carry_n_1\,
      CO(1) => \s_axis_rc_tdata0_inferred__0/i__carry_n_2\,
      CO(0) => \s_axis_rc_tdata0_inferred__0/i__carry_n_3\,
      CYINIT => '1',
      DI(3) => \i__carry_i_1__0_n_0\,
      DI(2) => \i__carry_i_2__1_n_0\,
      DI(1) => \i__carry_i_3__1_n_0\,
      DI(0) => \i__carry_i_4__1_n_0\,
      O(3 downto 0) => \NLW_s_axis_rc_tdata0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5__0_n_0\,
      S(2) => \i__carry_i_6__1_n_0\,
      S(1) => \i__carry_i_7__1_n_0\,
      S(0) => \i__carry_i_8__1_n_0\
    );
\s_axis_rc_tdata0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \s_axis_rc_tdata0_inferred__0/i__carry_n_0\,
      CO(3 downto 1) => \NLW_s_axis_rc_tdata0_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => s_axis_rc_tdata0,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \i__carry__0_i_1__0_n_0\,
      O(3 downto 0) => \NLW_s_axis_rc_tdata0_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \i__carry__0_i_2_n_0\
    );
udma_wrapper_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[56]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(56),
      I4 => m_axis_tdata(24),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(56)
    );
udma_wrapper_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[55]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(55),
      I4 => m_axis_tdata(23),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(55)
    );
udma_wrapper_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[54]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(54),
      I4 => m_axis_tdata(22),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(54)
    );
udma_wrapper_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[53]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(53),
      I4 => m_axis_tdata(21),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(53)
    );
udma_wrapper_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[52]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(52),
      I4 => m_axis_tdata(20),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(52)
    );
udma_wrapper_i_15: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[51]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(51),
      I4 => m_axis_tdata(19),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(51)
    );
udma_wrapper_i_154: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I2 => udma_wrapper_i_155_n_0,
      I3 => SR(0),
      O => udma_wrapper_i_154_n_0
    );
udma_wrapper_i_155: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[0]\,
      I1 => \rc_64.wr_len_reg_n_0_[1]\,
      I2 => \FSM_onehot_rc_64.state[4]_i_3_n_0\,
      O => udma_wrapper_i_155_n_0
    );
udma_wrapper_i_156: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => udma_wrapper_i_155_n_0,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      O => udma_wrapper_i_156_n_0
    );
udma_wrapper_i_157: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \rc_64.wr_compl_status_reg_n_0_[2]\,
      I1 => \rc_64.wr_compl_status_reg_n_0_[0]\,
      I2 => \rc_64.wr_compl_status_reg_n_0_[1]\,
      O => udma_wrapper_i_157_n_0
    );
udma_wrapper_i_158: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008F8C"
    )
        port map (
      I0 => udma_wrapper_i_157_n_0,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I2 => udma_wrapper_i_155_n_0,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I4 => SR(0),
      O => udma_wrapper_i_158_n_0
    );
udma_wrapper_i_159: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => udma_wrapper_i_238_n_0,
      I1 => udma_wrapper_i_239_n_7,
      I2 => udma_wrapper_i_240_n_0,
      I3 => udma_wrapper_i_241_n_5,
      I4 => udma_wrapper_i_239_n_4,
      I5 => udma_wrapper_i_239_n_6,
      O => udma_wrapper_i_159_n_0
    );
udma_wrapper_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[50]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(50),
      I4 => m_axis_tdata(18),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(50)
    );
udma_wrapper_i_160: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      O => udma_wrapper_i_160_n_0
    );
udma_wrapper_i_161: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => udma_wrapper_i_161_n_0,
      CO(2) => udma_wrapper_i_161_n_1,
      CO(1) => udma_wrapper_i_161_n_2,
      CO(0) => udma_wrapper_i_161_n_3,
      CYINIT => '1',
      DI(3) => \rc_64.wr_len_reg_n_0_[3]\,
      DI(2) => \rc_64.wr_len_reg_n_0_[2]\,
      DI(1) => \rc_64.wr_len_reg_n_0_[1]\,
      DI(0) => \rc_64.wr_len_reg_n_0_[0]\,
      O(3) => udma_wrapper_i_161_n_4,
      O(2) => udma_wrapper_i_161_n_5,
      O(1) => udma_wrapper_i_161_n_6,
      O(0) => udma_wrapper_i_161_n_7,
      S(3) => udma_wrapper_i_242_n_0,
      S(2) => udma_wrapper_i_243_n_0,
      S(1) => udma_wrapper_i_244_n_0,
      S(0) => udma_wrapper_i_245_n_0
    );
udma_wrapper_i_162: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I1 => SR(0),
      O => udma_wrapper_i_162_n_0
    );
udma_wrapper_i_163: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000054"
    )
        port map (
      I0 => SR(0),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => udma_wrapper_i_239_n_7,
      I4 => udma_wrapper_i_161_n_5,
      I5 => udma_wrapper_i_161_n_4,
      O => udma_wrapper_i_163_n_0
    );
udma_wrapper_i_164: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => udma_wrapper_i_161_n_6,
      I1 => udma_wrapper_i_161_n_7,
      O => udma_wrapper_i_164_n_0
    );
udma_wrapper_i_165: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => udma_wrapper_i_240_n_0,
      I1 => udma_wrapper_i_241_n_5,
      I2 => udma_wrapper_i_239_n_4,
      I3 => udma_wrapper_i_239_n_6,
      O => udma_wrapper_i_165_n_0
    );
udma_wrapper_i_166: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008F88"
    )
        port map (
      I0 => udma_wrapper_i_157_n_0,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I2 => udma_wrapper_i_155_n_0,
      I3 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I4 => SR(0),
      O => udma_wrapper_i_166_n_0
    );
udma_wrapper_i_167: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000022F2"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => udma_wrapper_i_155_n_0,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      I3 => udma_wrapper_i_157_n_0,
      I4 => SR(0),
      O => udma_wrapper_i_167_n_0
    );
udma_wrapper_i_168: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => SR(0),
      O => udma_wrapper_i_168_n_0
    );
udma_wrapper_i_169: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state[3]_i_2_n_0\,
      I1 => udma_wrapper_i_239_n_6,
      I2 => udma_wrapper_i_239_n_4,
      I3 => udma_wrapper_i_241_n_5,
      I4 => udma_wrapper_i_240_n_0,
      O => udma_wrapper_i_169_n_0
    );
udma_wrapper_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[49]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(49),
      I4 => m_axis_tdata(17),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(49)
    );
udma_wrapper_i_18: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[48]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(48),
      I4 => m_axis_tdata(16),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(48)
    );
udma_wrapper_i_19: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(47),
      I1 => udma_wrapper_i_154_n_0,
      I2 => \rc_64.wr_data_reg_n_0_[47]\,
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(47)
    );
udma_wrapper_i_20: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[46]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(46),
      I4 => \rc_64.wr_ep_reg_n_0\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(46)
    );
udma_wrapper_i_21: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[45]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(45),
      I4 => \rc_64.wr_compl_status_reg_n_0_[2]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(45)
    );
udma_wrapper_i_22: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[44]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(44),
      I4 => \rc_64.wr_compl_status_reg_n_0_[1]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(44)
    );
udma_wrapper_i_23: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[43]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(43),
      I4 => \rc_64.wr_compl_status_reg_n_0_[0]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(43)
    );
udma_wrapper_i_238: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udma_wrapper_i_161_n_5,
      I1 => udma_wrapper_i_161_n_4,
      O => udma_wrapper_i_238_n_0
    );
udma_wrapper_i_239: unisim.vcomponents.CARRY4
     port map (
      CI => udma_wrapper_i_161_n_0,
      CO(3) => udma_wrapper_i_239_n_0,
      CO(2) => udma_wrapper_i_239_n_1,
      CO(1) => udma_wrapper_i_239_n_2,
      CO(0) => udma_wrapper_i_239_n_3,
      CYINIT => '0',
      DI(3) => \rc_64.wr_len_reg_n_0_[7]\,
      DI(2) => \rc_64.wr_len_reg_n_0_[6]\,
      DI(1) => \rc_64.wr_len_reg_n_0_[5]\,
      DI(0) => \rc_64.wr_len_reg_n_0_[4]\,
      O(3) => udma_wrapper_i_239_n_4,
      O(2) => udma_wrapper_i_239_n_5,
      O(1) => udma_wrapper_i_239_n_6,
      O(0) => udma_wrapper_i_239_n_7,
      S(3) => udma_wrapper_i_254_n_0,
      S(2) => udma_wrapper_i_255_n_0,
      S(1) => udma_wrapper_i_256_n_0,
      S(0) => udma_wrapper_i_257_n_0
    );
udma_wrapper_i_24: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(42),
      I1 => udma_wrapper_i_154_n_0,
      I2 => \rc_64.wr_data_reg_n_0_[42]\,
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(42)
    );
udma_wrapper_i_240: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => udma_wrapper_i_241_n_7,
      I1 => udma_wrapper_i_241_n_4,
      I2 => udma_wrapper_i_239_n_5,
      I3 => udma_wrapper_i_241_n_6,
      O => udma_wrapper_i_240_n_0
    );
udma_wrapper_i_241: unisim.vcomponents.CARRY4
     port map (
      CI => udma_wrapper_i_239_n_0,
      CO(3) => NLW_udma_wrapper_i_241_CO_UNCONNECTED(3),
      CO(2) => udma_wrapper_i_241_n_1,
      CO(1) => udma_wrapper_i_241_n_2,
      CO(0) => udma_wrapper_i_241_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \rc_64.wr_len_reg_n_0_[9]\,
      DI(0) => \rc_64.wr_len_reg_n_0_[8]\,
      O(3) => udma_wrapper_i_241_n_4,
      O(2) => udma_wrapper_i_241_n_5,
      O(1) => udma_wrapper_i_241_n_6,
      O(0) => udma_wrapper_i_241_n_7,
      S(3) => udma_wrapper_i_258_n_0,
      S(2) => udma_wrapper_i_259_n_0,
      S(1) => udma_wrapper_i_260_n_0,
      S(0) => udma_wrapper_i_261_n_0
    );
udma_wrapper_i_242: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[3]\,
      I1 => current_dw_count(3),
      O => udma_wrapper_i_242_n_0
    );
udma_wrapper_i_243: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[2]\,
      I1 => current_dw_count(2),
      O => udma_wrapper_i_243_n_0
    );
udma_wrapper_i_244: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[1]\,
      I1 => current_dw_count(1),
      O => udma_wrapper_i_244_n_0
    );
udma_wrapper_i_245: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[0]\,
      I1 => current_dw_count(0),
      O => udma_wrapper_i_245_n_0
    );
udma_wrapper_i_25: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[41]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(41),
      I4 => \rc_64.wr_len_reg_n_0_[9]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(41)
    );
udma_wrapper_i_254: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[7]\,
      I1 => current_dw_count(7),
      O => udma_wrapper_i_254_n_0
    );
udma_wrapper_i_255: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[6]\,
      I1 => current_dw_count(6),
      O => udma_wrapper_i_255_n_0
    );
udma_wrapper_i_256: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[5]\,
      I1 => current_dw_count(5),
      O => udma_wrapper_i_256_n_0
    );
udma_wrapper_i_257: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[4]\,
      I1 => current_dw_count(4),
      O => udma_wrapper_i_257_n_0
    );
udma_wrapper_i_258: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => current_dw_count(11),
      O => udma_wrapper_i_258_n_0
    );
udma_wrapper_i_259: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => current_dw_count(10),
      O => udma_wrapper_i_259_n_0
    );
udma_wrapper_i_26: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[40]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(40),
      I4 => \rc_64.wr_len_reg_n_0_[8]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(40)
    );
udma_wrapper_i_260: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[9]\,
      I1 => current_dw_count(9),
      O => udma_wrapper_i_260_n_0
    );
udma_wrapper_i_261: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rc_64.wr_len_reg_n_0_[8]\,
      I1 => current_dw_count(8),
      O => udma_wrapper_i_261_n_0
    );
udma_wrapper_i_27: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[39]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(39),
      I4 => \rc_64.wr_len_reg_n_0_[7]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(39)
    );
udma_wrapper_i_28: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[38]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(38),
      I4 => \rc_64.wr_len_reg_n_0_[6]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(38)
    );
udma_wrapper_i_29: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[37]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(37),
      I4 => \rc_64.wr_len_reg_n_0_[5]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(37)
    );
udma_wrapper_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[63]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(63),
      I4 => m_axis_tdata(31),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(63)
    );
udma_wrapper_i_30: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[36]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(36),
      I4 => \rc_64.wr_len_reg_n_0_[4]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(36)
    );
udma_wrapper_i_31: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[35]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(35),
      I4 => \rc_64.wr_len_reg_n_0_[3]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(35)
    );
udma_wrapper_i_32: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[34]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(34),
      I4 => \rc_64.wr_len_reg_n_0_[2]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(34)
    );
udma_wrapper_i_33: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[33]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(33),
      I4 => \rc_64.wr_len_reg_n_0_[1]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(33)
    );
udma_wrapper_i_34: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[32]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(32),
      I4 => \rc_64.wr_len_reg_n_0_[0]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(32)
    );
udma_wrapper_i_35: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44404040"
    )
        port map (
      I0 => SR(0),
      I1 => in16(63),
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I3 => udma_wrapper_i_155_n_0,
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      O => \s_axis_rc\\.tdata\(31)
    );
udma_wrapper_i_36: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(62),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(30),
      I4 => s_axis_rc_tdata0,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(30)
    );
udma_wrapper_i_37: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(29),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(61),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(29)
    );
udma_wrapper_i_38: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(28),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(60),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(28)
    );
udma_wrapper_i_39: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(59),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(27),
      I4 => p_1_in(9),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(27)
    );
udma_wrapper_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[62]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(62),
      I4 => m_axis_tdata(30),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(62)
    );
udma_wrapper_i_40: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(58),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(26),
      I4 => p_1_in(8),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(26)
    );
udma_wrapper_i_41: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(57),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(25),
      I4 => p_1_in(7),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(25)
    );
udma_wrapper_i_42: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F888"
    )
        port map (
      I0 => p_1_in(6),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I2 => udma_wrapper_i_156_n_0,
      I3 => in16(56),
      I4 => SR(0),
      O => \s_axis_rc\\.tdata\(24)
    );
udma_wrapper_i_43: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(55),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(23),
      I4 => p_1_in(5),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(23)
    );
udma_wrapper_i_44: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(54),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(22),
      I4 => p_1_in(4),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(22)
    );
udma_wrapper_i_45: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(53),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(21),
      I4 => p_1_in(3),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(21)
    );
udma_wrapper_i_46: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(52),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(20),
      I4 => p_1_in(2),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(20)
    );
udma_wrapper_i_47: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(51),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(19),
      I4 => p_1_in(1),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(19)
    );
udma_wrapper_i_48: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(50),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(18),
      I4 => p_1_in(0),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(18)
    );
udma_wrapper_i_49: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(49),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(17),
      I4 => \rc_64.wr_byte_reg_n_0_[1]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(17)
    );
udma_wrapper_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[61]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(61),
      I4 => m_axis_tdata(29),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(61)
    );
udma_wrapper_i_50: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(48),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(16),
      I4 => \rc_64.wr_byte_reg_n_0_[0]\,
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(16)
    );
udma_wrapper_i_51: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(15),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(47),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(15)
    );
udma_wrapper_i_52: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(14),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(46),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(14)
    );
udma_wrapper_i_53: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(45),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(13),
      I4 => \^s_axis_rc\\.tuser\(2),
      I5 => udma_wrapper_i_157_n_0,
      O => \s_axis_rc\\.tdata\(13)
    );
udma_wrapper_i_54: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(12),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(44),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(12)
    );
udma_wrapper_i_55: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(11),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(43),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(11)
    );
udma_wrapper_i_56: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(10),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(42),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(10)
    );
udma_wrapper_i_57: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(9),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(41),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(9)
    );
udma_wrapper_i_58: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(8),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(40),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(8)
    );
udma_wrapper_i_59: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => in16(7),
      I1 => udma_wrapper_i_154_n_0,
      I2 => in16(39),
      I3 => \^s_axis_rc\\.tuser\(0),
      O => \s_axis_rc\\.tdata\(7)
    );
udma_wrapper_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[60]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(60),
      I4 => m_axis_tdata(28),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(60)
    );
udma_wrapper_i_60: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(38),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(6),
      I4 => m_axis_tdata(6),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(6)
    );
udma_wrapper_i_61: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(37),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(5),
      I4 => m_axis_tdata(5),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(5)
    );
udma_wrapper_i_62: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(36),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(4),
      I4 => m_axis_tdata(4),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(4)
    );
udma_wrapper_i_63: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(35),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(3),
      I4 => m_axis_tdata(3),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(3)
    );
udma_wrapper_i_64: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(34),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(2),
      I4 => m_axis_tdata(2),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(2)
    );
udma_wrapper_i_65: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(33),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(1),
      I4 => m_axis_tdata(1),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(1)
    );
udma_wrapper_i_66: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => in16(32),
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(0),
      I4 => m_axis_tdata(0),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(0)
    );
udma_wrapper_i_67: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABAAABAAABAA"
    )
        port map (
      I0 => udma_wrapper_i_158_n_0,
      I1 => udma_wrapper_i_159_n_0,
      I2 => SR(0),
      I3 => udma_wrapper_i_160_n_0,
      I4 => udma_wrapper_i_161_n_7,
      I5 => udma_wrapper_i_161_n_6,
      O => \s_axis_rc\\.tlast\
    );
udma_wrapper_i_68: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF2222F222"
    )
        port map (
      I0 => udma_wrapper_i_162_n_0,
      I1 => udma_wrapper_i_155_n_0,
      I2 => udma_wrapper_i_163_n_0,
      I3 => udma_wrapper_i_164_n_0,
      I4 => udma_wrapper_i_165_n_0,
      I5 => udma_wrapper_i_166_n_0,
      O => \^s_axis_rc\\.tuser\(3)
    );
udma_wrapper_i_69: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I1 => SR(0),
      O => \^s_axis_rc\\.tuser\(2)
    );
udma_wrapper_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[59]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(59),
      I4 => m_axis_tdata(27),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(59)
    );
udma_wrapper_i_70: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF54545400"
    )
        port map (
      I0 => SR(0),
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => udma_wrapper_i_161_n_6,
      I4 => udma_wrapper_i_159_n_0,
      I5 => udma_wrapper_i_167_n_0,
      O => \^s_axis_rc\\.tuser\(1)
    );
udma_wrapper_i_71: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I1 => udma_wrapper_i_155_n_0,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I3 => SR(0),
      O => \^s_axis_rc\\.tuser\(0)
    );
udma_wrapper_i_72: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEAEEEE"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(2),
      I1 => udma_wrapper_i_168_n_0,
      I2 => udma_wrapper_i_169_n_0,
      I3 => udma_wrapper_i_161_n_6,
      I4 => udma_wrapper_i_161_n_7,
      I5 => udma_wrapper_i_167_n_0,
      O => \s_axis_rc\\.tkeep\(1)
    );
udma_wrapper_i_73: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF00FE"
    )
        port map (
      I0 => \FSM_onehot_rc_64.state_reg_n_0_[4]\,
      I1 => \FSM_onehot_rc_64.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_rc_64.state_reg_n_0_[1]\,
      I3 => SR(0),
      I4 => \FSM_onehot_rc_64.state_reg_n_0_[2]\,
      O => \s_axis_rc\\.tkeep\(0)
    );
udma_wrapper_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[58]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(58),
      I4 => m_axis_tdata(26),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(58)
    );
udma_wrapper_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \^s_axis_rc\\.tuser\(0),
      I1 => \rc_64.wr_data_reg_n_0_[57]\,
      I2 => udma_wrapper_i_154_n_0,
      I3 => in16(57),
      I4 => m_axis_tdata(25),
      I5 => \^s_axis_rc\\.tuser\(2),
      O => \s_axis_rc\\.tdata\(57)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_dma_req is
  port (
    \FSM_sequential_tx_64.state_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_tx_64.state_reg[0]_0\ : out STD_LOGIC;
    \Head_reg[2]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 21 downto 0 );
    D : out STD_LOGIC_VECTOR ( 46 downto 0 );
    \tx_64.req_4dw_reg_0\ : out STD_LOGIC;
    \tx_64.wr_data_reg[55]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \tx_64.req_4dw_reg_1\ : out STD_LOGIC;
    \tx_64.req_4dw_reg_2\ : out STD_LOGIC;
    \tx_64.req_4dw_reg_3\ : out STD_LOGIC;
    \Head_reg[36]\ : out STD_LOGIC;
    \tx_64.wr_data_reg[58]_0\ : out STD_LOGIC;
    \tx_64.wr_data_reg[52]_0\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[2]_1\ : out STD_LOGIC;
    \tx_64.req_addr_reg[35]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[36]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[37]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[38]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[40]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[41]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[42]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[43]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[44]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[46]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[50]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[52]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[53]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[54]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[62]_0\ : out STD_LOGIC;
    \Head_reg[56]\ : out STD_LOGIC;
    \Head_reg[56]_0\ : out STD_LOGIC;
    \Head_reg[56]_1\ : out STD_LOGIC;
    \Head_reg[56]_2\ : out STD_LOGIC;
    \Head_reg[56]_3\ : out STD_LOGIC;
    \Head_reg[56]_4\ : out STD_LOGIC;
    \Head_reg[56]_5\ : out STD_LOGIC;
    \Head_reg[56]_6\ : out STD_LOGIC;
    \Head_reg[56]_7\ : out STD_LOGIC;
    \Head_reg[56]_8\ : out STD_LOGIC;
    \Head_reg[56]_9\ : out STD_LOGIC;
    \Head_reg[56]_10\ : out STD_LOGIC;
    \Head_reg[56]_11\ : out STD_LOGIC;
    \Head_reg[56]_12\ : out STD_LOGIC;
    \Head_reg[56]_13\ : out STD_LOGIC;
    \Head_reg[56]_14\ : out STD_LOGIC;
    s_axis_tx_req_tvalid : out STD_LOGIC;
    \m_axis_rq\\.tready\ : out STD_LOGIC;
    s_axis_tx_req_tlast : out STD_LOGIC;
    \tx_64.req_addr_reg[57]_0\ : out STD_LOGIC;
    \tx_64.req_addr_reg[59]_0\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[2]_2\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[2]_3\ : out STD_LOGIC;
    \tx_64.seq_num_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_out : in STD_LOGIC;
    \s_axis_tx_tkeep_reg[7]\ : in STD_LOGIC;
    \s_axis_tx_tkeep_reg[7]_0\ : in STD_LOGIC;
    \s_axis_tx_tkeep_reg[7]_1\ : in STD_LOGIC;
    s_axis_tx_req_tready : in STD_LOGIC;
    \m_axis_rq\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    transfer_SM : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_tx_tready : in STD_LOGIC;
    \s_axis_tx_tdata[30]_i_2_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[2]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[7]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[29]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[15]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[16]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[17]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[19]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[23]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[24]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[25]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[26]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[27]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[28]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[31]\ : in STD_LOGIC;
    \m_axis_cc\\.tdata\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
    \s_axis_tx_tdata_reg[34]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[34]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[35]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[36]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[37]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[38]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[39]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[40]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[41]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[42]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[43]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[45]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[46]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[47]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[0]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[1]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[2]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[48]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[48]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[49]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[49]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[50]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[50]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[51]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[51]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[52]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[52]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[53]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[53]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[54]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[54]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[55]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[55]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[56]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[56]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[57]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[57]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[58]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[58]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[59]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[59]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[60]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[60]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[61]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[61]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[62]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[62]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[63]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[63]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[29]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[32]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[33]\ : in STD_LOGIC;
    s_axis_tx_tgt_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
    \s_axis_tx_tdata_reg[25]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[27]_0\ : in STD_LOGIC;
    cfg_function_number_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_device_number_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_bus_number_o : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \m_axis_rq\\.tvalid\ : in STD_LOGIC;
    \m_axis_rq\\.tlast\ : in STD_LOGIC;
    \m_axis_rq\\.tuser\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_dma_req : entity is "xdma_0_dma_req";
end xdma_0_xdma_0_dma_req;

architecture STRUCTURE of xdma_0_xdma_0_dma_req is
  signal \FSM_sequential_tx_64.state[0]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_20_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_21_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_22_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_23_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_24_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_25_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_26_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_27_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_28_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_29_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_30_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_31_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_32_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_33_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_34_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_35_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_36_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_37_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_38_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_39_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[2]_i_9_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_tx_64.state_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^fsm_sequential_tx_64.state_reg[2]_1\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_1\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_4\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_14_n_7\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_15_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_15_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_15_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_15_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_15_n_7\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_1\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_4\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_16_n_7\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_17_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_17_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_17_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_17_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_17_n_7\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_1\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_4\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_18_n_7\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_1\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_2\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_3\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_4\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_5\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_6\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state_reg[2]_i_19_n_7\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal current_dw_count : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal dw_count : STD_LOGIC_VECTOR ( 10 downto 1 );
  signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_1_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_4_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__0_n_0\ : STD_LOGIC;
  signal \in26__0\ : STD_LOGIC_VECTOR ( 6 downto 4 );
  signal \in28__0\ : STD_LOGIC_VECTOR ( 10 downto 3 );
  signal in_packet_q : STD_LOGIC;
  signal \in_packet_q_i_1__0_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 55 downto 0 );
  signal p_0_out : STD_LOGIC_VECTOR ( 39 downto 10 );
  signal req_at : STD_LOGIC;
  signal req_len : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \s_axis_tx_tdata[0]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[10]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[11]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[12]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[13]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[13]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[13]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[13]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[13]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[14]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[15]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[15]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[16]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[16]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[17]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[17]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[18]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[19]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[19]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[1]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[20]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[21]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[22]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[23]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[23]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[24]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[24]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[25]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[26]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[26]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[27]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[28]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[28]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[29]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[2]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_10_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_8_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[31]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[31]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[31]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[32]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[32]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[33]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[33]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[34]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[35]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[36]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[37]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[38]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[39]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[3]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[40]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[41]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[42]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[43]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[45]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[46]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[47]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[47]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[48]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[49]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[4]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[50]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[51]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[52]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[53]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[54]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[55]_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[56]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[57]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[58]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[59]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[5]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[60]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[61]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[62]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[63]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[63]_i_9_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[6]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[7]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[8]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[9]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_1\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_4\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_5\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_6\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__0_n_7\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_n_5\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_n_6\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry__1_n_7\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_1_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_i_8_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_1\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_4\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_5\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_6\ : STD_LOGIC;
  signal \s_axis_tx_tkeep2__0_carry_n_7\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_10_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_11_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_14_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_16_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_17_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_18_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_19_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_20_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_21_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_22_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_23_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_24_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_25_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_26_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_8_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep[7]_i_9_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_12_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_12_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_13_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_13_n_1\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_13_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_13_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_15_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_15_n_1\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_15_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tkeep_reg[7]_i_15_n_3\ : STD_LOGIC;
  signal \s_axis_tx_tlast0_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tlast0_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \s_axis_tx_tlast0_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \s_axis_tx_tlast0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 10 downto 1 );
  signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \state2_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \state2_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \state2_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \state2_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \state2_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \state2_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal state3_i_1_n_0 : STD_LOGIC;
  signal \state3_inferred__0/i__n_0\ : STD_LOGIC;
  signal state3_n_0 : STD_LOGIC;
  signal \tx_64.current_dw_count[10]_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[10]_i_3_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[10]_i_4_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[10]_i_6_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[5]_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[6]_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[8]_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[8]_i_3_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count[9]_i_3_n_0\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.current_dw_count_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_64.dw_count[10]_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.dw_count[10]_i_3_n_0\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.dw_count_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_3_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_4_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_5_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_6_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_7_n_0\ : STD_LOGIC;
  signal \tx_64.req_4dw_i_8_n_0\ : STD_LOGIC;
  signal \^tx_64.req_4dw_reg_0\ : STD_LOGIC;
  signal \^tx_64.req_4dw_reg_2\ : STD_LOGIC;
  signal \^tx_64.req_4dw_reg_3\ : STD_LOGIC;
  signal \tx_64.req_4dw_reg_n_0\ : STD_LOGIC;
  signal \tx_64.req_len[9]_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[9]\ : STD_LOGIC;
  signal \^tx_64.wr_data_reg[55]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal udma_wrapper_i_253_n_0 : STD_LOGIC;
  signal udma_wrapper_i_263_n_0 : STD_LOGIC;
  signal udma_wrapper_i_264_n_0 : STD_LOGIC;
  signal wr_data : STD_LOGIC;
  signal wreq_data_le : STD_LOGIC_VECTOR ( 62 downto 0 );
  signal \NLW_FSM_sequential_tx_64.state_reg[2]_i_15_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_FSM_sequential_tx_64.state_reg[2]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_FSM_sequential_tx_64.state_reg[2]_i_17_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_FSM_sequential_tx_64.state_reg[2]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_s_axis_tx_tkeep2__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_s_axis_tx_tkeep2__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_s_axis_tx_tkeep_reg[7]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_s_axis_tx_tkeep_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_s_axis_tx_tkeep_reg[7]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_s_axis_tx_tlast0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state2_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state2_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_state2_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[0]_i_10\ : label is "soft_lutpair2013";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[0]_i_11\ : label is "soft_lutpair2024";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[0]_i_6\ : label is "soft_lutpair2001";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[0]_i_7\ : label is "soft_lutpair2022";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[1]_i_10\ : label is "soft_lutpair2022";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[1]_i_8\ : label is "soft_lutpair2003";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[0]\ : label is "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[1]\ : label is "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[2]\ : label is "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_14\ : label is 35;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_15\ : label is 35;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_16\ : label is 35;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_17\ : label is 35;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_18\ : label is 35;
  attribute ADDER_THRESHOLD of \FSM_sequential_tx_64.state_reg[2]_i_19\ : label is 35;
  attribute SOFT_HLUTNM of \i__carry_i_10\ : label is "soft_lutpair2006";
  attribute SOFT_HLUTNM of \i__carry_i_6\ : label is "soft_lutpair2017";
  attribute SOFT_HLUTNM of \i__carry_i_7\ : label is "soft_lutpair2017";
  attribute SOFT_HLUTNM of \i__carry_i_8\ : label is "soft_lutpair2002";
  attribute SOFT_HLUTNM of \i__carry_i_9\ : label is "soft_lutpair2006";
  attribute SOFT_HLUTNM of \in_packet_q_i_1__0\ : label is "soft_lutpair2013";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[13]_i_4\ : label is "soft_lutpair2009";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[13]_i_6\ : label is "soft_lutpair2021";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[29]_i_2\ : label is "soft_lutpair2007";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[2]_i_6\ : label is "soft_lutpair2010";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[30]_i_10\ : label is "soft_lutpair2021";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[30]_i_5\ : label is "soft_lutpair2015";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[30]_i_6\ : label is "soft_lutpair2019";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[30]_i_8\ : label is "soft_lutpair2003";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[31]_i_2\ : label is "soft_lutpair2010";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[47]_i_2\ : label is "soft_lutpair2008";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[47]_i_6\ : label is "soft_lutpair2007";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[55]_i_3\ : label is "soft_lutpair2008";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[63]_i_4\ : label is "soft_lutpair2009";
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep2__0_carry\ : label is 35;
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep2__0_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep2__0_carry__1\ : label is 35;
  attribute SOFT_HLUTNM of \s_axis_tx_tkeep[7]_i_4\ : label is "soft_lutpair2004";
  attribute SOFT_HLUTNM of \s_axis_tx_tkeep[7]_i_7\ : label is "soft_lutpair2018";
  attribute SOFT_HLUTNM of \s_axis_tx_tkeep[7]_i_8\ : label is "soft_lutpair2018";
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep_reg[7]_i_12\ : label is 35;
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep_reg[7]_i_13\ : label is 35;
  attribute ADDER_THRESHOLD of \s_axis_tx_tkeep_reg[7]_i_15\ : label is 35;
  attribute SOFT_HLUTNM of s_axis_tx_tlast_i_2 : label is "soft_lutpair2016";
  attribute SOFT_HLUTNM of s_axis_tx_tvalid_i_2 : label is "soft_lutpair2005";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \state2_inferred__0/i__carry\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \state2_inferred__0/i__carry__0\ : label is 11;
  attribute SOFT_HLUTNM of state3_i_1 : label is "soft_lutpair2002";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[0]_i_1\ : label is "soft_lutpair2015";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[10]_i_3\ : label is "soft_lutpair2019";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[10]_i_4\ : label is "soft_lutpair2020";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[10]_i_5\ : label is "soft_lutpair2011";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[10]_i_6\ : label is "soft_lutpair2023";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[8]_i_2\ : label is "soft_lutpair2020";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[9]_i_2\ : label is "soft_lutpair2011";
  attribute SOFT_HLUTNM of \tx_64.current_dw_count[9]_i_3\ : label is "soft_lutpair2004";
  attribute SOFT_HLUTNM of \tx_64.dw_count[1]_i_1\ : label is "soft_lutpair2024";
  attribute SOFT_HLUTNM of \tx_64.dw_count[2]_i_1\ : label is "soft_lutpair2014";
  attribute SOFT_HLUTNM of \tx_64.dw_count[3]_i_1\ : label is "soft_lutpair2014";
  attribute SOFT_HLUTNM of \tx_64.dw_count[6]_i_1\ : label is "soft_lutpair2023";
  attribute SOFT_HLUTNM of \tx_64.dw_count[7]_i_1\ : label is "soft_lutpair2012";
  attribute SOFT_HLUTNM of \tx_64.dw_count[8]_i_1\ : label is "soft_lutpair2012";
  attribute SOFT_HLUTNM of \tx_64.req_len[0]_i_1__0\ : label is "soft_lutpair2025";
  attribute SOFT_HLUTNM of \tx_64.req_len[1]_i_1__0\ : label is "soft_lutpair2025";
  attribute SOFT_HLUTNM of \tx_64.req_len[2]_i_1__0\ : label is "soft_lutpair2026";
  attribute SOFT_HLUTNM of \tx_64.req_len[3]_i_1__0\ : label is "soft_lutpair2026";
  attribute SOFT_HLUTNM of \tx_64.req_len[4]_i_1__0\ : label is "soft_lutpair2027";
  attribute SOFT_HLUTNM of \tx_64.req_len[5]_i_1__0\ : label is "soft_lutpair2027";
  attribute SOFT_HLUTNM of \tx_64.req_len[6]_i_1__0\ : label is "soft_lutpair2028";
  attribute SOFT_HLUTNM of \tx_64.req_len[7]_i_1__0\ : label is "soft_lutpair2028";
  attribute SOFT_HLUTNM of \tx_64.req_len[8]_i_1__0\ : label is "soft_lutpair2029";
  attribute SOFT_HLUTNM of \tx_64.req_len[9]_i_2\ : label is "soft_lutpair2029";
  attribute SOFT_HLUTNM of udma_wrapper_i_1 : label is "soft_lutpair2005";
  attribute SOFT_HLUTNM of udma_wrapper_i_237 : label is "soft_lutpair2016";
  attribute SOFT_HLUTNM of udma_wrapper_i_253 : label is "soft_lutpair2001";
begin
  \FSM_sequential_tx_64.state_reg[2]_0\(0) <= \^fsm_sequential_tx_64.state_reg[2]_0\(0);
  \FSM_sequential_tx_64.state_reg[2]_1\ <= \^fsm_sequential_tx_64.state_reg[2]_1\;
  Q(21 downto 0) <= \^q\(21 downto 0);
  \tx_64.req_4dw_reg_0\ <= \^tx_64.req_4dw_reg_0\;
  \tx_64.req_4dw_reg_2\ <= \^tx_64.req_4dw_reg_2\;
  \tx_64.req_4dw_reg_3\ <= \^tx_64.req_4dw_reg_3\;
  \tx_64.wr_data_reg[55]_0\(9 downto 0) <= \^tx_64.wr_data_reg[55]_0\(9 downto 0);
\FSM_sequential_tx_64.state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF04FFFFFF040000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[0]_i_2_n_0\,
      I1 => \FSM_sequential_tx_64.state[0]_i_3_n_0\,
      I2 => \FSM_sequential_tx_64.state[0]_i_4_n_0\,
      I3 => \FSM_sequential_tx_64.state[0]_i_5_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_6_n_0\,
      I5 => state(0),
      O => \FSM_sequential_tx_64.state[0]_i_1_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => in_packet_q,
      I1 => \m_axis_rq\\.tvalid\,
      O => \FSM_sequential_tx_64.state[0]_i_10_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      O => \FSM_sequential_tx_64.state[0]_i_11_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00FF0C5500FF"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[0]_i_6_n_0\,
      I1 => \state2_inferred__0/i__carry__0_n_2\,
      I2 => \FSM_sequential_tx_64.state[0]_i_7_n_0\,
      I3 => state(0),
      I4 => s_axis_tx_req_tready,
      I5 => \FSM_sequential_tx_64.state[0]_i_8_n_0\,
      O => \FSM_sequential_tx_64.state[0]_i_2_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEE0"
    )
        port map (
      I0 => state(0),
      I1 => state(1),
      I2 => \FSM_sequential_tx_64.state[1]_i_6_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I5 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      O => \FSM_sequential_tx_64.state[0]_i_3_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[2]_i_10_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_11_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_12_n_0\,
      I3 => s_axis_tx_req_tready,
      I4 => \FSM_sequential_tx_64.state[1]_i_10_n_0\,
      I5 => \FSM_sequential_tx_64.state[0]_i_9_n_0\,
      O => \FSM_sequential_tx_64.state[0]_i_4_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1111111111111110"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[0]_i_10_n_0\,
      I1 => \FSM_sequential_tx_64.state[0]_i_11_n_0\,
      I2 => \FSM_sequential_tx_64.state[1]_i_6_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I5 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      O => \FSM_sequential_tx_64.state[0]_i_5_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      I1 => \tx_64.req_len_reg_n_0_[1]\,
      I2 => udma_wrapper_i_263_n_0,
      O => \FSM_sequential_tx_64.state[0]_i_6_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => state(1),
      O => \FSM_sequential_tx_64.state[0]_i_7_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => \s_axis_tx_tkeep[7]_i_7_n_0\,
      I2 => \m_axis_rq\\.tdata\(13),
      I3 => \m_axis_rq\\.tdata\(14),
      I4 => \m_axis_rq\\.tdata\(12),
      I5 => \m_axis_rq\\.tdata\(11),
      O => \FSM_sequential_tx_64.state[0]_i_8_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A00000000000000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => in_packet_q,
      I2 => \m_axis_rq\\.tvalid\,
      I3 => transfer_SM(0),
      I4 => s_axis_tx_tready,
      I5 => transfer_SM(1),
      O => \FSM_sequential_tx_64.state[0]_i_9_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFFFFFEEE0000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[1]_i_2__0_n_0\,
      I1 => \FSM_sequential_tx_64.state[1]_i_3_n_0\,
      I2 => \FSM_sequential_tx_64.state[1]_i_4_n_0\,
      I3 => \FSM_sequential_tx_64.state[1]_i_5_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_6_n_0\,
      I5 => state(1),
      O => \FSM_sequential_tx_64.state[1]_i_1_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => state(1),
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => state(0),
      O => \FSM_sequential_tx_64.state[1]_i_10_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE000000000000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      I3 => \FSM_sequential_tx_64.state[1]_i_6_n_0\,
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => \FSM_sequential_tx_64.state[1]_i_7_n_0\,
      O => \FSM_sequential_tx_64.state[1]_i_2__0_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[1]_i_8_n_0\,
      I1 => \FSM_sequential_tx_64.state[1]_i_6_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      O => \FSM_sequential_tx_64.state[1]_i_3_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFFAAAA"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[1]_i_9_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_10_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_11_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_12_n_0\,
      I4 => \FSM_sequential_tx_64.state[1]_i_10_n_0\,
      O => \FSM_sequential_tx_64.state[1]_i_4_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FFFE"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[1]_i_6_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => \FSM_sequential_tx_64.state[1]_i_5_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7FFFFFFF"
    )
        port map (
      I0 => transfer_SM(1),
      I1 => s_axis_tx_tready,
      I2 => transfer_SM(0),
      I3 => state(0),
      I4 => state(1),
      I5 => \tx_64.req_4dw_reg_n_0\,
      O => \FSM_sequential_tx_64.state[1]_i_6_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5540FFFF"
    )
        port map (
      I0 => state(0),
      I1 => \tx_64.req_len_reg_n_0_[0]\,
      I2 => \tx_64.req_len_reg_n_0_[1]\,
      I3 => udma_wrapper_i_263_n_0,
      I4 => s_axis_tx_req_tready,
      O => \FSM_sequential_tx_64.state[1]_i_7_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => \state2_inferred__0/i__carry__0_n_2\,
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => state(1),
      I3 => state(0),
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => \FSM_sequential_tx_64.state[1]_i_8_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000800000000"
    )
        port map (
      I0 => \s_axis_tx_tkeep[7]_i_7_n_0\,
      I1 => s_axis_tx_req_tready,
      I2 => \m_axis_rq\\.tdata\(13),
      I3 => \m_axis_rq\\.tdata\(14),
      I4 => \m_axis_rq\\.tdata\(12),
      I5 => \m_axis_rq\\.tdata\(11),
      O => \FSM_sequential_tx_64.state[1]_i_9_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFE0FFFFFFE00000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[2]_i_2_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_3_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_4_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_5_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_6_n_0\,
      I5 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => \FSM_sequential_tx_64.state[2]_i_1_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_17_n_7\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_18_n_4\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_18_n_5\,
      I3 => \FSM_sequential_tx_64.state_reg[2]_i_18_n_6\,
      O => \FSM_sequential_tx_64.state[2]_i_10_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0007"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_19_n_7\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_19_n_6\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_17_n_5\,
      I3 => \FSM_sequential_tx_64.state_reg[2]_i_17_n_6\,
      O => \FSM_sequential_tx_64.state[2]_i_11_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_18_n_7\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_19_n_4\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_19_n_5\,
      O => \FSM_sequential_tx_64.state[2]_i_12_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAA00300000"
    )
        port map (
      I0 => \s_axis_tx_tdata[30]_i_2_0\,
      I1 => \tx_64.req_len_reg_n_0_[0]\,
      I2 => \tx_64.req_len_reg_n_0_[1]\,
      I3 => udma_wrapper_i_263_n_0,
      I4 => state(1),
      I5 => state(0),
      O => \FSM_sequential_tx_64.state[2]_i_13_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \state2_inferred__0/i__carry__0_n_2\,
      I1 => state(0),
      I2 => \tx_64.req_4dw_reg_n_0\,
      I3 => \FSM_sequential_tx_64.state[2]_i_7_n_0\,
      I4 => \FSM_sequential_tx_64.state[2]_i_8_n_0\,
      I5 => \FSM_sequential_tx_64.state[2]_i_9_n_0\,
      O => \FSM_sequential_tx_64.state[2]_i_2_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_20\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \tx_64.dw_count_reg_n_0_[3]\,
      I2 => \tx_64.dw_count_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[1]\,
      O => \FSM_sequential_tx_64.state[2]_i_20_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[2]\,
      I1 => \tx_64.dw_count_reg_n_0_[2]\,
      I2 => \tx_64.dw_count_reg_n_0_[1]\,
      O => \FSM_sequential_tx_64.state[2]_i_21_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_22\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      O => \FSM_sequential_tx_64.state[2]_i_22_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55955555"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[10]\,
      I1 => \tx_64.dw_count_reg_n_0_[9]\,
      I2 => \tx_64.dw_count_reg_n_0_[8]\,
      I3 => \tx_64.dw_count[10]_i_3_n_0\,
      I4 => \tx_64.dw_count_reg_n_0_[7]\,
      O => \FSM_sequential_tx_64.state[2]_i_23_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DF2020DF"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[8]\,
      I1 => \tx_64.dw_count[10]_i_3_n_0\,
      I2 => \tx_64.dw_count_reg_n_0_[7]\,
      I3 => \tx_64.dw_count_reg_n_0_[9]\,
      I4 => \tx_64.req_len_reg_n_0_[9]\,
      O => \FSM_sequential_tx_64.state[2]_i_24_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[7]\,
      I1 => \tx_64.dw_count[10]_i_3_n_0\,
      I2 => \tx_64.dw_count_reg_n_0_[8]\,
      I3 => \tx_64.req_len_reg_n_0_[8]\,
      O => \FSM_sequential_tx_64.state[2]_i_25_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \tx_64.dw_count[10]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[7]\,
      I2 => \tx_64.req_len_reg_n_0_[7]\,
      O => \FSM_sequential_tx_64.state[2]_i_26_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[6]\,
      I1 => \in26__0\(6),
      O => \FSM_sequential_tx_64.state[2]_i_27_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6999999999999999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[5]\,
      I1 => \tx_64.dw_count_reg_n_0_[5]\,
      I2 => \tx_64.dw_count_reg_n_0_[3]\,
      I3 => \tx_64.dw_count_reg_n_0_[2]\,
      I4 => \tx_64.dw_count_reg_n_0_[1]\,
      I5 => \tx_64.dw_count_reg_n_0_[4]\,
      O => \FSM_sequential_tx_64.state[2]_i_28_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69999999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[4]\,
      I1 => \tx_64.dw_count_reg_n_0_[4]\,
      I2 => \tx_64.dw_count_reg_n_0_[1]\,
      I3 => \tx_64.dw_count_reg_n_0_[2]\,
      I4 => \tx_64.dw_count_reg_n_0_[3]\,
      O => \FSM_sequential_tx_64.state[2]_i_29_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state[2]_i_10_n_0\,
      I1 => \FSM_sequential_tx_64.state[2]_i_11_n_0\,
      I2 => \FSM_sequential_tx_64.state[2]_i_12_n_0\,
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => state(0),
      I5 => \FSM_sequential_tx_64.state[2]_i_13_n_0\,
      O => \FSM_sequential_tx_64.state[2]_i_3_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"65555555"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[10]\,
      I1 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[9]\,
      O => \FSM_sequential_tx_64.state[2]_i_30_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_31\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99996999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[9]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I4 => \tx_64.current_dw_count[8]_i_3_n_0\,
      O => \FSM_sequential_tx_64.state[2]_i_31_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9699"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[8]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I2 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I3 => \tx_64.current_dw_count_reg_n_0_[7]\,
      O => \FSM_sequential_tx_64.state[2]_i_32_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[7]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I2 => \tx_64.current_dw_count[8]_i_3_n_0\,
      O => \FSM_sequential_tx_64.state[2]_i_33_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6999999999999999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[5]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[5]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I5 => \tx_64.current_dw_count_reg_n_0_[4]\,
      O => \FSM_sequential_tx_64.state[2]_i_34_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_35\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69999999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[4]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => \FSM_sequential_tx_64.state[2]_i_35_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6999"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[1]\,
      O => \FSM_sequential_tx_64.state[2]_i_36_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[2]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      O => \FSM_sequential_tx_64.state[2]_i_37_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[1]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[1]\,
      O => \FSM_sequential_tx_64.state[2]_i_38_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      O => \FSM_sequential_tx_64.state[2]_i_39_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080008000800000"
    )
        port map (
      I0 => transfer_SM(0),
      I1 => s_axis_tx_tready,
      I2 => transfer_SM(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(1),
      I5 => \FSM_sequential_tx_64.state[2]_i_13_n_0\,
      O => \FSM_sequential_tx_64.state[2]_i_4_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08888888"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(0),
      I2 => transfer_SM(0),
      I3 => s_axis_tx_tready,
      I4 => transfer_SM(1),
      O => \FSM_sequential_tx_64.state[2]_i_5_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F5D5D5D5D5D5D5D"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(0),
      I2 => state(1),
      I3 => transfer_SM(1),
      I4 => s_axis_tx_tready,
      I5 => transfer_SM(0),
      O => \FSM_sequential_tx_64.state[2]_i_6_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_14_n_4\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_14_n_7\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_15_n_6\,
      I3 => \FSM_sequential_tx_64.state_reg[2]_i_14_n_5\,
      O => \FSM_sequential_tx_64.state[2]_i_7_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_15_n_5\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_15_n_7\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_16_n_7\,
      I3 => \FSM_sequential_tx_64.state_reg[2]_i_16_n_6\,
      O => \FSM_sequential_tx_64.state[2]_i_8_n_0\
    );
\FSM_sequential_tx_64.state[2]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[2]_i_16_n_5\,
      I1 => \FSM_sequential_tx_64.state_reg[2]_i_16_n_4\,
      I2 => \FSM_sequential_tx_64.state_reg[2]_i_14_n_6\,
      O => \FSM_sequential_tx_64.state[2]_i_9_n_0\
    );
\FSM_sequential_tx_64.state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_tx_64.state[0]_i_1_n_0\,
      Q => state(0),
      R => SR(0)
    );
\FSM_sequential_tx_64.state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_tx_64.state[1]_i_1_n_0\,
      Q => state(1),
      R => SR(0)
    );
\FSM_sequential_tx_64.state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_tx_64.state[2]_i_1_n_0\,
      Q => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      R => SR(0)
    );
\FSM_sequential_tx_64.state_reg[2]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_0\,
      CO(2) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_1\,
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_3\,
      CYINIT => '1',
      DI(3) => \tx_64.req_len_reg_n_0_[3]\,
      DI(2) => \tx_64.req_len_reg_n_0_[2]\,
      DI(1) => \tx_64.req_len_reg_n_0_[1]\,
      DI(0) => \tx_64.req_len_reg_n_0_[0]\,
      O(3) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_4\,
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_14_n_7\,
      S(3) => \FSM_sequential_tx_64.state[2]_i_20_n_0\,
      S(2) => \FSM_sequential_tx_64.state[2]_i_21_n_0\,
      S(1) => \state3_inferred__0/i__n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_22_n_0\
    );
\FSM_sequential_tx_64.state_reg[2]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \FSM_sequential_tx_64.state_reg[2]_i_16_n_0\,
      CO(3 downto 2) => \NLW_FSM_sequential_tx_64.state_reg[2]_i_15_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_15_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \tx_64.req_len_reg_n_0_[9]\,
      DI(0) => \tx_64.req_len_reg_n_0_[8]\,
      O(3) => \NLW_FSM_sequential_tx_64.state_reg[2]_i_15_O_UNCONNECTED\(3),
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_15_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_15_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_15_n_7\,
      S(3) => '0',
      S(2) => \FSM_sequential_tx_64.state[2]_i_23_n_0\,
      S(1) => \FSM_sequential_tx_64.state[2]_i_24_n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_25_n_0\
    );
\FSM_sequential_tx_64.state_reg[2]_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \FSM_sequential_tx_64.state_reg[2]_i_14_n_0\,
      CO(3) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_0\,
      CO(2) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_1\,
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_3\,
      CYINIT => '0',
      DI(3) => \tx_64.req_len_reg_n_0_[7]\,
      DI(2) => \tx_64.req_len_reg_n_0_[6]\,
      DI(1) => \tx_64.req_len_reg_n_0_[5]\,
      DI(0) => \tx_64.req_len_reg_n_0_[4]\,
      O(3) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_4\,
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_16_n_7\,
      S(3) => \FSM_sequential_tx_64.state[2]_i_26_n_0\,
      S(2) => \FSM_sequential_tx_64.state[2]_i_27_n_0\,
      S(1) => \FSM_sequential_tx_64.state[2]_i_28_n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_29_n_0\
    );
\FSM_sequential_tx_64.state_reg[2]_i_17\: unisim.vcomponents.CARRY4
     port map (
      CI => \FSM_sequential_tx_64.state_reg[2]_i_18_n_0\,
      CO(3 downto 2) => \NLW_FSM_sequential_tx_64.state_reg[2]_i_17_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_17_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_17_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \tx_64.req_len_reg_n_0_[9]\,
      DI(0) => \tx_64.req_len_reg_n_0_[8]\,
      O(3) => \NLW_FSM_sequential_tx_64.state_reg[2]_i_17_O_UNCONNECTED\(3),
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_17_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_17_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_17_n_7\,
      S(3) => '0',
      S(2) => \FSM_sequential_tx_64.state[2]_i_30_n_0\,
      S(1) => \FSM_sequential_tx_64.state[2]_i_31_n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_32_n_0\
    );
\FSM_sequential_tx_64.state_reg[2]_i_18\: unisim.vcomponents.CARRY4
     port map (
      CI => \FSM_sequential_tx_64.state_reg[2]_i_19_n_0\,
      CO(3) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_0\,
      CO(2) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_1\,
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_3\,
      CYINIT => '0',
      DI(3) => \tx_64.req_len_reg_n_0_[7]\,
      DI(2) => \tx_64.req_len_reg_n_0_[6]\,
      DI(1) => \tx_64.req_len_reg_n_0_[5]\,
      DI(0) => \tx_64.req_len_reg_n_0_[4]\,
      O(3) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_4\,
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_18_n_7\,
      S(3) => \FSM_sequential_tx_64.state[2]_i_33_n_0\,
      S(2) => state3_n_0,
      S(1) => \FSM_sequential_tx_64.state[2]_i_34_n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_35_n_0\
    );
\FSM_sequential_tx_64.state_reg[2]_i_19\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_0\,
      CO(2) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_1\,
      CO(1) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_2\,
      CO(0) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_3\,
      CYINIT => '1',
      DI(3) => \tx_64.req_len_reg_n_0_[3]\,
      DI(2) => \tx_64.req_len_reg_n_0_[2]\,
      DI(1) => \tx_64.req_len_reg_n_0_[1]\,
      DI(0) => \tx_64.req_len_reg_n_0_[0]\,
      O(3) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_4\,
      O(2) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_5\,
      O(1) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_6\,
      O(0) => \FSM_sequential_tx_64.state_reg[2]_i_19_n_7\,
      S(3) => \FSM_sequential_tx_64.state[2]_i_36_n_0\,
      S(2) => \FSM_sequential_tx_64.state[2]_i_37_n_0\,
      S(1) => \FSM_sequential_tx_64.state[2]_i_38_n_0\,
      S(0) => \FSM_sequential_tx_64.state[2]_i_39_n_0\
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"51550400D3DD4544"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[9]\,
      I1 => \tx_64.dw_count_reg_n_0_[8]\,
      I2 => \tx_64.dw_count[10]_i_3_n_0\,
      I3 => \tx_64.dw_count_reg_n_0_[7]\,
      I4 => \tx_64.dw_count_reg_n_0_[9]\,
      I5 => \tx_64.req_len_reg_n_0_[8]\,
      O => \i__carry__0_i_1_n_0\
    );
\i__carry__0_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55955555"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[10]\,
      I1 => \tx_64.dw_count_reg_n_0_[9]\,
      I2 => \tx_64.dw_count_reg_n_0_[8]\,
      I3 => \tx_64.dw_count[10]_i_3_n_0\,
      I4 => \tx_64.dw_count_reg_n_0_[7]\,
      O => \i__carry__0_i_2__0_n_0\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9A45002000209A45"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[8]\,
      I1 => \tx_64.dw_count[10]_i_3_n_0\,
      I2 => \tx_64.dw_count_reg_n_0_[7]\,
      I3 => \tx_64.req_len_reg_n_0_[8]\,
      I4 => \tx_64.dw_count_reg_n_0_[9]\,
      I5 => \tx_64.req_len_reg_n_0_[9]\,
      O => \i__carry__0_i_3_n_0\
    );
\i__carry_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AA6A00805515"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I3 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I4 => \tx_64.current_dw_count_reg_n_0_[10]\,
      I5 => \tx_64.req_len_reg_n_0_[9]\,
      O => \i__carry_i_1_n_0\
    );
\i__carry_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[3]\,
      I1 => \tx_64.dw_count_reg_n_0_[2]\,
      I2 => \tx_64.dw_count_reg_n_0_[1]\,
      I3 => \tx_64.dw_count_reg_n_0_[4]\,
      O => \in26__0\(4)
    );
\i__carry_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09099F09"
    )
        port map (
      I0 => \tx_64.dw_count[10]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[7]\,
      I2 => \tx_64.req_len_reg_n_0_[7]\,
      I3 => \in26__0\(6),
      I4 => \tx_64.req_len_reg_n_0_[6]\,
      O => \i__carry_i_1__2_n_0\
    );
\i__carry_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A20808A2"
    )
        port map (
      I0 => \i__carry_i_5_n_0\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I2 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I3 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I4 => \tx_64.req_len_reg_n_0_[8]\,
      O => \i__carry_i_2_n_0\
    );
\i__carry_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[5]\,
      I1 => \in26__0\(5),
      I2 => \in26__0\(4),
      I3 => \tx_64.req_len_reg_n_0_[4]\,
      O => \i__carry_i_2__0_n_0\
    );
\i__carry_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \in28__0\(3),
      I2 => \tx_64.req_len_reg_n_0_[4]\,
      I3 => \in28__0\(4),
      I4 => \in28__0\(5),
      I5 => \tx_64.req_len_reg_n_0_[5]\,
      O => \i__carry_i_3_n_0\
    );
\i__carry_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15403D54"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \tx_64.dw_count_reg_n_0_[1]\,
      I2 => \tx_64.dw_count_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[3]\,
      I4 => \tx_64.req_len_reg_n_0_[2]\,
      O => \i__carry_i_3__0_n_0\
    );
\i__carry_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0082410041000082"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[1]\,
      I1 => \tx_64.req_len_reg_n_0_[0]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I5 => \tx_64.req_len_reg_n_0_[2]\,
      O => \i__carry_i_4_n_0\
    );
\i__carry_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[1]\,
      I1 => \tx_64.req_len_reg_n_0_[1]\,
      O => \i__carry_i_4__0_n_0\
    );
\i__carry_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09906009"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I1 => \tx_64.req_len_reg_n_0_[7]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I3 => state3_i_1_n_0,
      I4 => \tx_64.req_len_reg_n_0_[6]\,
      O => \i__carry_i_5_n_0\
    );
\i__carry_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90096006"
    )
        port map (
      I0 => \tx_64.dw_count[10]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[7]\,
      I2 => \in26__0\(6),
      I3 => \tx_64.req_len_reg_n_0_[6]\,
      I4 => \tx_64.req_len_reg_n_0_[7]\,
      O => \i__carry_i_5__2_n_0\
    );
\i__carry_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => \in28__0\(3)
    );
\i__carry_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \in26__0\(4),
      I1 => \tx_64.req_len_reg_n_0_[4]\,
      I2 => \in26__0\(5),
      I3 => \tx_64.req_len_reg_n_0_[5]\,
      O => \i__carry_i_6__0_n_0\
    );
\i__carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[4]\,
      O => \in28__0\(4)
    );
\i__carry_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"61080861"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[2]\,
      I1 => \tx_64.dw_count_reg_n_0_[1]\,
      I2 => \tx_64.req_len_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[3]\,
      I4 => \tx_64.req_len_reg_n_0_[3]\,
      O => \i__carry_i_7__0_n_0\
    );
\i__carry_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[5]\,
      O => \in28__0\(5)
    );
\i__carry_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[1]\,
      I1 => \tx_64.req_len_reg_n_0_[1]\,
      I2 => \tx_64.req_len_reg_n_0_[0]\,
      O => \i__carry_i_8__0_n_0\
    );
\i__carry_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[4]\,
      I1 => \tx_64.dw_count_reg_n_0_[1]\,
      I2 => \tx_64.dw_count_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[3]\,
      I4 => \tx_64.dw_count_reg_n_0_[5]\,
      O => \in26__0\(5)
    );
\in_packet_q_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05444444"
    )
        port map (
      I0 => SR(0),
      I1 => in_packet_q,
      I2 => \m_axis_rq\\.tlast\,
      I3 => \m_axis_rq\\.tvalid\,
      I4 => s_axis_tx_req_tready,
      O => \in_packet_q_i_1__0_n_0\
    );
in_packet_q_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \in_packet_q_i_1__0_n_0\,
      Q => in_packet_q,
      R => '0'
    );
\s_axis_tx_tdata[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[0]_i_2_n_0\,
      I1 => wreq_data_le(0),
      I2 => \^tx_64.req_4dw_reg_3\,
      I3 => p_0_in(0),
      I4 => \^tx_64.req_4dw_reg_0\,
      I5 => \s_axis_tx_tdata_reg[0]\,
      O => D(0)
    );
\s_axis_tx_tdata[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => wreq_data_le(32),
      I3 => \m_axis_rq\\.tdata\(0),
      I4 => \s_axis_tx_tdata[13]_i_3_n_0\,
      O => \s_axis_tx_tdata[0]_i_2_n_0\
    );
\s_axis_tx_tdata[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(10),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(8),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[10]_i_4_n_0\,
      O => \tx_64.req_addr_reg[42]_0\
    );
\s_axis_tx_tdata[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(42),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(10),
      I4 => p_0_out(10),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[10]_i_4_n_0\
    );
\s_axis_tx_tdata[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(11),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(9),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[11]_i_4_n_0\,
      O => \tx_64.req_addr_reg[43]_0\
    );
\s_axis_tx_tdata[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(43),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(11),
      I4 => p_0_out(11),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[11]_i_4_n_0\
    );
\s_axis_tx_tdata[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(12),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => p_0_in(44),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[12]_i_4_n_0\,
      O => \tx_64.req_addr_reg[44]_0\
    );
\s_axis_tx_tdata[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(44),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(12),
      I4 => \m_axis_rq\\.tdata\(60),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[12]_i_4_n_0\
    );
\s_axis_tx_tdata[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[13]_i_2_n_0\,
      I1 => \m_axis_rq\\.tdata\(61),
      I2 => \s_axis_tx_tdata[13]_i_3_n_0\,
      I3 => \^q\(10),
      I4 => \s_axis_tx_tdata[13]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[13]_i_5_n_0\,
      O => D(3)
    );
\s_axis_tx_tdata[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888F888"
    )
        port map (
      I0 => wreq_data_le(13),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => s_axis_tx_tgt_tdata(0),
      I3 => transfer_SM(0),
      I4 => transfer_SM(1),
      O => \s_axis_tx_tdata[13]_i_2_n_0\
    );
\s_axis_tx_tdata[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000004000000000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => transfer_SM(1),
      I2 => transfer_SM(0),
      I3 => SR(0),
      I4 => state(1),
      I5 => state(0),
      O => \s_axis_tx_tdata[13]_i_3_n_0\
    );
\s_axis_tx_tdata[13]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000040"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => state(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(0),
      O => \s_axis_tx_tdata[13]_i_4_n_0\
    );
\s_axis_tx_tdata[13]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8888888888888"
    )
        port map (
      I0 => p_0_in(13),
      I1 => \^tx_64.req_4dw_reg_0\,
      I2 => \s_axis_tx_tdata[13]_i_6_n_0\,
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => wreq_data_le(45),
      I5 => \s_axis_tx_tkeep_reg[7]\,
      O => \s_axis_tx_tdata[13]_i_5_n_0\
    );
\s_axis_tx_tdata[13]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"18"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => \s_axis_tx_tdata[13]_i_6_n_0\
    );
\s_axis_tx_tdata[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(14),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(11),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[14]_i_4_n_0\,
      O => \tx_64.req_addr_reg[46]_0\
    );
\s_axis_tx_tdata[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(46),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(14),
      I4 => \m_axis_rq\\.tdata\(15),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[14]_i_4_n_0\
    );
\s_axis_tx_tdata[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(12),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(15),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[15]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[15]\,
      O => D(4)
    );
\s_axis_tx_tdata[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[15]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(15),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[15]_i_2_n_0\
    );
\s_axis_tx_tdata[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(15),
      I1 => wreq_data_le(15),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(12),
      I5 => \^tx_64.wr_data_reg[55]_0\(9),
      O => \s_axis_tx_tdata[15]_i_4_n_0\
    );
\s_axis_tx_tdata[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(48),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(16),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[16]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[16]\,
      O => D(5)
    );
\s_axis_tx_tdata[16]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[16]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(16),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[16]_i_2_n_0\
    );
\s_axis_tx_tdata[16]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(16),
      I1 => wreq_data_le(16),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => p_0_in(48),
      I5 => \^tx_64.wr_data_reg[55]_0\(5),
      O => \s_axis_tx_tdata[16]_i_4_n_0\
    );
\s_axis_tx_tdata[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(49),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(17),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[17]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[17]\,
      O => D(6)
    );
\s_axis_tx_tdata[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[17]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(17),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[17]_i_2_n_0\
    );
\s_axis_tx_tdata[17]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(17),
      I1 => wreq_data_le(17),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => p_0_in(49),
      I5 => \^tx_64.wr_data_reg[55]_0\(6),
      O => \s_axis_tx_tdata[17]_i_4_n_0\
    );
\s_axis_tx_tdata[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(18),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => p_0_in(50),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[18]_i_4_n_0\,
      O => \tx_64.req_addr_reg[50]_0\
    );
\s_axis_tx_tdata[18]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(50),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(18),
      I4 => \m_axis_rq\\.tdata\(62),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[18]_i_4_n_0\
    );
\s_axis_tx_tdata[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(51),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(19),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[19]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[19]\,
      O => D(7)
    );
\s_axis_tx_tdata[19]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[19]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(19),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[19]_i_2_n_0\
    );
\s_axis_tx_tdata[19]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(19),
      I1 => wreq_data_le(19),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => p_0_in(51),
      I5 => \^tx_64.wr_data_reg[55]_0\(7),
      O => \s_axis_tx_tdata[19]_i_4_n_0\
    );
\s_axis_tx_tdata[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[1]_i_2_n_0\,
      I1 => wreq_data_le(1),
      I2 => \^tx_64.req_4dw_reg_3\,
      I3 => p_0_in(1),
      I4 => \^tx_64.req_4dw_reg_0\,
      I5 => \s_axis_tx_tdata_reg[1]\,
      O => D(1)
    );
\s_axis_tx_tdata[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => wreq_data_le(33),
      I3 => \m_axis_rq\\.tdata\(1),
      I4 => \s_axis_tx_tdata[13]_i_3_n_0\,
      O => \s_axis_tx_tdata[1]_i_2_n_0\
    );
\s_axis_tx_tdata[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(20),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => p_0_in(52),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[20]_i_4_n_0\,
      O => \tx_64.req_addr_reg[52]_0\
    );
\s_axis_tx_tdata[20]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(52),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(20),
      I4 => \m_axis_rq\\.tdata\(57),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[20]_i_4_n_0\
    );
\s_axis_tx_tdata[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(21),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => p_0_in(53),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[21]_i_4_n_0\,
      O => \tx_64.req_addr_reg[53]_0\
    );
\s_axis_tx_tdata[21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(53),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(21),
      I4 => \m_axis_rq\\.tdata\(58),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[21]_i_4_n_0\
    );
\s_axis_tx_tdata[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(22),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => p_0_in(54),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[22]_i_6_n_0\,
      O => \tx_64.req_addr_reg[54]_0\
    );
\s_axis_tx_tdata[22]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(54),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(22),
      I4 => \m_axis_rq\\.tdata\(59),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[22]_i_6_n_0\
    );
\s_axis_tx_tdata[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(55),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(23),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[23]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[23]\,
      O => D(8)
    );
\s_axis_tx_tdata[23]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[23]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(23),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[23]_i_2_n_0\
    );
\s_axis_tx_tdata[23]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(23),
      I1 => wreq_data_le(23),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => p_0_in(55),
      I5 => \^tx_64.wr_data_reg[55]_0\(8),
      O => \s_axis_tx_tdata[23]_i_4_n_0\
    );
\s_axis_tx_tdata[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(13),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(24),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[24]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[24]\,
      O => D(9)
    );
\s_axis_tx_tdata[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[24]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(24),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[24]_i_2_n_0\
    );
\s_axis_tx_tdata[24]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(24),
      I1 => wreq_data_le(24),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(13),
      I5 => \^tx_64.wr_data_reg[55]_0\(1),
      O => \s_axis_tx_tdata[24]_i_4_n_0\
    );
\s_axis_tx_tdata[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(25),
      I1 => \^tx_64.req_4dw_reg_2\,
      I2 => \^q\(14),
      I3 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I4 => \s_axis_tx_tdata_reg[25]\,
      I5 => \s_axis_tx_tdata[25]_i_3_n_0\,
      O => D(10)
    );
\s_axis_tx_tdata[25]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I1 => wreq_data_le(57),
      I2 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I3 => wreq_data_le(25),
      I4 => \s_axis_tx_tdata_reg[25]_0\,
      O => \s_axis_tx_tdata[25]_i_3_n_0\
    );
\s_axis_tx_tdata[25]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(25),
      I1 => wreq_data_le(25),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(14),
      I5 => wreq_data_le(57),
      O => \tx_64.req_addr_reg[57]_0\
    );
\s_axis_tx_tdata[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(15),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(26),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[26]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[26]\,
      O => D(11)
    );
\s_axis_tx_tdata[26]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[26]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(26),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[26]_i_2_n_0\
    );
\s_axis_tx_tdata[26]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(26),
      I1 => wreq_data_le(26),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(15),
      I5 => \^tx_64.wr_data_reg[55]_0\(2),
      O => \s_axis_tx_tdata[26]_i_4_n_0\
    );
\s_axis_tx_tdata[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(27),
      I1 => \^tx_64.req_4dw_reg_2\,
      I2 => \^q\(16),
      I3 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I4 => \s_axis_tx_tdata_reg[27]\,
      I5 => \s_axis_tx_tdata[27]_i_3_n_0\,
      O => D(12)
    );
\s_axis_tx_tdata[27]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I1 => wreq_data_le(59),
      I2 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I3 => wreq_data_le(27),
      I4 => \s_axis_tx_tdata_reg[27]_0\,
      O => \s_axis_tx_tdata[27]_i_3_n_0\
    );
\s_axis_tx_tdata[27]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(27),
      I1 => wreq_data_le(27),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(16),
      I5 => wreq_data_le(59),
      O => \tx_64.req_addr_reg[59]_0\
    );
\s_axis_tx_tdata[27]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => transfer_SM(1),
      I2 => transfer_SM(0),
      I3 => SR(0),
      I4 => state(1),
      O => \FSM_sequential_tx_64.state_reg[2]_2\
    );
\s_axis_tx_tdata[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(17),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(28),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[28]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[28]\,
      O => D(13)
    );
\s_axis_tx_tdata[28]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[28]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(28),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[28]_i_2_n_0\
    );
\s_axis_tx_tdata[28]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(28),
      I1 => wreq_data_le(28),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(17),
      I5 => \^tx_64.wr_data_reg[55]_0\(3),
      O => \s_axis_tx_tdata[28]_i_4_n_0\
    );
\s_axis_tx_tdata[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => p_0_in(29),
      I1 => \^tx_64.req_4dw_reg_0\,
      I2 => wreq_data_le(29),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[29]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[29]\,
      O => D(14)
    );
\s_axis_tx_tdata[29]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000080"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => state(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(0),
      O => \^tx_64.req_4dw_reg_0\
    );
\s_axis_tx_tdata[29]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAFAAAAAAAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[29]_0\,
      I1 => wreq_data_le(29),
      I2 => \tx_64.req_4dw_reg_n_0\,
      I3 => \s_axis_tx_tdata_reg[2]\,
      I4 => state(1),
      I5 => state(0),
      O => \s_axis_tx_tdata[29]_i_3_n_0\
    );
\s_axis_tx_tdata[29]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF200020002000"
    )
        port map (
      I0 => \s_axis_tx_tdata[13]_i_6_n_0\,
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => wreq_data_le(61),
      I3 => \s_axis_tx_tkeep_reg[7]\,
      I4 => \^q\(18),
      I5 => \s_axis_tx_tdata[13]_i_4_n_0\,
      O => \tx_64.req_4dw_reg_1\
    );
\s_axis_tx_tdata[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEAAAEAAAEAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[2]_0\,
      I1 => wreq_data_le(34),
      I2 => \s_axis_tx_tkeep_reg[7]\,
      I3 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I4 => \^tx_64.req_4dw_reg_3\,
      I5 => wreq_data_le(2),
      O => \tx_64.wr_data_reg[58]_0\
    );
\s_axis_tx_tdata[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(2),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \^q\(0),
      I5 => \s_axis_tx_tdata[13]_i_4_n_0\,
      O => \Head_reg[2]\
    );
\s_axis_tx_tdata[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0042"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(0),
      I2 => state(1),
      I3 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[2]_i_6_n_0\
    );
\s_axis_tx_tdata[30]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => state(0),
      O => \s_axis_tx_tdata[30]_i_10_n_0\
    );
\s_axis_tx_tdata[30]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(30),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(19),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[30]_i_7_n_0\,
      O => \tx_64.req_addr_reg[62]_0\
    );
\s_axis_tx_tdata[30]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4200"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[30]_i_5_n_0\
    );
\s_axis_tx_tdata[30]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0042"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[30]_i_6_n_0\
    );
\s_axis_tx_tdata[30]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888FFFFF888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(62),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(30),
      I4 => \s_axis_tx_tdata[30]_i_2_0\,
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[30]_i_7_n_0\
    );
\s_axis_tx_tdata[30]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4200"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(0),
      I2 => state(1),
      I3 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[30]_i_8_n_0\
    );
\s_axis_tx_tdata[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^q\(20),
      I1 => \s_axis_tx_tdata[31]_i_2_n_0\,
      I2 => wreq_data_le(31),
      I3 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I4 => \s_axis_tx_tdata[31]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[31]\,
      O => D(15)
    );
\s_axis_tx_tdata[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => state(0),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(1),
      O => \s_axis_tx_tdata[31]_i_2_n_0\
    );
\s_axis_tx_tdata[31]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata[31]_i_5_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => p_0_in(31),
      I4 => \^tx_64.req_4dw_reg_2\,
      O => \s_axis_tx_tdata[31]_i_3_n_0\
    );
\s_axis_tx_tdata[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAFFCAF0CA0FCA00"
    )
        port map (
      I0 => p_0_in(31),
      I1 => wreq_data_le(31),
      I2 => state(0),
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => \^q\(20),
      I5 => \^tx_64.wr_data_reg[55]_0\(4),
      O => \s_axis_tx_tdata[31]_i_5_n_0\
    );
\s_axis_tx_tdata[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEFEEEFEEE"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[32]\,
      I1 => \s_axis_tx_tdata[32]_i_3_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I3 => \m_axis_rq\\.tdata\(24),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => wreq_data_le(32),
      O => D(16)
    );
\s_axis_tx_tdata[32]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[32]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => \m_axis_cc\\.tdata\(7),
      I3 => \s_axis_tx_tdata_reg[34]\,
      O => \s_axis_tx_tdata[32]_i_3_n_0\
    );
\s_axis_tx_tdata[32]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0CCAACC0000AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(24),
      I1 => p_0_out(32),
      I2 => wreq_data_le(32),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[32]_i_4_n_0\
    );
\s_axis_tx_tdata[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFEEEFEEEFEEE"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[33]\,
      I1 => \s_axis_tx_tdata[33]_i_3_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I3 => \m_axis_rq\\.tdata\(25),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => wreq_data_le(33),
      O => D(17)
    );
\s_axis_tx_tdata[33]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[33]_i_4_n_0\,
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => \m_axis_cc\\.tdata\(8),
      I3 => \s_axis_tx_tdata_reg[34]\,
      O => \s_axis_tx_tdata[33]_i_3_n_0\
    );
\s_axis_tx_tdata[33]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0CCAACC0000AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(25),
      I1 => p_0_out(33),
      I2 => wreq_data_le(33),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[33]_i_4_n_0\
    );
\s_axis_tx_tdata[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(34),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(9),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[34]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[34]_0\,
      O => D(18)
    );
\s_axis_tx_tdata[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(34),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(26),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[34]_i_2_n_0\
    );
\s_axis_tx_tdata[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(35),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(10),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[35]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[35]\,
      O => D(19)
    );
\s_axis_tx_tdata[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(35),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(27),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[35]_i_2_n_0\
    );
\s_axis_tx_tdata[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(36),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(11),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[36]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[36]\,
      O => D(20)
    );
\s_axis_tx_tdata[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(36),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(28),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[36]_i_2_n_0\
    );
\s_axis_tx_tdata[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(37),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(12),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[37]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[37]\,
      O => D(21)
    );
\s_axis_tx_tdata[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(37),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(29),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[37]_i_2_n_0\
    );
\s_axis_tx_tdata[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(38),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(13),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[38]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[38]\,
      O => D(22)
    );
\s_axis_tx_tdata[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(38),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(30),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[38]_i_2_n_0\
    );
\s_axis_tx_tdata[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(39),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(14),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[39]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[39]\,
      O => D(23)
    );
\s_axis_tx_tdata[39]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => p_0_out(39),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(31),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[39]_i_2_n_0\
    );
\s_axis_tx_tdata[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(3),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(1),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[3]_i_4_n_0\,
      O => \tx_64.req_addr_reg[35]_0\
    );
\s_axis_tx_tdata[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(35),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(3),
      I4 => \m_axis_rq\\.tdata\(3),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[3]_i_4_n_0\
    );
\s_axis_tx_tdata[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(40),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(0),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[40]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[40]\,
      O => D(24)
    );
\s_axis_tx_tdata[40]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(32),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(16),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[40]_i_2_n_0\
    );
\s_axis_tx_tdata[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(41),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(1),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[41]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[41]\,
      O => D(25)
    );
\s_axis_tx_tdata[41]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(33),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(17),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[41]_i_2_n_0\
    );
\s_axis_tx_tdata[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(42),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(2),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[42]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[42]\,
      O => D(26)
    );
\s_axis_tx_tdata[42]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(34),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(18),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[42]_i_2_n_0\
    );
\s_axis_tx_tdata[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(43),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(3),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[43]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[43]\,
      O => D(27)
    );
\s_axis_tx_tdata[43]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(35),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(19),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[43]_i_2_n_0\
    );
\s_axis_tx_tdata[44]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(36),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(20),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \Head_reg[36]\
    );
\s_axis_tx_tdata[44]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => wreq_data_le(44),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => p_0_in(44),
      I3 => \^tx_64.req_4dw_reg_0\,
      O => \tx_64.wr_data_reg[52]_0\
    );
\s_axis_tx_tdata[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(45),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(4),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[45]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[45]\,
      O => D(28)
    );
\s_axis_tx_tdata[45]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(37),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(21),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[45]_i_2_n_0\
    );
\s_axis_tx_tdata[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(46),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(5),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[46]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[46]\,
      O => D(29)
    );
\s_axis_tx_tdata[46]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(38),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(22),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[46]_i_2_n_0\
    );
\s_axis_tx_tdata[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^tx_64.wr_data_reg[55]_0\(9),
      I1 => \^tx_64.req_4dw_reg_3\,
      I2 => \m_axis_cc\\.tdata\(6),
      I3 => \s_axis_tx_tdata_reg[34]\,
      I4 => \s_axis_tx_tdata[47]_i_4_n_0\,
      I5 => \s_axis_tx_tdata_reg[47]\,
      O => D(30)
    );
\s_axis_tx_tdata[47]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000080"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => state(0),
      I4 => state(1),
      O => \^tx_64.req_4dw_reg_3\
    );
\s_axis_tx_tdata[47]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF080008000800"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(39),
      I1 => \s_axis_tx_tdata_reg[2]\,
      I2 => state(1),
      I3 => state(0),
      I4 => \m_axis_rq\\.tdata\(23),
      I5 => \s_axis_tx_tdata[47]_i_6_n_0\,
      O => \s_axis_tx_tdata[47]_i_4_n_0\
    );
\s_axis_tx_tdata[47]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001A00"
    )
        port map (
      I0 => state(1),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => \s_axis_tx_tkeep_reg[7]\,
      I4 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[47]_i_6_n_0\
    );
\s_axis_tx_tdata[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[48]\,
      I1 => p_0_in(48),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => \^tx_64.wr_data_reg[55]_0\(5),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => D(31)
    );
\s_axis_tx_tdata[48]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[48]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_function_number_o(0),
      I5 => \m_axis_rq\\.tdata\(16),
      O => \Head_reg[56]\
    );
\s_axis_tx_tdata[48]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(8),
      I1 => p_0_in(48),
      I2 => \^tx_64.wr_data_reg[55]_0\(5),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[48]_i_5_n_0\
    );
\s_axis_tx_tdata[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[49]\,
      I1 => p_0_in(49),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => \^tx_64.wr_data_reg[55]_0\(6),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[49]_0\,
      O => D(32)
    );
\s_axis_tx_tdata[49]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[49]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_function_number_o(1),
      I5 => \m_axis_rq\\.tdata\(17),
      O => \Head_reg[56]_0\
    );
\s_axis_tx_tdata[49]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(9),
      I1 => p_0_in(49),
      I2 => \^tx_64.wr_data_reg[55]_0\(6),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[49]_i_5_n_0\
    );
\s_axis_tx_tdata[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(4),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(2),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[4]_i_4_n_0\,
      O => \tx_64.req_addr_reg[36]_0\
    );
\s_axis_tx_tdata[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(36),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(4),
      I4 => \m_axis_rq\\.tdata\(4),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[4]_i_4_n_0\
    );
\s_axis_tx_tdata[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[50]\,
      I1 => p_0_in(50),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => wreq_data_le(50),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[50]_0\,
      O => D(33)
    );
\s_axis_tx_tdata[50]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[50]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_function_number_o(2),
      I5 => \m_axis_rq\\.tdata\(18),
      O => \Head_reg[56]_1\
    );
\s_axis_tx_tdata[50]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(10),
      I1 => p_0_in(50),
      I2 => wreq_data_le(50),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[50]_i_5_n_0\
    );
\s_axis_tx_tdata[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[51]\,
      I1 => p_0_in(51),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => \^tx_64.wr_data_reg[55]_0\(7),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[51]_0\,
      O => D(34)
    );
\s_axis_tx_tdata[51]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[51]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_device_number_o(0),
      I5 => \m_axis_rq\\.tdata\(19),
      O => \Head_reg[56]_2\
    );
\s_axis_tx_tdata[51]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(11),
      I1 => p_0_in(51),
      I2 => \^tx_64.wr_data_reg[55]_0\(7),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[51]_i_5_n_0\
    );
\s_axis_tx_tdata[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[52]\,
      I1 => p_0_in(52),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => wreq_data_le(52),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[52]_0\,
      O => D(35)
    );
\s_axis_tx_tdata[52]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[52]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_device_number_o(1),
      I5 => \m_axis_rq\\.tdata\(20),
      O => \Head_reg[56]_3\
    );
\s_axis_tx_tdata[52]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(12),
      I1 => p_0_in(52),
      I2 => wreq_data_le(52),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[52]_i_5_n_0\
    );
\s_axis_tx_tdata[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[53]\,
      I1 => p_0_in(53),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => wreq_data_le(53),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[53]_0\,
      O => D(36)
    );
\s_axis_tx_tdata[53]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[53]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_device_number_o(2),
      I5 => \m_axis_rq\\.tdata\(21),
      O => \Head_reg[56]_4\
    );
\s_axis_tx_tdata[53]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(13),
      I1 => p_0_in(53),
      I2 => wreq_data_le(53),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[53]_i_5_n_0\
    );
\s_axis_tx_tdata[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[54]\,
      I1 => p_0_in(54),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => wreq_data_le(54),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[54]_0\,
      O => D(37)
    );
\s_axis_tx_tdata[54]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[54]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_device_number_o(3),
      I5 => \m_axis_rq\\.tdata\(22),
      O => \Head_reg[56]_5\
    );
\s_axis_tx_tdata[54]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(14),
      I1 => p_0_in(54),
      I2 => wreq_data_le(54),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[54]_i_5_n_0\
    );
\s_axis_tx_tdata[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[55]\,
      I1 => p_0_in(55),
      I2 => \^tx_64.req_4dw_reg_2\,
      I3 => \^tx_64.wr_data_reg[55]_0\(8),
      I4 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I5 => \s_axis_tx_tdata_reg[55]_0\,
      O => D(38)
    );
\s_axis_tx_tdata[55]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \s_axis_tx_tkeep_reg[7]\,
      I2 => state(0),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(1),
      O => \^tx_64.req_4dw_reg_2\
    );
\s_axis_tx_tdata[55]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_7_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_device_number_o(4),
      I5 => \m_axis_rq\\.tdata\(23),
      O => \Head_reg[56]_6\
    );
\s_axis_tx_tdata[55]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(15),
      I1 => p_0_in(55),
      I2 => \^tx_64.wr_data_reg[55]_0\(8),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[55]_i_7_n_0\
    );
\s_axis_tx_tdata[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^tx_64.wr_data_reg[55]_0\(1),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(0),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[56]\,
      I5 => \s_axis_tx_tdata_reg[56]_0\,
      O => D(39)
    );
\s_axis_tx_tdata[56]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[56]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(0),
      I5 => \m_axis_rq\\.tdata\(24),
      O => \Head_reg[56]_7\
    );
\s_axis_tx_tdata[56]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(0),
      I1 => \^q\(13),
      I2 => \^tx_64.wr_data_reg[55]_0\(1),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[56]_i_5_n_0\
    );
\s_axis_tx_tdata[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(57),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[57]\,
      I5 => \s_axis_tx_tdata_reg[57]_0\,
      O => D(40)
    );
\s_axis_tx_tdata[57]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[57]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(1),
      I5 => \m_axis_rq\\.tdata\(25),
      O => \Head_reg[56]_8\
    );
\s_axis_tx_tdata[57]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(1),
      I1 => \^q\(14),
      I2 => wreq_data_le(57),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[57]_i_5_n_0\
    );
\s_axis_tx_tdata[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^tx_64.wr_data_reg[55]_0\(2),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(2),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[58]\,
      I5 => \s_axis_tx_tdata_reg[58]_0\,
      O => D(41)
    );
\s_axis_tx_tdata[58]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[58]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(2),
      I5 => \m_axis_rq\\.tdata\(26),
      O => \Head_reg[56]_9\
    );
\s_axis_tx_tdata[58]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(2),
      I1 => \^q\(15),
      I2 => \^tx_64.wr_data_reg[55]_0\(2),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[58]_i_5_n_0\
    );
\s_axis_tx_tdata[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(59),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(3),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[59]\,
      I5 => \s_axis_tx_tdata_reg[59]_0\,
      O => D(42)
    );
\s_axis_tx_tdata[59]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[59]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(3),
      I5 => \m_axis_rq\\.tdata\(27),
      O => \Head_reg[56]_10\
    );
\s_axis_tx_tdata[59]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(3),
      I1 => \^q\(16),
      I2 => wreq_data_le(59),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[59]_i_5_n_0\
    );
\s_axis_tx_tdata[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(5),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(3),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[5]_i_4_n_0\,
      O => \tx_64.req_addr_reg[37]_0\
    );
\s_axis_tx_tdata[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(37),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(5),
      I4 => \m_axis_rq\\.tdata\(5),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[5]_i_4_n_0\
    );
\s_axis_tx_tdata[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^tx_64.wr_data_reg[55]_0\(3),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(4),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[60]\,
      I5 => \s_axis_tx_tdata_reg[60]_0\,
      O => D(43)
    );
\s_axis_tx_tdata[60]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[60]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(4),
      I5 => \m_axis_rq\\.tdata\(28),
      O => \Head_reg[56]_11\
    );
\s_axis_tx_tdata[60]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(4),
      I1 => \^q\(17),
      I2 => \^tx_64.wr_data_reg[55]_0\(3),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[60]_i_5_n_0\
    );
\s_axis_tx_tdata[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(61),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(5),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[61]\,
      I5 => \s_axis_tx_tdata_reg[61]_0\,
      O => D(44)
    );
\s_axis_tx_tdata[61]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[61]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(5),
      I5 => \m_axis_rq\\.tdata\(29),
      O => \Head_reg[56]_12\
    );
\s_axis_tx_tdata[61]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(5),
      I1 => \^q\(18),
      I2 => wreq_data_le(61),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[61]_i_5_n_0\
    );
\s_axis_tx_tdata[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => wreq_data_le(62),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(6),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[62]\,
      I5 => \s_axis_tx_tdata_reg[62]_0\,
      O => D(45)
    );
\s_axis_tx_tdata[62]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[62]_i_5_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(6),
      I5 => \m_axis_rq\\.tdata\(30),
      O => \Head_reg[56]_13\
    );
\s_axis_tx_tdata[62]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(6),
      I1 => \^q\(19),
      I2 => wreq_data_le(62),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[62]_i_5_n_0\
    );
\s_axis_tx_tdata[63]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \^tx_64.wr_data_reg[55]_0\(4),
      I1 => \s_axis_tx_tdata[63]_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(7),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_1\,
      I4 => \s_axis_tx_tdata_reg[63]\,
      I5 => \s_axis_tx_tdata_reg[63]_0\,
      O => D(46)
    );
\s_axis_tx_tdata[63]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I2 => state(0),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      O => \s_axis_tx_tdata[63]_i_3_n_0\
    );
\s_axis_tx_tdata[63]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000008"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I2 => state(0),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      O => \^fsm_sequential_tx_64.state_reg[2]_1\
    );
\s_axis_tx_tdata[63]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFAAAEAAABAAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata[63]_i_9_n_0\,
      I1 => \m_axis_rq\\.tdata\(56),
      I2 => state(0),
      I3 => state(1),
      I4 => cfg_bus_number_o(7),
      I5 => \m_axis_rq\\.tdata\(31),
      O => \Head_reg[56]_14\
    );
\s_axis_tx_tdata[63]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F000AA00CC00AA00"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(7),
      I1 => \^q\(20),
      I2 => \^tx_64.wr_data_reg[55]_0\(4),
      I3 => state(1),
      I4 => \tx_64.req_4dw_reg_n_0\,
      I5 => state(0),
      O => \s_axis_tx_tdata[63]_i_9_n_0\
    );
\s_axis_tx_tdata[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(6),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(4),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[6]_i_4_n_0\,
      O => \tx_64.req_addr_reg[38]_0\
    );
\s_axis_tx_tdata[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(38),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(6),
      I4 => \m_axis_rq\\.tdata\(6),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[6]_i_4_n_0\
    );
\s_axis_tx_tdata[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(7),
      I1 => \s_axis_tx_tdata[13]_i_3_n_0\,
      I2 => \^q\(5),
      I3 => \s_axis_tx_tdata[13]_i_4_n_0\,
      I4 => \s_axis_tx_tdata[7]_i_2_n_0\,
      I5 => \s_axis_tx_tdata_reg[7]\,
      O => D(2)
    );
\s_axis_tx_tdata[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8888888888888"
    )
        port map (
      I0 => p_0_in(7),
      I1 => \^tx_64.req_4dw_reg_0\,
      I2 => \s_axis_tx_tdata[13]_i_6_n_0\,
      I3 => \tx_64.req_4dw_reg_n_0\,
      I4 => wreq_data_le(39),
      I5 => \s_axis_tx_tkeep_reg[7]\,
      O => \s_axis_tx_tdata[7]_i_2_n_0\
    );
\s_axis_tx_tdata[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(8),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(6),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[8]_i_4_n_0\,
      O => \tx_64.req_addr_reg[40]_0\
    );
\s_axis_tx_tdata[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(40),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(8),
      I4 => \m_axis_rq\\.tdata\(8),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[8]_i_4_n_0\
    );
\s_axis_tx_tdata[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA808080"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]\,
      I1 => p_0_in(9),
      I2 => \s_axis_tx_tdata[30]_i_5_n_0\,
      I3 => \^q\(7),
      I4 => \s_axis_tx_tdata[30]_i_6_n_0\,
      I5 => \s_axis_tx_tdata[9]_i_4_n_0\,
      O => \tx_64.req_addr_reg[41]_0\
    );
\s_axis_tx_tdata[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[2]_i_6_n_0\,
      I1 => wreq_data_le(41),
      I2 => \s_axis_tx_tdata[30]_i_8_n_0\,
      I3 => wreq_data_le(9),
      I4 => \m_axis_rq\\.tdata\(9),
      I5 => \s_axis_tx_tdata[30]_i_10_n_0\,
      O => \s_axis_tx_tdata[9]_i_4_n_0\
    );
\s_axis_tx_tkeep2__0_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \s_axis_tx_tkeep2__0_carry_n_0\,
      CO(2) => \s_axis_tx_tkeep2__0_carry_n_1\,
      CO(1) => \s_axis_tx_tkeep2__0_carry_n_2\,
      CO(0) => \s_axis_tx_tkeep2__0_carry_n_3\,
      CYINIT => '1',
      DI(3) => \s_axis_tx_tkeep2__0_carry_i_1_n_0\,
      DI(2) => \s_axis_tx_tkeep2__0_carry_i_2_n_0\,
      DI(1) => \s_axis_tx_tkeep2__0_carry_i_3_n_0\,
      DI(0) => \s_axis_tx_tkeep2__0_carry_i_4_n_0\,
      O(3) => \s_axis_tx_tkeep2__0_carry_n_4\,
      O(2) => \s_axis_tx_tkeep2__0_carry_n_5\,
      O(1) => \s_axis_tx_tkeep2__0_carry_n_6\,
      O(0) => \s_axis_tx_tkeep2__0_carry_n_7\,
      S(3) => \s_axis_tx_tkeep2__0_carry_i_5_n_0\,
      S(2) => \s_axis_tx_tkeep2__0_carry_i_6_n_0\,
      S(1) => \s_axis_tx_tkeep2__0_carry_i_7_n_0\,
      S(0) => \s_axis_tx_tkeep2__0_carry_i_8_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \s_axis_tx_tkeep2__0_carry_n_0\,
      CO(3) => \s_axis_tx_tkeep2__0_carry__0_n_0\,
      CO(2) => \s_axis_tx_tkeep2__0_carry__0_n_1\,
      CO(1) => \s_axis_tx_tkeep2__0_carry__0_n_2\,
      CO(0) => \s_axis_tx_tkeep2__0_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \s_axis_tx_tkeep2__0_carry__0_i_1_n_0\,
      DI(2) => \s_axis_tx_tkeep2__0_carry__0_i_2_n_0\,
      DI(1) => \s_axis_tx_tkeep2__0_carry__0_i_3_n_0\,
      DI(0) => \s_axis_tx_tkeep2__0_carry__0_i_4_n_0\,
      O(3) => \s_axis_tx_tkeep2__0_carry__0_n_4\,
      O(2) => \s_axis_tx_tkeep2__0_carry__0_n_5\,
      O(1) => \s_axis_tx_tkeep2__0_carry__0_n_6\,
      O(0) => \s_axis_tx_tkeep2__0_carry__0_n_7\,
      S(3) => \s_axis_tx_tkeep2__0_carry__0_i_5_n_0\,
      S(2) => \s_axis_tx_tkeep2__0_carry__0_i_6_n_0\,
      S(1) => \s_axis_tx_tkeep2__0_carry__0_i_7_n_0\,
      S(0) => \s_axis_tx_tkeep2__0_carry__0_i_8_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I1 => \tx_64.req_len_reg_n_0_[6]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_1_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[5]\,
      I1 => \tx_64.req_len_reg_n_0_[5]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_2_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I1 => \tx_64.req_len_reg_n_0_[4]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_3_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I1 => \tx_64.req_len_reg_n_0_[3]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_4_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[6]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I2 => \tx_64.req_len_reg_n_0_[7]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[7]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_5_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[5]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[5]\,
      I2 => \tx_64.req_len_reg_n_0_[6]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[6]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_6_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[4]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I2 => \tx_64.req_len_reg_n_0_[5]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[5]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_7_n_0\
    );
\s_axis_tx_tkeep2__0_carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I2 => \tx_64.req_len_reg_n_0_[4]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[4]\,
      O => \s_axis_tx_tkeep2__0_carry__0_i_8_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \s_axis_tx_tkeep2__0_carry__0_n_0\,
      CO(3 downto 2) => \NLW_s_axis_tx_tkeep2__0_carry__1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \s_axis_tx_tkeep2__0_carry__1_n_2\,
      CO(0) => \s_axis_tx_tkeep2__0_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \s_axis_tx_tkeep2__0_carry__1_i_1_n_0\,
      DI(0) => \s_axis_tx_tkeep2__0_carry__1_i_2_n_0\,
      O(3) => \NLW_s_axis_tx_tkeep2__0_carry__1_O_UNCONNECTED\(3),
      O(2) => \s_axis_tx_tkeep2__0_carry__1_n_5\,
      O(1) => \s_axis_tx_tkeep2__0_carry__1_n_6\,
      O(0) => \s_axis_tx_tkeep2__0_carry__1_n_7\,
      S(3) => '0',
      S(2) => \s_axis_tx_tkeep2__0_carry__1_i_3_n_0\,
      S(1) => \s_axis_tx_tkeep2__0_carry__1_i_4_n_0\,
      S(0) => \s_axis_tx_tkeep2__0_carry__1_i_5_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I1 => \tx_64.req_len_reg_n_0_[8]\,
      O => \s_axis_tx_tkeep2__0_carry__1_i_1_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I1 => \tx_64.req_len_reg_n_0_[7]\,
      O => \s_axis_tx_tkeep2__0_carry__1_i_2_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2D"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I1 => \tx_64.req_len_reg_n_0_[9]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[10]\,
      O => \s_axis_tx_tkeep2__0_carry__1_i_3_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[8]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I2 => \tx_64.req_len_reg_n_0_[9]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[9]\,
      O => \s_axis_tx_tkeep2__0_carry__1_i_4_n_0\
    );
\s_axis_tx_tkeep2__0_carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[7]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I2 => \tx_64.req_len_reg_n_0_[8]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[8]\,
      O => \s_axis_tx_tkeep2__0_carry__1_i_5_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I1 => \tx_64.req_len_reg_n_0_[2]\,
      O => \s_axis_tx_tkeep2__0_carry_i_1_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I1 => \tx_64.req_len_reg_n_0_[1]\,
      O => \s_axis_tx_tkeep2__0_carry_i_2_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I1 => \tx_64.req_len_reg_n_0_[0]\,
      O => \s_axis_tx_tkeep2__0_carry_i_3_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      O => \s_axis_tx_tkeep2__0_carry_i_4_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[2]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.req_len_reg_n_0_[3]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => \s_axis_tx_tkeep2__0_carry_i_5_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B44B"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[1]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I2 => \tx_64.req_len_reg_n_0_[2]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      O => \s_axis_tx_tkeep2__0_carry_i_6_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2DD2"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.req_len_reg_n_0_[1]\,
      O => \s_axis_tx_tkeep2__0_carry_i_7_n_0\
    );
\s_axis_tx_tkeep2__0_carry_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I1 => \tx_64.req_len_reg_n_0_[0]\,
      O => \s_axis_tx_tkeep2__0_carry_i_8_n_0\
    );
\s_axis_tx_tkeep[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAABAAABAEAFA"
    )
        port map (
      I0 => \s_axis_tx_tkeep[7]_i_2_n_0\,
      I1 => state(0),
      I2 => \s_axis_tx_tkeep_reg[7]\,
      I3 => \s_axis_tx_tkeep[7]_i_4_n_0\,
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I5 => \s_axis_tx_tkeep[7]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_0\
    );
\s_axis_tx_tkeep[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \s_axis_tx_tkeep2__0_carry__0_n_5\,
      I1 => \s_axis_tx_tkeep2__0_carry__0_n_6\,
      I2 => \s_axis_tx_tkeep2__0_carry__0_n_7\,
      I3 => \s_axis_tx_tkeep2__0_carry_n_4\,
      O => \s_axis_tx_tkeep[7]_i_10_n_0\
    );
\s_axis_tx_tkeep[7]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => sel0(6),
      I1 => sel0(5),
      I2 => sel0(4),
      I3 => sel0(3),
      O => \s_axis_tx_tkeep[7]_i_11_n_0\
    );
\s_axis_tx_tkeep[7]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0110"
    )
        port map (
      I0 => sel0(2),
      I1 => sel0(1),
      I2 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I3 => \tx_64.req_len_reg_n_0_[0]\,
      O => \s_axis_tx_tkeep[7]_i_14_n_0\
    );
\s_axis_tx_tkeep[7]_i_16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[10]\,
      O => \s_axis_tx_tkeep[7]_i_16_n_0\
    );
\s_axis_tx_tkeep[7]_i_17\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[9]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[9]\,
      O => \s_axis_tx_tkeep[7]_i_17_n_0\
    );
\s_axis_tx_tkeep[7]_i_18\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[8]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[8]\,
      O => \s_axis_tx_tkeep[7]_i_18_n_0\
    );
\s_axis_tx_tkeep[7]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[7]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      O => \s_axis_tx_tkeep[7]_i_19_n_0\
    );
\s_axis_tx_tkeep[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFAFAFAFAFAFA"
    )
        port map (
      I0 => \s_axis_tx_tkeep_reg[7]_0\,
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => \s_axis_tx_tkeep_reg[7]_1\,
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => \s_axis_tx_tkeep[7]_i_7_n_0\,
      I5 => \s_axis_tx_tkeep_reg[7]\,
      O => \s_axis_tx_tkeep[7]_i_2_n_0\
    );
\s_axis_tx_tkeep[7]_i_20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[6]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[6]\,
      O => \s_axis_tx_tkeep[7]_i_20_n_0\
    );
\s_axis_tx_tkeep[7]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[5]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[5]\,
      O => \s_axis_tx_tkeep[7]_i_21_n_0\
    );
\s_axis_tx_tkeep[7]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[4]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[4]\,
      O => \s_axis_tx_tkeep[7]_i_22_n_0\
    );
\s_axis_tx_tkeep[7]_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[3]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => \s_axis_tx_tkeep[7]_i_23_n_0\
    );
\s_axis_tx_tkeep[7]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[2]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      O => \s_axis_tx_tkeep[7]_i_24_n_0\
    );
\s_axis_tx_tkeep[7]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[1]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[1]\,
      O => \s_axis_tx_tkeep[7]_i_25_n_0\
    );
\s_axis_tx_tkeep[7]_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[0]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      O => \s_axis_tx_tkeep[7]_i_26_n_0\
    );
\s_axis_tx_tkeep[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F9999999"
    )
        port map (
      I0 => state(1),
      I1 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I2 => \s_axis_tx_tkeep[7]_i_8_n_0\,
      I3 => \s_axis_tx_tkeep[7]_i_9_n_0\,
      I4 => \s_axis_tx_tkeep[7]_i_10_n_0\,
      O => \s_axis_tx_tkeep[7]_i_4_n_0\
    );
\s_axis_tx_tkeep[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \s_axis_tx_tkeep[7]_i_11_n_0\,
      I1 => sel0(10),
      I2 => sel0(9),
      I3 => sel0(8),
      I4 => sel0(7),
      I5 => \s_axis_tx_tkeep[7]_i_14_n_0\,
      O => \s_axis_tx_tkeep[7]_i_5_n_0\
    );
\s_axis_tx_tkeep[7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state(0),
      I1 => state(1),
      O => \s_axis_tx_tkeep[7]_i_7_n_0\
    );
\s_axis_tx_tkeep[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => state(1),
      I1 => \s_axis_tx_tkeep2__0_carry_n_7\,
      I2 => \s_axis_tx_tkeep2__0_carry_n_5\,
      I3 => \s_axis_tx_tkeep2__0_carry_n_6\,
      O => \s_axis_tx_tkeep[7]_i_8_n_0\
    );
\s_axis_tx_tkeep[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \s_axis_tx_tkeep2__0_carry__1_n_5\,
      I1 => \s_axis_tx_tkeep2__0_carry__1_n_6\,
      I2 => \s_axis_tx_tkeep2__0_carry__1_n_7\,
      I3 => \s_axis_tx_tkeep2__0_carry__0_n_4\,
      O => \s_axis_tx_tkeep[7]_i_9_n_0\
    );
\s_axis_tx_tkeep_reg[7]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \s_axis_tx_tkeep_reg[7]_i_13_n_0\,
      CO(3 downto 2) => \NLW_s_axis_tx_tkeep_reg[7]_i_12_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \s_axis_tx_tkeep_reg[7]_i_12_n_2\,
      CO(0) => \s_axis_tx_tkeep_reg[7]_i_12_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \tx_64.req_len_reg_n_0_[9]\,
      DI(0) => \tx_64.req_len_reg_n_0_[8]\,
      O(3) => \NLW_s_axis_tx_tkeep_reg[7]_i_12_O_UNCONNECTED\(3),
      O(2 downto 0) => sel0(10 downto 8),
      S(3) => '0',
      S(2) => \s_axis_tx_tkeep[7]_i_16_n_0\,
      S(1) => \s_axis_tx_tkeep[7]_i_17_n_0\,
      S(0) => \s_axis_tx_tkeep[7]_i_18_n_0\
    );
\s_axis_tx_tkeep_reg[7]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \s_axis_tx_tkeep_reg[7]_i_15_n_0\,
      CO(3) => \s_axis_tx_tkeep_reg[7]_i_13_n_0\,
      CO(2) => \s_axis_tx_tkeep_reg[7]_i_13_n_1\,
      CO(1) => \s_axis_tx_tkeep_reg[7]_i_13_n_2\,
      CO(0) => \s_axis_tx_tkeep_reg[7]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \tx_64.req_len_reg_n_0_[7]\,
      DI(2) => \tx_64.req_len_reg_n_0_[6]\,
      DI(1) => \tx_64.req_len_reg_n_0_[5]\,
      DI(0) => \tx_64.req_len_reg_n_0_[4]\,
      O(3 downto 0) => sel0(7 downto 4),
      S(3) => \s_axis_tx_tkeep[7]_i_19_n_0\,
      S(2) => \s_axis_tx_tkeep[7]_i_20_n_0\,
      S(1) => \s_axis_tx_tkeep[7]_i_21_n_0\,
      S(0) => \s_axis_tx_tkeep[7]_i_22_n_0\
    );
\s_axis_tx_tkeep_reg[7]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \s_axis_tx_tkeep_reg[7]_i_15_n_0\,
      CO(2) => \s_axis_tx_tkeep_reg[7]_i_15_n_1\,
      CO(1) => \s_axis_tx_tkeep_reg[7]_i_15_n_2\,
      CO(0) => \s_axis_tx_tkeep_reg[7]_i_15_n_3\,
      CYINIT => '1',
      DI(3) => \tx_64.req_len_reg_n_0_[3]\,
      DI(2) => \tx_64.req_len_reg_n_0_[2]\,
      DI(1) => \tx_64.req_len_reg_n_0_[1]\,
      DI(0) => \tx_64.req_len_reg_n_0_[0]\,
      O(3 downto 1) => sel0(3 downto 1),
      O(0) => \NLW_s_axis_tx_tkeep_reg[7]_i_15_O_UNCONNECTED\(0),
      S(3) => \s_axis_tx_tkeep[7]_i_23_n_0\,
      S(2) => \s_axis_tx_tkeep[7]_i_24_n_0\,
      S(1) => \s_axis_tx_tkeep[7]_i_25_n_0\,
      S(0) => \s_axis_tx_tkeep[7]_i_26_n_0\
    );
\s_axis_tx_tlast0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \s_axis_tx_tlast0_inferred__0/i__carry_n_0\,
      CO(2) => \s_axis_tx_tlast0_inferred__0/i__carry_n_1\,
      CO(1) => \s_axis_tx_tlast0_inferred__0/i__carry_n_2\,
      CO(0) => \s_axis_tx_tlast0_inferred__0/i__carry_n_3\,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_s_axis_tx_tlast0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_1_n_0\,
      S(2) => \i__carry_i_2_n_0\,
      S(1) => \i__carry_i_3_n_0\,
      S(0) => \i__carry_i_4_n_0\
    );
s_axis_tx_tlast_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0320"
    )
        port map (
      I0 => udma_wrapper_i_253_n_0,
      I1 => SR(0),
      I2 => state(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => s_axis_tx_req_tlast
    );
s_axis_tx_tvalid_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0332"
    )
        port map (
      I0 => state(0),
      I1 => SR(0),
      I2 => state(1),
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => s_axis_tx_req_tvalid
    );
\state2_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \state2_inferred__0/i__carry_n_0\,
      CO(2) => \state2_inferred__0/i__carry_n_1\,
      CO(1) => \state2_inferred__0/i__carry_n_2\,
      CO(0) => \state2_inferred__0/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1__2_n_0\,
      DI(2) => \i__carry_i_2__0_n_0\,
      DI(1) => \i__carry_i_3__0_n_0\,
      DI(0) => \i__carry_i_4__0_n_0\,
      O(3 downto 0) => \NLW_state2_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5__2_n_0\,
      S(2) => \i__carry_i_6__0_n_0\,
      S(1) => \i__carry_i_7__0_n_0\,
      S(0) => \i__carry_i_8__0_n_0\
    );
\state2_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \state2_inferred__0/i__carry_n_0\,
      CO(3 downto 2) => \NLW_state2_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \state2_inferred__0/i__carry__0_n_2\,
      CO(0) => \state2_inferred__0/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"001",
      DI(0) => \i__carry__0_i_1_n_0\,
      O(3 downto 0) => \NLW_state2_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \i__carry__0_i_2__0_n_0\,
      S(0) => \i__carry__0_i_3_n_0\
    );
state3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[6]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I2 => state3_i_1_n_0,
      O => state3_n_0
    );
state3_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[5]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => state3_i_1_n_0
    );
\state3_inferred__0/i_\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[1]\,
      I1 => \tx_64.dw_count_reg_n_0_[1]\,
      O => \state3_inferred__0/i__n_0\
    );
\tx_64.current_dw_count[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00890000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I1 => state(0),
      I2 => \tx_64.req_4dw_reg_n_0\,
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(1),
      O => current_dw_count(0)
    );
\tx_64.current_dw_count[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02330223"
    )
        port map (
      I0 => s_axis_tx_req_tready,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => state(1),
      I4 => state(0),
      O => \tx_64.current_dw_count[10]_i_1_n_0\
    );
\tx_64.current_dw_count[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF884888488848"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[10]\,
      I1 => \tx_64.current_dw_count[10]_i_3_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I3 => \tx_64.current_dw_count[10]_i_4_n_0\,
      I4 => \in28__0\(10),
      I5 => \tx_64.current_dw_count[10]_i_6_n_0\,
      O => current_dw_count(10)
    );
\tx_64.current_dw_count[10]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => state(0),
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => state(1),
      O => \tx_64.current_dw_count[10]_i_3_n_0\
    );
\tx_64.current_dw_count[10]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I2 => \tx_64.current_dw_count[6]_i_2_n_0\,
      I3 => \tx_64.current_dw_count_reg_n_0_[6]\,
      O => \tx_64.current_dw_count[10]_i_4_n_0\
    );
\tx_64.current_dw_count[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF7F0080"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I3 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I4 => \tx_64.current_dw_count_reg_n_0_[10]\,
      O => \in28__0\(10)
    );
\tx_64.current_dw_count[10]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => state(0),
      O => \tx_64.current_dw_count[10]_i_6_n_0\
    );
\tx_64.current_dw_count[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000B0001000A00"
    )
        port map (
      I0 => state(0),
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => state(1),
      I4 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I5 => \tx_64.current_dw_count_reg_n_0_[0]\,
      O => current_dw_count(1)
    );
\tx_64.current_dw_count[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FF0000013200000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => state(0),
      O => current_dw_count(2)
    );
\tx_64.current_dw_count[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4FFFF0004CCC8000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I1 => \tx_64.current_dw_count[10]_i_3_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I5 => \tx_64.current_dw_count[10]_i_6_n_0\,
      O => current_dw_count(3)
    );
\tx_64.current_dw_count[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F00F000051040000"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I2 => \tx_64.current_dw_count[5]_i_2_n_0\,
      I3 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => state(0),
      O => current_dw_count(4)
    );
\tx_64.current_dw_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF2F00F0AA2A0080"
    )
        port map (
      I0 => \tx_64.current_dw_count[10]_i_3_n_0\,
      I1 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I3 => \tx_64.current_dw_count[5]_i_2_n_0\,
      I4 => \tx_64.current_dw_count_reg_n_0_[5]\,
      I5 => \tx_64.current_dw_count[10]_i_6_n_0\,
      O => current_dw_count(5)
    );
\tx_64.current_dw_count[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[3]\,
      O => \tx_64.current_dw_count[5]_i_2_n_0\
    );
\tx_64.current_dw_count[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FF0000041410000"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \tx_64.current_dw_count[6]_i_2_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I3 => state3_i_1_n_0,
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => state(0),
      O => current_dw_count(6)
    );
\tx_64.current_dw_count[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[0]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I5 => \tx_64.current_dw_count_reg_n_0_[5]\,
      O => \tx_64.current_dw_count[6]_i_2_n_0\
    );
\tx_64.current_dw_count[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F00F000011440000"
    )
        port map (
      I0 => \tx_64.req_4dw_reg_n_0\,
      I1 => \tx_64.current_dw_count[8]_i_2_n_0\,
      I2 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I3 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => state(0),
      O => current_dw_count(7)
    );
\tx_64.current_dw_count[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF2F80F02A2A8080"
    )
        port map (
      I0 => \tx_64.current_dw_count[10]_i_3_n_0\,
      I1 => \tx_64.current_dw_count[8]_i_2_n_0\,
      I2 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I3 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I4 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I5 => \tx_64.current_dw_count[10]_i_6_n_0\,
      O => current_dw_count(8)
    );
\tx_64.current_dw_count[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I1 => \tx_64.current_dw_count[6]_i_2_n_0\,
      O => \tx_64.current_dw_count[8]_i_2_n_0\
    );
\tx_64.current_dw_count[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[6]\,
      I1 => \tx_64.current_dw_count_reg_n_0_[3]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[2]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[1]\,
      I4 => \tx_64.current_dw_count_reg_n_0_[4]\,
      I5 => \tx_64.current_dw_count_reg_n_0_[5]\,
      O => \tx_64.current_dw_count[8]_i_3_n_0\
    );
\tx_64.current_dw_count[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00000021210000"
    )
        port map (
      I0 => \tx_64.current_dw_count_reg_n_0_[9]\,
      I1 => \tx_64.req_4dw_reg_n_0\,
      I2 => \tx_64.current_dw_count[10]_i_4_n_0\,
      I3 => \in28__0\(9),
      I4 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I5 => state(0),
      O => current_dw_count(9)
    );
\tx_64.current_dw_count[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF40"
    )
        port map (
      I0 => \tx_64.current_dw_count[8]_i_3_n_0\,
      I1 => \tx_64.current_dw_count_reg_n_0_[8]\,
      I2 => \tx_64.current_dw_count_reg_n_0_[7]\,
      I3 => \tx_64.current_dw_count_reg_n_0_[9]\,
      O => \in28__0\(9)
    );
\tx_64.current_dw_count[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state(1),
      I1 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => \tx_64.current_dw_count[9]_i_3_n_0\
    );
\tx_64.current_dw_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(0),
      Q => \tx_64.current_dw_count_reg_n_0_[0]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(10),
      Q => \tx_64.current_dw_count_reg_n_0_[10]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(1),
      Q => \tx_64.current_dw_count_reg_n_0_[1]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(2),
      Q => \tx_64.current_dw_count_reg_n_0_[2]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(3),
      Q => \tx_64.current_dw_count_reg_n_0_[3]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(4),
      Q => \tx_64.current_dw_count_reg_n_0_[4]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(5),
      Q => \tx_64.current_dw_count_reg_n_0_[5]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(6),
      Q => \tx_64.current_dw_count_reg_n_0_[6]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(7),
      Q => \tx_64.current_dw_count_reg_n_0_[7]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(8),
      Q => \tx_64.current_dw_count_reg_n_0_[8]\,
      R => '0'
    );
\tx_64.current_dw_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.current_dw_count[10]_i_1_n_0\,
      D => current_dw_count(9),
      Q => \tx_64.current_dw_count_reg_n_0_[9]\,
      R => '0'
    );
\tx_64.dw_count[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF800000FF80FF"
    )
        port map (
      I0 => transfer_SM(1),
      I1 => s_axis_tx_tready,
      I2 => transfer_SM(0),
      I3 => state(1),
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I5 => state(0),
      O => \tx_64.dw_count[10]_i_1_n_0\
    );
\tx_64.dw_count[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888288888888888"
    )
        port map (
      I0 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[10]\,
      I2 => \tx_64.dw_count_reg_n_0_[9]\,
      I3 => \tx_64.dw_count_reg_n_0_[8]\,
      I4 => \tx_64.dw_count[10]_i_3_n_0\,
      I5 => \tx_64.dw_count_reg_n_0_[7]\,
      O => dw_count(10)
    );
\tx_64.dw_count[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[6]\,
      I1 => \tx_64.dw_count_reg_n_0_[3]\,
      I2 => \tx_64.dw_count_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[1]\,
      I4 => \tx_64.dw_count_reg_n_0_[4]\,
      I5 => \tx_64.dw_count_reg_n_0_[5]\,
      O => \tx_64.dw_count[10]_i_3_n_0\
    );
\tx_64.dw_count[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => \tx_64.dw_count_reg_n_0_[1]\,
      O => dw_count(1)
    );
\tx_64.dw_count[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0440"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => \tx_64.dw_count_reg_n_0_[2]\,
      I3 => \tx_64.dw_count_reg_n_0_[1]\,
      O => dw_count(2)
    );
\tx_64.dw_count[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04404040"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => \tx_64.dw_count_reg_n_0_[3]\,
      I3 => \tx_64.dw_count_reg_n_0_[2]\,
      I4 => \tx_64.dw_count_reg_n_0_[1]\,
      O => dw_count(3)
    );
\tx_64.dw_count[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0440404040404040"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => \tx_64.dw_count_reg_n_0_[4]\,
      I3 => \tx_64.dw_count_reg_n_0_[1]\,
      I4 => \tx_64.dw_count_reg_n_0_[2]\,
      I5 => \tx_64.dw_count_reg_n_0_[3]\,
      O => dw_count(4)
    );
\tx_64.dw_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888888888888"
    )
        port map (
      I0 => \tx_64.current_dw_count[9]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[5]\,
      I2 => \tx_64.dw_count_reg_n_0_[3]\,
      I3 => \tx_64.dw_count_reg_n_0_[2]\,
      I4 => \tx_64.dw_count_reg_n_0_[1]\,
      I5 => \tx_64.dw_count_reg_n_0_[4]\,
      O => dw_count(5)
    );
\tx_64.dw_count[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => \in26__0\(6),
      O => dw_count(6)
    );
\tx_64.dw_count[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[3]\,
      I1 => \tx_64.dw_count_reg_n_0_[2]\,
      I2 => \tx_64.dw_count_reg_n_0_[1]\,
      I3 => \tx_64.dw_count_reg_n_0_[4]\,
      I4 => \tx_64.dw_count_reg_n_0_[5]\,
      I5 => \tx_64.dw_count_reg_n_0_[6]\,
      O => \in26__0\(6)
    );
\tx_64.dw_count[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0900"
    )
        port map (
      I0 => \tx_64.dw_count[10]_i_3_n_0\,
      I1 => \tx_64.dw_count_reg_n_0_[7]\,
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I3 => state(1),
      O => dw_count(7)
    );
\tx_64.dw_count[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00D20000"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[7]\,
      I1 => \tx_64.dw_count[10]_i_3_n_0\,
      I2 => \tx_64.dw_count_reg_n_0_[8]\,
      I3 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I4 => state(1),
      O => dw_count(8)
    );
\tx_64.dw_count[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000DF2000000000"
    )
        port map (
      I0 => \tx_64.dw_count_reg_n_0_[8]\,
      I1 => \tx_64.dw_count[10]_i_3_n_0\,
      I2 => \tx_64.dw_count_reg_n_0_[7]\,
      I3 => \tx_64.dw_count_reg_n_0_[9]\,
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I5 => state(1),
      O => dw_count(9)
    );
\tx_64.dw_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(10),
      Q => \tx_64.dw_count_reg_n_0_[10]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(1),
      Q => \tx_64.dw_count_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(2),
      Q => \tx_64.dw_count_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(3),
      Q => \tx_64.dw_count_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(4),
      Q => \tx_64.dw_count_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(5),
      Q => \tx_64.dw_count_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(6),
      Q => \tx_64.dw_count_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(7),
      Q => \tx_64.dw_count_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(8),
      Q => \tx_64.dw_count_reg_n_0_[8]\,
      R => SR(0)
    );
\tx_64.dw_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.dw_count[10]_i_1_n_0\,
      D => dw_count(9),
      Q => \tx_64.dw_count_reg_n_0_[9]\,
      R => SR(0)
    );
\tx_64.req_4dw_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \tx_64.req_4dw_i_2_n_0\,
      I1 => \tx_64.req_4dw_i_3_n_0\,
      I2 => \m_axis_rq\\.tdata\(57),
      I3 => \m_axis_rq\\.tdata\(56),
      I4 => \m_axis_rq\\.tdata\(55),
      I5 => \m_axis_rq\\.tdata\(54),
      O => \tx_64.req_4dw_i_1_n_0\
    );
\tx_64.req_4dw_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tx_64.req_4dw_i_4_n_0\,
      I1 => \m_axis_rq\\.tdata\(58),
      I2 => \m_axis_rq\\.tdata\(59),
      I3 => \m_axis_rq\\.tdata\(60),
      I4 => \m_axis_rq\\.tdata\(61),
      O => \tx_64.req_4dw_i_2_n_0\
    );
\tx_64.req_4dw_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(49),
      I1 => \m_axis_rq\\.tdata\(48),
      I2 => \tx_64.req_4dw_i_5_n_0\,
      I3 => \tx_64.req_4dw_i_6_n_0\,
      I4 => \tx_64.req_4dw_i_7_n_0\,
      I5 => \tx_64.req_4dw_i_8_n_0\,
      O => \tx_64.req_4dw_i_3_n_0\
    );
\tx_64.req_4dw_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(50),
      I1 => \m_axis_rq\\.tdata\(51),
      I2 => \m_axis_rq\\.tdata\(52),
      I3 => \m_axis_rq\\.tdata\(53),
      I4 => \m_axis_rq\\.tdata\(63),
      I5 => \m_axis_rq\\.tdata\(62),
      O => \tx_64.req_4dw_i_4_n_0\
    );
\tx_64.req_4dw_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(39),
      I1 => \m_axis_rq\\.tdata\(38),
      I2 => \m_axis_rq\\.tdata\(37),
      I3 => \m_axis_rq\\.tdata\(36),
      O => \tx_64.req_4dw_i_5_n_0\
    );
\tx_64.req_4dw_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(35),
      I1 => \m_axis_rq\\.tdata\(34),
      I2 => \m_axis_rq\\.tdata\(33),
      I3 => \m_axis_rq\\.tdata\(32),
      O => \tx_64.req_4dw_i_6_n_0\
    );
\tx_64.req_4dw_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(47),
      I1 => \m_axis_rq\\.tdata\(46),
      I2 => \m_axis_rq\\.tdata\(45),
      I3 => \m_axis_rq\\.tdata\(44),
      O => \tx_64.req_4dw_i_7_n_0\
    );
\tx_64.req_4dw_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(43),
      I1 => \m_axis_rq\\.tdata\(42),
      I2 => \m_axis_rq\\.tdata\(41),
      I3 => \m_axis_rq\\.tdata\(40),
      O => \tx_64.req_4dw_i_8_n_0\
    );
\tx_64.req_4dw_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \tx_64.req_4dw_i_1_n_0\,
      Q => \tx_64.req_4dw_reg_n_0\,
      R => SR(0)
    );
\tx_64.req_addr_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(10),
      Q => \^q\(8),
      R => SR(0)
    );
\tx_64.req_addr_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(11),
      Q => \^q\(9),
      R => SR(0)
    );
\tx_64.req_addr_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(12),
      Q => p_0_in(44),
      R => SR(0)
    );
\tx_64.req_addr_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(13),
      Q => \^q\(10),
      R => SR(0)
    );
\tx_64.req_addr_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(14),
      Q => \^q\(11),
      R => SR(0)
    );
\tx_64.req_addr_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(15),
      Q => \^q\(12),
      R => SR(0)
    );
\tx_64.req_addr_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(16),
      Q => p_0_in(48),
      R => SR(0)
    );
\tx_64.req_addr_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(17),
      Q => p_0_in(49),
      R => SR(0)
    );
\tx_64.req_addr_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(18),
      Q => p_0_in(50),
      R => SR(0)
    );
\tx_64.req_addr_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(19),
      Q => p_0_in(51),
      R => SR(0)
    );
\tx_64.req_addr_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(20),
      Q => p_0_in(52),
      R => SR(0)
    );
\tx_64.req_addr_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(21),
      Q => p_0_in(53),
      R => SR(0)
    );
\tx_64.req_addr_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(22),
      Q => p_0_in(54),
      R => SR(0)
    );
\tx_64.req_addr_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(23),
      Q => p_0_in(55),
      R => SR(0)
    );
\tx_64.req_addr_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(24),
      Q => \^q\(13),
      R => SR(0)
    );
\tx_64.req_addr_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(25),
      Q => \^q\(14),
      R => SR(0)
    );
\tx_64.req_addr_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(26),
      Q => \^q\(15),
      R => SR(0)
    );
\tx_64.req_addr_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(27),
      Q => \^q\(16),
      R => SR(0)
    );
\tx_64.req_addr_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(28),
      Q => \^q\(17),
      R => SR(0)
    );
\tx_64.req_addr_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(29),
      Q => \^q\(18),
      R => SR(0)
    );
\tx_64.req_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(2),
      Q => \^q\(0),
      R => SR(0)
    );
\tx_64.req_addr_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(30),
      Q => \^q\(19),
      R => SR(0)
    );
\tx_64.req_addr_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(31),
      Q => \^q\(20),
      R => SR(0)
    );
\tx_64.req_addr_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(32),
      Q => p_0_in(0),
      R => SR(0)
    );
\tx_64.req_addr_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(33),
      Q => p_0_in(1),
      R => SR(0)
    );
\tx_64.req_addr_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(34),
      Q => \^q\(21),
      R => SR(0)
    );
\tx_64.req_addr_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(35),
      Q => p_0_in(3),
      R => SR(0)
    );
\tx_64.req_addr_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(36),
      Q => p_0_in(4),
      R => SR(0)
    );
\tx_64.req_addr_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(37),
      Q => p_0_in(5),
      R => SR(0)
    );
\tx_64.req_addr_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(38),
      Q => p_0_in(6),
      R => SR(0)
    );
\tx_64.req_addr_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(39),
      Q => p_0_in(7),
      R => SR(0)
    );
\tx_64.req_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(3),
      Q => \^q\(1),
      R => SR(0)
    );
\tx_64.req_addr_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(40),
      Q => p_0_in(8),
      R => SR(0)
    );
\tx_64.req_addr_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(41),
      Q => p_0_in(9),
      R => SR(0)
    );
\tx_64.req_addr_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(42),
      Q => p_0_in(10),
      R => SR(0)
    );
\tx_64.req_addr_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(43),
      Q => p_0_in(11),
      R => SR(0)
    );
\tx_64.req_addr_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(44),
      Q => p_0_in(12),
      R => SR(0)
    );
\tx_64.req_addr_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(45),
      Q => p_0_in(13),
      R => SR(0)
    );
\tx_64.req_addr_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(46),
      Q => p_0_in(14),
      R => SR(0)
    );
\tx_64.req_addr_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(47),
      Q => p_0_in(15),
      R => SR(0)
    );
\tx_64.req_addr_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(48),
      Q => p_0_in(16),
      R => SR(0)
    );
\tx_64.req_addr_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(49),
      Q => p_0_in(17),
      R => SR(0)
    );
\tx_64.req_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(4),
      Q => \^q\(2),
      R => SR(0)
    );
\tx_64.req_addr_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(50),
      Q => p_0_in(18),
      R => SR(0)
    );
\tx_64.req_addr_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(51),
      Q => p_0_in(19),
      R => SR(0)
    );
\tx_64.req_addr_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(52),
      Q => p_0_in(20),
      R => SR(0)
    );
\tx_64.req_addr_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(53),
      Q => p_0_in(21),
      R => SR(0)
    );
\tx_64.req_addr_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(54),
      Q => p_0_in(22),
      R => SR(0)
    );
\tx_64.req_addr_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(55),
      Q => p_0_in(23),
      R => SR(0)
    );
\tx_64.req_addr_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(56),
      Q => p_0_in(24),
      R => SR(0)
    );
\tx_64.req_addr_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(57),
      Q => p_0_in(25),
      R => SR(0)
    );
\tx_64.req_addr_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(58),
      Q => p_0_in(26),
      R => SR(0)
    );
\tx_64.req_addr_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(59),
      Q => p_0_in(27),
      R => SR(0)
    );
\tx_64.req_addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(5),
      Q => \^q\(3),
      R => SR(0)
    );
\tx_64.req_addr_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(60),
      Q => p_0_in(28),
      R => SR(0)
    );
\tx_64.req_addr_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(61),
      Q => p_0_in(29),
      R => SR(0)
    );
\tx_64.req_addr_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(62),
      Q => p_0_in(30),
      R => SR(0)
    );
\tx_64.req_addr_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(63),
      Q => p_0_in(31),
      R => SR(0)
    );
\tx_64.req_addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(6),
      Q => \^q\(4),
      R => SR(0)
    );
\tx_64.req_addr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(7),
      Q => \^q\(5),
      R => SR(0)
    );
\tx_64.req_addr_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(8),
      Q => \^q\(6),
      R => SR(0)
    );
\tx_64.req_addr_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(9),
      Q => \^q\(7),
      R => SR(0)
    );
\tx_64.req_at[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010001000000010"
    )
        port map (
      I0 => state(1),
      I1 => in_packet_q,
      I2 => \m_axis_rq\\.tvalid\,
      I3 => state(0),
      I4 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I5 => s_axis_tx_req_tready,
      O => req_at
    );
\tx_64.req_at_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(0),
      Q => p_0_out(10),
      R => SR(0)
    );
\tx_64.req_at_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tdata\(1),
      Q => p_0_out(11),
      R => SR(0)
    );
\tx_64.req_fbe_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(0),
      Q => p_0_out(32),
      R => SR(0)
    );
\tx_64.req_fbe_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(1),
      Q => p_0_out(33),
      R => SR(0)
    );
\tx_64.req_fbe_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(2),
      Q => p_0_out(34),
      R => SR(0)
    );
\tx_64.req_fbe_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(3),
      Q => p_0_out(35),
      R => SR(0)
    );
\tx_64.req_lbe_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(4),
      Q => p_0_out(36),
      R => SR(0)
    );
\tx_64.req_lbe_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(5),
      Q => p_0_out(37),
      R => SR(0)
    );
\tx_64.req_lbe_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(6),
      Q => p_0_out(38),
      R => SR(0)
    );
\tx_64.req_lbe_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(7),
      Q => p_0_out(39),
      R => SR(0)
    );
\tx_64.req_len[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(0),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(0)
    );
\tx_64.req_len[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(1),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(1)
    );
\tx_64.req_len[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(2),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(2)
    );
\tx_64.req_len[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(3),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(3)
    );
\tx_64.req_len[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(4),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(4)
    );
\tx_64.req_len[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(5),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(5)
    );
\tx_64.req_len[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(6),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(6)
    );
\tx_64.req_len[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(7),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(7)
    );
\tx_64.req_len[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(8),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(8)
    );
\tx_64.req_len[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"31"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => state(0),
      O => \tx_64.req_len[9]_i_1_n_0\
    );
\tx_64.req_len[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(9),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      O => req_len(9)
    );
\tx_64.req_len_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(0),
      Q => \tx_64.req_len_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_len_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(1),
      Q => \tx_64.req_len_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_len_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(2),
      Q => \tx_64.req_len_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_len_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(3),
      Q => \tx_64.req_len_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_len_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(4),
      Q => \tx_64.req_len_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_len_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(5),
      Q => \tx_64.req_len_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_len_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(6),
      Q => \tx_64.req_len_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_len_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(7),
      Q => \tx_64.req_len_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_len_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(8),
      Q => \tx_64.req_len_reg_n_0_[8]\,
      R => SR(0)
    );
\tx_64.req_len_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_len[9]_i_1_n_0\,
      D => req_len(9),
      Q => \tx_64.req_len_reg_n_0_[9]\,
      R => SR(0)
    );
\tx_64.seq_num_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(8),
      Q => \tx_64.seq_num_reg[3]_0\(0),
      R => SR(0)
    );
\tx_64.seq_num_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(9),
      Q => \tx_64.seq_num_reg[3]_0\(1),
      R => SR(0)
    );
\tx_64.seq_num_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(10),
      Q => \tx_64.seq_num_reg[3]_0\(2),
      R => SR(0)
    );
\tx_64.seq_num_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => req_at,
      D => \m_axis_rq\\.tuser\(11),
      Q => \tx_64.seq_num_reg[3]_0\(3),
      R => SR(0)
    );
\tx_64.wr_data[63]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => transfer_SM(0),
      I3 => s_axis_tx_tready,
      I4 => transfer_SM(1),
      O => wr_data
    );
\tx_64.wr_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(0),
      Q => wreq_data_le(24),
      R => SR(0)
    );
\tx_64.wr_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(10),
      Q => wreq_data_le(18),
      R => SR(0)
    );
\tx_64.wr_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(11),
      Q => wreq_data_le(19),
      R => SR(0)
    );
\tx_64.wr_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(12),
      Q => wreq_data_le(20),
      R => SR(0)
    );
\tx_64.wr_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(13),
      Q => wreq_data_le(21),
      R => SR(0)
    );
\tx_64.wr_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(14),
      Q => wreq_data_le(22),
      R => SR(0)
    );
\tx_64.wr_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(15),
      Q => wreq_data_le(23),
      R => SR(0)
    );
\tx_64.wr_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(16),
      Q => wreq_data_le(8),
      R => SR(0)
    );
\tx_64.wr_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(17),
      Q => wreq_data_le(9),
      R => SR(0)
    );
\tx_64.wr_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(18),
      Q => wreq_data_le(10),
      R => SR(0)
    );
\tx_64.wr_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(19),
      Q => wreq_data_le(11),
      R => SR(0)
    );
\tx_64.wr_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(1),
      Q => wreq_data_le(25),
      R => SR(0)
    );
\tx_64.wr_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(20),
      Q => wreq_data_le(12),
      R => SR(0)
    );
\tx_64.wr_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(21),
      Q => wreq_data_le(13),
      R => SR(0)
    );
\tx_64.wr_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(22),
      Q => wreq_data_le(14),
      R => SR(0)
    );
\tx_64.wr_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(23),
      Q => wreq_data_le(15),
      R => SR(0)
    );
\tx_64.wr_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(24),
      Q => wreq_data_le(0),
      R => SR(0)
    );
\tx_64.wr_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(25),
      Q => wreq_data_le(1),
      R => SR(0)
    );
\tx_64.wr_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(26),
      Q => wreq_data_le(2),
      R => SR(0)
    );
\tx_64.wr_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(27),
      Q => wreq_data_le(3),
      R => SR(0)
    );
\tx_64.wr_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(28),
      Q => wreq_data_le(4),
      R => SR(0)
    );
\tx_64.wr_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(29),
      Q => wreq_data_le(5),
      R => SR(0)
    );
\tx_64.wr_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(2),
      Q => wreq_data_le(26),
      R => SR(0)
    );
\tx_64.wr_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(30),
      Q => wreq_data_le(6),
      R => SR(0)
    );
\tx_64.wr_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(31),
      Q => \^tx_64.wr_data_reg[55]_0\(0),
      R => SR(0)
    );
\tx_64.wr_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(32),
      Q => \^tx_64.wr_data_reg[55]_0\(1),
      R => SR(0)
    );
\tx_64.wr_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(33),
      Q => wreq_data_le(57),
      R => SR(0)
    );
\tx_64.wr_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(34),
      Q => \^tx_64.wr_data_reg[55]_0\(2),
      R => SR(0)
    );
\tx_64.wr_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(35),
      Q => wreq_data_le(59),
      R => SR(0)
    );
\tx_64.wr_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(36),
      Q => \^tx_64.wr_data_reg[55]_0\(3),
      R => SR(0)
    );
\tx_64.wr_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(37),
      Q => wreq_data_le(61),
      R => SR(0)
    );
\tx_64.wr_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(38),
      Q => wreq_data_le(62),
      R => SR(0)
    );
\tx_64.wr_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(39),
      Q => \^tx_64.wr_data_reg[55]_0\(4),
      R => SR(0)
    );
\tx_64.wr_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(3),
      Q => wreq_data_le(27),
      R => SR(0)
    );
\tx_64.wr_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(40),
      Q => \^tx_64.wr_data_reg[55]_0\(5),
      R => SR(0)
    );
\tx_64.wr_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(41),
      Q => \^tx_64.wr_data_reg[55]_0\(6),
      R => SR(0)
    );
\tx_64.wr_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(42),
      Q => wreq_data_le(50),
      R => SR(0)
    );
\tx_64.wr_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(43),
      Q => \^tx_64.wr_data_reg[55]_0\(7),
      R => SR(0)
    );
\tx_64.wr_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(44),
      Q => wreq_data_le(52),
      R => SR(0)
    );
\tx_64.wr_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(45),
      Q => wreq_data_le(53),
      R => SR(0)
    );
\tx_64.wr_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(46),
      Q => wreq_data_le(54),
      R => SR(0)
    );
\tx_64.wr_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(47),
      Q => \^tx_64.wr_data_reg[55]_0\(8),
      R => SR(0)
    );
\tx_64.wr_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(48),
      Q => wreq_data_le(40),
      R => SR(0)
    );
\tx_64.wr_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(49),
      Q => wreq_data_le(41),
      R => SR(0)
    );
\tx_64.wr_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(4),
      Q => wreq_data_le(28),
      R => SR(0)
    );
\tx_64.wr_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(50),
      Q => wreq_data_le(42),
      R => SR(0)
    );
\tx_64.wr_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(51),
      Q => wreq_data_le(43),
      R => SR(0)
    );
\tx_64.wr_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(52),
      Q => wreq_data_le(44),
      R => SR(0)
    );
\tx_64.wr_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(53),
      Q => wreq_data_le(45),
      R => SR(0)
    );
\tx_64.wr_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(54),
      Q => wreq_data_le(46),
      R => SR(0)
    );
\tx_64.wr_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(55),
      Q => \^tx_64.wr_data_reg[55]_0\(9),
      R => SR(0)
    );
\tx_64.wr_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(56),
      Q => wreq_data_le(32),
      R => SR(0)
    );
\tx_64.wr_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(57),
      Q => wreq_data_le(33),
      R => SR(0)
    );
\tx_64.wr_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(58),
      Q => wreq_data_le(34),
      R => SR(0)
    );
\tx_64.wr_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(59),
      Q => wreq_data_le(35),
      R => SR(0)
    );
\tx_64.wr_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(5),
      Q => wreq_data_le(29),
      R => SR(0)
    );
\tx_64.wr_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(60),
      Q => wreq_data_le(36),
      R => SR(0)
    );
\tx_64.wr_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(61),
      Q => wreq_data_le(37),
      R => SR(0)
    );
\tx_64.wr_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(62),
      Q => wreq_data_le(38),
      R => SR(0)
    );
\tx_64.wr_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(63),
      Q => wreq_data_le(39),
      R => SR(0)
    );
\tx_64.wr_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(6),
      Q => wreq_data_le(30),
      R => SR(0)
    );
\tx_64.wr_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(7),
      Q => wreq_data_le(31),
      R => SR(0)
    );
\tx_64.wr_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(8),
      Q => wreq_data_le(16),
      R => SR(0)
    );
\tx_64.wr_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => wr_data,
      D => \m_axis_rq\\.tdata\(9),
      Q => wreq_data_le(17),
      R => SR(0)
    );
udma_wrapper_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF89"
    )
        port map (
      I0 => state(1),
      I1 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I2 => state(0),
      I3 => s_axis_tx_req_tready,
      I4 => SR(0),
      O => \m_axis_rq\\.tready\
    );
udma_wrapper_i_237: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0602"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[2]_0\(0),
      I1 => state(1),
      I2 => SR(0),
      I3 => udma_wrapper_i_253_n_0,
      O => \FSM_sequential_tx_64.state_reg[2]_3\
    );
udma_wrapper_i_253: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF100010"
    )
        port map (
      I0 => udma_wrapper_i_263_n_0,
      I1 => \tx_64.req_len_reg_n_0_[1]\,
      I2 => \tx_64.req_len_reg_n_0_[0]\,
      I3 => state(0),
      I4 => \s_axis_tx_tlast0_inferred__0/i__carry_n_0\,
      O => udma_wrapper_i_253_n_0
    );
udma_wrapper_i_263: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[7]\,
      I1 => \tx_64.req_len_reg_n_0_[6]\,
      I2 => \tx_64.req_len_reg_n_0_[9]\,
      I3 => \tx_64.req_len_reg_n_0_[8]\,
      I4 => udma_wrapper_i_264_n_0,
      O => udma_wrapper_i_263_n_0
    );
udma_wrapper_i_264: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tx_64.req_len_reg_n_0_[4]\,
      I1 => \tx_64.req_len_reg_n_0_[5]\,
      I2 => \tx_64.req_len_reg_n_0_[2]\,
      I3 => \tx_64.req_len_reg_n_0_[3]\,
      O => udma_wrapper_i_264_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_rx_null_gen is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cur_state_reg_0 : out STD_LOGIC;
    \reg_tkeep[7]_i_7_0\ : out STD_LOGIC;
    \reg_pkt_len_counter_reg[0]_0\ : out STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cur_state_reg_1 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \m_axis_rx_tuser_reg[19]\ : in STD_LOGIC;
    null_mux_sel : in STD_LOGIC;
    \m_axis_rx_tuser_reg[21]\ : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    cur_state_reg_2 : in STD_LOGIC;
    m_axis_rx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    new_pkt_len : in STD_LOGIC_VECTOR ( 10 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_rx_null_gen : entity is "xdma_0_pcie2_ip_axi_basic_rx_null_gen";
end xdma_0_xdma_0_pcie2_ip_axi_basic_rx_null_gen;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_rx_null_gen is
  signal cur_state : STD_LOGIC;
  signal \^cur_state_reg_0\ : STD_LOGIC;
  signal next_state : STD_LOGIC;
  signal pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal pkt_len_counter_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \pkt_len_counter_dec__0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_n_1\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_n_2\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__0_n_3\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__1_n_2\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry__1_n_3\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_i_1_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_i_2_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_i_3_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_i_4_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_i_5_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_n_0\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_n_1\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_n_2\ : STD_LOGIC;
  signal \pkt_len_counter_dec__0_carry_n_3\ : STD_LOGIC;
  signal reg_pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \reg_pkt_len_counter[11]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_4_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_4_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_5_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_6_n_0\ : STD_LOGIC;
  signal \^reg_tkeep[7]_i_7_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_7_n_0\ : STD_LOGIC;
  signal reg_tlast_i_3_n_0 : STD_LOGIC;
  signal reg_tlast_i_4_n_0 : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 11 downto 2 );
  signal \NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry\ : label is 35;
  attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \pkt_len_counter_dec__0_carry__1\ : label is 35;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[0]_i_1\ : label is "soft_lutpair1910";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[10]_i_1\ : label is "soft_lutpair1911";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[11]_i_1\ : label is "soft_lutpair1912";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[1]_i_1\ : label is "soft_lutpair1914";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[3]_i_1\ : label is "soft_lutpair1909";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[4]_i_1\ : label is "soft_lutpair1913";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[5]_i_1\ : label is "soft_lutpair1908";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[6]_i_1\ : label is "soft_lutpair1913";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[7]_i_1\ : label is "soft_lutpair1907";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[8]_i_1\ : label is "soft_lutpair1906";
  attribute SOFT_HLUTNM of \reg_pkt_len_counter[9]_i_1\ : label is "soft_lutpair1912";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_3\ : label is "soft_lutpair1914";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_4\ : label is "soft_lutpair1907";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_5\ : label is "soft_lutpair1906";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_6\ : label is "soft_lutpair1909";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_7\ : label is "soft_lutpair1908";
  attribute SOFT_HLUTNM of reg_tlast_i_3 : label is "soft_lutpair1911";
  attribute SOFT_HLUTNM of reg_tlast_i_4 : label is "soft_lutpair1910";
begin
  cur_state_reg_0 <= \^cur_state_reg_0\;
  \reg_tkeep[7]_i_7_0\ <= \^reg_tkeep[7]_i_7_0\;
cur_state_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAEA"
    )
        port map (
      I0 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I1 => m_axis_rx_tready,
      I2 => cur_state_reg_2,
      I3 => cur_state,
      I4 => m_axis_rx_tuser(0),
      O => next_state
    );
cur_state_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => next_state,
      Q => cur_state,
      R => cur_state_reg_1
    );
\m_axis_rx_tuser[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404045404040404"
    )
        port map (
      I0 => cur_state_reg_1,
      I1 => \m_axis_rx_tuser_reg[19]\,
      I2 => null_mux_sel,
      I3 => pkt_len_counter_0(0),
      I4 => \^cur_state_reg_0\,
      I5 => \^reg_tkeep[7]_i_7_0\,
      O => D(0)
    );
\m_axis_rx_tuser[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4505054540000040"
    )
        port map (
      I0 => cur_state_reg_1,
      I1 => \^reg_tkeep[7]_i_7_0\,
      I2 => null_mux_sel,
      I3 => pkt_len_counter_0(0),
      I4 => \^cur_state_reg_0\,
      I5 => \m_axis_rx_tuser_reg[21]\,
      O => D(1)
    );
\pkt_len_counter_dec__0_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \pkt_len_counter_dec__0_carry_n_0\,
      CO(2) => \pkt_len_counter_dec__0_carry_n_1\,
      CO(1) => \pkt_len_counter_dec__0_carry_n_2\,
      CO(0) => \pkt_len_counter_dec__0_carry_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => reg_pkt_len_counter(3 downto 2),
      DI(1) => \pkt_len_counter_dec__0_carry_i_1_n_0\,
      DI(0) => '0',
      O(3 downto 0) => pkt_len_counter(4 downto 1),
      S(3) => \pkt_len_counter_dec__0_carry_i_2_n_0\,
      S(2) => \pkt_len_counter_dec__0_carry_i_3_n_0\,
      S(1) => \pkt_len_counter_dec__0_carry_i_4_n_0\,
      S(0) => \pkt_len_counter_dec__0_carry_i_5_n_0\
    );
\pkt_len_counter_dec__0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \pkt_len_counter_dec__0_carry_n_0\,
      CO(3) => \pkt_len_counter_dec__0_carry__0_n_0\,
      CO(2) => \pkt_len_counter_dec__0_carry__0_n_1\,
      CO(1) => \pkt_len_counter_dec__0_carry__0_n_2\,
      CO(0) => \pkt_len_counter_dec__0_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => reg_pkt_len_counter(7 downto 4),
      O(3 downto 0) => pkt_len_counter(8 downto 5),
      S(3) => \pkt_len_counter_dec__0_carry__0_i_1_n_0\,
      S(2) => \pkt_len_counter_dec__0_carry__0_i_2_n_0\,
      S(1) => \pkt_len_counter_dec__0_carry__0_i_3_n_0\,
      S(0) => \pkt_len_counter_dec__0_carry__0_i_4_n_0\
    );
\pkt_len_counter_dec__0_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(7),
      I1 => reg_pkt_len_counter(8),
      O => \pkt_len_counter_dec__0_carry__0_i_1_n_0\
    );
\pkt_len_counter_dec__0_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(6),
      I1 => reg_pkt_len_counter(7),
      O => \pkt_len_counter_dec__0_carry__0_i_2_n_0\
    );
\pkt_len_counter_dec__0_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(5),
      I1 => reg_pkt_len_counter(6),
      O => \pkt_len_counter_dec__0_carry__0_i_3_n_0\
    );
\pkt_len_counter_dec__0_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(4),
      I1 => reg_pkt_len_counter(5),
      O => \pkt_len_counter_dec__0_carry__0_i_4_n_0\
    );
\pkt_len_counter_dec__0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \pkt_len_counter_dec__0_carry__0_n_0\,
      CO(3 downto 2) => \NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \pkt_len_counter_dec__0_carry__1_n_2\,
      CO(0) => \pkt_len_counter_dec__0_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => reg_pkt_len_counter(9 downto 8),
      O(3) => \NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED\(3),
      O(2 downto 0) => pkt_len_counter(11 downto 9),
      S(3) => '0',
      S(2) => \pkt_len_counter_dec__0_carry__1_i_1_n_0\,
      S(1) => \pkt_len_counter_dec__0_carry__1_i_2_n_0\,
      S(0) => \pkt_len_counter_dec__0_carry__1_i_3_n_0\
    );
\pkt_len_counter_dec__0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(10),
      I1 => reg_pkt_len_counter(11),
      O => \pkt_len_counter_dec__0_carry__1_i_1_n_0\
    );
\pkt_len_counter_dec__0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(9),
      I1 => reg_pkt_len_counter(10),
      O => \pkt_len_counter_dec__0_carry__1_i_2_n_0\
    );
\pkt_len_counter_dec__0_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(8),
      I1 => reg_pkt_len_counter(9),
      O => \pkt_len_counter_dec__0_carry__1_i_3_n_0\
    );
\pkt_len_counter_dec__0_carry_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => m_axis_rx_tready,
      O => \pkt_len_counter_dec__0_carry_i_1_n_0\
    );
\pkt_len_counter_dec__0_carry_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(3),
      I1 => reg_pkt_len_counter(4),
      O => \pkt_len_counter_dec__0_carry_i_2_n_0\
    );
\pkt_len_counter_dec__0_carry_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(2),
      I1 => reg_pkt_len_counter(3),
      O => \pkt_len_counter_dec__0_carry_i_3_n_0\
    );
\pkt_len_counter_dec__0_carry_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => reg_pkt_len_counter(1),
      I2 => reg_pkt_len_counter(2),
      O => \pkt_len_counter_dec__0_carry_i_4_n_0\
    );
\pkt_len_counter_dec__0_carry_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => m_axis_rx_tready,
      O => \pkt_len_counter_dec__0_carry_i_5_n_0\
    );
\reg_pkt_len_counter[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => reg_pkt_len_counter(0),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(0),
      O => pkt_len_counter_0(0)
    );
\reg_pkt_len_counter[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(10),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(10),
      O => sel0(10)
    );
\reg_pkt_len_counter[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => pkt_len_counter(11),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      O => sel0(11)
    );
\reg_pkt_len_counter[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => cur_state,
      I1 => reg_pkt_len_counter(4),
      I2 => reg_pkt_len_counter(7),
      I3 => reg_pkt_len_counter(8),
      I4 => \reg_pkt_len_counter[11]_i_3_n_0\,
      I5 => \reg_pkt_len_counter[11]_i_4_n_0\,
      O => \reg_pkt_len_counter[11]_i_2_n_0\
    );
\reg_pkt_len_counter[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => reg_pkt_len_counter(3),
      I2 => reg_pkt_len_counter(9),
      I3 => reg_pkt_len_counter(2),
      O => \reg_pkt_len_counter[11]_i_3_n_0\
    );
\reg_pkt_len_counter[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => reg_pkt_len_counter(5),
      I1 => reg_pkt_len_counter(6),
      I2 => reg_pkt_len_counter(10),
      I3 => reg_pkt_len_counter(11),
      I4 => reg_pkt_len_counter(0),
      I5 => reg_pkt_len_counter(1),
      O => \reg_pkt_len_counter[11]_i_4_n_0\
    );
\reg_pkt_len_counter[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(1),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(1),
      O => pkt_len_counter_0(1)
    );
\reg_pkt_len_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(2),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(2),
      O => sel0(2)
    );
\reg_pkt_len_counter[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(3),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(3),
      O => sel0(3)
    );
\reg_pkt_len_counter[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EEE"
    )
        port map (
      I0 => Q(2),
      I1 => Q(3),
      I2 => Q(1),
      I3 => Q(4),
      O => S(1)
    );
\reg_pkt_len_counter[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6999"
    )
        port map (
      I0 => Q(3),
      I1 => Q(2),
      I2 => Q(4),
      I3 => Q(0),
      O => S(0)
    );
\reg_pkt_len_counter[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(4),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(4),
      O => sel0(4)
    );
\reg_pkt_len_counter[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(5),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(5),
      O => sel0(5)
    );
\reg_pkt_len_counter[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(6),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(6),
      O => sel0(6)
    );
\reg_pkt_len_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(7),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(7),
      O => sel0(7)
    );
\reg_pkt_len_counter[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(8),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(8),
      O => sel0(8)
    );
\reg_pkt_len_counter[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => pkt_len_counter(9),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(9),
      O => sel0(9)
    );
\reg_pkt_len_counter_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pkt_len_counter_0(0),
      Q => reg_pkt_len_counter(0),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(10),
      Q => reg_pkt_len_counter(10),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(11),
      Q => reg_pkt_len_counter(11),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pkt_len_counter_0(1),
      Q => reg_pkt_len_counter(1),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(2),
      Q => reg_pkt_len_counter(2),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(3),
      Q => reg_pkt_len_counter(3),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(4),
      Q => reg_pkt_len_counter(4),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(5),
      Q => reg_pkt_len_counter(5),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(6),
      Q => reg_pkt_len_counter(6),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(7),
      Q => reg_pkt_len_counter(7),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(8),
      Q => reg_pkt_len_counter(8),
      R => cur_state_reg_1
    );
\reg_pkt_len_counter_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => sel0(9),
      Q => reg_pkt_len_counter(9),
      R => cur_state_reg_1
    );
\reg_tkeep[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => sel0(11),
      I1 => sel0(10),
      I2 => \reg_tkeep[7]_i_4_n_0\,
      I3 => \reg_tkeep[7]_i_5_n_0\,
      I4 => \reg_tkeep[7]_i_6_n_0\,
      I5 => \reg_tkeep[7]_i_7_n_0\,
      O => \^reg_tkeep[7]_i_7_0\
    );
\reg_tkeep[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1D"
    )
        port map (
      I0 => new_pkt_len(1),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => pkt_len_counter(1),
      O => \^cur_state_reg_0\
    );
\reg_tkeep[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(7),
      I1 => pkt_len_counter(7),
      I2 => new_pkt_len(6),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => pkt_len_counter(6),
      O => \reg_tkeep[7]_i_4_n_0\
    );
\reg_tkeep[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(8),
      I1 => pkt_len_counter(8),
      I2 => new_pkt_len(9),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => pkt_len_counter(9),
      O => \reg_tkeep[7]_i_5_n_0\
    );
\reg_tkeep[7]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(3),
      I1 => pkt_len_counter(3),
      I2 => new_pkt_len(2),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => pkt_len_counter(2),
      O => \reg_tkeep[7]_i_6_n_0\
    );
\reg_tkeep[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(5),
      I1 => pkt_len_counter(5),
      I2 => new_pkt_len(4),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => pkt_len_counter(4),
      O => \reg_tkeep[7]_i_7_n_0\
    );
reg_tlast_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \reg_tkeep[7]_i_7_n_0\,
      I1 => \reg_tkeep[7]_i_6_n_0\,
      I2 => \reg_tkeep[7]_i_5_n_0\,
      I3 => \reg_tkeep[7]_i_4_n_0\,
      I4 => reg_tlast_i_3_n_0,
      I5 => reg_tlast_i_4_n_0,
      O => \reg_pkt_len_counter_reg[0]_0\
    );
reg_tlast_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0535"
    )
        port map (
      I0 => new_pkt_len(10),
      I1 => pkt_len_counter(10),
      I2 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I3 => pkt_len_counter(11),
      O => reg_tlast_i_3_n_0
    );
reg_tlast_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C0AAC000"
    )
        port map (
      I0 => new_pkt_len(0),
      I1 => reg_pkt_len_counter(0),
      I2 => pkt_len_counter(1),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(1),
      O => reg_tlast_i_4_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_rx_pipeline is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc_d : out STD_LOGIC;
    m_axis_rx_tvalid_reg_0 : out STD_LOGIC;
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    null_mux_sel : out STD_LOGIC;
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_reof_prev_reg_0 : out STD_LOGIC;
    \trn_rrem_prev_reg[0]_0\ : out STD_LOGIC;
    new_pkt_len : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \trn_rbar_hit_prev_reg[0]_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered : in STD_LOGIC;
    trn_reof : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    trn_in_packet_reg_0 : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    null_mux_sel_reg_0 : in STD_LOGIC;
    \reg_tkeep_reg[7]_0\ : in STD_LOGIC;
    \reg_tkeep_reg[7]_1\ : in STD_LOGIC;
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 );
    S : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_rx_pipeline : entity is "xdma_0_pcie2_ip_axi_basic_rx_pipeline";
end xdma_0_xdma_0_pcie2_ip_axi_basic_rx_pipeline;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_rx_pipeline is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal data_hold : STD_LOGIC;
  signal data_prev : STD_LOGIC;
  signal \m_axis_rx_tdata[63]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[14]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[14]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[18]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[1]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[21]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[2]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[3]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[4]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[5]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[6]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[7]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser[8]_i_1_n_0\ : STD_LOGIC;
  signal m_axis_rx_tvalid_i_1_n_0 : STD_LOGIC;
  signal \^m_axis_rx_tvalid_reg_0\ : STD_LOGIC;
  signal \^null_mux_sel\ : STD_LOGIC;
  signal null_mux_sel_i_1_n_0 : STD_LOGIC;
  signal null_mux_sel_i_2_n_0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal packet_overhead : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal reg_dsc_detect_i_1_n_0 : STD_LOGIC;
  signal \^reg_dsc_detect_reg_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[10]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[10]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[3]_i_5_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[3]_i_6_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_5_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_6_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal reg_tkeep : STD_LOGIC_VECTOR ( 7 to 7 );
  signal reg_tlast_i_1_n_0 : STD_LOGIC;
  signal trn_rbar_hit_prev : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd_prev : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy_i_1_n_0 : STD_LOGIC;
  signal trn_recrc_err_prev : STD_LOGIC;
  signal trn_reof_prev : STD_LOGIC;
  signal trn_rerrfwd_prev : STD_LOGIC;
  signal trn_rrem_prev : STD_LOGIC;
  signal trn_rsof_prev : STD_LOGIC;
  signal trn_rsrc_dsc_prev : STD_LOGIC;
  signal trn_rsrc_rdy_prev : STD_LOGIC;
  signal \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[0]_i_1\ : label is "soft_lutpair1944";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[10]_i_1\ : label is "soft_lutpair1947";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[11]_i_1\ : label is "soft_lutpair1946";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[12]_i_1\ : label is "soft_lutpair1942";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[13]_i_1\ : label is "soft_lutpair1940";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[14]_i_1\ : label is "soft_lutpair1950";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[15]_i_1\ : label is "soft_lutpair1943";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[16]_i_1\ : label is "soft_lutpair1939";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[17]_i_1\ : label is "soft_lutpair1936";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[18]_i_1\ : label is "soft_lutpair1934";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[19]_i_1\ : label is "soft_lutpair1948";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[20]_i_1\ : label is "soft_lutpair1943";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[21]_i_1\ : label is "soft_lutpair1938";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[22]_i_1\ : label is "soft_lutpair1947";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[23]_i_1\ : label is "soft_lutpair1948";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[24]_i_1\ : label is "soft_lutpair1944";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[25]_i_1\ : label is "soft_lutpair1931";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[26]_i_1\ : label is "soft_lutpair1931";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[27]_i_1\ : label is "soft_lutpair1932";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[28]_i_1\ : label is "soft_lutpair1939";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[29]_i_1\ : label is "soft_lutpair1929";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[2]_i_1\ : label is "soft_lutpair1941";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[30]_i_1\ : label is "soft_lutpair1930";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[31]_i_1\ : label is "soft_lutpair1923";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[32]_i_1\ : label is "soft_lutpair1928";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[33]_i_1\ : label is "soft_lutpair1918";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[34]_i_1\ : label is "soft_lutpair1927";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[35]_i_1\ : label is "soft_lutpair1920";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[36]_i_1\ : label is "soft_lutpair1928";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[37]_i_1\ : label is "soft_lutpair1921";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[38]_i_1\ : label is "soft_lutpair1927";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[39]_i_1\ : label is "soft_lutpair1925";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[3]_i_1\ : label is "soft_lutpair1950";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[40]_i_1\ : label is "soft_lutpair1926";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[41]_i_1\ : label is "soft_lutpair1924";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[42]_i_1\ : label is "soft_lutpair1922";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[43]_i_1\ : label is "soft_lutpair1925";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[44]_i_1\ : label is "soft_lutpair1930";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[45]_i_1\ : label is "soft_lutpair1929";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[46]_i_1\ : label is "soft_lutpair1922";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[47]_i_1\ : label is "soft_lutpair1933";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[48]_i_1\ : label is "soft_lutpair1921";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[49]_i_1\ : label is "soft_lutpair1937";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[4]_i_1\ : label is "soft_lutpair1949";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[50]_i_1\ : label is "soft_lutpair1934";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[51]_i_1\ : label is "soft_lutpair1933";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[52]_i_1\ : label is "soft_lutpair1920";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[53]_i_1\ : label is "soft_lutpair1926";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[54]_i_1\ : label is "soft_lutpair1923";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[55]_i_1\ : label is "soft_lutpair1924";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[56]_i_1\ : label is "soft_lutpair1941";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[57]_i_1\ : label is "soft_lutpair1937";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[58]_i_1\ : label is "soft_lutpair1940";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[59]_i_1\ : label is "soft_lutpair1932";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[5]_i_1\ : label is "soft_lutpair1938";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[60]_i_1\ : label is "soft_lutpair1935";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[61]_i_1\ : label is "soft_lutpair1945";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[62]_i_1\ : label is "soft_lutpair1935";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[63]_i_2\ : label is "soft_lutpair1949";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[6]_i_1\ : label is "soft_lutpair1936";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[7]_i_1\ : label is "soft_lutpair1946";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[8]_i_1\ : label is "soft_lutpair1945";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata[9]_i_1\ : label is "soft_lutpair1942";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[14]_i_2\ : label is "soft_lutpair1916";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[18]_i_1\ : label is "soft_lutpair1917";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[19]_i_2\ : label is "soft_lutpair1918";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[21]_i_3\ : label is "soft_lutpair1915";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[2]_i_1\ : label is "soft_lutpair1917";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser[7]_i_1\ : label is "soft_lutpair1916";
  attribute SOFT_HLUTNM of null_mux_sel_i_2 : label is "soft_lutpair1919";
  attribute SOFT_HLUTNM of reg_dsc_detect_i_1 : label is "soft_lutpair1919";
  attribute SOFT_HLUTNM of reg_tlast_i_1 : label is "soft_lutpair1915";
begin
  E(0) <= \^e\(0);
  Q(63 downto 0) <= \^q\(63 downto 0);
  m_axis_rx_tvalid_reg_0 <= \^m_axis_rx_tvalid_reg_0\;
  null_mux_sel <= \^null_mux_sel\;
  reg_dsc_detect_reg_0 <= \^reg_dsc_detect_reg_0\;
data_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^m_axis_rx_tvalid_reg_0\,
      I1 => m_axis_rx_tready,
      O => data_hold
    );
data_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => data_hold,
      Q => data_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(0),
      I1 => data_prev,
      I2 => trn_rd(32),
      O => p_1_in(0)
    );
\m_axis_rx_tdata[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(10),
      I1 => data_prev,
      I2 => trn_rd(42),
      O => p_1_in(10)
    );
\m_axis_rx_tdata[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(11),
      I1 => data_prev,
      I2 => trn_rd(43),
      O => p_1_in(11)
    );
\m_axis_rx_tdata[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(12),
      I1 => data_prev,
      I2 => trn_rd(44),
      O => p_1_in(12)
    );
\m_axis_rx_tdata[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(13),
      I1 => data_prev,
      I2 => trn_rd(45),
      O => p_1_in(13)
    );
\m_axis_rx_tdata[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(14),
      I1 => data_prev,
      I2 => trn_rd(46),
      O => p_1_in(14)
    );
\m_axis_rx_tdata[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(15),
      I1 => data_prev,
      I2 => trn_rd(47),
      O => p_1_in(15)
    );
\m_axis_rx_tdata[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(16),
      I1 => data_prev,
      I2 => trn_rd(48),
      O => p_1_in(16)
    );
\m_axis_rx_tdata[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(17),
      I1 => data_prev,
      I2 => trn_rd(49),
      O => p_1_in(17)
    );
\m_axis_rx_tdata[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(18),
      I1 => data_prev,
      I2 => trn_rd(50),
      O => p_1_in(18)
    );
\m_axis_rx_tdata[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(19),
      I1 => data_prev,
      I2 => trn_rd(51),
      O => p_1_in(19)
    );
\m_axis_rx_tdata[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(1),
      I1 => data_prev,
      I2 => trn_rd(33),
      O => p_1_in(1)
    );
\m_axis_rx_tdata[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(20),
      I1 => data_prev,
      I2 => trn_rd(52),
      O => p_1_in(20)
    );
\m_axis_rx_tdata[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(21),
      I1 => data_prev,
      I2 => trn_rd(53),
      O => p_1_in(21)
    );
\m_axis_rx_tdata[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(22),
      I1 => data_prev,
      I2 => trn_rd(54),
      O => p_1_in(22)
    );
\m_axis_rx_tdata[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(23),
      I1 => data_prev,
      I2 => trn_rd(55),
      O => p_1_in(23)
    );
\m_axis_rx_tdata[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(24),
      I1 => data_prev,
      I2 => trn_rd(56),
      O => p_1_in(24)
    );
\m_axis_rx_tdata[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(25),
      I1 => data_prev,
      I2 => trn_rd(57),
      O => p_1_in(25)
    );
\m_axis_rx_tdata[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(26),
      I1 => data_prev,
      I2 => trn_rd(58),
      O => p_1_in(26)
    );
\m_axis_rx_tdata[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(27),
      I1 => data_prev,
      I2 => trn_rd(59),
      O => p_1_in(27)
    );
\m_axis_rx_tdata[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(28),
      I1 => data_prev,
      I2 => trn_rd(60),
      O => p_1_in(28)
    );
\m_axis_rx_tdata[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(29),
      I1 => data_prev,
      I2 => trn_rd(61),
      O => p_1_in(29)
    );
\m_axis_rx_tdata[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(2),
      I1 => data_prev,
      I2 => trn_rd(34),
      O => p_1_in(2)
    );
\m_axis_rx_tdata[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(30),
      I1 => data_prev,
      I2 => trn_rd(62),
      O => p_1_in(30)
    );
\m_axis_rx_tdata[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(31),
      I1 => data_prev,
      I2 => trn_rd(63),
      O => p_1_in(31)
    );
\m_axis_rx_tdata[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(32),
      I1 => data_prev,
      I2 => trn_rd(0),
      O => p_1_in(32)
    );
\m_axis_rx_tdata[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(33),
      I1 => data_prev,
      I2 => trn_rd(1),
      O => p_1_in(33)
    );
\m_axis_rx_tdata[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(34),
      I1 => data_prev,
      I2 => trn_rd(2),
      O => p_1_in(34)
    );
\m_axis_rx_tdata[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(35),
      I1 => data_prev,
      I2 => trn_rd(3),
      O => p_1_in(35)
    );
\m_axis_rx_tdata[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(36),
      I1 => data_prev,
      I2 => trn_rd(4),
      O => p_1_in(36)
    );
\m_axis_rx_tdata[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(37),
      I1 => data_prev,
      I2 => trn_rd(5),
      O => p_1_in(37)
    );
\m_axis_rx_tdata[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(38),
      I1 => data_prev,
      I2 => trn_rd(6),
      O => p_1_in(38)
    );
\m_axis_rx_tdata[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(39),
      I1 => data_prev,
      I2 => trn_rd(7),
      O => p_1_in(39)
    );
\m_axis_rx_tdata[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(3),
      I1 => data_prev,
      I2 => trn_rd(35),
      O => p_1_in(3)
    );
\m_axis_rx_tdata[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(40),
      I1 => data_prev,
      I2 => trn_rd(8),
      O => p_1_in(40)
    );
\m_axis_rx_tdata[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(41),
      I1 => data_prev,
      I2 => trn_rd(9),
      O => p_1_in(41)
    );
\m_axis_rx_tdata[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(42),
      I1 => data_prev,
      I2 => trn_rd(10),
      O => p_1_in(42)
    );
\m_axis_rx_tdata[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(43),
      I1 => data_prev,
      I2 => trn_rd(11),
      O => p_1_in(43)
    );
\m_axis_rx_tdata[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(44),
      I1 => data_prev,
      I2 => trn_rd(12),
      O => p_1_in(44)
    );
\m_axis_rx_tdata[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(45),
      I1 => data_prev,
      I2 => trn_rd(13),
      O => p_1_in(45)
    );
\m_axis_rx_tdata[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(46),
      I1 => data_prev,
      I2 => trn_rd(14),
      O => p_1_in(46)
    );
\m_axis_rx_tdata[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(47),
      I1 => data_prev,
      I2 => trn_rd(15),
      O => p_1_in(47)
    );
\m_axis_rx_tdata[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(48),
      I1 => data_prev,
      I2 => trn_rd(16),
      O => p_1_in(48)
    );
\m_axis_rx_tdata[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(49),
      I1 => data_prev,
      I2 => trn_rd(17),
      O => p_1_in(49)
    );
\m_axis_rx_tdata[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(4),
      I1 => data_prev,
      I2 => trn_rd(36),
      O => p_1_in(4)
    );
\m_axis_rx_tdata[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(50),
      I1 => data_prev,
      I2 => trn_rd(18),
      O => p_1_in(50)
    );
\m_axis_rx_tdata[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(51),
      I1 => data_prev,
      I2 => trn_rd(19),
      O => p_1_in(51)
    );
\m_axis_rx_tdata[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(52),
      I1 => data_prev,
      I2 => trn_rd(20),
      O => p_1_in(52)
    );
\m_axis_rx_tdata[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(53),
      I1 => data_prev,
      I2 => trn_rd(21),
      O => p_1_in(53)
    );
\m_axis_rx_tdata[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(54),
      I1 => data_prev,
      I2 => trn_rd(22),
      O => p_1_in(54)
    );
\m_axis_rx_tdata[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(55),
      I1 => data_prev,
      I2 => trn_rd(23),
      O => p_1_in(55)
    );
\m_axis_rx_tdata[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(56),
      I1 => data_prev,
      I2 => trn_rd(24),
      O => p_1_in(56)
    );
\m_axis_rx_tdata[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(57),
      I1 => data_prev,
      I2 => trn_rd(25),
      O => p_1_in(57)
    );
\m_axis_rx_tdata[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(58),
      I1 => data_prev,
      I2 => trn_rd(26),
      O => p_1_in(58)
    );
\m_axis_rx_tdata[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(59),
      I1 => data_prev,
      I2 => trn_rd(27),
      O => p_1_in(59)
    );
\m_axis_rx_tdata[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(5),
      I1 => data_prev,
      I2 => trn_rd(37),
      O => p_1_in(5)
    );
\m_axis_rx_tdata[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(60),
      I1 => data_prev,
      I2 => trn_rd(28),
      O => p_1_in(60)
    );
\m_axis_rx_tdata[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(61),
      I1 => data_prev,
      I2 => trn_rd(29),
      O => p_1_in(61)
    );
\m_axis_rx_tdata[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(62),
      I1 => data_prev,
      I2 => trn_rd(30),
      O => p_1_in(62)
    );
\m_axis_rx_tdata[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => \^m_axis_rx_tvalid_reg_0\,
      O => \m_axis_rx_tdata[63]_i_1_n_0\
    );
\m_axis_rx_tdata[63]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(63),
      I1 => data_prev,
      I2 => trn_rd(31),
      O => p_1_in(63)
    );
\m_axis_rx_tdata[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(6),
      I1 => data_prev,
      I2 => trn_rd(38),
      O => p_1_in(6)
    );
\m_axis_rx_tdata[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(7),
      I1 => data_prev,
      I2 => trn_rd(39),
      O => p_1_in(7)
    );
\m_axis_rx_tdata[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(8),
      I1 => data_prev,
      I2 => trn_rd(40),
      O => p_1_in(8)
    );
\m_axis_rx_tdata[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(9),
      I1 => data_prev,
      I2 => trn_rd(41),
      O => p_1_in(9)
    );
\m_axis_rx_tdata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(0),
      Q => \^q\(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(10),
      Q => \^q\(10),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(11),
      Q => \^q\(11),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(12),
      Q => \^q\(12),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(13),
      Q => \^q\(13),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(14),
      Q => \^q\(14),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(15),
      Q => \^q\(15),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(16),
      Q => \^q\(16),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(17),
      Q => \^q\(17),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(18),
      Q => \^q\(18),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(19),
      Q => \^q\(19),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(1),
      Q => \^q\(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(20),
      Q => \^q\(20),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(21),
      Q => \^q\(21),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(22),
      Q => \^q\(22),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(23),
      Q => \^q\(23),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(24),
      Q => \^q\(24),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(25),
      Q => \^q\(25),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(26),
      Q => \^q\(26),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(27),
      Q => \^q\(27),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(28),
      Q => \^q\(28),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(29),
      Q => \^q\(29),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(2),
      Q => \^q\(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(30),
      Q => \^q\(30),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(31),
      Q => \^q\(31),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(32),
      Q => \^q\(32),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(33),
      Q => \^q\(33),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(34),
      Q => \^q\(34),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(35),
      Q => \^q\(35),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(36),
      Q => \^q\(36),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(37),
      Q => \^q\(37),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(38),
      Q => \^q\(38),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(39),
      Q => \^q\(39),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(3),
      Q => \^q\(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(40),
      Q => \^q\(40),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(41),
      Q => \^q\(41),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(42),
      Q => \^q\(42),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(43),
      Q => \^q\(43),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(44),
      Q => \^q\(44),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(45),
      Q => \^q\(45),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(46),
      Q => \^q\(46),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(47),
      Q => \^q\(47),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(48),
      Q => \^q\(48),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(49),
      Q => \^q\(49),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(4),
      Q => \^q\(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(50),
      Q => \^q\(50),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(51),
      Q => \^q\(51),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(52),
      Q => \^q\(52),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(53),
      Q => \^q\(53),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(54),
      Q => \^q\(54),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(55),
      Q => \^q\(55),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(56),
      Q => \^q\(56),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(57),
      Q => \^q\(57),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(58),
      Q => \^q\(58),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(59),
      Q => \^q\(59),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(5),
      Q => \^q\(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(60),
      Q => \^q\(60),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(61),
      Q => \^q\(61),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(62),
      Q => \^q\(62),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(63),
      Q => \^q\(63),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(6),
      Q => \^q\(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(7),
      Q => \^q\(7),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(8),
      Q => \^q\(8),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => p_1_in(9),
      Q => \^q\(9),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tuser[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_recrc_err,
      I1 => data_prev,
      I2 => trn_recrc_err_prev,
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[0]_i_1_n_0\
    );
\m_axis_rx_tuser[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004F40404"
    )
        port map (
      I0 => trn_rsrc_dsc,
      I1 => trn_rsof,
      I2 => data_prev,
      I3 => trn_rsrc_dsc_prev,
      I4 => trn_rsof_prev,
      I5 => \m_axis_rx_tuser[14]_i_2_n_0\,
      O => \m_axis_rx_tuser[14]_i_1_n_0\
    );
\m_axis_rx_tuser[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      I1 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[14]_i_2_n_0\
    );
\m_axis_rx_tuser[18]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      O => \m_axis_rx_tuser[18]_i_1_n_0\
    );
\m_axis_rx_tuser[19]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rrem_prev,
      I1 => data_prev,
      I2 => trn_rrem(0),
      O => \trn_rrem_prev_reg[0]_0\
    );
\m_axis_rx_tuser[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rerrfwd,
      I1 => data_prev,
      I2 => trn_rerrfwd_prev,
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[1]_i_1_n_0\
    );
\m_axis_rx_tuser[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      I1 => m_axis_rx_tready,
      I2 => \^m_axis_rx_tvalid_reg_0\,
      O => \m_axis_rx_tuser[21]_i_1_n_0\
    );
\m_axis_rx_tuser[21]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_reof_prev,
      I1 => data_prev,
      I2 => trn_reof,
      O => trn_reof_prev_reg_0
    );
\m_axis_rx_tuser[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(0),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(0),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[2]_i_1_n_0\
    );
\m_axis_rx_tuser[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(1),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(1),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[3]_i_1_n_0\
    );
\m_axis_rx_tuser[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(2),
      I1 => data_prev,
      I2 => trn_rbar_hit(2),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[4]_i_1_n_0\
    );
\m_axis_rx_tuser[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(3),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(3),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[5]_i_1_n_0\
    );
\m_axis_rx_tuser[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(4),
      I1 => data_prev,
      I2 => trn_rbar_hit(4),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[6]_i_1_n_0\
    );
\m_axis_rx_tuser[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(5),
      I1 => data_prev,
      I2 => trn_rbar_hit(5),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[7]_i_1_n_0\
    );
\m_axis_rx_tuser[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(6),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(6),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => \m_axis_rx_tuser[8]_i_1_n_0\
    );
\m_axis_rx_tuser_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[0]_i_1_n_0\,
      Q => m_axis_rx_tuser(0),
      R => '0'
    );
\m_axis_rx_tuser_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[14]_i_1_n_0\,
      Q => m_axis_rx_tuser(9),
      R => '0'
    );
\m_axis_rx_tuser_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[18]_i_1_n_0\,
      Q => m_axis_rx_tuser(10),
      R => '0'
    );
\m_axis_rx_tuser_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => D(0),
      Q => m_axis_rx_tuser(11),
      R => '0'
    );
\m_axis_rx_tuser_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[1]_i_1_n_0\,
      Q => m_axis_rx_tuser(1),
      R => '0'
    );
\m_axis_rx_tuser_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => D(1),
      Q => m_axis_rx_tuser(12),
      R => '0'
    );
\m_axis_rx_tuser_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[2]_i_1_n_0\,
      Q => m_axis_rx_tuser(2),
      R => '0'
    );
\m_axis_rx_tuser_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[3]_i_1_n_0\,
      Q => m_axis_rx_tuser(3),
      R => '0'
    );
\m_axis_rx_tuser_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[4]_i_1_n_0\,
      Q => m_axis_rx_tuser(4),
      R => '0'
    );
\m_axis_rx_tuser_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[5]_i_1_n_0\,
      Q => m_axis_rx_tuser(5),
      R => '0'
    );
\m_axis_rx_tuser_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[6]_i_1_n_0\,
      Q => m_axis_rx_tuser(6),
      R => '0'
    );
\m_axis_rx_tuser_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[7]_i_1_n_0\,
      Q => m_axis_rx_tuser(7),
      R => '0'
    );
\m_axis_rx_tuser_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tuser[21]_i_1_n_0\,
      D => \m_axis_rx_tuser[8]_i_1_n_0\,
      Q => m_axis_rx_tuser(8),
      R => '0'
    );
m_axis_rx_tvalid_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFECE"
    )
        port map (
      I0 => rsrc_rdy_filtered,
      I1 => \^null_mux_sel\,
      I2 => data_prev,
      I3 => trn_rsrc_rdy_prev,
      I4 => \^reg_dsc_detect_reg_0\,
      I5 => dsc_detect,
      O => m_axis_rx_tvalid_i_1_n_0
    );
m_axis_rx_tvalid_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => m_axis_rx_tvalid_i_1_n_0,
      Q => \^m_axis_rx_tvalid_reg_0\,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
null_mux_sel_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000055FF3303"
    )
        port map (
      I0 => null_mux_sel_reg_0,
      I1 => null_mux_sel_i_2_n_0,
      I2 => \^m_axis_rx_tvalid_reg_0\,
      I3 => m_axis_rx_tready,
      I4 => \^null_mux_sel\,
      I5 => \trn_rbar_hit_prev_reg[0]_0\,
      O => null_mux_sel_i_1_n_0
    );
null_mux_sel_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reg_dsc_detect_reg_0\,
      I1 => dsc_detect,
      O => null_mux_sel_i_2_n_0
    );
null_mux_sel_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => null_mux_sel_i_1_n_0,
      Q => \^null_mux_sel\,
      R => '0'
    );
reg_dsc_detect_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \^null_mux_sel\,
      I1 => dsc_detect,
      I2 => \^reg_dsc_detect_reg_0\,
      O => reg_dsc_detect_i_1_n_0
    );
reg_dsc_detect_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reg_dsc_detect_i_1_n_0,
      Q => \^reg_dsc_detect_reg_0\,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\reg_pkt_len_counter[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(9),
      O => \reg_pkt_len_counter[10]_i_3_n_0\
    );
\reg_pkt_len_counter[10]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(8),
      O => \reg_pkt_len_counter[10]_i_4_n_0\
    );
\reg_pkt_len_counter[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(29),
      I1 => \^q\(15),
      O => packet_overhead(1)
    );
\reg_pkt_len_counter[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(15),
      I1 => \^q\(29),
      O => packet_overhead(0)
    );
\reg_pkt_len_counter[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(3),
      O => \reg_pkt_len_counter[3]_i_5_n_0\
    );
\reg_pkt_len_counter[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(2),
      O => \reg_pkt_len_counter[3]_i_6_n_0\
    );
\reg_pkt_len_counter[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(7),
      O => \reg_pkt_len_counter[7]_i_3_n_0\
    );
\reg_pkt_len_counter[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(6),
      O => \reg_pkt_len_counter[7]_i_4_n_0\
    );
\reg_pkt_len_counter[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(5),
      O => \reg_pkt_len_counter[7]_i_5_n_0\
    );
\reg_pkt_len_counter[7]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(4),
      O => \reg_pkt_len_counter[7]_i_6_n_0\
    );
\reg_pkt_len_counter_reg[10]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \reg_pkt_len_counter_reg[7]_i_2_n_0\,
      CO(3) => \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\(3),
      CO(2) => new_pkt_len(10),
      CO(1) => \NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED\(1),
      CO(0) => \reg_pkt_len_counter_reg[10]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => new_pkt_len(9 downto 8),
      S(3 downto 2) => B"01",
      S(1) => \reg_pkt_len_counter[10]_i_3_n_0\,
      S(0) => \reg_pkt_len_counter[10]_i_4_n_0\
    );
\reg_pkt_len_counter_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \reg_pkt_len_counter_reg[3]_i_2_n_0\,
      CO(2) => \reg_pkt_len_counter_reg[3]_i_2_n_1\,
      CO(1) => \reg_pkt_len_counter_reg[3]_i_2_n_2\,
      CO(0) => \reg_pkt_len_counter_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => packet_overhead(1 downto 0),
      O(3 downto 0) => new_pkt_len(3 downto 0),
      S(3) => \reg_pkt_len_counter[3]_i_5_n_0\,
      S(2) => \reg_pkt_len_counter[3]_i_6_n_0\,
      S(1 downto 0) => S(1 downto 0)
    );
\reg_pkt_len_counter_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \reg_pkt_len_counter_reg[3]_i_2_n_0\,
      CO(3) => \reg_pkt_len_counter_reg[7]_i_2_n_0\,
      CO(2) => \reg_pkt_len_counter_reg[7]_i_2_n_1\,
      CO(1) => \reg_pkt_len_counter_reg[7]_i_2_n_2\,
      CO(0) => \reg_pkt_len_counter_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => new_pkt_len(7 downto 4),
      S(3) => \reg_pkt_len_counter[7]_i_3_n_0\,
      S(2) => \reg_pkt_len_counter[7]_i_4_n_0\,
      S(1) => \reg_pkt_len_counter[7]_i_5_n_0\,
      S(0) => \reg_pkt_len_counter[7]_i_6_n_0\
    );
\reg_tkeep[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F707F7F7F707070"
    )
        port map (
      I0 => \reg_tkeep_reg[7]_0\,
      I1 => \reg_tkeep_reg[7]_1\,
      I2 => \^null_mux_sel\,
      I3 => trn_rrem_prev,
      I4 => data_prev,
      I5 => trn_rrem(0),
      O => reg_tkeep(7)
    );
\reg_tkeep_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => reg_tkeep(7),
      Q => m_axis_rx_tkeep(0),
      S => \trn_rbar_hit_prev_reg[0]_0\
    );
reg_tlast_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => null_mux_sel_reg_0,
      I1 => \^null_mux_sel\,
      I2 => trn_reof_prev,
      I3 => data_prev,
      I4 => trn_reof,
      O => reg_tlast_i_1_n_0
    );
reg_tlast_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \m_axis_rx_tdata[63]_i_1_n_0\,
      D => reg_tlast_i_1_n_0,
      Q => m_axis_rx_tlast,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_in_packet_reg_0,
      Q => trn_in_packet,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(0),
      Q => trn_rbar_hit_prev(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(1),
      Q => trn_rbar_hit_prev(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(2),
      Q => trn_rbar_hit_prev(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(3),
      Q => trn_rbar_hit_prev(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(4),
      Q => trn_rbar_hit_prev(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(5),
      Q => trn_rbar_hit_prev(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(6),
      Q => trn_rbar_hit_prev(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(32),
      Q => trn_rd_prev(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(42),
      Q => trn_rd_prev(10),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(43),
      Q => trn_rd_prev(11),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(44),
      Q => trn_rd_prev(12),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(45),
      Q => trn_rd_prev(13),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(46),
      Q => trn_rd_prev(14),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(47),
      Q => trn_rd_prev(15),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(48),
      Q => trn_rd_prev(16),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(49),
      Q => trn_rd_prev(17),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(50),
      Q => trn_rd_prev(18),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(51),
      Q => trn_rd_prev(19),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(33),
      Q => trn_rd_prev(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(52),
      Q => trn_rd_prev(20),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(53),
      Q => trn_rd_prev(21),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(54),
      Q => trn_rd_prev(22),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(55),
      Q => trn_rd_prev(23),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(56),
      Q => trn_rd_prev(24),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(57),
      Q => trn_rd_prev(25),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(58),
      Q => trn_rd_prev(26),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(59),
      Q => trn_rd_prev(27),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(60),
      Q => trn_rd_prev(28),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(61),
      Q => trn_rd_prev(29),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(34),
      Q => trn_rd_prev(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(62),
      Q => trn_rd_prev(30),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(63),
      Q => trn_rd_prev(31),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(0),
      Q => trn_rd_prev(32),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(1),
      Q => trn_rd_prev(33),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(2),
      Q => trn_rd_prev(34),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(3),
      Q => trn_rd_prev(35),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(4),
      Q => trn_rd_prev(36),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(5),
      Q => trn_rd_prev(37),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(6),
      Q => trn_rd_prev(38),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(7),
      Q => trn_rd_prev(39),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(35),
      Q => trn_rd_prev(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(8),
      Q => trn_rd_prev(40),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(9),
      Q => trn_rd_prev(41),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(10),
      Q => trn_rd_prev(42),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(11),
      Q => trn_rd_prev(43),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(12),
      Q => trn_rd_prev(44),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(13),
      Q => trn_rd_prev(45),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(14),
      Q => trn_rd_prev(46),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(15),
      Q => trn_rd_prev(47),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(16),
      Q => trn_rd_prev(48),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(17),
      Q => trn_rd_prev(49),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(36),
      Q => trn_rd_prev(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(18),
      Q => trn_rd_prev(50),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(19),
      Q => trn_rd_prev(51),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(20),
      Q => trn_rd_prev(52),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(21),
      Q => trn_rd_prev(53),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(22),
      Q => trn_rd_prev(54),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(23),
      Q => trn_rd_prev(55),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(24),
      Q => trn_rd_prev(56),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(25),
      Q => trn_rd_prev(57),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(26),
      Q => trn_rd_prev(58),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(27),
      Q => trn_rd_prev(59),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(37),
      Q => trn_rd_prev(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(28),
      Q => trn_rd_prev(60),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(29),
      Q => trn_rd_prev(61),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(30),
      Q => trn_rd_prev(62),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(31),
      Q => trn_rd_prev(63),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(38),
      Q => trn_rd_prev(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(39),
      Q => trn_rd_prev(7),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(40),
      Q => trn_rd_prev(8),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(41),
      Q => trn_rd_prev(9),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rdst_rdy_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080808C808080BF"
    )
        port map (
      I0 => null_mux_sel_reg_0,
      I1 => m_axis_rx_tready,
      I2 => \^null_mux_sel\,
      I3 => dsc_detect,
      I4 => \^reg_dsc_detect_reg_0\,
      I5 => \^m_axis_rx_tvalid_reg_0\,
      O => trn_rdst_rdy_i_1_n_0
    );
trn_rdst_rdy_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_rdst_rdy_i_1_n_0,
      Q => \^e\(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_recrc_err_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_recrc_err,
      Q => trn_recrc_err_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_reof_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_reof,
      Q => trn_reof_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rerrfwd_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rerrfwd,
      Q => trn_rerrfwd_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rrem_prev_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rrem(0),
      Q => trn_rrem_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsof_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rsof,
      Q => trn_rsof_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_dsc_d_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_rsrc_dsc,
      Q => trn_rsrc_dsc_d,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_dsc_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rsrc_dsc_prev0,
      Q => trn_rsrc_dsc_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_rdy_prev_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \^e\(0),
      D => rsrc_rdy_filtered,
      Q => trn_rsrc_rdy_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_tx_pipeline is
  port (
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    axi_in_packet : out STD_LOGIC;
    reg_disable_trn : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    \throttle_ctl_pipeline.reg_tdata_reg[63]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    CLK : in STD_LOGIC;
    reg_tsrc_rdy0 : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    axi_in_packet_reg_0 : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\ : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_tx_pipeline : entity is "xdma_0_pcie2_ip_axi_basic_tx_pipeline";
end xdma_0_xdma_0_pcie2_ip_axi_basic_tx_pipeline;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_tx_pipeline is
  signal \^axi_in_packet\ : STD_LOGIC;
  signal \^reg_disable_trn\ : STD_LOGIC;
  signal reg_tvalid : STD_LOGIC;
  signal \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\ : STD_LOGIC;
  signal trn_in_packet : STD_LOGIC;
  signal \trn_in_packet_i_1__0_n_0\ : STD_LOGIC;
  signal \^trn_teof\ : STD_LOGIC;
  signal \^trn_tsrc_rdy\ : STD_LOGIC;
begin
  axi_in_packet <= \^axi_in_packet\;
  reg_disable_trn <= \^reg_disable_trn\;
  trn_teof <= \^trn_teof\;
  trn_tsrc_rdy <= \^trn_tsrc_rdy\;
axi_in_packet_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => axi_in_packet_reg_0,
      Q => \^axi_in_packet\,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
pcie_block_i_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reg_tvalid,
      I1 => trn_in_packet,
      O => trn_tsof
    );
\throttle_ctl_pipeline.reg_tdata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(0),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(0),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(10),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(10),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(11),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(11),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(12),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(12),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(13),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(13),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(14),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(14),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(15),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(15),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(16),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(16),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(17),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(17),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(18),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(18),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(19),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(19),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(1),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(1),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(20),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(20),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(21),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(21),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(22),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(22),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(23),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(23),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(24),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(24),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(25),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(25),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(26),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(26),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(27),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(27),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(28),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(28),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(29),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(29),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(2),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(2),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(30),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(30),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(31),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(31),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(32),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(32),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(33),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(33),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(34),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(34),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(35),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(35),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(36),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(36),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(37),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(37),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(38),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(38),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(39),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(39),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(3),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(3),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(40),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(40),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(41),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(41),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(42),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(42),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(43),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(43),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(44),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(44),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(45),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(45),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(46),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(46),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(47),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(47),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(48),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(48),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(49),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(49),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(4),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(4),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(50),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(50),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(51),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(51),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(52),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(52),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(53),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(53),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(54),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(54),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(55),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(55),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(56),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(56),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(57),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(57),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(58),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(58),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(59),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(59),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(5),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(5),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(60),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(60),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(61),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(61),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(62),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(62),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(63),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(63),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(6),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(6),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(7),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(7),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(8),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(8),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tdata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(9),
      Q => \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(9),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tkeep_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tkeep(0),
      Q => trn_trem(0),
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tlast_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tlast,
      Q => \^trn_teof\,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tsrc_rdy_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reg_tsrc_rdy0,
      Q => \^trn_tsrc_rdy\,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\throttle_ctl_pipeline.reg_tvalid_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tvalid,
      Q => reg_tvalid,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\thrtl_ctl_trn_flush.reg_disable_trn_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFFFFFF04444444"
    )
        port map (
      I0 => \out\,
      I1 => \^axi_in_packet\,
      I2 => \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\,
      I3 => s_axis_tx_tvalid,
      I4 => s_axis_tx_tlast,
      I5 => \^reg_disable_trn\,
      O => \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\
    );
\thrtl_ctl_trn_flush.reg_disable_trn_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0\,
      Q => \^reg_disable_trn\,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
\trn_in_packet_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F088F000F000"
    )
        port map (
      I0 => trn_tdst_rdy,
      I1 => reg_tvalid,
      I2 => \out\,
      I3 => trn_in_packet,
      I4 => \^trn_teof\,
      I5 => \^trn_tsrc_rdy\,
      O => \trn_in_packet_i_1__0_n_0\
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \trn_in_packet_i_1__0_n_0\,
      Q => trn_in_packet,
      R => \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl is
  port (
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_reg_0 : out STD_LOGIC;
    ppm_L1_thrtl : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    s_axis_tx_tlast_reg : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    reg_tsrc_rdy0 : out STD_LOGIC;
    \tbuf_gap_cnt_reg[0]_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    ppm_L1_thrtl_reg_0 : in STD_LOGIC;
    lnk_up_thrtl_reg_0 : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    axi_in_packet : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    tcfg_req_trig : in STD_LOGIC;
    tready_thrtl_i_3_0 : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    reg_disable_trn : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl : entity is "xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl";
end xdma_0_xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl is
  signal cfg_pcie_link_state_d : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cur_state : STD_LOGIC;
  signal \^lnk_up_thrtl\ : STD_LOGIC;
  signal next_state : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal \^ppm_l1_thrtl\ : STD_LOGIC;
  signal \^ppm_l1_trig\ : STD_LOGIC;
  signal reg_axi_in_pkt : STD_LOGIC;
  signal reg_axi_in_pkt_i_1_n_0 : STD_LOGIC;
  signal \^reg_tcfg_gnt\ : STD_LOGIC;
  signal tbuf_av_d : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal tbuf_av_gap_thrtl : STD_LOGIC;
  signal tbuf_av_gap_thrtl_i_1_n_0 : STD_LOGIC;
  signal tbuf_av_gap_trig : STD_LOGIC;
  signal tbuf_av_min_thrtl : STD_LOGIC;
  signal \tbuf_gap_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal tcfg_gnt_pending : STD_LOGIC;
  signal tcfg_gnt_pending_i_1_n_0 : STD_LOGIC;
  signal tcfg_req_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \tcfg_req_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tcfg_req_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal tcfg_req_thrtl : STD_LOGIC;
  signal tcfg_req_thrtl_i_1_n_0 : STD_LOGIC;
  signal tready_thrtl_i_2_n_0 : STD_LOGIC;
  signal tready_thrtl_i_5_n_0 : STD_LOGIC;
  signal tready_thrtl_i_6_n_0 : STD_LOGIC;
  signal tready_thrtl_i_8_n_0 : STD_LOGIC;
  signal tready_thrtl_i_9_n_0 : STD_LOGIC;
  signal tready_thrtl_mux10_in : STD_LOGIC;
  signal \^tready_thrtl_reg_0\ : STD_LOGIC;
  signal trn_tcfg_req_d : STD_LOGIC;
  signal trn_tdst_rdy_d : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of pcie_block_i_i_7 : label is "soft_lutpair1953";
  attribute SOFT_HLUTNM of \tbuf_gap_cnt[0]_i_1\ : label is "soft_lutpair1953";
  attribute SOFT_HLUTNM of \tcfg_req_cnt[1]_i_1\ : label is "soft_lutpair1952";
  attribute SOFT_HLUTNM of tcfg_req_thrtl_i_2 : label is "soft_lutpair1952";
  attribute SOFT_HLUTNM of tready_thrtl_i_2 : label is "soft_lutpair1951";
  attribute SOFT_HLUTNM of tready_thrtl_i_9 : label is "soft_lutpair1951";
begin
  lnk_up_thrtl <= \^lnk_up_thrtl\;
  ppm_L1_thrtl <= \^ppm_l1_thrtl\;
  ppm_L1_trig <= \^ppm_l1_trig\;
  reg_tcfg_gnt <= \^reg_tcfg_gnt\;
  tready_thrtl_reg_0 <= \^tready_thrtl_reg_0\;
axi_in_packet_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F40"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \^tready_thrtl_reg_0\,
      I3 => axi_in_packet,
      O => s_axis_tx_tlast_reg
    );
\cfg_pcie_link_state_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(0),
      Q => cfg_pcie_link_state_d(0),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\cfg_pcie_link_state_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(1),
      Q => cfg_pcie_link_state_d(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\cfg_pcie_link_state_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(2),
      Q => cfg_pcie_link_state_d(2),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\cur_state_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555554"
    )
        port map (
      I0 => tready_thrtl_i_2_n_0,
      I1 => tbuf_av_gap_thrtl,
      I2 => tbuf_av_min_thrtl,
      I3 => \^ppm_l1_thrtl\,
      I4 => tcfg_req_thrtl,
      I5 => \^lnk_up_thrtl\,
      O => next_state
    );
cur_state_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => next_state,
      Q => cur_state,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
lnk_up_thrtl_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => lnk_up_thrtl_reg_0,
      Q => \^lnk_up_thrtl\,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
pcie_block_i_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00D0"
    )
        port map (
      I0 => cur_state,
      I1 => tcfg_gnt_pending,
      I2 => tcfg_req_thrtl,
      I3 => tready_thrtl_i_2_n_0,
      O => trn_tcfg_gnt
    );
ppm_L1_thrtl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => cfg_pcie_link_state_d(1),
      I1 => cfg_pcie_link_state_d(2),
      I2 => cfg_pcie_link_state_d(0),
      I3 => cfg_pcie_link_state(0),
      I4 => cfg_pcie_link_state(1),
      I5 => cfg_pcie_link_state(2),
      O => \^ppm_l1_trig\
    );
ppm_L1_thrtl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ppm_L1_thrtl_reg_0,
      Q => \^ppm_l1_thrtl\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
reg_axi_in_pkt_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005F40"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => \^tready_thrtl_reg_0\,
      I2 => s_axis_tx_tvalid,
      I3 => reg_axi_in_pkt,
      I4 => \tbuf_gap_cnt_reg[0]_0\,
      O => reg_axi_in_pkt_i_1_n_0
    );
reg_axi_in_pkt_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reg_axi_in_pkt_i_1_n_0,
      Q => reg_axi_in_pkt,
      R => '0'
    );
reg_tcfg_gnt_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '1',
      Q => \^reg_tcfg_gnt\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(0),
      Q => tbuf_av_d(0),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(1),
      Q => tbuf_av_d(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(2),
      Q => tbuf_av_d(2),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(3),
      Q => tbuf_av_d(3),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(4),
      Q => tbuf_av_d(4),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(5),
      Q => tbuf_av_d(5),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tbuf_av_gap_thrtl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => tbuf_av_gap_trig,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => tbuf_av_gap_thrtl,
      O => tbuf_av_gap_thrtl_i_1_n_0
    );
tbuf_av_gap_thrtl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tbuf_av_gap_thrtl_i_1_n_0,
      Q => tbuf_av_gap_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tbuf_av_min_thrtl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tbuf_av_min_trig,
      Q => tbuf_av_min_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_gap_cnt[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => tbuf_av_gap_thrtl,
      I1 => cur_state,
      O => \tbuf_gap_cnt[0]_i_1_n_0\
    );
\tbuf_gap_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \tbuf_gap_cnt[0]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[0]\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tcfg_gnt_pending_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4FF4444"
    )
        port map (
      I0 => trn_tcfg_req_d,
      I1 => trn_tcfg_req,
      I2 => tready_thrtl_i_2_n_0,
      I3 => tcfg_req_thrtl,
      I4 => tcfg_gnt_pending,
      O => tcfg_gnt_pending_i_1_n_0
    );
tcfg_gnt_pending_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tcfg_gnt_pending_i_1_n_0,
      Q => tcfg_gnt_pending,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tcfg_req_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000D00"
    )
        port map (
      I0 => trn_tcfg_req,
      I1 => trn_tcfg_req_d,
      I2 => tcfg_gnt_pending,
      I3 => tcfg_req_cnt(1),
      I4 => tcfg_req_cnt(0),
      I5 => \tbuf_gap_cnt_reg[0]_0\,
      O => \tcfg_req_cnt[0]_i_1_n_0\
    );
\tcfg_req_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => tcfg_req_cnt(0),
      I1 => tcfg_req_cnt(1),
      I2 => trn_tcfg_req,
      I3 => trn_tcfg_req_d,
      I4 => tcfg_gnt_pending,
      O => \tcfg_req_cnt[1]_i_1_n_0\
    );
\tcfg_req_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \tcfg_req_cnt[0]_i_1_n_0\,
      Q => tcfg_req_cnt(0),
      R => '0'
    );
\tcfg_req_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \tcfg_req_cnt[1]_i_1_n_0\,
      Q => tcfg_req_cnt(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tcfg_req_thrtl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => \^reg_tcfg_gnt\,
      I1 => trn_tcfg_req,
      I2 => trn_tdst_rdy_d,
      I3 => trn_tdst_rdy,
      I4 => p_2_in,
      I5 => tcfg_req_thrtl,
      O => tcfg_req_thrtl_i_1_n_0
    );
tcfg_req_thrtl_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tcfg_req_cnt(1),
      I1 => tcfg_req_cnt(0),
      O => p_2_in
    );
tcfg_req_thrtl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tcfg_req_thrtl_i_1_n_0,
      Q => tcfg_req_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\throttle_ctl_pipeline.reg_tsrc_rdy_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \^tready_thrtl_reg_0\,
      I1 => s_axis_tx_tvalid,
      I2 => \out\,
      I3 => reg_disable_trn,
      O => reg_tsrc_rdy0
    );
tready_thrtl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAABAA"
    )
        port map (
      I0 => tready_thrtl_i_2_n_0,
      I1 => tbuf_av_gap_trig,
      I2 => tbuf_av_min_trig,
      I3 => \out\,
      I4 => tcfg_req_trig,
      I5 => tready_thrtl_i_5_n_0,
      O => tready_thrtl_mux10_in
    );
tready_thrtl_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080C08"
    )
        port map (
      I0 => reg_axi_in_pkt,
      I1 => \^tready_thrtl_reg_0\,
      I2 => cur_state,
      I3 => s_axis_tx_tvalid,
      I4 => s_axis_tx_tlast,
      O => tready_thrtl_i_2_n_0
    );
tready_thrtl_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => tcfg_req_cnt(0),
      I1 => tcfg_req_cnt(1),
      I2 => trn_tdst_rdy,
      I3 => trn_tdst_rdy_d,
      I4 => tcfg_req_thrtl,
      I5 => tready_thrtl_i_6_n_0,
      O => tbuf_av_gap_trig
    );
tready_thrtl_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^ppm_l1_trig\,
      I1 => tbuf_av_gap_thrtl,
      I2 => tbuf_av_min_thrtl,
      I3 => \^ppm_l1_thrtl\,
      I4 => tcfg_req_thrtl,
      I5 => \^lnk_up_thrtl\,
      O => tready_thrtl_i_5_n_0
    );
tready_thrtl_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000020AAAAAAAA"
    )
        port map (
      I0 => tready_thrtl_i_3_0,
      I1 => tbuf_av_d(5),
      I2 => tbuf_av_d(0),
      I3 => tbuf_av_d(4),
      I4 => tready_thrtl_i_8_n_0,
      I5 => tready_thrtl_i_9_n_0,
      O => tready_thrtl_i_6_n_0
    );
tready_thrtl_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => trn_tbuf_av(1),
      I1 => tbuf_av_d(3),
      I2 => tbuf_av_d(1),
      I3 => tbuf_av_d(2),
      O => tready_thrtl_i_8_n_0
    );
tready_thrtl_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \^tready_thrtl_reg_0\,
      O => tready_thrtl_i_9_n_0
    );
tready_thrtl_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => tready_thrtl_mux10_in,
      Q => \^tready_thrtl_reg_0\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
trn_tcfg_req_d_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tcfg_req,
      Q => trn_tcfg_req_d,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
trn_tdst_rdy_d_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => trn_tdst_rdy,
      Q => trn_tdst_rdy_d,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x is
  port (
    gt_rxvalid_q_reg_0 : out STD_LOGIC;
    gt_rx_phy_status_q : out STD_LOGIC;
    gt_rxelecidle_q : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXELECIDLE : in STD_LOGIC;
    gt_rxvalid_q_reg_1 : in STD_LOGIC;
    gt_rxvalid_q_reg_2 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x : entity is "xdma_0_pcie2_ip_gt_rx_valid_filter_7x";
end xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x is
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal \^gt_rxdata_q_reg[15]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \gt_rxvalid_q__0\ : STD_LOGIC;
  signal gt_rxvalid_q_i_2_n_0 : STD_LOGIC;
  signal gt_rxvalid_q_i_4_n_0 : STD_LOGIC;
  signal gt_rxvalid_q_n_0 : STD_LOGIC;
  signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \reg_state_eios_det[0]_i_2_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_2_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_3_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_4_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_5_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[3]_i_3_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_1_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_3_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_4_n_0\ : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of gt_rxvalid_q_i_2 : label is "soft_lutpair1810";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\ : label is "soft_lutpair1811";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1\ : label is "soft_lutpair1811";
  attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_2\ : label is "soft_lutpair1808";
  attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1\ : label is "soft_lutpair1809";
  attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1__0\ : label is "soft_lutpair1809";
  attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2__0\ : label is "soft_lutpair1808";
  attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_2\ : label is "soft_lutpair1810";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
begin
  \gt_rxdata_q_reg[15]_0\(15 downto 0) <= \^gt_rxdata_q_reg[15]_0\(15 downto 0);
  gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\;
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => gt_rx_phy_status_q,
      R => SR(0)
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(0),
      Q => \gt_rx_status_q_reg[2]_0\(0),
      R => SR(0)
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(1),
      Q => \gt_rx_status_q_reg[2]_0\(1),
      R => SR(0)
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(2),
      Q => \gt_rx_status_q_reg[2]_0\(2),
      R => SR(0)
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => SR(0)
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => p_1_in,
      R => SR(0)
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(0),
      Q => \^gt_rxdata_q_reg[15]_0\(0),
      R => SR(0)
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(10),
      Q => \^gt_rxdata_q_reg[15]_0\(10),
      R => SR(0)
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(11),
      Q => \^gt_rxdata_q_reg[15]_0\(11),
      R => SR(0)
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(12),
      Q => \^gt_rxdata_q_reg[15]_0\(12),
      R => SR(0)
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(13),
      Q => \^gt_rxdata_q_reg[15]_0\(13),
      R => SR(0)
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(14),
      Q => \^gt_rxdata_q_reg[15]_0\(14),
      R => SR(0)
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(15),
      Q => \^gt_rxdata_q_reg[15]_0\(15),
      R => SR(0)
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(1),
      Q => \^gt_rxdata_q_reg[15]_0\(1),
      R => SR(0)
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(2),
      Q => \^gt_rxdata_q_reg[15]_0\(2),
      R => SR(0)
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(3),
      Q => \^gt_rxdata_q_reg[15]_0\(3),
      R => SR(0)
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(4),
      Q => \^gt_rxdata_q_reg[15]_0\(4),
      R => SR(0)
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(5),
      Q => \^gt_rxdata_q_reg[15]_0\(5),
      R => SR(0)
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(6),
      Q => \^gt_rxdata_q_reg[15]_0\(6),
      R => SR(0)
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(7),
      Q => \^gt_rxdata_q_reg[15]_0\(7),
      R => SR(0)
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(8),
      Q => \^gt_rxdata_q_reg[15]_0\(8),
      R => SR(0)
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(9),
      Q => \^gt_rxdata_q_reg[15]_0\(9),
      R => SR(0)
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => SYNC_RXELECIDLE,
      Q => gt_rxelecidle_q,
      R => SR(0)
    );
gt_rxvalid_q: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => state_eios_det(1),
      I2 => state_eios_det(2),
      I3 => state_eios_det(3),
      I4 => state_eios_det(4),
      O => gt_rxvalid_q_n_0
    );
gt_rxvalid_q_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFFB"
    )
        port map (
      I0 => gt_rxvalid_q_i_2_n_0,
      I1 => gt_rxvalid_q_n_0,
      I2 => state_eios_det(0),
      I3 => \reg_state_eios_det[0]_i_2_n_0\,
      I4 => gt_rxvalid_q_reg_1,
      I5 => gt_rxvalid_q_i_4_n_0,
      O => \gt_rxvalid_q__0\
    );
gt_rxvalid_q_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(1),
      I1 => \reg_state_eios_det[4]_i_3_n_0\,
      O => gt_rxvalid_q_i_2_n_0
    );
gt_rxvalid_q_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => gt_rxvalid_q_reg_2,
      I1 => state_eios_det(0),
      I2 => state_eios_det(4),
      I3 => state_eios_det(2),
      I4 => state_eios_det(1),
      I5 => state_eios_det(3),
      O => gt_rxvalid_q_i_4_n_0
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxvalid_q__0\,
      Q => \^gt_rxvalid_q_reg_0\,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt_rxvalid_q_reg_0\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \gt_rxcharisk_q_reg[1]_0\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_1_in,
      I1 => \^gt_rxvalid_q_reg_0\,
      I2 => symbol_after_eios,
      O => \gt_rxcharisk_q_reg[1]_0\(1)
    );
\reg_state_eios_det[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF8080FF80"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => \reg_state_eios_det[2]_i_2_n_0\,
      I2 => \reg_state_eios_det[2]_i_3_n_0\,
      I3 => state_eios_det(1),
      I4 => \reg_state_eios_det[4]_i_3_n_0\,
      I5 => \reg_state_eios_det[0]_i_2_n_0\,
      O => \p_1_in__0\(0)
    );
\reg_state_eios_det[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88FA"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_3_n_0\,
      I2 => state_eios_det(3),
      I3 => \reg_state_eios_det[4]_i_3_n_0\,
      I4 => state_eios_det(4),
      O => \reg_state_eios_det[0]_i_2_n_0\
    );
\reg_state_eios_det[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => \reg_state_eios_det[2]_i_2_n_0\,
      O => \p_1_in__0\(1)
    );
\reg_state_eios_det[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => \reg_state_eios_det[2]_i_2_n_0\,
      I2 => \reg_state_eios_det[2]_i_3_n_0\,
      O => \p_1_in__0\(2)
    );
\reg_state_eios_det[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \reg_state_eios_det[3]_i_3_n_0\,
      I1 => \reg_state_eios_det[2]_i_4_n_0\,
      I2 => \^gt_rxdata_q_reg[15]_0\(3),
      I3 => \^gt_rxdata_q_reg[15]_0\(5),
      I4 => \^gt_rxdata_q_reg[15]_0\(2),
      I5 => \^gt_rxdata_q_reg[15]_0\(4),
      O => \reg_state_eios_det[2]_i_2_n_0\
    );
\reg_state_eios_det[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFFFF"
    )
        port map (
      I0 => \^gt_rxdata_q_reg[15]_0\(8),
      I1 => \^gt_rxdata_q_reg[15]_0\(11),
      I2 => \^gt_rxdata_q_reg[15]_0\(10),
      I3 => \reg_state_eios_det[2]_i_5_n_0\,
      I4 => \^gt_rxdata_q_reg[15]_0\(15),
      I5 => \^gt_rxdata_q_reg[15]_0\(14),
      O => \reg_state_eios_det[2]_i_3_n_0\
    );
\reg_state_eios_det[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
        port map (
      I0 => \gt_rxcharisk_q_reg_n_0_[0]\,
      I1 => \^gt_rxdata_q_reg[15]_0\(0),
      I2 => \^gt_rxdata_q_reg[15]_0\(6),
      I3 => \^gt_rxdata_q_reg[15]_0\(7),
      I4 => \^gt_rxdata_q_reg[15]_0\(1),
      O => \reg_state_eios_det[2]_i_4_n_0\
    );
\reg_state_eios_det[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => p_1_in,
      I1 => \^gt_rxdata_q_reg[15]_0\(13),
      I2 => \^gt_rxdata_q_reg[15]_0\(12),
      I3 => \^gt_rxdata_q_reg[15]_0\(9),
      O => \reg_state_eios_det[2]_i_5_n_0\
    );
\reg_state_eios_det[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_2__0_n_0\,
      O => \p_1_in__0\(3)
    );
\reg_state_eios_det[3]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \reg_state_eios_det[3]_i_3_n_0\,
      I1 => \reg_state_eios_det[4]_i_3_n_0\,
      O => \reg_state_eios_det[3]_i_2__0_n_0\
    );
\reg_state_eios_det[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFFFF"
    )
        port map (
      I0 => \^gt_rxdata_q_reg[15]_0\(8),
      I1 => \^gt_rxdata_q_reg[15]_0\(11),
      I2 => \^gt_rxdata_q_reg[15]_0\(10),
      I3 => \reg_state_eios_det[2]_i_5_n_0\,
      I4 => \^gt_rxdata_q_reg[15]_0\(14),
      I5 => \^gt_rxdata_q_reg[15]_0\(15),
      O => \reg_state_eios_det[3]_i_3_n_0\
    );
\reg_state_eios_det[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => state_eios_det(4),
      I2 => state_eios_det(3),
      I3 => state_eios_det(0),
      I4 => state_eios_det(1),
      O => \reg_state_eios_det[4]_i_1_n_0\
    );
\reg_state_eios_det[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => state_eios_det(3),
      I1 => \reg_state_eios_det[4]_i_3_n_0\,
      I2 => state_eios_det(1),
      O => \p_1_in__0\(4)
    );
\reg_state_eios_det[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000200"
    )
        port map (
      I0 => \gt_rxcharisk_q_reg_n_0_[0]\,
      I1 => \^gt_rxdata_q_reg[15]_0\(1),
      I2 => \^gt_rxdata_q_reg[15]_0\(7),
      I3 => \^gt_rxdata_q_reg[15]_0\(6),
      I4 => \^gt_rxdata_q_reg[15]_0\(0),
      I5 => \reg_state_eios_det[4]_i_4_n_0\,
      O => \reg_state_eios_det[4]_i_3_n_0\
    );
\reg_state_eios_det[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^gt_rxdata_q_reg[15]_0\(3),
      I1 => \^gt_rxdata_q_reg[15]_0\(5),
      I2 => \^gt_rxdata_q_reg[15]_0\(2),
      I3 => \^gt_rxdata_q_reg[15]_0\(4),
      O => \reg_state_eios_det[4]_i_4_n_0\
    );
\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1_n_0\,
      D => \p_1_in__0\(0),
      Q => state_eios_det(0),
      S => SR(0)
    );
\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1_n_0\,
      D => \p_1_in__0\(1),
      Q => state_eios_det(1),
      R => SR(0)
    );
\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1_n_0\,
      D => \p_1_in__0\(2),
      Q => state_eios_det(2),
      R => SR(0)
    );
\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1_n_0\,
      D => \p_1_in__0\(3),
      Q => state_eios_det(3),
      R => SR(0)
    );
\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1_n_0\,
      D => \p_1_in__0\(4),
      Q => state_eios_det(4),
      R => SR(0)
    );
reg_symbol_after_eios_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_2__0_n_0\,
      I2 => state_eios_det(3),
      I3 => state_eios_det(4),
      I4 => state_eios_det(0),
      I5 => state_eios_det(1),
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30 is
  port (
    gt_rxvalid_q_reg_0 : out STD_LOGIC;
    gt_rx_phy_status_q_reg_0 : out STD_LOGIC;
    gt_rxelecidle_q_reg_0 : out STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXELECIDLE : in STD_LOGIC;
    gt_rxvalid_q_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30 : entity is "xdma_0_pcie2_ip_gt_rx_valid_filter_7x";
end xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30 is
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal \^gt_rxdata_q_reg[15]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \gt_rxvalid_q__0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__0_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_4__0_n_0\ : STD_LOGIC;
  signal gt_rxvalid_q_n_0 : STD_LOGIC;
  signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^pl_ltssm_state_q_reg[5]\ : STD_LOGIC;
  signal \reg_state_eios_det[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[1]_i_2_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[1]_i_3_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[3]_i_2_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \reg_state_eios_det[4]_i_4__0_n_0\ : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal state_eios_det : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt_rxvalid_q_i_2__0\ : label is "soft_lutpair1813";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\ : label is "soft_lutpair1814";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0\ : label is "soft_lutpair1814";
  attribute SOFT_HLUTNM of \reg_state_eios_det[0]_i_2__0\ : label is "soft_lutpair1812";
  attribute SOFT_HLUTNM of \reg_state_eios_det[1]_i_1__0\ : label is "soft_lutpair1815";
  attribute SOFT_HLUTNM of \reg_state_eios_det[2]_i_1\ : label is "soft_lutpair1815";
  attribute SOFT_HLUTNM of \reg_state_eios_det[3]_i_2\ : label is "soft_lutpair1812";
  attribute SOFT_HLUTNM of \reg_state_eios_det[4]_i_2__0\ : label is "soft_lutpair1813";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[0]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[1]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[2]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[3]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
  attribute FSM_ENCODED_STATES of \reg_state_eios_det_reg[4]\ : label is "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000";
begin
  \gt_rxdata_q_reg[15]_0\(15 downto 0) <= \^gt_rxdata_q_reg[15]_0\(15 downto 0);
  gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\;
  \pl_ltssm_state_q_reg[5]\ <= \^pl_ltssm_state_q_reg[5]\;
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => gt_rx_phy_status_q_reg_0,
      R => SS(0)
    );
\gt_rx_status_q[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => Q(5),
      I1 => Q(0),
      I2 => Q(3),
      I3 => Q(2),
      I4 => Q(1),
      I5 => Q(4),
      O => \^pl_ltssm_state_q_reg[5]\
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(0),
      Q => \gt_rx_status_q_reg[2]_0\(0),
      R => SS(0)
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(1),
      Q => \gt_rx_status_q_reg[2]_0\(1),
      R => SS(0)
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_1\(2),
      Q => \gt_rx_status_q_reg[2]_0\(2),
      R => SS(0)
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => SS(0)
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => p_1_in,
      R => SS(0)
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(0),
      Q => \^gt_rxdata_q_reg[15]_0\(0),
      R => SS(0)
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(10),
      Q => \^gt_rxdata_q_reg[15]_0\(10),
      R => SS(0)
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(11),
      Q => \^gt_rxdata_q_reg[15]_0\(11),
      R => SS(0)
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(12),
      Q => \^gt_rxdata_q_reg[15]_0\(12),
      R => SS(0)
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(13),
      Q => \^gt_rxdata_q_reg[15]_0\(13),
      R => SS(0)
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(14),
      Q => \^gt_rxdata_q_reg[15]_0\(14),
      R => SS(0)
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(15),
      Q => \^gt_rxdata_q_reg[15]_0\(15),
      R => SS(0)
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(1),
      Q => \^gt_rxdata_q_reg[15]_0\(1),
      R => SS(0)
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(2),
      Q => \^gt_rxdata_q_reg[15]_0\(2),
      R => SS(0)
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(3),
      Q => \^gt_rxdata_q_reg[15]_0\(3),
      R => SS(0)
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(4),
      Q => \^gt_rxdata_q_reg[15]_0\(4),
      R => SS(0)
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(5),
      Q => \^gt_rxdata_q_reg[15]_0\(5),
      R => SS(0)
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(6),
      Q => \^gt_rxdata_q_reg[15]_0\(6),
      R => SS(0)
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(7),
      Q => \^gt_rxdata_q_reg[15]_0\(7),
      R => SS(0)
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(8),
      Q => \^gt_rxdata_q_reg[15]_0\(8),
      R => SS(0)
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]_1\(9),
      Q => \^gt_rxdata_q_reg[15]_0\(9),
      R => SS(0)
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => SYNC_RXELECIDLE,
      Q => gt_rxelecidle_q_reg_0,
      R => SS(0)
    );
gt_rxvalid_q: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => state_eios_det(1),
      I2 => state_eios_det(2),
      I3 => state_eios_det(3),
      I4 => state_eios_det(4),
      O => gt_rxvalid_q_n_0
    );
\gt_rxvalid_q_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FFFB"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__0_n_0\,
      I1 => gt_rxvalid_q_n_0,
      I2 => state_eios_det(0),
      I3 => \reg_state_eios_det[0]_i_2__0_n_0\,
      I4 => gt_rxvalid_q_reg_1,
      I5 => \gt_rxvalid_q_i_4__0_n_0\,
      O => \gt_rxvalid_q__0\
    );
\gt_rxvalid_q_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(1),
      I1 => \reg_state_eios_det[4]_i_3__0_n_0\,
      O => \gt_rxvalid_q_i_2__0_n_0\
    );
\gt_rxvalid_q_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \^pl_ltssm_state_q_reg[5]\,
      I1 => state_eios_det(0),
      I2 => state_eios_det(4),
      I3 => state_eios_det(2),
      I4 => state_eios_det(1),
      I5 => state_eios_det(3),
      O => \gt_rxvalid_q_i_4__0_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxvalid_q__0\,
      Q => \^gt_rxvalid_q_reg_0\,
      R => SS(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt_rxvalid_q_reg_0\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \gt_rxcharisk_q_reg[1]_0\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_1_in,
      I1 => \^gt_rxvalid_q_reg_0\,
      I2 => symbol_after_eios,
      O => \gt_rxcharisk_q_reg[1]_0\(1)
    );
\reg_state_eios_det[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAEAAAFFFFEAAA"
    )
        port map (
      I0 => \reg_state_eios_det[0]_i_2__0_n_0\,
      I1 => \reg_state_eios_det[2]_i_2__0_n_0\,
      I2 => \reg_state_eios_det[1]_i_2_n_0\,
      I3 => state_eios_det(0),
      I4 => state_eios_det(1),
      I5 => \reg_state_eios_det[4]_i_3__0_n_0\,
      O => \p_1_in__0\(0)
    );
\reg_state_eios_det[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88FA"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_3__0_n_0\,
      I2 => state_eios_det(3),
      I3 => \reg_state_eios_det[4]_i_3__0_n_0\,
      I4 => state_eios_det(4),
      O => \reg_state_eios_det[0]_i_2__0_n_0\
    );
\reg_state_eios_det[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => \reg_state_eios_det[1]_i_2_n_0\,
      O => \p_1_in__0\(1)
    );
\reg_state_eios_det[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \reg_state_eios_det[3]_i_3__0_n_0\,
      I1 => \reg_state_eios_det[1]_i_3_n_0\,
      I2 => \^gt_rxdata_q_reg[15]_0\(3),
      I3 => \^gt_rxdata_q_reg[15]_0\(5),
      I4 => \^gt_rxdata_q_reg[15]_0\(2),
      I5 => \^gt_rxdata_q_reg[15]_0\(4),
      O => \reg_state_eios_det[1]_i_2_n_0\
    );
\reg_state_eios_det[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
        port map (
      I0 => \gt_rxcharisk_q_reg_n_0_[0]\,
      I1 => \^gt_rxdata_q_reg[15]_0\(0),
      I2 => \^gt_rxdata_q_reg[15]_0\(6),
      I3 => \^gt_rxdata_q_reg[15]_0\(7),
      I4 => \^gt_rxdata_q_reg[15]_0\(1),
      O => \reg_state_eios_det[1]_i_3_n_0\
    );
\reg_state_eios_det[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(0),
      I1 => \reg_state_eios_det[2]_i_2__0_n_0\,
      O => \p_1_in__0\(2)
    );
\reg_state_eios_det[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFFFFFF"
    )
        port map (
      I0 => \reg_state_eios_det[2]_i_3__0_n_0\,
      I1 => \^gt_rxdata_q_reg[15]_0\(8),
      I2 => \^gt_rxdata_q_reg[15]_0\(11),
      I3 => \^gt_rxdata_q_reg[15]_0\(10),
      I4 => \^gt_rxdata_q_reg[15]_0\(15),
      I5 => \^gt_rxdata_q_reg[15]_0\(14),
      O => \reg_state_eios_det[2]_i_2__0_n_0\
    );
\reg_state_eios_det[2]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => p_1_in,
      I1 => \^gt_rxdata_q_reg[15]_0\(13),
      I2 => \^gt_rxdata_q_reg[15]_0\(12),
      I3 => \^gt_rxdata_q_reg[15]_0\(9),
      O => \reg_state_eios_det[2]_i_3__0_n_0\
    );
\reg_state_eios_det[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_2_n_0\,
      O => \p_1_in__0\(3)
    );
\reg_state_eios_det[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \reg_state_eios_det[3]_i_3__0_n_0\,
      I1 => \reg_state_eios_det[4]_i_3__0_n_0\,
      O => \reg_state_eios_det[3]_i_2_n_0\
    );
\reg_state_eios_det[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFFFFFF"
    )
        port map (
      I0 => \reg_state_eios_det[2]_i_3__0_n_0\,
      I1 => \^gt_rxdata_q_reg[15]_0\(8),
      I2 => \^gt_rxdata_q_reg[15]_0\(11),
      I3 => \^gt_rxdata_q_reg[15]_0\(10),
      I4 => \^gt_rxdata_q_reg[15]_0\(14),
      I5 => \^gt_rxdata_q_reg[15]_0\(15),
      O => \reg_state_eios_det[3]_i_3__0_n_0\
    );
\reg_state_eios_det[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => state_eios_det(4),
      I2 => state_eios_det(3),
      I3 => state_eios_det(0),
      I4 => state_eios_det(1),
      O => \reg_state_eios_det[4]_i_1__0_n_0\
    );
\reg_state_eios_det[4]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \reg_state_eios_det[4]_i_3__0_n_0\,
      I1 => state_eios_det(3),
      I2 => state_eios_det(1),
      O => \p_1_in__0\(4)
    );
\reg_state_eios_det[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \reg_state_eios_det[4]_i_4__0_n_0\,
      I1 => \^gt_rxdata_q_reg[15]_0\(7),
      I2 => \^gt_rxdata_q_reg[15]_0\(6),
      I3 => \^gt_rxdata_q_reg[15]_0\(1),
      I4 => \^gt_rxdata_q_reg[15]_0\(0),
      I5 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \reg_state_eios_det[4]_i_3__0_n_0\
    );
\reg_state_eios_det[4]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^gt_rxdata_q_reg[15]_0\(3),
      I1 => \^gt_rxdata_q_reg[15]_0\(5),
      I2 => \^gt_rxdata_q_reg[15]_0\(2),
      I3 => \^gt_rxdata_q_reg[15]_0\(4),
      O => \reg_state_eios_det[4]_i_4__0_n_0\
    );
\reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1__0_n_0\,
      D => \p_1_in__0\(0),
      Q => state_eios_det(0),
      S => SS(0)
    );
\reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1__0_n_0\,
      D => \p_1_in__0\(1),
      Q => state_eios_det(1),
      R => SS(0)
    );
\reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1__0_n_0\,
      D => \p_1_in__0\(2),
      Q => state_eios_det(2),
      R => SS(0)
    );
\reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1__0_n_0\,
      D => \p_1_in__0\(3),
      Q => state_eios_det(3),
      R => SS(0)
    );
\reg_state_eios_det_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => \reg_state_eios_det[4]_i_1__0_n_0\,
      D => \p_1_in__0\(4),
      Q => state_eios_det(4),
      R => SS(0)
    );
\reg_symbol_after_eios_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => state_eios_det(2),
      I1 => \reg_state_eios_det[3]_i_2_n_0\,
      I2 => state_eios_det(3),
      I3 => state_eios_det(4),
      I4 => state_eios_det(0),
      I5 => state_eios_det(1),
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_wrapper is
  port (
    \resetovrd.reset_reg[4]\ : out STD_LOGIC;
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd.reset_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_0 : out STD_LOGIC;
    pipe_rx0_chanisaligned_gt : out STD_LOGIC;
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXPHALIGNDONE_M : out STD_LOGIC;
    \resetovrd.reset_reg[4]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_0 : out STD_LOGIC;
    gt_rxresetdone_0 : out STD_LOGIC;
    SYNC_RXSYNCDONE : out STD_LOGIC;
    gt_rxsyncout_0 : out STD_LOGIC;
    gt_rxvalid_0 : out STD_LOGIC;
    \resetovrd.reset_reg[4]_2\ : out STD_LOGIC;
    \resetovrd.reset_reg[4]_3\ : out STD_LOGIC;
    \resetovrd.reset_reg[4]_4\ : out STD_LOGIC;
    gt_txratedone_0 : out STD_LOGIC;
    gt_txresetdone_0 : out STD_LOGIC;
    SYNC_TXSYNCDONE : out STD_LOGIC;
    gt_txsyncout_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    RXSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SYNC_TXDLYSRESETDONE : out STD_LOGIC;
    SYNC_RXDLYSRESETDONE : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    drp_mux_en_0 : in STD_LOGIC;
    rdy_reg1_reg : in STD_LOGIC;
    user_eyescanreset_0 : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_gtreset : in STD_LOGIC;
    rdy_reg1_reg_0 : in STD_LOGIC;
    rdy_reg1_reg_1 : in STD_LOGIC;
    user_resetovrd_0 : in STD_LOGIC;
    user_rxbufreset_0 : in STD_LOGIC;
    user_rxcdrfreqreset_0 : in STD_LOGIC;
    user_rxcdrreset_0 : in STD_LOGIC;
    user_rxpcsreset_0 : in STD_LOGIC;
    user_rxpmareset_0 : in STD_LOGIC;
    pipe_rx0_polarity_gt : in STD_LOGIC;
    rxsyncallin : in STD_LOGIC;
    rst_userrdy : in STD_LOGIC;
    rdy_reg1_reg_2 : in STD_LOGIC;
    user_oobclk_0 : in STD_LOGIC;
    pipe_tx_deemph_gt : in STD_LOGIC;
    pipe_tx_rcvr_det_gt : in STD_LOGIC;
    sync_txdlyen_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx0_elec_idle_gt : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdy_reg1_reg_4 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rdy_reg1_reg_5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXCHARDISPMODE : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdy_reg1_reg_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 0 to 0 );
    txdlysresetdone_reg1_reg : in STD_LOGIC;
    rxdlysresetdone_reg1_reg : in STD_LOGIC;
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_wrapper : entity is "xdma_0_pcie2_ip_gt_wrapper";
end xdma_0_xdma_0_pcie2_ip_gt_wrapper;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_wrapper is
  signal \^rxstatus\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^gt_rxsyncout_0\ : STD_LOGIC;
  signal \^gt_txsyncout_0\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_1\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_103\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_104\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_105\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_110\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_111\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_112\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_113\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_114\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_115\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_116\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_117\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_118\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_119\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_120\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_121\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_122\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_123\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_124\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_125\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_126\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_127\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_14\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_156\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_157\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_158\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_159\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_160\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_161\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_162\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_163\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_17\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_24\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_29\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_36\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_48\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_49\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_50\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_51\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_52\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_53\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_54\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_55\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_56\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_57\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_58\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_59\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_60\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_61\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_62\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_7\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_8\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1__0\ : label is "soft_lutpair1822";
  attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1__0\ : label is "soft_lutpair1822";
  attribute box_type : string;
  attribute box_type of \gtp_channel.gtpe2_channel_i\ : label is "PRIMITIVE";
begin
  RXSTATUS(0) <= \^rxstatus\(0);
  gt_rxsyncout_0 <= \^gt_rxsyncout_0\;
  gt_txsyncout_0 <= \^gt_txsyncout_0\;
\gt_rx_status_q[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_111\,
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(0)
    );
\gt_rx_status_q[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_110\,
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(1)
    );
\gt_rx_status_q[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^rxstatus\(0),
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(2)
    );
\gtp_channel.gtpe2_channel_i\: unisim.vcomponents.GTPE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => B"00000000000000000000",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => B"1001001000000000000000001000000111010000000",
      CFOK_CFG2 => B"0100000",
      CFOK_CFG3 => B"0100000",
      CFOK_CFG4 => '0',
      CFOK_CFG5 => B"00",
      CFOK_CFG6 => B"0000",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_COMMON_SWING => '0',
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"010",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"000000000100",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_LOOPBACK_CFG => '0',
      PMA_RSV => X"00000333",
      PMA_RSV2 => X"00002040",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"0000",
      PMA_RSV5 => '0',
      PMA_RSV6 => '0',
      PMA_RSV7 => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0000107FE406001041010",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPMRESET_TIME => B"0001111",
      RXLPM_BIAS_STARTUP_DISABLE => '0',
      RXLPM_CFG => B"0110",
      RXLPM_CFG1 => '0',
      RXLPM_CM_CFG => '0',
      RXLPM_GC_CFG => B"111100010",
      RXLPM_GC_CFG2 => B"001",
      RXLPM_HF_CFG => B"00001111110000",
      RXLPM_HF_CFG2 => B"01010",
      RXLPM_HF_CFG3 => B"0000",
      RXLPM_HOLD_DURING_EIDLE => '1',
      RXLPM_INCM_CFG => '1',
      RXLPM_IPCM_CFG => '0',
      RXLPM_LF_CFG => B"000000001111110000",
      RXLPM_LF_CFG2 => B"01010",
      RXLPM_OSINT_CFG => B"100",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "FABRIC",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"000",
      RXPI_CFG1 => '1',
      RXPI_CFG2 => '1',
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '1',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"0000111100110011",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_EN => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SATA_PLL_CFG => "VCO_3000MHZ",
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "1.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '1',
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"000",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00011",
      TXSYNC_MULTILANE => '1',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 4,
      TX_CLKMUX_EN => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"010100",
      TX_DEEMPH1 => B"001011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"010",
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => \gtp_channel.gtpe2_channel_i_n_48\,
      DMONITOROUT(13) => \gtp_channel.gtpe2_channel_i_n_49\,
      DMONITOROUT(12) => \gtp_channel.gtpe2_channel_i_n_50\,
      DMONITOROUT(11) => \gtp_channel.gtpe2_channel_i_n_51\,
      DMONITOROUT(10) => \gtp_channel.gtpe2_channel_i_n_52\,
      DMONITOROUT(9) => \gtp_channel.gtpe2_channel_i_n_53\,
      DMONITOROUT(8) => \gtp_channel.gtpe2_channel_i_n_54\,
      DMONITOROUT(7) => \gtp_channel.gtpe2_channel_i_n_55\,
      DMONITOROUT(6) => \gtp_channel.gtpe2_channel_i_n_56\,
      DMONITOROUT(5) => \gtp_channel.gtpe2_channel_i_n_57\,
      DMONITOROUT(4) => \gtp_channel.gtpe2_channel_i_n_58\,
      DMONITOROUT(3) => \gtp_channel.gtpe2_channel_i_n_59\,
      DMONITOROUT(2) => \gtp_channel.gtpe2_channel_i_n_60\,
      DMONITOROUT(1) => \gtp_channel.gtpe2_channel_i_n_61\,
      DMONITOROUT(0) => \gtp_channel.gtpe2_channel_i_n_62\,
      DRPADDR(8 downto 5) => B"0000",
      DRPADDR(4) => DRPADDR(0),
      DRPADDR(3 downto 1) => B"000",
      DRPADDR(0) => DRPADDR(0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => D(15 downto 0),
      DRPEN => drp_mux_en_0,
      DRPRDY => \resetovrd.reset_reg[4]\,
      DRPWE => rdy_reg1_reg,
      EYESCANDATAERROR => \gtp_channel.gtpe2_channel_i_n_1\,
      EYESCANMODE => '0',
      EYESCANRESET => user_eyescanreset_0,
      EYESCANTRIGGER => '0',
      GTPRXN => pci_exp_rxn(0),
      GTPRXP => pci_exp_rxp(0),
      GTPTXN => pci_exp_txn(0),
      GTPTXP => pci_exp_txp(0),
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => rst_gtreset,
      GTTXRESET => rst_gtreset,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDOUT(15 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => \resetovrd.reset_reg[4]_0\(0),
      PLL0CLK => rdy_reg1_reg_0,
      PLL0REFCLK => rdy_reg1_reg_1,
      PLL1CLK => '0',
      PLL1REFCLK => '0',
      PMARSVDIN0 => '0',
      PMARSVDIN1 => '0',
      PMARSVDIN2 => '0',
      PMARSVDIN3 => '0',
      PMARSVDIN4 => '0',
      PMARSVDOUT0 => \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED\,
      PMARSVDOUT1 => \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED\,
      RESETOVRD => user_resetovrd_0,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => user_rxbufreset_0,
      RXBUFSTATUS(2) => \gtp_channel.gtpe2_channel_i_n_103\,
      RXBUFSTATUS(1) => \gtp_channel.gtpe2_channel_i_n_104\,
      RXBUFSTATUS(0) => \gtp_channel.gtpe2_channel_i_n_105\,
      RXBYTEISALIGNED => \gtp_channel.gtpe2_channel_i_n_7\,
      RXBYTEREALIGN => \gtp_channel.gtpe2_channel_i_n_8\,
      RXCDRFREQRESET => user_rxcdrfreqreset_0,
      RXCDRHOLD => '0',
      RXCDRLOCK => gt_rxcdrlock_0,
      RXCDROVRDEN => '0',
      RXCDRRESET => user_rxcdrreset_0,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => pipe_rx0_chanisaligned_gt,
      RXCHANREALIGN => \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(3) => \gtp_channel.gtpe2_channel_i_n_144\,
      RXCHARISCOMMA(2) => \gtp_channel.gtpe2_channel_i_n_145\,
      RXCHARISCOMMA(1) => \gtp_channel.gtpe2_channel_i_n_146\,
      RXCHARISCOMMA(0) => \gtp_channel.gtpe2_channel_i_n_147\,
      RXCHARISK(3) => \gtp_channel.gtpe2_channel_i_n_148\,
      RXCHARISK(2) => \gtp_channel.gtpe2_channel_i_n_149\,
      RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0),
      RXCHBONDEN => '1',
      RXCHBONDI(3 downto 0) => B"0000",
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => '1',
      RXCHBONDO(3 downto 0) => RXCHBONDO(3 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => \gtp_channel.gtpe2_channel_i_n_14\,
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(31) => \gtp_channel.gtpe2_channel_i_n_112\,
      RXDATA(30) => \gtp_channel.gtpe2_channel_i_n_113\,
      RXDATA(29) => \gtp_channel.gtpe2_channel_i_n_114\,
      RXDATA(28) => \gtp_channel.gtpe2_channel_i_n_115\,
      RXDATA(27) => \gtp_channel.gtpe2_channel_i_n_116\,
      RXDATA(26) => \gtp_channel.gtpe2_channel_i_n_117\,
      RXDATA(25) => \gtp_channel.gtpe2_channel_i_n_118\,
      RXDATA(24) => \gtp_channel.gtpe2_channel_i_n_119\,
      RXDATA(23) => \gtp_channel.gtpe2_channel_i_n_120\,
      RXDATA(22) => \gtp_channel.gtpe2_channel_i_n_121\,
      RXDATA(21) => \gtp_channel.gtpe2_channel_i_n_122\,
      RXDATA(20) => \gtp_channel.gtpe2_channel_i_n_123\,
      RXDATA(19) => \gtp_channel.gtpe2_channel_i_n_124\,
      RXDATA(18) => \gtp_channel.gtpe2_channel_i_n_125\,
      RXDATA(17) => \gtp_channel.gtpe2_channel_i_n_126\,
      RXDATA(16) => \gtp_channel.gtpe2_channel_i_n_127\,
      RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0),
      RXDATAVALID(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED\(1 downto 0),
      RXDDIEN => '0',
      RXDFEXYDEN => '0',
      RXDISPERR(3) => \gtp_channel.gtpe2_channel_i_n_156\,
      RXDISPERR(2) => \gtp_channel.gtpe2_channel_i_n_157\,
      RXDISPERR(1) => \gtp_channel.gtpe2_channel_i_n_158\,
      RXDISPERR(0) => \gtp_channel.gtpe2_channel_i_n_159\,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => \gtp_channel.gtpe2_channel_i_n_17\,
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1 downto 0) => B"00",
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFOVRDEN => '0',
      RXLPMOSINTNTRLEN => '0',
      RXLPMRESET => '0',
      RXMCOMMAALIGNEN => '1',
      RXNOTINTABLE(3) => \gtp_channel.gtpe2_channel_i_n_160\,
      RXNOTINTABLE(2) => \gtp_channel.gtpe2_channel_i_n_161\,
      RXNOTINTABLE(1) => \gtp_channel.gtpe2_channel_i_n_162\,
      RXNOTINTABLE(0) => \gtp_channel.gtpe2_channel_i_n_163\,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0010",
      RXOSINTDONE => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED\,
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTPD => '0',
      RXOSINTSTARTED => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED\,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED\,
      RXOSINTSTROBESTARTED => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED\,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => \gtp_channel.gtpe2_channel_i_n_24\,
      RXOUTCLKFABRIC => \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2 downto 0) => B"000",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => user_rxpcsreset_0,
      RXPD(1 downto 0) => rdy_reg1_reg_3(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => SYNC_RXPHALIGNDONE_M,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => user_rxpmareset_0,
      RXPMARESETDONE => \resetovrd.reset_reg[4]_1\(0),
      RXPOLARITY => pipe_rx0_polarity_gt,
      RXPRBSCNTRESET => '0',
      RXPRBSERR => \gtp_channel.gtpe2_channel_i_n_29\,
      RXPRBSSEL(2 downto 0) => B"000",
      RXRATE(2 downto 1) => B"00",
      RXRATE(0) => RXRATE(0),
      RXRATEDONE => gt_rxratedone_0,
      RXRATEMODE => '0',
      RXRESETDONE => gt_rxresetdone_0,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\(1 downto 0),
      RXSTATUS(2) => \^rxstatus\(0),
      RXSTATUS(1) => \gtp_channel.gtpe2_channel_i_n_110\,
      RXSTATUS(0) => \gtp_channel.gtpe2_channel_i_n_111\,
      RXSYNCALLIN => rxsyncallin,
      RXSYNCDONE => SYNC_RXSYNCDONE,
      RXSYNCIN => \^gt_rxsyncout_0\,
      RXSYNCMODE => '1',
      RXSYNCOUT => \^gt_rxsyncout_0\,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => rst_userrdy,
      RXUSRCLK => rdy_reg1_reg_2,
      RXUSRCLK2 => rdy_reg1_reg_2,
      RXVALID => gt_rxvalid_0,
      SETERRSTATUS => '0',
      SIGVALIDCLK => user_oobclk_0,
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(3 downto 0) => B"0000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(3 downto 1) => B"000",
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      TXCHARDISPVAL(3 downto 0) => B"0000",
      TXCHARISK(3 downto 2) => B"00",
      TXCHARISK(1 downto 0) => rdy_reg1_reg_6(1 downto 0),
      TXCOMFINISH => \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(31 downto 16) => B"0000000000000000",
      TXDATA(15 downto 0) => rdy_reg1_reg_5(15 downto 0),
      TXDEEMPH => pipe_tx_deemph_gt,
      TXDETECTRX => pipe_tx_rcvr_det_gt,
      TXDIFFCTRL(3 downto 0) => B"1100",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => sync_txdlyen_0,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => Q(0),
      TXDLYSRESETDONE => \gtp_channel.gtpe2_channel_i_n_36\,
      TXDLYUPDOWN => '0',
      TXELECIDLE => pipe_tx0_elec_idle_gt,
      TXGEARBOXREADY => \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => rdy_reg1_reg_4(2 downto 0),
      TXOUTCLK => \resetovrd.reset_reg[4]_2\,
      TXOUTCLKFABRIC => \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => rdy_reg1_reg_3(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => Q(2),
      TXPHALIGNDONE => \resetovrd.reset_reg[4]_3\,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => Q(1),
      TXPHINITDONE => \resetovrd.reset_reg[4]_4\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED\,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXRATE(2 downto 1) => B"00",
      TXRATE(0) => RXRATE(0),
      TXRATEDONE => gt_txratedone_0,
      TXRATEMODE => '0',
      TXRESETDONE => gt_txresetdone_0,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => SYNC_TXPHALIGNDONE,
      TXSYNCDONE => SYNC_TXSYNCDONE,
      TXSYNCIN => \^gt_txsyncout_0\,
      TXSYNCMODE => '1',
      TXSYNCOUT => \^gt_txsyncout_0\,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => rst_userrdy,
      TXUSRCLK => rdy_reg1_reg_2,
      TXUSRCLK2 => rdy_reg1_reg_2
    );
rxdlysresetdone_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_17\,
      I1 => rxdlysresetdone_reg1_reg,
      O => SYNC_RXDLYSRESETDONE
    );
txdlysresetdone_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_36\,
      I1 => txdlysresetdone_reg1_reg,
      O => SYNC_TXDLYSRESETDONE
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_wrapper_31 is
  port (
    \resetovrd.reset_reg[4]\ : out STD_LOGIC;
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd.reset_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_1 : out STD_LOGIC;
    pipe_rx1_chanisaligned_gt : out STD_LOGIC;
    \resetovrd.reset_reg[4]_1\ : out STD_LOGIC;
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXPHALIGNDONE_S : out STD_LOGIC;
    \resetovrd.reset_reg[4]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_1 : out STD_LOGIC;
    gt_rxresetdone_1 : out STD_LOGIC;
    SYNC_RXSYNCDONE : out STD_LOGIC;
    gt_rxvalid_1 : out STD_LOGIC;
    \resetovrd.reset_reg[4]_3\ : out STD_LOGIC;
    \resetovrd.reset_reg[4]_4\ : out STD_LOGIC;
    \resetovrd.reset_reg[4]_5\ : out STD_LOGIC;
    gt_txratedone_1 : out STD_LOGIC;
    gt_txresetdone_1 : out STD_LOGIC;
    SYNC_TXSYNCDONE : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    RXSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    CLK : in STD_LOGIC;
    drp_mux_en_1 : in STD_LOGIC;
    rdy_reg1_reg : in STD_LOGIC;
    user_eyescanreset_1 : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_gtreset : in STD_LOGIC;
    rdy_reg1_reg_0 : in STD_LOGIC;
    rdy_reg1_reg_1 : in STD_LOGIC;
    user_resetovrd_1 : in STD_LOGIC;
    user_rxbufreset_1 : in STD_LOGIC;
    user_rxcdrfreqreset_1 : in STD_LOGIC;
    user_rxcdrreset_1 : in STD_LOGIC;
    user_rxpcsreset_1 : in STD_LOGIC;
    user_rxpmareset_1 : in STD_LOGIC;
    pipe_rx1_polarity_gt : in STD_LOGIC;
    rxsyncallin : in STD_LOGIC;
    gt_rxsyncout_0 : in STD_LOGIC;
    rst_userrdy : in STD_LOGIC;
    rdy_reg1_reg_2 : in STD_LOGIC;
    user_oobclk_1 : in STD_LOGIC;
    pipe_tx_deemph_gt : in STD_LOGIC;
    pipe_tx_rcvr_det_gt : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx1_elec_idle_gt : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    gt_txsyncout_0 : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdy_reg1_reg_4 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rdy_reg1_reg_5 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rdy_reg1_reg_6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rdy_reg1_reg_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_wrapper_31 : entity is "xdma_0_pcie2_ip_gt_wrapper";
end xdma_0_xdma_0_pcie2_ip_gt_wrapper_31;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_wrapper_31 is
  signal \^rxstatus\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \gtp_channel.gtpe2_channel_i_n_1\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_103\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_104\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_105\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_110\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_111\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_112\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_113\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_114\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_115\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_116\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_117\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_118\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_119\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_120\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_121\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_122\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_123\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_124\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_125\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_126\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_127\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_14\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_154\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_155\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_156\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_157\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_158\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_159\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_160\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_161\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_162\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_163\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_24\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_29\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_33\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_38\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_47\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_48\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_49\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_50\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_51\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_52\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_53\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_54\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_55\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_56\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_57\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_58\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_59\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_60\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_61\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_62\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_7\ : STD_LOGIC;
  signal \gtp_channel.gtpe2_channel_i_n_8\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1\ : label is "soft_lutpair1868";
  attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1\ : label is "soft_lutpair1868";
  attribute box_type : string;
  attribute box_type of \gtp_channel.gtpe2_channel_i\ : label is "PRIMITIVE";
begin
  RXSTATUS(0) <= \^rxstatus\(0);
\gt_rx_status_q[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_111\,
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(0)
    );
\gt_rx_status_q[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \gtp_channel.gtpe2_channel_i_n_110\,
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(1)
    );
\gt_rx_status_q[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => \^rxstatus\(0),
      I1 => \gt_rx_status_q_reg[0]\,
      I2 => \gt_rx_status_q_reg[2]\,
      O => gt_rxvalid_q_reg(2)
    );
\gtp_channel.gtpe2_channel_i\: unisim.vcomponents.GTPE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => B"00000000000000000000",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => B"1001001000000000000000001000000111010000000",
      CFOK_CFG2 => B"0100000",
      CFOK_CFG3 => B"0100000",
      CFOK_CFG4 => '0',
      CFOK_CFG5 => B"00",
      CFOK_CFG6 => B"0000",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_COMMON_SWING => '0',
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"010",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"000000000100",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_LOOPBACK_CFG => '0',
      PMA_RSV => X"00000333",
      PMA_RSV2 => X"00002040",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"0000",
      PMA_RSV5 => '0',
      PMA_RSV6 => '0',
      PMA_RSV7 => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0000107FE406001041010",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPMRESET_TIME => B"0001111",
      RXLPM_BIAS_STARTUP_DISABLE => '0',
      RXLPM_CFG => B"0110",
      RXLPM_CFG1 => '0',
      RXLPM_CM_CFG => '0',
      RXLPM_GC_CFG => B"111100010",
      RXLPM_GC_CFG2 => B"001",
      RXLPM_HF_CFG => B"00001111110000",
      RXLPM_HF_CFG2 => B"01010",
      RXLPM_HF_CFG3 => B"0000",
      RXLPM_HOLD_DURING_EIDLE => '1',
      RXLPM_INCM_CFG => '1',
      RXLPM_IPCM_CFG => '0',
      RXLPM_LF_CFG => B"000000001111110000",
      RXLPM_LF_CFG2 => B"01010",
      RXLPM_OSINT_CFG => B"100",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "FABRIC",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"000",
      RXPI_CFG1 => '1',
      RXPI_CFG2 => '1',
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RXSYNC_MULTILANE => '1',
      RXSYNC_OVRD => '1',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"0000111100110011",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_EN => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SATA_PLL_CFG => "VCO_3000MHZ",
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "1.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '1',
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"000",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00011",
      TXSYNC_MULTILANE => '1',
      TXSYNC_OVRD => '1',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 4,
      TX_CLKMUX_EN => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"010100",
      TX_DEEMPH1 => B"001011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"010",
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14) => \gtp_channel.gtpe2_channel_i_n_48\,
      DMONITOROUT(13) => \gtp_channel.gtpe2_channel_i_n_49\,
      DMONITOROUT(12) => \gtp_channel.gtpe2_channel_i_n_50\,
      DMONITOROUT(11) => \gtp_channel.gtpe2_channel_i_n_51\,
      DMONITOROUT(10) => \gtp_channel.gtpe2_channel_i_n_52\,
      DMONITOROUT(9) => \gtp_channel.gtpe2_channel_i_n_53\,
      DMONITOROUT(8) => \gtp_channel.gtpe2_channel_i_n_54\,
      DMONITOROUT(7) => \gtp_channel.gtpe2_channel_i_n_55\,
      DMONITOROUT(6) => \gtp_channel.gtpe2_channel_i_n_56\,
      DMONITOROUT(5) => \gtp_channel.gtpe2_channel_i_n_57\,
      DMONITOROUT(4) => \gtp_channel.gtpe2_channel_i_n_58\,
      DMONITOROUT(3) => \gtp_channel.gtpe2_channel_i_n_59\,
      DMONITOROUT(2) => \gtp_channel.gtpe2_channel_i_n_60\,
      DMONITOROUT(1) => \gtp_channel.gtpe2_channel_i_n_61\,
      DMONITOROUT(0) => \gtp_channel.gtpe2_channel_i_n_62\,
      DRPADDR(8 downto 5) => B"0000",
      DRPADDR(4) => DRPADDR(0),
      DRPADDR(3 downto 1) => B"000",
      DRPADDR(0) => DRPADDR(0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => D(15 downto 0),
      DRPEN => drp_mux_en_1,
      DRPRDY => \resetovrd.reset_reg[4]\,
      DRPWE => rdy_reg1_reg,
      EYESCANDATAERROR => \gtp_channel.gtpe2_channel_i_n_1\,
      EYESCANMODE => '0',
      EYESCANRESET => user_eyescanreset_1,
      EYESCANTRIGGER => '0',
      GTPRXN => pci_exp_rxn(0),
      GTPRXP => pci_exp_rxp(0),
      GTPTXN => pci_exp_txn(0),
      GTPTXP => pci_exp_txp(0),
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => rst_gtreset,
      GTTXRESET => rst_gtreset,
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDOUT(15 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => \resetovrd.reset_reg[4]_0\(0),
      PLL0CLK => rdy_reg1_reg_0,
      PLL0REFCLK => rdy_reg1_reg_1,
      PLL1CLK => '0',
      PLL1REFCLK => '0',
      PMARSVDIN0 => '0',
      PMARSVDIN1 => '0',
      PMARSVDIN2 => '0',
      PMARSVDIN3 => '0',
      PMARSVDIN4 => '0',
      PMARSVDOUT0 => \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED\,
      PMARSVDOUT1 => \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED\,
      RESETOVRD => user_resetovrd_1,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => user_rxbufreset_1,
      RXBUFSTATUS(2) => \gtp_channel.gtpe2_channel_i_n_103\,
      RXBUFSTATUS(1) => \gtp_channel.gtpe2_channel_i_n_104\,
      RXBUFSTATUS(0) => \gtp_channel.gtpe2_channel_i_n_105\,
      RXBYTEISALIGNED => \gtp_channel.gtpe2_channel_i_n_7\,
      RXBYTEREALIGN => \gtp_channel.gtpe2_channel_i_n_8\,
      RXCDRFREQRESET => user_rxcdrfreqreset_1,
      RXCDRHOLD => '0',
      RXCDRLOCK => gt_rxcdrlock_1,
      RXCDROVRDEN => '0',
      RXCDRRESET => user_rxcdrreset_1,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => pipe_rx1_chanisaligned_gt,
      RXCHANREALIGN => \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(3) => \gtp_channel.gtpe2_channel_i_n_144\,
      RXCHARISCOMMA(2) => \gtp_channel.gtpe2_channel_i_n_145\,
      RXCHARISCOMMA(1) => \gtp_channel.gtpe2_channel_i_n_146\,
      RXCHARISCOMMA(0) => \gtp_channel.gtpe2_channel_i_n_147\,
      RXCHARISK(3) => \gtp_channel.gtpe2_channel_i_n_148\,
      RXCHARISK(2) => \gtp_channel.gtpe2_channel_i_n_149\,
      RXCHARISK(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0),
      RXCHBONDEN => '1',
      RXCHBONDI(3 downto 0) => RXCHBONDO(3 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(3) => \gtp_channel.gtpe2_channel_i_n_152\,
      RXCHBONDO(2) => \gtp_channel.gtpe2_channel_i_n_153\,
      RXCHBONDO(1) => \gtp_channel.gtpe2_channel_i_n_154\,
      RXCHBONDO(0) => \gtp_channel.gtpe2_channel_i_n_155\,
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => \gtp_channel.gtpe2_channel_i_n_14\,
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(31) => \gtp_channel.gtpe2_channel_i_n_112\,
      RXDATA(30) => \gtp_channel.gtpe2_channel_i_n_113\,
      RXDATA(29) => \gtp_channel.gtpe2_channel_i_n_114\,
      RXDATA(28) => \gtp_channel.gtpe2_channel_i_n_115\,
      RXDATA(27) => \gtp_channel.gtpe2_channel_i_n_116\,
      RXDATA(26) => \gtp_channel.gtpe2_channel_i_n_117\,
      RXDATA(25) => \gtp_channel.gtpe2_channel_i_n_118\,
      RXDATA(24) => \gtp_channel.gtpe2_channel_i_n_119\,
      RXDATA(23) => \gtp_channel.gtpe2_channel_i_n_120\,
      RXDATA(22) => \gtp_channel.gtpe2_channel_i_n_121\,
      RXDATA(21) => \gtp_channel.gtpe2_channel_i_n_122\,
      RXDATA(20) => \gtp_channel.gtpe2_channel_i_n_123\,
      RXDATA(19) => \gtp_channel.gtpe2_channel_i_n_124\,
      RXDATA(18) => \gtp_channel.gtpe2_channel_i_n_125\,
      RXDATA(17) => \gtp_channel.gtpe2_channel_i_n_126\,
      RXDATA(16) => \gtp_channel.gtpe2_channel_i_n_127\,
      RXDATA(15 downto 0) => gt_rx_data_wire_filter(15 downto 0),
      RXDATAVALID(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED\(1 downto 0),
      RXDDIEN => '0',
      RXDFEXYDEN => '0',
      RXDISPERR(3) => \gtp_channel.gtpe2_channel_i_n_156\,
      RXDISPERR(2) => \gtp_channel.gtpe2_channel_i_n_157\,
      RXDISPERR(1) => \gtp_channel.gtpe2_channel_i_n_158\,
      RXDISPERR(0) => \gtp_channel.gtpe2_channel_i_n_159\,
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => \resetovrd.reset_reg[4]_1\,
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1 downto 0) => B"00",
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFOVRDEN => '0',
      RXLPMOSINTNTRLEN => '0',
      RXLPMRESET => '0',
      RXMCOMMAALIGNEN => '1',
      RXNOTINTABLE(3) => \gtp_channel.gtpe2_channel_i_n_160\,
      RXNOTINTABLE(2) => \gtp_channel.gtpe2_channel_i_n_161\,
      RXNOTINTABLE(1) => \gtp_channel.gtpe2_channel_i_n_162\,
      RXNOTINTABLE(0) => \gtp_channel.gtpe2_channel_i_n_163\,
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0010",
      RXOSINTDONE => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED\,
      RXOSINTEN => '1',
      RXOSINTHOLD => '0',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTPD => '0',
      RXOSINTSTARTED => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED\,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED\,
      RXOSINTSTROBESTARTED => \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED\,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => \gtp_channel.gtpe2_channel_i_n_24\,
      RXOUTCLKFABRIC => \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2 downto 0) => B"000",
      RXPCOMMAALIGNEN => '1',
      RXPCSRESET => user_rxpcsreset_1,
      RXPD(1 downto 0) => rdy_reg1_reg_3(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => SYNC_RXPHALIGNDONE_S,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => user_rxpmareset_1,
      RXPMARESETDONE => \resetovrd.reset_reg[4]_2\(0),
      RXPOLARITY => pipe_rx1_polarity_gt,
      RXPRBSCNTRESET => '0',
      RXPRBSERR => \gtp_channel.gtpe2_channel_i_n_29\,
      RXPRBSSEL(2 downto 0) => B"000",
      RXRATE(2 downto 1) => B"00",
      RXRATE(0) => RXRATE(0),
      RXRATEDONE => gt_rxratedone_1,
      RXRATEMODE => '0',
      RXRESETDONE => gt_rxresetdone_1,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\(1 downto 0),
      RXSTATUS(2) => \^rxstatus\(0),
      RXSTATUS(1) => \gtp_channel.gtpe2_channel_i_n_110\,
      RXSTATUS(0) => \gtp_channel.gtpe2_channel_i_n_111\,
      RXSYNCALLIN => rxsyncallin,
      RXSYNCDONE => SYNC_RXSYNCDONE,
      RXSYNCIN => gt_rxsyncout_0,
      RXSYNCMODE => '0',
      RXSYNCOUT => \gtp_channel.gtpe2_channel_i_n_33\,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => rst_userrdy,
      RXUSRCLK => rdy_reg1_reg_2,
      RXUSRCLK2 => rdy_reg1_reg_2,
      RXVALID => gt_rxvalid_1,
      SETERRSTATUS => '0',
      SIGVALIDCLK => user_oobclk_1,
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(3 downto 0) => B"0000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(3 downto 1) => B"000",
      TXCHARDISPMODE(0) => rdy_reg1_reg_6(0),
      TXCHARDISPVAL(3 downto 0) => B"0000",
      TXCHARISK(3 downto 2) => B"00",
      TXCHARISK(1 downto 0) => rdy_reg1_reg_7(1 downto 0),
      TXCOMFINISH => \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(31 downto 16) => B"0000000000000000",
      TXDATA(15 downto 0) => rdy_reg1_reg_5(15 downto 0),
      TXDEEMPH => pipe_tx_deemph_gt,
      TXDETECTRX => pipe_tx_rcvr_det_gt,
      TXDIFFCTRL(3 downto 0) => B"1100",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => Q(0),
      TXDLYSRESETDONE => \resetovrd.reset_reg[4]_3\,
      TXDLYUPDOWN => '0',
      TXELECIDLE => pipe_tx1_elec_idle_gt,
      TXGEARBOXREADY => \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => rdy_reg1_reg_4(2 downto 0),
      TXOUTCLK => \gtp_channel.gtpe2_channel_i_n_38\,
      TXOUTCLKFABRIC => \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2 downto 0) => B"000",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => rdy_reg1_reg_3(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => Q(2),
      TXPHALIGNDONE => \resetovrd.reset_reg[4]_4\,
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => Q(1),
      TXPHINITDONE => \resetovrd.reset_reg[4]_5\,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '0',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED\,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXRATE(2 downto 1) => B"00",
      TXRATE(0) => RXRATE(0),
      TXRATEDONE => gt_txratedone_1,
      TXRATEMODE => '0',
      TXRESETDONE => gt_txresetdone_1,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => SYNC_TXPHALIGNDONE,
      TXSYNCDONE => SYNC_TXSYNCDONE,
      TXSYNCIN => gt_txsyncout_0,
      TXSYNCMODE => '0',
      TXSYNCOUT => \gtp_channel.gtpe2_channel_i_n_47\,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => rst_userrdy,
      TXUSRCLK => rdy_reg1_reg_2,
      TXUSRCLK2 => rdy_reg1_reg_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_cpllpd_ovrd is
  port (
    cpllpd : out STD_LOGIC;
    cpllrst : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_cpllpd_ovrd : entity is "xdma_0_pcie2_ip_gtp_cpllpd_ovrd";
end xdma_0_xdma_0_pcie2_ip_gtp_cpllpd_ovrd;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_cpllpd_ovrd is
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp is
  port (
    done_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \fsm_reg[1]_0\ : out STD_LOGIC;
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 0 to 0 );
    drp_mux_en_0 : out STD_LOGIC;
    rst_dclk_reset : in STD_LOGIC;
    DRP_START00_out : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rdy_reg1_reg_0 : in STD_LOGIC;
    DRP_X160 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp : entity is "xdma_0_pcie2_ip_gtp_pipe_drp";
end xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp is
  signal addr_reg : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \di_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal done0 : STD_LOGIC;
  signal drp_addr_0 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal drp_di_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \index[4]_i_1_n_0\ : STD_LOGIC;
  signal \index[4]_i_3_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \load_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 11 to 11 );
  signal p_2_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal sel0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  signal x16_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO";
  attribute async_reg of x16_reg1 : signal is "true";
  signal x16_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO";
  attribute async_reg of x16_reg2 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_1\ : label is "soft_lutpair1833";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_10\ : label is "soft_lutpair1828";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_11\ : label is "soft_lutpair1827";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_12\ : label is "soft_lutpair1827";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_13\ : label is "soft_lutpair1826";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_14\ : label is "soft_lutpair1826";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_15\ : label is "soft_lutpair1825";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_16\ : label is "soft_lutpair1825";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_17\ : label is "soft_lutpair1824";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_18\ : label is "soft_lutpair1824";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_19\ : label is "soft_lutpair1823";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_2\ : label is "soft_lutpair1823";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_37__0\ : label is "soft_lutpair1831";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_4\ : label is "soft_lutpair1831";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_5\ : label is "soft_lutpair1830";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_6\ : label is "soft_lutpair1830";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_7\ : label is "soft_lutpair1829";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_8\ : label is "soft_lutpair1829";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_9\ : label is "soft_lutpair1828";
  attribute SOFT_HLUTNM of \index[0]_i_1\ : label is "soft_lutpair1832";
  attribute SOFT_HLUTNM of \index[1]_i_1\ : label is "soft_lutpair1833";
  attribute SOFT_HLUTNM of \index[4]_i_3\ : label is "soft_lutpair1832";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO";
begin
\addr_reg[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => sel0(0),
      I1 => sel0(1),
      I2 => sel0(3),
      I3 => sel0(4),
      I4 => sel0(2),
      O => addr_reg(4)
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(4),
      Q => drp_addr_0(4),
      R => rst_dclk_reset
    );
\di_reg[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => x16_reg2,
      O => p_1_in(11)
    );
\di_reg[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rst_dclk_reset,
      I1 => sel0(2),
      I2 => sel0(4),
      I3 => sel0(3),
      I4 => sel0(1),
      I5 => sel0(0),
      O => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(0),
      Q => drp_di_0(0),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(10),
      Q => drp_di_0(10),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_1_in(11),
      Q => drp_di_0(11),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(12),
      Q => drp_di_0(12),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(13),
      Q => drp_di_0(13),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(14),
      Q => drp_di_0(14),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(15),
      Q => drp_di_0(15),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(1),
      Q => drp_di_0(1),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(2),
      Q => drp_di_0(2),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(3),
      Q => drp_di_0(3),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(4),
      Q => drp_di_0(4),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(5),
      Q => drp_di_0(5),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(6),
      Q => drp_di_0(6),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(7),
      Q => drp_di_0(7),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(8),
      Q => drp_di_0(8),
      R => \di_reg[15]_i_1_n_0\
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(9),
      Q => drp_di_0(9),
      R => \di_reg[15]_i_1_n_0\
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => do_reg1(0),
      R => rst_dclk_reset
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(10),
      Q => do_reg1(10),
      R => rst_dclk_reset
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(11),
      Q => do_reg1(11),
      R => rst_dclk_reset
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(12),
      Q => do_reg1(12),
      R => rst_dclk_reset
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(13),
      Q => do_reg1(13),
      R => rst_dclk_reset
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(14),
      Q => do_reg1(14),
      R => rst_dclk_reset
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(15),
      Q => do_reg1(15),
      R => rst_dclk_reset
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => do_reg1(1),
      R => rst_dclk_reset
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => do_reg1(2),
      R => rst_dclk_reset
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => do_reg1(3),
      R => rst_dclk_reset
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => do_reg1(4),
      R => rst_dclk_reset
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => do_reg1(5),
      R => rst_dclk_reset
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(6),
      Q => do_reg1(6),
      R => rst_dclk_reset
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(7),
      Q => do_reg1(7),
      R => rst_dclk_reset
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(8),
      Q => do_reg1(8),
      R => rst_dclk_reset
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(9),
      Q => do_reg1(9),
      R => rst_dclk_reset
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => rst_dclk_reset
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => rst_dclk_reset
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => rst_dclk_reset
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => rst_dclk_reset
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => rst_dclk_reset
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => rst_dclk_reset
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => rst_dclk_reset
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => rst_dclk_reset
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => rst_dclk_reset
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => rst_dclk_reset
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => rst_dclk_reset
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => rst_dclk_reset
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => rst_dclk_reset
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => rst_dclk_reset
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => rst_dclk_reset
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => rst_dclk_reset
    );
done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FA000003"
    )
        port map (
      I0 => addr_reg(4),
      I1 => start_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[1]\,
      O => done0
    );
done_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => done0,
      Q => done_reg_0(0),
      S => rst_dclk_reset
    );
\fsm[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000557F5F7F"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => addr_reg(4),
      I5 => \fsm[0]_i_2_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FC050C05"
    )
        port map (
      I0 => start_reg2,
      I1 => load_cnt(0),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => rdy_reg2,
      I5 => \fsm_reg_n_0_[2]\,
      O => \fsm[0]_i_2_n_0\
    );
\fsm[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0333E020"
    )
        port map (
      I0 => load_cnt(0),
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => rdy_reg2,
      I4 => \fsm_reg_n_0_[1]\,
      O => fsm(1)
    );
\fsm[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40AA"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(0),
      Q => \fsm_reg_n_0_[0]\,
      R => rst_dclk_reset
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(1),
      Q => \fsm_reg_n_0_[1]\,
      R => rst_dclk_reset
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(2),
      Q => \fsm_reg_n_0_[2]\,
      R => rst_dclk_reset
    );
\gtp_channel.gtpe2_channel_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => drp_mux_en_0
    );
\gtp_channel.gtpe2_channel_i_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(9),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(9)
    );
\gtp_channel.gtpe2_channel_i_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(8),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(8)
    );
\gtp_channel.gtpe2_channel_i_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(7),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(7)
    );
\gtp_channel.gtpe2_channel_i_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(6),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(6)
    );
\gtp_channel.gtpe2_channel_i_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(5),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(5)
    );
\gtp_channel.gtpe2_channel_i_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(4),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(4)
    );
\gtp_channel.gtpe2_channel_i_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(3),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(3)
    );
\gtp_channel.gtpe2_channel_i_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(2),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(2)
    );
\gtp_channel.gtpe2_channel_i_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(1),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(1)
    );
\gtp_channel.gtpe2_channel_i_i_19\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(0),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(0)
    );
\gtp_channel.gtpe2_channel_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \fsm_reg[1]_0\
    );
\gtp_channel.gtpe2_channel_i_i_37__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_addr_0(4),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPADDR(0)
    );
\gtp_channel.gtpe2_channel_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(15),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(15)
    );
\gtp_channel.gtpe2_channel_i_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(14),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(14)
    );
\gtp_channel.gtpe2_channel_i_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(13),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(13)
    );
\gtp_channel.gtpe2_channel_i_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(12),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(12)
    );
\gtp_channel.gtpe2_channel_i_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(11),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(11)
    );
\gtp_channel.gtpe2_channel_i_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_0(10),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(10)
    );
\index[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => addr_reg(4),
      I3 => sel0(0),
      O => p_2_in(0)
    );
\index[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0600"
    )
        port map (
      I0 => sel0(1),
      I1 => sel0(0),
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[2]\,
      O => p_2_in(1)
    );
\index[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004040404000000"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => addr_reg(4),
      I3 => sel0(1),
      I4 => sel0(0),
      I5 => sel0(2),
      O => p_2_in(2)
    );
\index[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \index[4]_i_3_n_0\,
      I1 => sel0(2),
      I2 => sel0(0),
      I3 => sel0(1),
      I4 => sel0(3),
      O => p_2_in(3)
    );
\index[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C1"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      O => \index[4]_i_1_n_0\
    );
\index[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \index[4]_i_3_n_0\,
      I1 => sel0(3),
      I2 => sel0(1),
      I3 => sel0(0),
      I4 => sel0(2),
      I5 => sel0(4),
      O => p_2_in(4)
    );
\index[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => addr_reg(4),
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \index[4]_i_3_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => p_2_in(0),
      Q => sel0(0),
      R => rst_dclk_reset
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => p_2_in(1),
      Q => sel0(1),
      R => rst_dclk_reset
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => p_2_in(2),
      Q => sel0(2),
      R => rst_dclk_reset
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => p_2_in(3),
      Q => sel0(3),
      R => rst_dclk_reset
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => p_2_in(4),
      Q => sel0(4),
      R => rst_dclk_reset
    );
\load_cnt[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \load_cnt[0]_i_1__0_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1__0_n_0\,
      Q => load_cnt(0),
      R => rst_dclk_reset
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1_reg_0,
      Q => rdy_reg1,
      R => rst_dclk_reset
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => rst_dclk_reset
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DRP_START00_out,
      Q => start_reg1,
      R => rst_dclk_reset
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => rst_dclk_reset
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DRP_X160,
      Q => x16_reg1,
      R => rst_dclk_reset
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => rst_dclk_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp_32 is
  port (
    done_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \fsm_reg[1]_0\ : out STD_LOGIC;
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 0 to 0 );
    drp_mux_en_1 : out STD_LOGIC;
    rst_dclk_reset : in STD_LOGIC;
    DRP_START0 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rdy_reg1_reg_0 : in STD_LOGIC;
    DRP_X1602_out : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp_32 : entity is "xdma_0_pcie2_ip_gtp_pipe_drp";
end xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp_32;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp_32 is
  signal addr_reg : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \di_reg[15]_i_1__0_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal done0 : STD_LOGIC;
  signal drp_addr_9 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal drp_di_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \index[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__0_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \load_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 11 to 11 );
  signal p_2_in : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal sel0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  signal x16_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO";
  attribute async_reg of x16_reg1 : signal is "true";
  signal x16_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO";
  attribute async_reg of x16_reg2 : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_10__0\ : label is "soft_lutpair1875";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_11__0\ : label is "soft_lutpair1874";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_12__0\ : label is "soft_lutpair1874";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_13__0\ : label is "soft_lutpair1873";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_14__0\ : label is "soft_lutpair1873";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_15__0\ : label is "soft_lutpair1872";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_16__0\ : label is "soft_lutpair1872";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_17__0\ : label is "soft_lutpair1871";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_18__0\ : label is "soft_lutpair1871";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_19__0\ : label is "soft_lutpair1870";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_1__0\ : label is "soft_lutpair1879";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_20__0\ : label is "soft_lutpair1870";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_21__0\ : label is "soft_lutpair1869";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_2__0\ : label is "soft_lutpair1869";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_39\ : label is "soft_lutpair1877";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_6__0\ : label is "soft_lutpair1877";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_7__0\ : label is "soft_lutpair1876";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_8__0\ : label is "soft_lutpair1876";
  attribute SOFT_HLUTNM of \gtp_channel.gtpe2_channel_i_i_9__0\ : label is "soft_lutpair1875";
  attribute SOFT_HLUTNM of \index[0]_i_1__0\ : label is "soft_lutpair1878";
  attribute SOFT_HLUTNM of \index[1]_i_1__0\ : label is "soft_lutpair1879";
  attribute SOFT_HLUTNM of \index[4]_i_3__0\ : label is "soft_lutpair1878";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO";
begin
\addr_reg[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => sel0(0),
      I1 => sel0(1),
      I2 => sel0(3),
      I3 => sel0(2),
      I4 => sel0(4),
      O => addr_reg(4)
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(4),
      Q => drp_addr_9(4),
      R => rst_dclk_reset
    );
\di_reg[11]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => x16_reg2,
      O => p_1_in(11)
    );
\di_reg[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rst_dclk_reset,
      I1 => sel0(4),
      I2 => sel0(2),
      I3 => sel0(3),
      I4 => sel0(1),
      I5 => sel0(0),
      O => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(0),
      Q => drp_di_16(0),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(10),
      Q => drp_di_16(10),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => p_1_in(11),
      Q => drp_di_16(11),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(12),
      Q => drp_di_16(12),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(13),
      Q => drp_di_16(13),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(14),
      Q => drp_di_16(14),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(15),
      Q => drp_di_16(15),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(1),
      Q => drp_di_16(1),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(2),
      Q => drp_di_16(2),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(3),
      Q => drp_di_16(3),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(4),
      Q => drp_di_16(4),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(5),
      Q => drp_di_16(5),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(6),
      Q => drp_di_16(6),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(7),
      Q => drp_di_16(7),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(8),
      Q => drp_di_16(8),
      R => \di_reg[15]_i_1__0_n_0\
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => do_reg2(9),
      Q => drp_di_16(9),
      R => \di_reg[15]_i_1__0_n_0\
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => do_reg1(0),
      R => rst_dclk_reset
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(10),
      Q => do_reg1(10),
      R => rst_dclk_reset
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(11),
      Q => do_reg1(11),
      R => rst_dclk_reset
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(12),
      Q => do_reg1(12),
      R => rst_dclk_reset
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(13),
      Q => do_reg1(13),
      R => rst_dclk_reset
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(14),
      Q => do_reg1(14),
      R => rst_dclk_reset
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(15),
      Q => do_reg1(15),
      R => rst_dclk_reset
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => do_reg1(1),
      R => rst_dclk_reset
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => do_reg1(2),
      R => rst_dclk_reset
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => do_reg1(3),
      R => rst_dclk_reset
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => do_reg1(4),
      R => rst_dclk_reset
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => do_reg1(5),
      R => rst_dclk_reset
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(6),
      Q => do_reg1(6),
      R => rst_dclk_reset
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(7),
      Q => do_reg1(7),
      R => rst_dclk_reset
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(8),
      Q => do_reg1(8),
      R => rst_dclk_reset
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(9),
      Q => do_reg1(9),
      R => rst_dclk_reset
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => rst_dclk_reset
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => rst_dclk_reset
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => rst_dclk_reset
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => rst_dclk_reset
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => rst_dclk_reset
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => rst_dclk_reset
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => rst_dclk_reset
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => rst_dclk_reset
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => rst_dclk_reset
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => rst_dclk_reset
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => rst_dclk_reset
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => rst_dclk_reset
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => rst_dclk_reset
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => rst_dclk_reset
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => rst_dclk_reset
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => rst_dclk_reset
    );
\done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FA000003"
    )
        port map (
      I0 => addr_reg(4),
      I1 => start_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[1]\,
      O => done0
    );
done_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => done0,
      Q => done_reg_0(0),
      S => rst_dclk_reset
    );
\fsm[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000557F5F7F"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => addr_reg(4),
      I5 => \fsm[0]_i_2__0_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FC050C05"
    )
        port map (
      I0 => start_reg2,
      I1 => load_cnt(0),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => rdy_reg2,
      I5 => \fsm_reg_n_0_[2]\,
      O => \fsm[0]_i_2__0_n_0\
    );
\fsm[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0333E020"
    )
        port map (
      I0 => load_cnt(0),
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => rdy_reg2,
      I4 => \fsm_reg_n_0_[1]\,
      O => fsm(1)
    );
\fsm[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40AA"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(0),
      Q => \fsm_reg_n_0_[0]\,
      R => rst_dclk_reset
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(1),
      Q => \fsm_reg_n_0_[1]\,
      R => rst_dclk_reset
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(2),
      Q => \fsm_reg_n_0_[2]\,
      R => rst_dclk_reset
    );
\gtp_channel.gtpe2_channel_i_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(11),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(11)
    );
\gtp_channel.gtpe2_channel_i_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(10),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(10)
    );
\gtp_channel.gtpe2_channel_i_i_12__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(9),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(9)
    );
\gtp_channel.gtpe2_channel_i_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(8),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(8)
    );
\gtp_channel.gtpe2_channel_i_i_14__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(7),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(7)
    );
\gtp_channel.gtpe2_channel_i_i_15__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(6),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(6)
    );
\gtp_channel.gtpe2_channel_i_i_16__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(5),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(5)
    );
\gtp_channel.gtpe2_channel_i_i_17__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(4),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(4)
    );
\gtp_channel.gtpe2_channel_i_i_18__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(3),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(3)
    );
\gtp_channel.gtpe2_channel_i_i_19__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(2),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(2)
    );
\gtp_channel.gtpe2_channel_i_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => drp_mux_en_1
    );
\gtp_channel.gtpe2_channel_i_i_20__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(1),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(1)
    );
\gtp_channel.gtpe2_channel_i_i_21__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(0),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(0)
    );
\gtp_channel.gtpe2_channel_i_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \fsm_reg[1]_0\
    );
\gtp_channel.gtpe2_channel_i_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_addr_9(4),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPADDR(0)
    );
\gtp_channel.gtpe2_channel_i_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(15),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(15)
    );
\gtp_channel.gtpe2_channel_i_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(14),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(14)
    );
\gtp_channel.gtpe2_channel_i_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(13),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(13)
    );
\gtp_channel.gtpe2_channel_i_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => drp_di_16(12),
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[1]\,
      O => DRPDI(12)
    );
\index[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => addr_reg(4),
      I3 => sel0(0),
      O => p_2_in(0)
    );
\index[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0600"
    )
        port map (
      I0 => sel0(1),
      I1 => sel0(0),
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[2]\,
      O => p_2_in(1)
    );
\index[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004040404000000"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => addr_reg(4),
      I3 => sel0(1),
      I4 => sel0(0),
      I5 => sel0(2),
      O => p_2_in(2)
    );
\index[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => \index[4]_i_3__0_n_0\,
      I1 => sel0(2),
      I2 => sel0(0),
      I3 => sel0(1),
      I4 => sel0(3),
      O => p_2_in(3)
    );
\index[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C1"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      O => \index[4]_i_1__0_n_0\
    );
\index[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => \index[4]_i_3__0_n_0\,
      I1 => sel0(3),
      I2 => sel0(1),
      I3 => sel0(0),
      I4 => sel0(2),
      I5 => sel0(4),
      O => p_2_in(4)
    );
\index[4]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => addr_reg(4),
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \index[4]_i_3__0_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => p_2_in(0),
      Q => sel0(0),
      R => rst_dclk_reset
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => p_2_in(1),
      Q => sel0(1),
      R => rst_dclk_reset
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => p_2_in(2),
      Q => sel0(2),
      R => rst_dclk_reset
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => p_2_in(3),
      Q => sel0(3),
      R => rst_dclk_reset
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => p_2_in(4),
      Q => sel0(4),
      R => rst_dclk_reset
    );
\load_cnt[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \load_cnt[0]_i_1__1_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1__1_n_0\,
      Q => load_cnt(0),
      R => rst_dclk_reset
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1_reg_0,
      Q => rdy_reg1,
      R => rst_dclk_reset
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => rst_dclk_reset
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DRP_START0,
      Q => start_reg1,
      R => rst_dclk_reset
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => rst_dclk_reset
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => DRP_X1602_out,
      Q => x16_reg1,
      R => rst_dclk_reset
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => rst_dclk_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate is
  port (
    pclk_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRP_X160 : out STD_LOGIC;
    DRP_START00_out : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_cpllreset : in STD_LOGIC;
    drp_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txdata_wait_cnt_reg[0]_0\ : in STD_LOGIC;
    rxpmaresetdone_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_txratedone_0 : in STD_LOGIC;
    phystatus_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_0 : in STD_LOGIC;
    txsync_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_drp_x16 : in STD_LOGIC;
    rst_drp_start : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate : entity is "xdma_0_pcie2_ip_gtp_pipe_rate";
end xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate is
  signal \FSM_onehot_fsm[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[11]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal p_0_in1_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal pclk_sel : STD_LOGIC;
  signal pclk_sel_i_1_n_0 : STD_LOGIC;
  signal \^pclk_sel_reg_0\ : STD_LOGIC;
  signal phystatus_i_1_n_0 : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO";
  attribute async_reg of rate_in_reg1 : signal is "true";
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO";
  attribute async_reg of rate_in_reg2 : signal is "true";
  signal rate_out : STD_LOGIC;
  signal \rate_out[0]_i_1_n_0\ : STD_LOGIC;
  signal ratedone_i_1_n_0 : STD_LOGIC;
  signal ratedone_i_2_n_0 : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal rxratedone_i_1_n_0 : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO";
  attribute async_reg of rxratedone_reg1 : signal is "true";
  signal rxratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO";
  attribute async_reg of rxratedone_reg2 : signal is "true";
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txratedone_i_1_n_0 : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO";
  attribute async_reg of txratedone_reg1 : signal is "true";
  signal txratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO";
  attribute async_reg of txratedone_reg2 : signal is "true";
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_1\ : label is "soft_lutpair1836";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[8]_i_2\ : label is "soft_lutpair1834";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[10]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[11]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[12]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[9]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of start_reg1_i_1 : label is "soft_lutpair1837";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1\ : label is "soft_lutpair1835";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1\ : label is "soft_lutpair1835";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1\ : label is "soft_lutpair1834";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1\ : label is "soft_lutpair1836";
  attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of x16_reg1_i_1 : label is "soft_lutpair1837";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  RXRATE(0) <= \^rxrate\(0);
  pclk_sel_reg_0 <= \^pclk_sel_reg_0\;
\FSM_onehot_fsm[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => pclk_sel,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[0]_i_1__0_n_0\
    );
\FSM_onehot_fsm[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => p_3_in,
      I2 => p_2_in,
      O => \FSM_onehot_fsm[10]_i_1__0_n_0\
    );
\FSM_onehot_fsm[11]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => ratedone_reg_n_0,
      I1 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I2 => p_3_in,
      I3 => drp_done_reg2,
      O => \FSM_onehot_fsm[11]_i_1__0_n_0\
    );
\FSM_onehot_fsm[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => rate_out,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => rxpmaresetdone_reg2,
      O => \FSM_onehot_fsm[12]_i_1__0_n_0\
    );
\FSM_onehot_fsm[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => p_0_in1_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[1]_i_1__2_n_0\
    );
\FSM_onehot_fsm[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => drp_done_reg2,
      O => \FSM_onehot_fsm[2]_i_1__0_n_0\
    );
\FSM_onehot_fsm[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[3]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EBAAAAEBAAAAAAAA"
    )
        port map (
      I0 => \^q\(1),
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg1(0),
      I4 => rate_in_reg2(0),
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[4]_i_1__2_n_0\
    );
\FSM_onehot_fsm[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[5]_i_1__0_n_0\
    );
\FSM_onehot_fsm[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      O => \FSM_onehot_fsm[6]_i_1__0_n_0\
    );
\FSM_onehot_fsm[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I1 => ratedone_reg_n_0,
      I2 => \^q\(2),
      I3 => txsync_done_reg2,
      O => \FSM_onehot_fsm[7]_i_1__0_n_0\
    );
\FSM_onehot_fsm[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BEFFFFBEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[8]_i_2_n_0\,
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg1(0),
      I4 => rate_in_reg2(0),
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[8]_i_1_n_0\
    );
\FSM_onehot_fsm[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[8]_i_2_n_0\
    );
\FSM_onehot_fsm[9]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => drp_done_reg2,
      I3 => p_2_in,
      O => \FSM_onehot_fsm[9]_i_1__0_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[10]_i_1__0_n_0\,
      Q => p_3_in,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[11]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[12]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__2_n_0\,
      Q => p_0_in1_in,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__0_n_0\,
      Q => rate_out,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1_n_0\,
      Q => pclk_sel,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__2_n_0\,
      Q => \^q\(0),
      S => rst_cpllreset
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1__0_n_0\,
      Q => \^q\(1),
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[6]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1__0_n_0\,
      Q => \^q\(2),
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[9]_i_1__0_n_0\,
      Q => p_2_in,
      R => rst_cpllreset
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1_reg_0(0),
      Q => drp_done_reg1,
      R => rst_cpllreset
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => rst_cpllreset
    );
pclk_sel_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => pclk_sel,
      I3 => \^pclk_sel_reg_0\,
      O => pclk_sel_i_1_n_0
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => pclk_sel_i_1_n_0,
      Q => \^pclk_sel_reg_0\,
      R => rst_cpllreset
    );
phystatus_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => phystatus_reg_n_0,
      O => phystatus_i_1_n_0
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => phystatus_i_1_n_0,
      Q => phystatus_reg_n_0,
      R => rst_cpllreset
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1_reg_0(0),
      Q => phystatus_reg1,
      R => rst_cpllreset
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => rst_cpllreset
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => D(0),
      Q => rate_in_reg1(0),
      R => rst_cpllreset
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => rst_cpllreset
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => rst_cpllreset
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => rst_cpllreset
    );
\rate_out[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_out,
      I3 => \^rxrate\(0),
      O => \rate_out[0]_i_1_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \rate_out[0]_i_1_n_0\,
      Q => \^rxrate\(0),
      R => rst_cpllreset
    );
ratedone_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55554000"
    )
        port map (
      I0 => ratedone_i_2_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => rxratedone_reg_n_0,
      I4 => ratedone_reg_n_0,
      O => ratedone_i_1_n_0
    );
ratedone_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => p_3_in,
      I1 => p_2_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      O => ratedone_i_2_n_0
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => ratedone_i_1_n_0,
      Q => ratedone_reg_n_0,
      R => rst_cpllreset
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1_reg_0(0),
      Q => rxpmaresetdone_reg1,
      R => rst_cpllreset
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => rst_cpllreset
    );
rxratedone_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => rxratedone_reg_n_0,
      O => rxratedone_i_1_n_0
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxratedone_i_1_n_0,
      Q => rxratedone_reg_n_0,
      R => rst_cpllreset
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => gt_rxratedone_0,
      Q => rxratedone_reg1,
      R => rst_cpllreset
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => rst_cpllreset
    );
start_reg1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rst_drp_start,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => p_2_in,
      O => DRP_START00_out
    );
\txdata_wait_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(2),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0606060"
    )
        port map (
      I0 => txdata_wait_cnt_reg(0),
      I1 => txdata_wait_cnt_reg(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA006A00"
    )
        port map (
      I0 => txdata_wait_cnt_reg(2),
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(1),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(2),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => txdata_wait_cnt_reg(0),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => txdata_wait_cnt_reg(1),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => txdata_wait_cnt_reg(2),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => txdata_wait_cnt_reg(3),
      R => rst_cpllreset
    );
txratedone_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => txratedone_reg_n_0,
      O => txratedone_i_1_n_0
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txratedone_i_1_n_0,
      Q => txratedone_reg_n_0,
      R => rst_cpllreset
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => gt_txratedone_0,
      Q => txratedone_reg1,
      R => rst_cpllreset
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => rst_cpllreset
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1_reg_0(0),
      Q => txsync_done_reg1,
      R => rst_cpllreset
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => rst_cpllreset
    );
x16_reg1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rst_drp_x16,
      I1 => p_0_in1_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => DRP_X160
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate_33 is
  port (
    pclk_sel_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRP_X1602_out : out STD_LOGIC;
    DRP_START0 : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_cpllreset : in STD_LOGIC;
    drp_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txdata_wait_cnt_reg[0]_0\ : in STD_LOGIC;
    rxpmaresetdone_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_txratedone_1 : in STD_LOGIC;
    phystatus_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_1 : in STD_LOGIC;
    txsync_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_drp_x16 : in STD_LOGIC;
    rst_drp_start : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate_33 : entity is "xdma_0_pcie2_ip_gtp_pipe_rate";
end xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate_33;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate_33 is
  signal \FSM_onehot_fsm[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[11]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal p_0_in1_in : STD_LOGIC;
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_2_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal pclk_sel : STD_LOGIC;
  signal \pclk_sel_i_1__0_n_0\ : STD_LOGIC;
  signal \^pclk_sel_reg_0\ : STD_LOGIC;
  signal \phystatus_i_1__0_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO";
  attribute async_reg of rate_in_reg1 : signal is "true";
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO";
  attribute async_reg of rate_in_reg2 : signal is "true";
  signal rate_out : STD_LOGIC;
  signal \rate_out[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__0_n_0\ : STD_LOGIC;
  signal \ratedone_i_2__0_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal \rxratedone_i_1__0_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO";
  attribute async_reg of rxratedone_reg1 : signal is "true";
  signal rxratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO";
  attribute async_reg of rxratedone_reg2 : signal is "true";
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txratedone_i_1__0_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO";
  attribute async_reg of txratedone_reg1 : signal is "true";
  signal txratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO";
  attribute async_reg of txratedone_reg2 : signal is "true";
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_1__0\ : label is "soft_lutpair1882";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[8]_i_2__0\ : label is "soft_lutpair1880";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[10]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[11]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[12]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[9]\ : label is "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \start_reg1_i_1__0\ : label is "soft_lutpair1883";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__0\ : label is "soft_lutpair1881";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__0\ : label is "soft_lutpair1881";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__0\ : label is "soft_lutpair1880";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__0\ : label is "soft_lutpair1882";
  attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \x16_reg1_i_1__0\ : label is "soft_lutpair1883";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  RXRATE(0) <= \^rxrate\(0);
  pclk_sel_reg_0 <= \^pclk_sel_reg_0\;
\FSM_onehot_fsm[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => pclk_sel,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[0]_i_1__1_n_0\
    );
\FSM_onehot_fsm[10]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => p_3_in,
      I2 => p_2_in,
      O => \FSM_onehot_fsm[10]_i_1__1_n_0\
    );
\FSM_onehot_fsm[11]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => ratedone_reg_n_0,
      I1 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I2 => p_3_in,
      I3 => drp_done_reg2,
      O => \FSM_onehot_fsm[11]_i_1__1_n_0\
    );
\FSM_onehot_fsm[12]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => rate_out,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => rxpmaresetdone_reg2,
      O => \FSM_onehot_fsm[12]_i_1__1_n_0\
    );
\FSM_onehot_fsm[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => p_0_in1_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[1]_i_1__3_n_0\
    );
\FSM_onehot_fsm[2]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in1_in,
      I1 => drp_done_reg2,
      O => \FSM_onehot_fsm[2]_i_1__2_n_0\
    );
\FSM_onehot_fsm[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EBAAAAEBAAAAAAAA"
    )
        port map (
      I0 => \^q\(1),
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg1(0),
      I4 => rate_in_reg2(0),
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[4]_i_1__3_n_0\
    );
\FSM_onehot_fsm[5]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[5]_i_1__1_n_0\
    );
\FSM_onehot_fsm[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      O => \FSM_onehot_fsm[6]_i_1__1_n_0\
    );
\FSM_onehot_fsm[7]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I1 => ratedone_reg_n_0,
      I2 => \^q\(2),
      I3 => txsync_done_reg2,
      O => \FSM_onehot_fsm[7]_i_1__1_n_0\
    );
\FSM_onehot_fsm[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BEFFFFBEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[8]_i_2__0_n_0\,
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg1(0),
      I4 => rate_in_reg2(0),
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[8]_i_1__0_n_0\
    );
\FSM_onehot_fsm[8]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[8]_i_2__0_n_0\
    );
\FSM_onehot_fsm[9]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => drp_done_reg2,
      I3 => p_2_in,
      O => \FSM_onehot_fsm[9]_i_1__1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[10]_i_1__1_n_0\,
      Q => p_3_in,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[11]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[12]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__3_n_0\,
      Q => p_0_in1_in,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__2_n_0\,
      Q => rate_out,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__0_n_0\,
      Q => pclk_sel,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__3_n_0\,
      Q => \^q\(0),
      S => rst_cpllreset
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1__1_n_0\,
      Q => \^q\(1),
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[6]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1__1_n_0\,
      Q => \^q\(2),
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[9]_i_1__1_n_0\,
      Q => p_2_in,
      R => rst_cpllreset
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1_reg_0(0),
      Q => drp_done_reg1,
      R => rst_cpllreset
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => rst_cpllreset
    );
\pclk_sel_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => pclk_sel,
      I3 => \^pclk_sel_reg_0\,
      O => \pclk_sel_i_1__0_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \pclk_sel_i_1__0_n_0\,
      Q => \^pclk_sel_reg_0\,
      R => rst_cpllreset
    );
\phystatus_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => phystatus_reg_n_0,
      O => \phystatus_i_1__0_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \phystatus_i_1__0_n_0\,
      Q => phystatus_reg_n_0,
      R => rst_cpllreset
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1_reg_0(0),
      Q => phystatus_reg1,
      R => rst_cpllreset
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => rst_cpllreset
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => D(0),
      Q => rate_in_reg1(0),
      R => rst_cpllreset
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => rst_cpllreset
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => rst_cpllreset
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => rst_cpllreset
    );
\rate_out[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_out,
      I3 => \^rxrate\(0),
      O => \rate_out[0]_i_1__0_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \rate_out[0]_i_1__0_n_0\,
      Q => \^rxrate\(0),
      R => rst_cpllreset
    );
\ratedone_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55554000"
    )
        port map (
      I0 => \ratedone_i_2__0_n_0\,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => rxratedone_reg_n_0,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__0_n_0\
    );
\ratedone_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => p_3_in,
      I1 => p_2_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      O => \ratedone_i_2__0_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \ratedone_i_1__0_n_0\,
      Q => ratedone_reg_n_0,
      R => rst_cpllreset
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1_reg_0(0),
      Q => rxpmaresetdone_reg1,
      R => rst_cpllreset
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => rst_cpllreset
    );
\rxratedone_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__0_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \rxratedone_i_1__0_n_0\,
      Q => rxratedone_reg_n_0,
      R => rst_cpllreset
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => gt_rxratedone_1,
      Q => rxratedone_reg1,
      R => rst_cpllreset
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => rst_cpllreset
    );
\start_reg1_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rst_drp_start,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => p_2_in,
      O => DRP_START0
    );
\txdata_wait_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(2),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(1),
      O => \p_0_in__3\(0)
    );
\txdata_wait_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0606060"
    )
        port map (
      I0 => txdata_wait_cnt_reg(0),
      I1 => txdata_wait_cnt_reg(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__3\(1)
    );
\txdata_wait_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA006A00"
    )
        port map (
      I0 => txdata_wait_cnt_reg(2),
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__3\(2)
    );
\txdata_wait_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(1),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(2),
      O => \p_0_in__3\(3)
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(0),
      Q => txdata_wait_cnt_reg(0),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(1),
      Q => txdata_wait_cnt_reg(1),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(2),
      Q => txdata_wait_cnt_reg(2),
      R => rst_cpllreset
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(3),
      Q => txdata_wait_cnt_reg(3),
      R => rst_cpllreset
    );
\txratedone_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFCAAAAAAA8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[11]\,
      I3 => p_2_in,
      I4 => p_3_in,
      I5 => txratedone_reg_n_0,
      O => \txratedone_i_1__0_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => \txratedone_i_1__0_n_0\,
      Q => txratedone_reg_n_0,
      R => rst_cpllreset
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => gt_txratedone_1,
      Q => txratedone_reg1,
      R => rst_cpllreset
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => rst_cpllreset
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1_reg_0(0),
      Q => txsync_done_reg1,
      R => rst_cpllreset
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \txdata_wait_cnt_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => rst_cpllreset
    );
\x16_reg1_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rst_drp_x16,
      I1 => p_0_in1_in,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => DRP_X1602_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gtp_pipe_reset is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_drp_start : out STD_LOGIC;
    rst_drp_x16 : out STD_LOGIC;
    rst_cpllreset : out STD_LOGIC;
    rxusrclk_rst_reg2_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rst_dclk_reset : out STD_LOGIC;
    rst_gtreset : out STD_LOGIC;
    rst_userrdy : out STD_LOGIC;
    PLL0RESET0 : out STD_LOGIC;
    SYNC_TXSYNC_START : out STD_LOGIC;
    \FSM_onehot_fsm_reg[11]_0\ : out STD_LOGIC;
    \FSM_onehot_fsm_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC;
    \cfg_wait_cnt_reg[5]_0\ : in STD_LOGIC;
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    CLK : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    cpllrst : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txsync_start_reg1_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \drp_done_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rxpmaresetdone_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phystatus_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \txsync_done_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rxcdrlock_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gtp_pipe_reset : entity is "xdma_0_pcie2_ip_gtp_pipe_reset";
end xdma_0_xdma_0_pcie2_ip_gtp_pipe_reset;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gtp_pipe_reset is
  signal \FSM_onehot_fsm[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[10]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[11]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[9]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[9]_i_2_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_fsm_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_fsm_reg_n_0_[10]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[9]\ : STD_LOGIC;
  signal RST_DRP_START0 : STD_LOGIC;
  signal RST_DRP_X160 : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \cfg_wait_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal cfg_wait_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal dclk_rst_reg1 : STD_LOGIC;
  signal \dclk_rst_reg1__0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal gtreset_i_1_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in0_in : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal plllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of plllock_reg1 : signal is "NO";
  attribute async_reg of plllock_reg1 : signal is "true";
  signal plllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of plllock_reg2 : signal is "NO";
  attribute async_reg of plllock_reg2 : signal is "true";
  signal pllreset_i_1_n_0 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal resetdone_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of resetdone_reg1 : signal is "NO";
  attribute async_reg of resetdone_reg1 : signal is "true";
  signal resetdone_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of resetdone_reg2 : signal is "NO";
  attribute async_reg of resetdone_reg2 : signal is "true";
  signal \^rst_cpllreset\ : STD_LOGIC;
  signal \^rst_gtreset\ : STD_LOGIC;
  signal rst_txsync_start : STD_LOGIC;
  signal \^rst_userrdy\ : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxpmaresetdone_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal rxusrclk_rst_reg1 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  signal userrdy : STD_LOGIC;
  signal userrdy_i_1_n_0 : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[10]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[11]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[12]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[13]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[14]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[9]\ : label is "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of RST_DRP_START_i_1 : label is "soft_lutpair1820";
  attribute SOFT_HLUTNM of RST_DRP_X16_i_1 : label is "soft_lutpair1820";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[0]_i_1\ : label is "soft_lutpair1818";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[1]_i_1\ : label is "soft_lutpair1816";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[2]_i_1\ : label is "soft_lutpair1816";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[4]_i_1\ : label is "soft_lutpair1817";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[5]_i_1\ : label is "soft_lutpair1817";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[5]_i_2\ : label is "soft_lutpair1818";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of gtreset_i_1 : label is "soft_lutpair1819";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of plllock_reg1_reg : label is std.standard.true;
  attribute KEEP of plllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of plllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of plllock_reg2_reg : label is std.standard.true;
  attribute KEEP of plllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of plllock_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of pllreset_i_1 : label is "soft_lutpair1819";
  attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of txsync_start_reg1_i_1 : label is "soft_lutpair1821";
  attribute SOFT_HLUTNM of \txsync_start_reg1_i_1__0\ : label is "soft_lutpair1821";
begin
  \FSM_onehot_fsm_reg[1]_0\(0) <= \^fsm_onehot_fsm_reg[1]_0\(0);
  SR(0) <= \^sr\(0);
  rst_cpllreset <= \^rst_cpllreset\;
  rst_gtreset <= \^rst_gtreset\;
  rst_userrdy <= \^rst_userrdy\;
\FSM_onehot_fsm[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => \FSM_onehot_fsm[12]_i_2_n_0\,
      O => \FSM_onehot_fsm[0]_i_1_n_0\
    );
\FSM_onehot_fsm[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B2A"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[10]\,
      I1 => drp_done_reg2(1),
      I2 => drp_done_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[9]\,
      O => \FSM_onehot_fsm[10]_i_1_n_0\
    );
\FSM_onehot_fsm[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF88888"
    )
        port map (
      I0 => \FSM_onehot_fsm[13]_i_2_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => txsync_done_reg2(1),
      I3 => txsync_done_reg2(0),
      I4 => rst_txsync_start,
      O => \FSM_onehot_fsm[11]_i_1_n_0\
    );
\FSM_onehot_fsm[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF444444444"
    )
        port map (
      I0 => \FSM_onehot_fsm[12]_i_2_n_0\,
      I1 => dclk_rst_reg1,
      I2 => resetdone_reg2(0),
      I3 => resetdone_reg2(1),
      I4 => plllock_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[12]\,
      O => \FSM_onehot_fsm[12]_i_1_n_0\
    );
\FSM_onehot_fsm[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => cfg_wait_cnt_reg(4),
      I1 => cfg_wait_cnt_reg(3),
      I2 => cfg_wait_cnt_reg(5),
      I3 => cfg_wait_cnt_reg(0),
      I4 => cfg_wait_cnt_reg(1),
      I5 => cfg_wait_cnt_reg(2),
      O => \FSM_onehot_fsm[12]_i_2_n_0\
    );
\FSM_onehot_fsm[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => userrdy,
      I1 => mmcm_lock_reg2,
      I2 => \FSM_onehot_fsm[13]_i_2_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => \FSM_onehot_fsm[13]_i_1_n_0\
    );
\FSM_onehot_fsm[13]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => phystatus_reg2(1),
      I1 => resetdone_reg2(1),
      I2 => resetdone_reg2(0),
      I3 => phystatus_reg2(0),
      O => \FSM_onehot_fsm[13]_i_2_n_0\
    );
\FSM_onehot_fsm[14]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \out\,
      O => \^sr\(0)
    );
\FSM_onehot_fsm[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4444444"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => userrdy,
      I2 => drp_done_reg2(1),
      I3 => drp_done_reg2(0),
      I4 => \FSM_onehot_fsm_reg_n_0_[5]\,
      O => \FSM_onehot_fsm[14]_i_2_n_0\
    );
\FSM_onehot_fsm[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[1]_0\(0),
      I1 => txsync_done_reg2(1),
      I2 => txsync_done_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[1]_i_1__1_n_0\
    );
\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => rxpmaresetdone_reg2(1),
      I2 => rxpmaresetdone_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[2]_i_1_n_0\
    );
\FSM_onehot_fsm[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E8A8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I1 => rxpmaresetdone_reg2(1),
      I2 => rxpmaresetdone_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_1__1_n_0\
    );
\FSM_onehot_fsm[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E0E0E0FFE0E0E0E0"
    )
        port map (
      I0 => drp_done_reg2(1),
      I1 => drp_done_reg2(0),
      I2 => p_0_in0_in,
      I3 => rxpmaresetdone_reg2(1),
      I4 => rxpmaresetdone_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_1__1_n_0\
    );
\FSM_onehot_fsm[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B2A"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => drp_done_reg2(1),
      I2 => drp_done_reg2(0),
      I3 => p_0_in0_in,
      O => \FSM_onehot_fsm[5]_i_1_n_0\
    );
\FSM_onehot_fsm[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => plllock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[6]_i_1_n_0\
    );
\FSM_onehot_fsm[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3F02"
    )
        port map (
      I0 => rst_txsync_start,
      I1 => txsync_done_reg2(1),
      I2 => txsync_done_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[7]_i_1_n_0\
    );
\FSM_onehot_fsm[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80FF8080"
    )
        port map (
      I0 => drp_done_reg2(1),
      I1 => drp_done_reg2(0),
      I2 => \FSM_onehot_fsm_reg_n_0_[10]\,
      I3 => plllock_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[8]_i_1__1_n_0\
    );
\FSM_onehot_fsm[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100FFFF01000100"
    )
        port map (
      I0 => resetdone_reg2(0),
      I1 => resetdone_reg2(1),
      I2 => plllock_reg2,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I4 => \FSM_onehot_fsm[9]_i_2_n_0\,
      I5 => \FSM_onehot_fsm_reg_n_0_[9]\,
      O => \FSM_onehot_fsm[9]_i_1_n_0\
    );
\FSM_onehot_fsm[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => drp_done_reg2(1),
      I1 => drp_done_reg2(0),
      O => \FSM_onehot_fsm[9]_i_2_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1_n_0\,
      Q => dclk_rst_reg1,
      S => \^sr\(0)
    );
\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[10]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[10]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[11]_i_1_n_0\,
      Q => rst_txsync_start,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[12]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[13]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[13]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[14]_i_2_n_0\,
      Q => userrdy,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__1_n_0\,
      Q => \^fsm_onehot_fsm_reg[1]_0\(0),
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__1_n_0\,
      Q => p_0_in0_in,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[5]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[6]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[6]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[7]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => \^sr\(0)
    );
\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[9]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[9]\,
      R => \^sr\(0)
    );
RST_DRP_START_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in0_in,
      I1 => \FSM_onehot_fsm_reg_n_0_[9]\,
      O => RST_DRP_START0
    );
RST_DRP_START_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => RST_DRP_START0,
      Q => rst_drp_start,
      R => \^sr\(0)
    );
RST_DRP_X16_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[9]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[10]\,
      O => RST_DRP_X160
    );
RST_DRP_X16_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => RST_DRP_X160,
      Q => rst_drp_x16,
      R => \^sr\(0)
    );
\cfg_wait_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => \FSM_onehot_fsm[12]_i_2_n_0\,
      I2 => cfg_wait_cnt_reg(0),
      O => p_0_in(0)
    );
\cfg_wait_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"28AA"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => cfg_wait_cnt_reg(0),
      I2 => cfg_wait_cnt_reg(1),
      I3 => \FSM_onehot_fsm[12]_i_2_n_0\,
      O => p_0_in(1)
    );
\cfg_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2888AAAA"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => cfg_wait_cnt_reg(2),
      I2 => cfg_wait_cnt_reg(1),
      I3 => cfg_wait_cnt_reg(0),
      I4 => \FSM_onehot_fsm[12]_i_2_n_0\,
      O => p_0_in(2)
    );
\cfg_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28888888AAAAAAAA"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => cfg_wait_cnt_reg(3),
      I2 => cfg_wait_cnt_reg(0),
      I3 => cfg_wait_cnt_reg(1),
      I4 => cfg_wait_cnt_reg(2),
      I5 => \FSM_onehot_fsm[12]_i_2_n_0\,
      O => p_0_in(3)
    );
\cfg_wait_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA006A00"
    )
        port map (
      I0 => cfg_wait_cnt_reg(4),
      I1 => \cfg_wait_cnt[5]_i_2_n_0\,
      I2 => cfg_wait_cnt_reg(3),
      I3 => dclk_rst_reg1,
      I4 => cfg_wait_cnt_reg(5),
      O => p_0_in(4)
    );
\cfg_wait_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => dclk_rst_reg1,
      I1 => cfg_wait_cnt_reg(5),
      I2 => \cfg_wait_cnt[5]_i_2_n_0\,
      I3 => cfg_wait_cnt_reg(3),
      I4 => cfg_wait_cnt_reg(4),
      O => p_0_in(5)
    );
\cfg_wait_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => cfg_wait_cnt_reg(2),
      I1 => cfg_wait_cnt_reg(1),
      I2 => cfg_wait_cnt_reg(0),
      O => \cfg_wait_cnt[5]_i_2_n_0\
    );
\cfg_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(0),
      Q => cfg_wait_cnt_reg(0),
      R => \^sr\(0)
    );
\cfg_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(1),
      Q => cfg_wait_cnt_reg(1),
      R => \^sr\(0)
    );
\cfg_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(2),
      Q => cfg_wait_cnt_reg(2),
      R => \^sr\(0)
    );
\cfg_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(3),
      Q => cfg_wait_cnt_reg(3),
      R => \^sr\(0)
    );
\cfg_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(4),
      Q => cfg_wait_cnt_reg(4),
      R => \^sr\(0)
    );
\cfg_wait_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => p_0_in(5),
      Q => cfg_wait_cnt_reg(5),
      R => \^sr\(0)
    );
dclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => dclk_rst_reg1,
      Q => \dclk_rst_reg1__0\,
      R => '0'
    );
dclk_rst_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \dclk_rst_reg1__0\,
      Q => rst_dclk_reset,
      R => '0'
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \drp_done_reg1_reg[1]_0\(0),
      Q => drp_done_reg1(0),
      R => \^sr\(0)
    );
\drp_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \drp_done_reg1_reg[1]_0\(1),
      Q => drp_done_reg1(1),
      R => \^sr\(0)
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => drp_done_reg1(0),
      Q => drp_done_reg2(0),
      R => \^sr\(0)
    );
\drp_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => drp_done_reg1(1),
      Q => drp_done_reg2(1),
      R => \^sr\(0)
    );
\gtp_common.gtpe2_common_i_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rst_cpllreset\,
      I1 => cpllrst,
      O => PLL0RESET0
    );
gtreset_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I2 => \^rst_gtreset\,
      O => gtreset_i_1_n_0
    );
gtreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => gtreset_i_1_n_0,
      Q => \^rst_gtreset\,
      R => \^sr\(0)
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => \^sr\(0)
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => \^sr\(0)
    );
\phystatus_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \phystatus_reg1_reg[1]_0\(0),
      Q => phystatus_reg1(0),
      R => \^sr\(0)
    );
\phystatus_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \phystatus_reg1_reg[1]_0\(1),
      Q => phystatus_reg1(1),
      R => \^sr\(0)
    );
\phystatus_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => phystatus_reg1(0),
      Q => phystatus_reg2(0),
      R => \^sr\(0)
    );
\phystatus_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => phystatus_reg1(1),
      Q => phystatus_reg2(1),
      R => \^sr\(0)
    );
plllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => plllock_reg1,
      R => \^sr\(0)
    );
plllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => plllock_reg1,
      Q => plllock_reg2,
      R => \^sr\(0)
    );
pllreset_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^rst_cpllreset\,
      O => pllreset_i_1_n_0
    );
pllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => pllreset_i_1_n_0,
      Q => \^rst_cpllreset\,
      R => \^sr\(0)
    );
\rate_idle_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => Q(0),
      Q => rate_idle_reg1(0),
      R => \^sr\(0)
    );
\rate_idle_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => txsync_start_reg1_reg(0),
      Q => rate_idle_reg1(1),
      R => \^sr\(0)
    );
\rate_idle_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rate_idle_reg1(0),
      Q => rate_idle_reg2(0),
      R => \^sr\(0)
    );
\rate_idle_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rate_idle_reg1(1),
      Q => rate_idle_reg2(1),
      R => \^sr\(0)
    );
\resetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => D(0),
      Q => resetdone_reg1(0),
      R => \^sr\(0)
    );
\resetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => D(1),
      Q => resetdone_reg1(1),
      R => \^sr\(0)
    );
\resetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => resetdone_reg1(0),
      Q => resetdone_reg2(0),
      R => \^sr\(0)
    );
\resetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => resetdone_reg1(1),
      Q => resetdone_reg2(1),
      R => \^sr\(0)
    );
\rxcdrlock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \rxcdrlock_reg1_reg[1]_0\(0),
      Q => rxcdrlock_reg1(0),
      R => \^sr\(0)
    );
\rxcdrlock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \rxcdrlock_reg1_reg[1]_0\(1),
      Q => rxcdrlock_reg1(1),
      R => \^sr\(0)
    );
\rxcdrlock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rxcdrlock_reg1(0),
      Q => rxcdrlock_reg2(0),
      R => \^sr\(0)
    );
\rxcdrlock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rxcdrlock_reg1(1),
      Q => rxcdrlock_reg2(1),
      R => \^sr\(0)
    );
\rxpmaresetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \rxpmaresetdone_reg1_reg[1]_0\(0),
      Q => rxpmaresetdone_reg1(0),
      R => \^sr\(0)
    );
\rxpmaresetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \rxpmaresetdone_reg1_reg[1]_0\(1),
      Q => rxpmaresetdone_reg1(1),
      R => \^sr\(0)
    );
\rxpmaresetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1(0),
      Q => rxpmaresetdone_reg2(0),
      R => \^sr\(0)
    );
\rxpmaresetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1(1),
      Q => rxpmaresetdone_reg2(1),
      R => \^sr\(0)
    );
rxusrclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \^rst_cpllreset\,
      Q => rxusrclk_rst_reg1,
      R => '0'
    );
rxusrclk_rst_reg2_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => rxusrclk_rst_reg1,
      Q => rxusrclk_rst_reg2_reg_0(0),
      S => \^rst_cpllreset\
    );
\txsync_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \txsync_done_reg1_reg[1]_0\(0),
      Q => txsync_done_reg1(0),
      R => \^sr\(0)
    );
\txsync_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => \txsync_done_reg1_reg[1]_0\(1),
      Q => txsync_done_reg1(1),
      R => \^sr\(0)
    );
\txsync_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => txsync_done_reg1(0),
      Q => txsync_done_reg2(0),
      R => \^sr\(0)
    );
\txsync_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => txsync_done_reg1(1),
      Q => txsync_done_reg2(1),
      R => \^sr\(0)
    );
txsync_start_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rst_txsync_start,
      I1 => Q(1),
      O => SYNC_TXSYNC_START
    );
\txsync_start_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rst_txsync_start,
      I1 => txsync_start_reg1_reg(1),
      O => \FSM_onehot_fsm_reg[11]_0\
    );
userrdy_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => userrdy,
      I2 => \^rst_userrdy\,
      O => userrdy_i_1_n_0
    );
userrdy_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \cfg_wait_cnt_reg[5]_0\,
      CE => '1',
      D => userrdy_i_1_n_0,
      Q => \^rst_userrdy\,
      R => \^sr\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane is
  port (
    pipe_rx1_valid : out STD_LOGIC;
    pipe_rx1_chanisaligned : out STD_LOGIC;
    pipe_rx1_phy_status : out STD_LOGIC;
    pipe_rx1_elec_idle : out STD_LOGIC;
    pipe_rx1_polarity_gt : out STD_LOGIC;
    \pipe_stages_1.pipe_tx_compliance_q_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx1_elec_idle_gt : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_valid_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_valid_q_reg_0\ : in STD_LOGIC;
    pipe_rx1_chanisaligned_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : in STD_LOGIC;
    pipe_rx1_polarity : in STD_LOGIC;
    pipe_tx1_compliance : in STD_LOGIC;
    pipe_tx1_elec_idle : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane : entity is "xdma_0_pcie2_ip_pcie_pipe_lane";
end xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx1_chanisaligned_gt,
      Q => pipe_rx1_chanisaligned,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(0),
      Q => Q(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1),
      Q => Q(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\,
      Q => pipe_rx1_elec_idle,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\,
      Q => pipe_rx1_phy_status,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx1_polarity,
      Q => pipe_rx1_polarity_gt,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx1_valid_gt,
      Q => pipe_rx1_valid,
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(0),
      Q => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1),
      Q => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_tx1_compliance,
      Q => \pipe_stages_1.pipe_tx_compliance_q_reg_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(0),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(10),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(11),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(12),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(13),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(14),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(1),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(2),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(3),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(4),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(5),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(6),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(7),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(8),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(9),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_tx1_elec_idle,
      Q => pipe_tx1_elec_idle_gt,
      S => SR(0)
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(0),
      Q => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1),
      Q => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1),
      S => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane_14 is
  port (
    pipe_rx0_polarity_gt : out STD_LOGIC;
    TXCHARDISPMODE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx0_elec_idle_gt : out STD_LOGIC;
    pipe_rx0_valid : out STD_LOGIC;
    pipe_rx0_chanisaligned : out STD_LOGIC;
    pipe_rx0_phy_status : out STD_LOGIC;
    pipe_rx0_elec_idle : out STD_LOGIC;
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx0_polarity : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_valid_q_reg_0\ : in STD_LOGIC;
    pipe_tx0_compliance : in STD_LOGIC;
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_rx0_valid_gt : in STD_LOGIC;
    pipe_rx0_chanisaligned_gt : in STD_LOGIC;
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane_14 : entity is "xdma_0_pcie2_ip_pcie_pipe_lane";
end xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane_14;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane_14 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx0_chanisaligned_gt,
      Q => pipe_rx0_chanisaligned,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(0),
      Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1),
      Q => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(0),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(10),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(10),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(11),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(11),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(12),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(12),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(13),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(13),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(14),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(14),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(1),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(2),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(3),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(3),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(4),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(4),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(5),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(5),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(6),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(6),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(7),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(7),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(8),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(8),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(9),
      Q => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(9),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => gt_rxelecidle_q,
      Q => pipe_rx0_elec_idle,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => gt_rx_phy_status_q,
      Q => pipe_rx0_phy_status,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx0_polarity,
      Q => pipe_rx0_polarity_gt,
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_rx0_valid_gt,
      Q => pipe_rx0_valid,
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(0),
      Q => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1),
      Q => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_tx0_compliance,
      Q => TXCHARDISPMODE(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(0),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(10),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(10),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(11),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(11),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(12),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(12),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(13),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(13),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(14),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(14),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(1),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(2),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(3),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(3),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(4),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(4),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(5),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(5),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(6),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(6),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(7),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(7),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(8),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(8),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(9),
      Q => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(9),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => pipe_tx0_elec_idle,
      Q => pipe_tx0_elec_idle_gt,
      S => SR(0)
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(0),
      Q => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => \pipe_stages_1.pipe_rx_valid_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1),
      Q => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1),
      S => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_pipe_misc is
  port (
    pipe_tx_rcvr_det_gt : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_deemph_gt : out STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_rcvr_det : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_deemph_q_reg_0\ : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_pipe_misc : entity is "xdma_0_pcie2_ip_pcie_pipe_misc";
end xdma_0_xdma_0_pcie2_ip_pcie_pipe_misc;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_pipe_misc is
begin
\pipe_stages_1.pipe_tx_deemph_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => pipe_tx_deemph,
      Q => pipe_tx_deemph_gt,
      S => SR(0)
    );
\pipe_stages_1.pipe_tx_margin_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(0),
      Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_margin_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(1),
      Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(1),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_margin_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(2),
      Q => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_rate_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => pipe_tx_rate,
      Q => D(0),
      R => SR(0)
    );
\pipe_stages_1.pipe_tx_rcvr_det_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => \pipe_stages_1.pipe_tx_deemph_q_reg_0\,
      CE => '1',
      D => pipe_tx_rcvr_det,
      Q => pipe_tx_rcvr_det_gt,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_clock is
  port (
    pclk_sel_reg_0 : out STD_LOGIC;
    CLK : out STD_LOGIC;
    mmcm_i_0 : out STD_LOGIC;
    SYNC_MMCM_LOCK : out STD_LOGIC;
    mmcm_i_1 : out STD_LOGIC;
    mmcm_lock_reg1_reg : in STD_LOGIC;
    \pclk_sel_reg1_reg[1]_0\ : in STD_LOGIC;
    \pclk_sel_reg1_reg[0]_0\ : in STD_LOGIC;
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_clock : entity is "xdma_0_pcie2_ip_pipe_clock";
end xdma_0_xdma_0_pcie2_ip_pipe_clock;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_clock is
  signal S00 : STD_LOGIC;
  signal \^sync_mmcm_lock\ : STD_LOGIC;
  signal clk_125mhz : STD_LOGIC;
  signal clk_250mhz : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_fb : STD_LOGIC;
  signal pclk_sel : STD_LOGIC;
  signal \pclk_sel_i_1__1_n_0\ : STD_LOGIC;
  signal pclk_sel_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal \^pclk_sel_reg_0\ : STD_LOGIC;
  signal pclk_sel_slave_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_slave_reg1 : signal is "NO";
  attribute async_reg of pclk_sel_slave_reg1 : signal is "true";
  signal pclk_sel_slave_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_slave_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_slave_reg2 : signal is "true";
  signal refclk : STD_LOGIC;
  signal userclk1 : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT0B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT1B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT2B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT4_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT6_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_PSDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute box_type : string;
  attribute box_type of \dclk_i_bufg.dclk_i\ : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute box_type of mmcm_i : label is "PRIMITIVE";
  attribute box_type of \pclk_i1_bufgctrl.pclk_i1\ : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean of \pclk_sel_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg2_reg[1]\ : label is "NO";
  attribute box_type of \txoutclk_i.txoutclk_i\ : label is "PRIMITIVE";
  attribute box_type of \userclk1_i1.usrclk1_i1\ : label is "PRIMITIVE";
begin
  SYNC_MMCM_LOCK <= \^sync_mmcm_lock\;
  pclk_sel_reg_0 <= \^pclk_sel_reg_0\;
\dclk_i_bufg.dclk_i\: unisim.vcomponents.BUFG
     port map (
      I => clk_125mhz,
      O => CLK
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => '0'
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => '0'
    );
mmcm_i: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT_F => 10.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 10.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 8.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => false,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 8,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 8,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 20,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => mmcm_fb,
      CLKFBOUT => mmcm_fb,
      CLKFBOUTB => NLW_mmcm_i_CLKFBOUTB_UNCONNECTED,
      CLKFBSTOPPED => NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED,
      CLKIN1 => refclk,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED,
      CLKOUT0 => clk_125mhz,
      CLKOUT0B => NLW_mmcm_i_CLKOUT0B_UNCONNECTED,
      CLKOUT1 => clk_250mhz,
      CLKOUT1B => NLW_mmcm_i_CLKOUT1B_UNCONNECTED,
      CLKOUT2 => userclk1,
      CLKOUT2B => NLW_mmcm_i_CLKOUT2B_UNCONNECTED,
      CLKOUT3 => NLW_mmcm_i_CLKOUT3_UNCONNECTED,
      CLKOUT3B => NLW_mmcm_i_CLKOUT3B_UNCONNECTED,
      CLKOUT4 => NLW_mmcm_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_mmcm_i_CLKOUT5_UNCONNECTED,
      CLKOUT6 => NLW_mmcm_i_CLKOUT6_UNCONNECTED,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => NLW_mmcm_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_mmcm_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => \^sync_mmcm_lock\,
      PSCLK => '0',
      PSDONE => NLW_mmcm_i_PSDONE_UNCONNECTED,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => '0'
    );
\pclk_i1_bufgctrl.pclk_i1\: unisim.vcomponents.BUFGCTRL
    generic map(
      CE_TYPE_CE0 => "SYNC",
      CE_TYPE_CE1 => "SYNC",
      INIT_OUT => 0,
      IS_CE0_INVERTED => '0',
      IS_CE1_INVERTED => '0',
      IS_I0_INVERTED => '0',
      IS_I1_INVERTED => '0',
      IS_IGNORE0_INVERTED => '0',
      IS_IGNORE1_INVERTED => '0',
      IS_S0_INVERTED => '0',
      IS_S1_INVERTED => '0',
      PRESELECT_I0 => false,
      PRESELECT_I1 => false,
      SIM_DEVICE => "7SERIES",
      STARTUP_SYNC => "FALSE"
    )
        port map (
      CE0 => '1',
      CE1 => '1',
      I0 => clk_125mhz,
      I1 => clk_250mhz,
      IGNORE0 => '0',
      IGNORE1 => '0',
      O => \^pclk_sel_reg_0\,
      S0 => S00,
      S1 => pclk_sel
    );
\pclk_i1_bufgctrl.pclk_i1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pclk_sel,
      O => S00
    );
\pclk_sel_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => pclk_sel_reg2(1),
      I1 => pclk_sel_reg2(0),
      I2 => pclk_sel,
      O => \pclk_sel_i_1__1_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => \pclk_sel_i_1__1_n_0\,
      Q => pclk_sel,
      R => '0'
    );
\pclk_sel_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => \pclk_sel_reg1_reg[0]_0\,
      Q => pclk_sel_reg1(0),
      R => '0'
    );
\pclk_sel_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => \pclk_sel_reg1_reg[1]_0\,
      Q => pclk_sel_reg1(1),
      R => '0'
    );
\pclk_sel_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_reg1(0),
      Q => pclk_sel_reg2(0),
      R => '0'
    );
\pclk_sel_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_reg1(1),
      Q => pclk_sel_reg2(1),
      R => '0'
    );
\pclk_sel_slave_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => int_pclk_sel_slave(0),
      Q => pclk_sel_slave_reg1(0),
      R => '0'
    );
\pclk_sel_slave_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => int_pclk_sel_slave(1),
      Q => pclk_sel_slave_reg1(1),
      R => '0'
    );
\pclk_sel_slave_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_slave_reg1(0),
      Q => pclk_sel_slave_reg2(0),
      R => '0'
    );
\pclk_sel_slave_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_slave_reg1(1),
      Q => pclk_sel_slave_reg2(1),
      R => '0'
    );
reg_clock_locked_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^sync_mmcm_lock\,
      O => mmcm_i_1
    );
\txoutclk_i.txoutclk_i\: unisim.vcomponents.BUFG
     port map (
      I => mmcm_lock_reg1_reg,
      O => refclk
    );
\userclk1_i1.usrclk1_i1\: unisim.vcomponents.BUFG
     port map (
      I => userclk1,
      O => mmcm_i_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_sync is
  port (
    p_1_in : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    p_1_in0_in : out STD_LOGIC;
    txphinitdone_reg3_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sync_txdlyen_0 : out STD_LOGIC;
    \txsync_fsm.txsync_done_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    \txsync_fsm.txsync_done_reg_1\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ : in STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    rxphaligndone_s_reg2_reg_0 : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    SYNC_MMCM_LOCK : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_TXSYNCDONE : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC;
    SYNC_RXSYNCDONE : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_sync : entity is "xdma_0_pcie2_ip_pipe_sync";
end xdma_0_xdma_0_pcie2_ip_pipe_sync;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_sync is
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg1 : signal is "true";
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg2 : signal is "true";
  signal rxelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO";
  attribute async_reg of rxelecidle_reg1 : signal is "true";
  signal rxelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO";
  attribute async_reg of rxelecidle_reg2 : signal is "true";
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg1 : signal is "true";
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg2 : signal is "true";
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg1 : signal is "true";
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg2 : signal is "true";
  signal rxsync_donem_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO";
  attribute async_reg of rxsync_donem_reg1 : signal is "true";
  signal rxsync_donem_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO";
  attribute async_reg of rxsync_donem_reg2 : signal is "true";
  signal rxsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO";
  attribute async_reg of rxsync_start_reg1 : signal is "true";
  signal rxsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO";
  attribute async_reg of rxsync_start_reg2 : signal is "true";
  signal rxsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO";
  attribute async_reg of rxsyncdone_reg1 : signal is "true";
  signal rxsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO";
  attribute async_reg of rxsyncdone_reg2 : signal is "true";
  signal \^sync_txdlyen_0\ : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg1 : signal is "true";
  signal txdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg2 : signal is "true";
  signal txdlysresetdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg3 : signal is "true";
  signal txphaligndone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO";
  attribute async_reg of txphaligndone_reg1 : signal is "true";
  signal txphaligndone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO";
  attribute async_reg of txphaligndone_reg2 : signal is "true";
  signal txphaligndone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO";
  attribute async_reg of txphaligndone_reg3 : signal is "true";
  signal txphinitdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO";
  attribute async_reg of txphinitdone_reg1 : signal is "true";
  signal txphinitdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO";
  attribute async_reg of txphinitdone_reg2 : signal is "true";
  signal txphinitdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO";
  attribute async_reg of txphinitdone_reg3 : signal is "true";
  signal \txsync_fsm.txdlyen_i_1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txsync_done_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal txsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO";
  attribute async_reg of txsync_start_reg1 : signal is "true";
  signal txsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO";
  attribute async_reg of txsync_start_reg2 : signal is "true";
  signal txsync_start_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO";
  attribute async_reg of txsync_start_reg3 : signal is "true";
  signal txsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO";
  attribute async_reg of txsyncdone_reg1 : signal is "true";
  signal txsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO";
  attribute async_reg of txsyncdone_reg2 : signal is "true";
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO";
  attribute async_reg of txsyncdone_reg3 : signal is "true";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \out\ <= txphaligndone_reg3;
  p_1_in <= txphaligndone_reg2;
  p_1_in0_in <= txphinitdone_reg2;
  sync_txdlyen_0 <= \^sync_txdlyen_0\;
  txphinitdone_reg3_reg_0 <= txphinitdone_reg3;
  \txsync_fsm.txsync_done_reg_0\(0) <= \^txsync_fsm.txsync_done_reg_0\(0);
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1D1DFF1D"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I2 => txsync_start_reg2,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I4 => \txsync_fsm.txsync_done_reg_1\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(1),
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I3 => txsync_start_reg2,
      O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD0D0D0"
    )
        port map (
      I0 => txdlysresetdone_reg2,
      I1 => txdlysresetdone_reg3,
      I2 => \^q\(0),
      I3 => mmcm_lock_reg2,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44F44444"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I1 => \^q\(1),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(0),
      O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF8F888888888"
    )
        port map (
      I0 => \txsync_fsm.txsync_done_reg_1\,
      I1 => \^q\(2),
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\,
      I3 => txphinitdone_reg3,
      I4 => txphinitdone_reg2,
      I5 => \^q\(1),
      O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAFFEAEA2A002A2A"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\,
      I3 => txphaligndone_reg3,
      I4 => txphaligndone_reg2,
      I5 => \^q\(2),
      O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\,
      Q => \^q\(0),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\,
      Q => \^q\(1),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\,
      Q => \^q\(2),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      R => rst_cpllreset
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => rst_cpllreset
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rst_cpllreset
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => rst_cpllreset
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => rst_cpllreset
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => rst_cpllreset
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => rst_cpllreset
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => rst_cpllreset
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rst_cpllreset
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE,
      Q => rxdlysresetdone_reg1,
      R => rst_cpllreset
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => rst_cpllreset
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => rst_cpllreset
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => rst_cpllreset
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_M,
      Q => rxphaligndone_m_reg1,
      R => rst_cpllreset
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => rst_cpllreset
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_S,
      Q => rxphaligndone_s_reg1,
      R => rst_cpllreset
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => rst_cpllreset
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => rxsync_donem_reg1,
      R => rst_cpllreset
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => rst_cpllreset
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => rxsync_start_reg1,
      R => rst_cpllreset
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => rst_cpllreset
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_RXSYNCDONE,
      Q => rxsyncdone_reg1,
      R => rst_cpllreset
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => rst_cpllreset
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE,
      Q => txdlysresetdone_reg1,
      R => rst_cpllreset
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => rst_cpllreset
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => rst_cpllreset
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => rst_cpllreset
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => rst_cpllreset
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => rst_cpllreset
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => rst_cpllreset
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => rst_cpllreset
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => rst_cpllreset
    );
\txsync_fsm.txdlyen_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABAAA8AA"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I2 => txsync_start_reg2,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I4 => \^sync_txdlyen_0\,
      O => \txsync_fsm.txdlyen_i_1_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1_n_0\,
      Q => \^sync_txdlyen_0\,
      R => rst_cpllreset
    );
\txsync_fsm.txsync_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222F222222202222"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I1 => \txsync_fsm.txsync_done_reg_1\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I3 => txsync_start_reg2,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I5 => \^txsync_fsm.txsync_done_reg_0\(0),
      O => \txsync_fsm.txsync_done_i_1_n_0\
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1_n_0\,
      Q => \^txsync_fsm.txsync_done_reg_0\(0),
      R => rst_cpllreset
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => rst_cpllreset
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => rst_cpllreset
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => rst_cpllreset
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => SYNC_TXSYNCDONE,
      Q => txsyncdone_reg1,
      R => rst_cpllreset
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => rst_cpllreset
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_0,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_sync_35 is
  port (
    p_1_in0_in : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txsync_done_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ : in STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    rxsyncdone_reg2_reg_0 : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    QRST_MMCM_LOCK : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_TXSYNCDONE : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC;
    SYNC_RXSYNCDONE : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_sync_35 : entity is "xdma_0_pcie2_ip_pipe_sync";
end xdma_0_xdma_0_pcie2_ip_pipe_sync_35;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_sync_35 is
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg1 : signal is "true";
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg2 : signal is "true";
  signal rxelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO";
  attribute async_reg of rxelecidle_reg1 : signal is "true";
  signal rxelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO";
  attribute async_reg of rxelecidle_reg2 : signal is "true";
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg1 : signal is "true";
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg2 : signal is "true";
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg1 : signal is "true";
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg2 : signal is "true";
  signal rxsync_donem_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO";
  attribute async_reg of rxsync_donem_reg1 : signal is "true";
  signal rxsync_donem_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO";
  attribute async_reg of rxsync_donem_reg2 : signal is "true";
  signal rxsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO";
  attribute async_reg of rxsync_start_reg1 : signal is "true";
  signal rxsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO";
  attribute async_reg of rxsync_start_reg2 : signal is "true";
  signal rxsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO";
  attribute async_reg of rxsyncdone_reg1 : signal is "true";
  signal rxsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO";
  attribute async_reg of rxsyncdone_reg2 : signal is "true";
  signal txdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg1 : signal is "true";
  signal txdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg2 : signal is "true";
  signal txdlysresetdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg3 : signal is "true";
  signal txphaligndone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO";
  attribute async_reg of txphaligndone_reg1 : signal is "true";
  signal txphaligndone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO";
  attribute async_reg of txphaligndone_reg2 : signal is "true";
  signal txphaligndone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO";
  attribute async_reg of txphaligndone_reg3 : signal is "true";
  signal txphinitdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO";
  attribute async_reg of txphinitdone_reg1 : signal is "true";
  signal txphinitdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO";
  attribute async_reg of txphinitdone_reg2 : signal is "true";
  signal txphinitdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO";
  attribute async_reg of txphinitdone_reg3 : signal is "true";
  signal \txsync_fsm.txsync_done_i_1__0_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txsync_done_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal txsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO";
  attribute async_reg of txsync_start_reg1 : signal is "true";
  signal txsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO";
  attribute async_reg of txsync_start_reg2 : signal is "true";
  signal txsync_start_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO";
  attribute async_reg of txsync_start_reg3 : signal is "true";
  signal txsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO";
  attribute async_reg of txsyncdone_reg1 : signal is "true";
  signal txsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO";
  attribute async_reg of txsyncdone_reg2 : signal is "true";
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO";
  attribute async_reg of txsyncdone_reg3 : signal is "true";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \out\ <= txphinitdone_reg3;
  p_1_in0_in <= txphinitdone_reg2;
  \txsync_fsm.txsync_done_reg_0\(0) <= \^txsync_fsm.txsync_done_reg_0\(0);
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I2 => txsync_start_reg2,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I3 => txsync_start_reg2,
      O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD0D0D0"
    )
        port map (
      I0 => txdlysresetdone_reg2,
      I1 => txdlysresetdone_reg3,
      I2 => \^q\(0),
      I3 => mmcm_lock_reg2,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44F44444"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I1 => \^q\(1),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(0),
      O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF450045004500"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => \^q\(2),
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I5 => \^q\(1),
      O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA080808"
    )
        port map (
      I0 => \^q\(2),
      I1 => txphaligndone_reg2,
      I2 => txphaligndone_reg3,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\,
      Q => \^q\(0),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\,
      Q => \^q\(1),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\,
      Q => \^q\(2),
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\,
      Q => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      R => rst_cpllreset
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => rst_cpllreset
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rst_cpllreset
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => QRST_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => rst_cpllreset
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => rst_cpllreset
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => rst_cpllreset
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => rst_cpllreset
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => rst_cpllreset
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rst_cpllreset
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE,
      Q => rxdlysresetdone_reg1,
      R => rst_cpllreset
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => rst_cpllreset
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => rst_cpllreset
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => rst_cpllreset
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_M,
      Q => rxphaligndone_m_reg1,
      R => rst_cpllreset
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => rst_cpllreset
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_S,
      Q => rxphaligndone_s_reg1,
      R => rst_cpllreset
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => rst_cpllreset
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => rxsync_donem_reg1,
      R => rst_cpllreset
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => rst_cpllreset
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => '0',
      Q => rxsync_start_reg1,
      R => rst_cpllreset
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => rst_cpllreset
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_RXSYNCDONE,
      Q => rxsyncdone_reg1,
      R => rst_cpllreset
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => rst_cpllreset
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE,
      Q => txdlysresetdone_reg1,
      R => rst_cpllreset
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => rst_cpllreset
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => rst_cpllreset
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => rst_cpllreset
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => rst_cpllreset
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => rst_cpllreset
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => rst_cpllreset
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => rst_cpllreset
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => rst_cpllreset
    );
\txsync_fsm.txsync_done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABAAA8AA"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6]\,
      I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\,
      I2 => txsync_start_reg2,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1]\,
      I4 => \^txsync_fsm.txsync_done_reg_0\(0),
      O => \txsync_fsm.txsync_done_i_1__0_n_0\
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__0_n_0\,
      Q => \^txsync_fsm.txsync_done_reg_0\(0),
      R => rst_cpllreset
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => rst_cpllreset
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => rst_cpllreset
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => rst_cpllreset
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => SYNC_TXSYNCDONE,
      Q => txsyncdone_reg1,
      R => rst_cpllreset
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => rst_cpllreset
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxsyncdone_reg2_reg_0,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_user is
  port (
    \out\ : out STD_LOGIC;
    txcompliance_reg2_reg_0 : out STD_LOGIC;
    rst_idle_reg2_reg_0 : out STD_LOGIC;
    user_oobclk_0 : out STD_LOGIC;
    user_rxbufreset_0 : out STD_LOGIC;
    user_rxpcsreset_0 : out STD_LOGIC;
    user_eyescanreset_0 : out STD_LOGIC;
    user_rxcdrfreqreset_0 : out STD_LOGIC;
    user_rxcdrreset_0 : out STD_LOGIC;
    user_rxpmareset_0 : out STD_LOGIC;
    rate_idle_reg2_reg_0 : out STD_LOGIC;
    user_resetovrd_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : out STD_LOGIC;
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    txcompliance_reg2_reg_1 : out STD_LOGIC;
    txcompliance_reg2_reg_2 : out STD_LOGIC;
    txelecidle_reg2_reg_0 : out STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    pclk_sel_reg1_reg_0 : in STD_LOGIC;
    \rxvalid_cnt_reg[3]_0\ : in STD_LOGIC;
    gt_rxresetdone_0 : in STD_LOGIC;
    gt_txresetdone_0 : in STD_LOGIC;
    pipe_tx0_elec_idle_gt : in STD_LOGIC;
    TXCHARDISPMODE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_0 : in STD_LOGIC;
    RXSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_idle_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    eq_rxeq_adapt_done_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg : in STD_LOGIC;
    gt_rx_phy_status_q_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    p_1_in0_in : in STD_LOGIC;
    \txsync_fsm.txsync_done_reg\ : in STD_LOGIC;
    p_1_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_user : entity is "xdma_0_pcie2_ip_pipe_user";
end xdma_0_xdma_0_pcie2_ip_pipe_user;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_user is
  signal \FSM_onehot_resetovrd.fsm[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal gt_rxvalid_q_i_5_n_0 : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1_n_0\ : STD_LOGIC;
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal rate_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO";
  attribute async_reg of rate_done_reg1 : signal is "true";
  signal rate_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO";
  attribute async_reg of rate_done_reg2 : signal is "true";
  signal rate_gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO";
  attribute async_reg of rate_gen3_reg1 : signal is "true";
  signal rate_gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO";
  attribute async_reg of rate_gen3_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rate_rxsync_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO";
  attribute async_reg of rate_rxsync_reg1 : signal is "true";
  signal rate_rxsync_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO";
  attribute async_reg of rate_rxsync_reg2 : signal is "true";
  signal reset_cnt0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \resetovrd.reset[0]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[1]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[2]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[3]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[4]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[5]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[6]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[7]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[7]_i_2_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[7]_i_1_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \resetovrd.reset_reg_n_0_[7]\ : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO";
  attribute async_reg of resetovrd_start_reg1 : signal is "true";
  signal resetovrd_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO";
  attribute async_reg of resetovrd_start_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg1 : signal is "true";
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg2 : signal is "true";
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxstatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO";
  attribute async_reg of rxstatus_reg1 : signal is "true";
  signal rxstatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO";
  attribute async_reg of rxstatus_reg2 : signal is "true";
  signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO";
  attribute async_reg of rxvalid_reg1 : signal is "true";
  signal rxvalid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO";
  attribute async_reg of rxvalid_reg2 : signal is "true";
  signal txcompliance_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO";
  attribute async_reg of txcompliance_reg1 : signal is "true";
  signal txcompliance_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO";
  attribute async_reg of txcompliance_reg2 : signal is "true";
  signal txelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO";
  attribute async_reg of txelecidle_reg1 : signal is "true";
  signal txelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO";
  attribute async_reg of txelecidle_reg2 : signal is "true";
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal \^user_eyescanreset_0\ : STD_LOGIC;
  signal \^user_rxbufreset_0\ : STD_LOGIC;
  signal \^user_rxcdrfreqreset_0\ : STD_LOGIC;
  signal \^user_rxcdrreset_0\ : STD_LOGIC;
  signal user_rxdfelpmreset_0 : STD_LOGIC;
  signal \^user_rxpcsreset_0\ : STD_LOGIC;
  signal \^user_rxpmareset_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[1]_i_2\ : label is "soft_lutpair1861";
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[2]_i_2\ : label is "soft_lutpair1860";
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[3]_i_2\ : label is "soft_lutpair1859";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[0]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[1]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[2]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[3]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair1867";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair1867";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \resetovrd.reset[1]_i_1\ : label is "soft_lutpair1866";
  attribute SOFT_HLUTNM of \resetovrd.reset[2]_i_1\ : label is "soft_lutpair1866";
  attribute SOFT_HLUTNM of \resetovrd.reset[3]_i_1\ : label is "soft_lutpair1865";
  attribute SOFT_HLUTNM of \resetovrd.reset[4]_i_1\ : label is "soft_lutpair1865";
  attribute SOFT_HLUTNM of \resetovrd.reset[5]_i_1\ : label is "soft_lutpair1861";
  attribute SOFT_HLUTNM of \resetovrd.reset[6]_i_1\ : label is "soft_lutpair1864";
  attribute SOFT_HLUTNM of \resetovrd.reset[7]_i_2\ : label is "soft_lutpair1864";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[0]_i_1\ : label is "soft_lutpair1863";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[1]_i_1\ : label is "soft_lutpair1863";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[2]_i_1\ : label is "soft_lutpair1862";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[3]_i_1\ : label is "soft_lutpair1862";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[4]_i_1\ : label is "soft_lutpair1860";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[7]_i_2\ : label is "soft_lutpair1859";
  attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
begin
  \out\ <= txelecidle_reg2;
  rst_idle_reg2_reg_0 <= rst_idle_reg2;
  txcompliance_reg2_reg_0 <= txcompliance_reg2;
  user_eyescanreset_0 <= \^user_eyescanreset_0\;
  user_rxbufreset_0 <= \^user_rxbufreset_0\;
  user_rxcdrfreqreset_0 <= \^user_rxcdrfreqreset_0\;
  user_rxcdrreset_0 <= \^user_rxcdrreset_0\;
  user_rxpcsreset_0 <= \^user_rxpcsreset_0\;
  user_rxpmareset_0 <= \^user_rxpmareset_0\;
\FSM_onehot_resetovrd.fsm[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_eyescanreset_0\,
      I2 => \^user_rxpcsreset_0\,
      I3 => \^user_rxpmareset_0\,
      I4 => \FSM_onehot_resetovrd.fsm[0]_i_2_n_0\,
      I5 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      O => \FSM_onehot_resetovrd.fsm[0]_i_1_n_0\
    );
\FSM_onehot_resetovrd.fsm[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \^user_rxbufreset_0\,
      I1 => \^user_rxcdrfreqreset_0\,
      I2 => \resetovrd.reset_reg_n_0_[7]\,
      I3 => rxresetdone_reg2,
      I4 => \^user_rxcdrreset_0\,
      I5 => user_rxdfelpmreset_0,
      O => \FSM_onehot_resetovrd.fsm[0]_i_2_n_0\
    );
\FSM_onehot_resetovrd.fsm[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => resetovrd_start_reg2,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_resetovrd.fsm[1]_i_2_n_0\,
      I3 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      O => \FSM_onehot_resetovrd.fsm[1]_i_1_n_0\
    );
\FSM_onehot_resetovrd.fsm[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^user_eyescanreset_0\,
      I1 => \^user_rxpcsreset_0\,
      I2 => \^user_rxpmareset_0\,
      I3 => \FSM_onehot_resetovrd.fsm[0]_i_2_n_0\,
      O => \FSM_onehot_resetovrd.fsm[1]_i_2_n_0\
    );
\FSM_onehot_resetovrd.fsm[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I1 => \resetovrd.reset_cnt_reg\(5),
      I2 => \resetovrd.reset_cnt_reg\(4),
      I3 => \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\,
      I4 => \resetovrd.reset_cnt_reg\(6),
      I5 => \resetovrd.reset_cnt_reg\(7),
      O => \FSM_onehot_resetovrd.fsm[2]_i_1_n_0\
    );
\FSM_onehot_resetovrd.fsm[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(3),
      I1 => \resetovrd.reset_cnt_reg\(0),
      I2 => \resetovrd.reset_cnt_reg\(1),
      I3 => \resetovrd.reset_cnt_reg\(2),
      O => \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\
    );
\FSM_onehot_resetovrd.fsm[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I2 => resetovrd_start_reg2,
      I3 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      O => \FSM_onehot_resetovrd.fsm[3]_i_1_n_0\
    );
\FSM_onehot_resetovrd.fsm[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(7),
      I1 => \resetovrd.reset_cnt_reg\(6),
      I2 => \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\,
      I3 => \resetovrd.reset_cnt_reg\(4),
      I4 => \resetovrd.reset_cnt_reg\(5),
      O => \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\
    );
\FSM_onehot_resetovrd.fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[0]_i_1_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[2]_i_1_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[3]_i_1_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\,
      I3 => p_1_in0_in,
      O => txcompliance_reg2_reg_1
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \txsync_fsm.txsync_done_reg\,
      I3 => p_1_in,
      O => txcompliance_reg2_reg_2
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => txelecidle_reg2_reg_0
    );
\gt_rx_phy_status_q_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => gt_rx_phy_status_q_reg(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
gt_rxvalid_q_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFBFFFFFFFBFFF"
    )
        port map (
      I0 => gt_rxvalid_q_i_5_n_0,
      I1 => gt_rxvalid_0,
      I2 => rate_idle_reg2,
      I3 => rst_idle_reg2,
      I4 => gt_rx_elec_idle_wire_filter(0),
      I5 => gt_rxvalid_q_reg,
      O => rate_idle_reg2_reg_0
    );
gt_rxvalid_q_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(0),
      I2 => rxvalid_cnt_reg(1),
      I3 => rxvalid_cnt_reg(2),
      O => gt_rxvalid_q_i_5_n_0
    );
\gtp_channel.gtpe2_channel_i_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      O => user_resetovrd_0
    );
\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => rst_cpllreset
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => rst_cpllreset
    );
\oobclk_div.oobclk_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \oobclk_div.oobclk_i_1_n_0\,
      Q => user_oobclk_0,
      R => rst_cpllreset
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pclk_sel_reg1_reg_0,
      Q => pclk_sel_reg1,
      R => rst_cpllreset
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => rst_cpllreset
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => Q(1),
      Q => rate_done_reg1,
      R => SR(0)
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => SR(0)
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => rate_gen3_reg1,
      R => SR(0)
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => SR(0)
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => Q(0),
      Q => rate_idle_reg1,
      R => SR(0)
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => SR(0)
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => rate_rxsync_reg1,
      R => SR(0)
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => SR(0)
    );
\resetdone_reg1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxresetdone_reg2,
      I1 => txresetdone_reg2,
      O => D(0)
    );
\resetovrd.reset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FB00F0"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I3 => rst_cpllreset,
      I4 => \^user_rxpmareset_0\,
      O => \resetovrd.reset[0]_i_1_n_0\
    );
\resetovrd.reset[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxpmareset_0\,
      O => \resetovrd.reset[1]_i_1_n_0\
    );
\resetovrd.reset[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxcdrreset_0\,
      O => \resetovrd.reset[2]_i_1_n_0\
    );
\resetovrd.reset[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxcdrfreqreset_0\,
      O => \resetovrd.reset[3]_i_1_n_0\
    );
\resetovrd.reset[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => user_rxdfelpmreset_0,
      O => \resetovrd.reset[4]_i_1_n_0\
    );
\resetovrd.reset[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_eyescanreset_0\,
      O => \resetovrd.reset[5]_i_1_n_0\
    );
\resetovrd.reset[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxpcsreset_0\,
      O => \resetovrd.reset[6]_i_1_n_0\
    );
\resetovrd.reset[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I3 => rst_cpllreset,
      O => \resetovrd.reset[7]_i_1_n_0\
    );
\resetovrd.reset[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxbufreset_0\,
      O => \resetovrd.reset[7]_i_2_n_0\
    );
\resetovrd.reset_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      O => reset_cnt0(0)
    );
\resetovrd.reset_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      I1 => \resetovrd.reset_cnt_reg\(1),
      O => \resetovrd.reset_cnt[1]_i_1_n_0\
    );
\resetovrd.reset_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      I1 => \resetovrd.reset_cnt_reg\(1),
      I2 => \resetovrd.reset_cnt_reg\(2),
      O => reset_cnt0(2)
    );
\resetovrd.reset_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(2),
      I1 => \resetovrd.reset_cnt_reg\(1),
      I2 => \resetovrd.reset_cnt_reg\(0),
      I3 => \resetovrd.reset_cnt_reg\(3),
      O => reset_cnt0(3)
    );
\resetovrd.reset_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(4),
      I1 => \resetovrd.reset_cnt_reg\(2),
      I2 => \resetovrd.reset_cnt_reg\(1),
      I3 => \resetovrd.reset_cnt_reg\(0),
      I4 => \resetovrd.reset_cnt_reg\(3),
      O => \resetovrd.reset_cnt[4]_i_1_n_0\
    );
\resetovrd.reset_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(5),
      I1 => \resetovrd.reset_cnt_reg\(3),
      I2 => \resetovrd.reset_cnt_reg\(0),
      I3 => \resetovrd.reset_cnt_reg\(1),
      I4 => \resetovrd.reset_cnt_reg\(2),
      I5 => \resetovrd.reset_cnt_reg\(4),
      O => reset_cnt0(5)
    );
\resetovrd.reset_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(6),
      I1 => \resetovrd.reset_cnt_reg\(5),
      I2 => \resetovrd.reset_cnt_reg\(4),
      I3 => \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\,
      O => reset_cnt0(6)
    );
\resetovrd.reset_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1FF"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I2 => rst_cpllreset,
      I3 => \FSM_onehot_resetovrd.fsm[3]_i_2_n_0\,
      O => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(7),
      I1 => \resetovrd.reset_cnt_reg\(6),
      I2 => \FSM_onehot_resetovrd.fsm[2]_i_2_n_0\,
      I3 => \resetovrd.reset_cnt_reg\(4),
      I4 => \resetovrd.reset_cnt_reg\(5),
      O => reset_cnt0(7)
    );
\resetovrd.reset_cnt_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(0),
      Q => \resetovrd.reset_cnt_reg\(0),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset_cnt[1]_i_1_n_0\,
      Q => \resetovrd.reset_cnt_reg\(1),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(2),
      Q => \resetovrd.reset_cnt_reg\(2),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(3),
      Q => \resetovrd.reset_cnt_reg\(3),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset_cnt[4]_i_1_n_0\,
      Q => \resetovrd.reset_cnt_reg\(4),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(5),
      Q => \resetovrd.reset_cnt_reg\(5),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(6),
      Q => \resetovrd.reset_cnt_reg\(6),
      S => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => reset_cnt0(7),
      Q => \resetovrd.reset_cnt_reg\(7),
      R => \resetovrd.reset_cnt[7]_i_1_n_0\
    );
\resetovrd.reset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset[0]_i_1_n_0\,
      Q => \^user_rxpmareset_0\,
      R => '0'
    );
\resetovrd.reset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[1]_i_1_n_0\,
      Q => \^user_rxcdrreset_0\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[2]_i_1_n_0\,
      Q => \^user_rxcdrfreqreset_0\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[3]_i_1_n_0\,
      Q => user_rxdfelpmreset_0,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[4]_i_1_n_0\,
      Q => \^user_eyescanreset_0\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[5]_i_1_n_0\,
      Q => \^user_rxpcsreset_0\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[6]_i_1_n_0\,
      Q => \^user_rxbufreset_0\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1_n_0\,
      D => \resetovrd.reset[7]_i_2_n_0\,
      Q => \resetovrd.reset_reg_n_0_[7]\,
      R => rst_cpllreset
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => resetovrd_start_reg1,
      R => rst_cpllreset
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => rst_cpllreset
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rst_idle_reg1_reg_0(0),
      Q => rst_idle_reg1,
      R => SR(0)
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => SR(0)
    );
\rxcdrlock_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(0),
      I3 => rxcdrlock_cnt_reg(1),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__1\(0)
    );
\rxcdrlock_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(0),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(2),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__1\(1)
    );
\rxcdrlock_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BCCC0000"
    )
        port map (
      I0 => rxcdrlock_cnt_reg(3),
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_reg2,
      O => \p_0_in__1\(2)
    );
\rxcdrlock_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__1\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => rxcdrlock_cnt_reg(0),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => rxcdrlock_cnt_reg(1),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__1\(2),
      Q => rxcdrlock_cnt_reg(2),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => rxcdrlock_cnt_reg(3),
      R => rst_cpllreset
    );
\rxcdrlock_reg1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => gt_rxcdrlock_0,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(2),
      O => SYNC_RXCDRLOCK
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxcdrlock_0,
      Q => rxcdrlock_reg1,
      R => rst_cpllreset
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rst_cpllreset
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => eq_rxeq_adapt_done_0,
      Q => rxeq_adapt_done_reg1,
      R => rst_cpllreset
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => rst_cpllreset
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxresetdone_0,
      Q => rxresetdone_reg1,
      R => rst_cpllreset
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => rst_cpllreset
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => RXSTATUS(0),
      Q => rxstatus_reg1,
      R => SR(0)
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => SR(0)
    );
\rxvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(2),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__2\(0)
    );
\rxvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => rxvalid_cnt_reg(0),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(2),
      I3 => rxvalid_cnt_reg(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__2\(1)
    );
\rxvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(0),
      I3 => rxvalid_cnt_reg(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__2\(2)
    );
\rxvalid_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => rxvalid_cnt_reg(3),
      I2 => rxvalid_cnt_reg(0),
      I3 => rxvalid_cnt_reg(1),
      I4 => rxvalid_cnt_reg(2),
      I5 => rxvalid_reg2,
      O => \p_0_in__2\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => rxvalid_cnt_reg(0),
      R => SR(0)
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => rxvalid_cnt_reg(1),
      R => SR(0)
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => rxvalid_cnt_reg(2),
      R => SR(0)
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => rxvalid_cnt_reg(3),
      R => SR(0)
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxvalid_0,
      Q => rxvalid_reg1,
      R => SR(0)
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => SR(0)
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => TXCHARDISPMODE(0),
      Q => txcompliance_reg1,
      R => rst_cpllreset
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => rst_cpllreset
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pipe_tx0_elec_idle_gt,
      Q => txelecidle_reg1,
      R => rst_cpllreset
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => rst_cpllreset
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_txresetdone_0,
      Q => txresetdone_reg1,
      R => rst_cpllreset
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_user_36 is
  port (
    \out\ : out STD_LOGIC;
    txcompliance_reg2_reg_0 : out STD_LOGIC;
    user_oobclk_1 : out STD_LOGIC;
    user_rxbufreset_1 : out STD_LOGIC;
    user_rxpcsreset_1 : out STD_LOGIC;
    user_eyescanreset_1 : out STD_LOGIC;
    user_rxcdrfreqreset_1 : out STD_LOGIC;
    user_rxcdrreset_1 : out STD_LOGIC;
    user_rxpmareset_1 : out STD_LOGIC;
    rate_idle_reg2_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : out STD_LOGIC;
    user_resetovrd_1 : out STD_LOGIC;
    rst_idle_reg2_reg_0 : out STD_LOGIC;
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_TXPHINITDONE : out STD_LOGIC;
    rxsyncallin : out STD_LOGIC;
    SYNC_TXPHALIGNDONE : out STD_LOGIC;
    txcompliance_reg2_reg_1 : out STD_LOGIC;
    txelecidle_reg2_reg_0 : out STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    pclk_sel_reg1_reg_0 : in STD_LOGIC;
    \rxvalid_cnt_reg[3]_0\ : in STD_LOGIC;
    gt_rxresetdone_1 : in STD_LOGIC;
    gt_txresetdone_1 : in STD_LOGIC;
    pipe_tx1_elec_idle_gt : in STD_LOGIC;
    txcompliance_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_1 : in STD_LOGIC;
    RXSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_idle_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    eq_rxeq_adapt_done_1 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg : in STD_LOGIC;
    reg_clock_locked : in STD_LOGIC;
    phy_rdy_n_int_reg : in STD_LOGIC;
    gt_rx_phy_status_q_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    txphinitdone_reg1_reg : in STD_LOGIC;
    txphinitdone_reg1_reg_0 : in STD_LOGIC;
    txphinitdone_reg1_reg_1 : in STD_LOGIC;
    txphinitdone_reg1_reg_2 : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    txphaligndone_reg1_reg : in STD_LOGIC;
    txphaligndone_reg1_reg_0 : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    p_1_in0_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_user_36 : entity is "xdma_0_pcie2_ip_pipe_user";
end xdma_0_xdma_0_pcie2_ip_pipe_user_36;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_user_36 is
  signal \FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__0_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__0_n_0\ : STD_LOGIC;
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal rate_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO";
  attribute async_reg of rate_done_reg1 : signal is "true";
  signal rate_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO";
  attribute async_reg of rate_done_reg2 : signal is "true";
  signal rate_gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO";
  attribute async_reg of rate_gen3_reg1 : signal is "true";
  signal rate_gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO";
  attribute async_reg of rate_gen3_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rate_rxsync_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO";
  attribute async_reg of rate_rxsync_reg1 : signal is "true";
  signal rate_rxsync_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO";
  attribute async_reg of rate_rxsync_reg2 : signal is "true";
  signal \reset_cnt0__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \resetovrd.reset[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \resetovrd.reset_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \resetovrd.reset_reg_n_0_[7]\ : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO";
  attribute async_reg of resetovrd_start_reg1 : signal is "true";
  signal resetovrd_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO";
  attribute async_reg of resetovrd_start_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg1 : signal is "true";
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg2 : signal is "true";
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxstatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO";
  attribute async_reg of rxstatus_reg1 : signal is "true";
  signal rxstatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO";
  attribute async_reg of rxstatus_reg2 : signal is "true";
  signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO";
  attribute async_reg of rxvalid_reg1 : signal is "true";
  signal rxvalid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO";
  attribute async_reg of rxvalid_reg2 : signal is "true";
  signal txcompliance_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO";
  attribute async_reg of txcompliance_reg1 : signal is "true";
  signal txcompliance_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO";
  attribute async_reg of txcompliance_reg2 : signal is "true";
  signal txelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO";
  attribute async_reg of txelecidle_reg1 : signal is "true";
  signal txelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO";
  attribute async_reg of txelecidle_reg2 : signal is "true";
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal \^user_eyescanreset_1\ : STD_LOGIC;
  signal \^user_rxbufreset_1\ : STD_LOGIC;
  signal \^user_rxcdrfreqreset_1\ : STD_LOGIC;
  signal \^user_rxcdrreset_1\ : STD_LOGIC;
  signal user_rxdfelpmreset_1 : STD_LOGIC;
  signal \^user_rxpcsreset_1\ : STD_LOGIC;
  signal \^user_rxpmareset_1\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[1]_i_2__0\ : label is "soft_lutpair1899";
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[2]_i_2__0\ : label is "soft_lutpair1898";
  attribute SOFT_HLUTNM of \FSM_onehot_resetovrd.fsm[3]_i_2__0\ : label is "soft_lutpair1897";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[0]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[1]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[2]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_resetovrd.fsm_reg[3]\ : label is "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair1905";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair1905";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \resetovrd.reset[1]_i_1__0\ : label is "soft_lutpair1904";
  attribute SOFT_HLUTNM of \resetovrd.reset[2]_i_1__0\ : label is "soft_lutpair1904";
  attribute SOFT_HLUTNM of \resetovrd.reset[3]_i_1__0\ : label is "soft_lutpair1903";
  attribute SOFT_HLUTNM of \resetovrd.reset[4]_i_1__0\ : label is "soft_lutpair1903";
  attribute SOFT_HLUTNM of \resetovrd.reset[5]_i_1__0\ : label is "soft_lutpair1899";
  attribute SOFT_HLUTNM of \resetovrd.reset[6]_i_1__0\ : label is "soft_lutpair1902";
  attribute SOFT_HLUTNM of \resetovrd.reset[7]_i_2__0\ : label is "soft_lutpair1902";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[0]_i_1__0\ : label is "soft_lutpair1901";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[1]_i_1__0\ : label is "soft_lutpair1901";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[2]_i_1__0\ : label is "soft_lutpair1900";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[3]_i_1__0\ : label is "soft_lutpair1900";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[4]_i_1__0\ : label is "soft_lutpair1898";
  attribute SOFT_HLUTNM of \resetovrd.reset_cnt[7]_i_2__0\ : label is "soft_lutpair1897";
  attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
begin
  \out\ <= txelecidle_reg2;
  txcompliance_reg2_reg_0 <= txcompliance_reg2;
  user_eyescanreset_1 <= \^user_eyescanreset_1\;
  user_rxbufreset_1 <= \^user_rxbufreset_1\;
  user_rxcdrfreqreset_1 <= \^user_rxcdrfreqreset_1\;
  user_rxcdrreset_1 <= \^user_rxcdrreset_1\;
  user_rxpcsreset_1 <= \^user_rxpcsreset_1\;
  user_rxpmareset_1 <= \^user_rxpmareset_1\;
\FSM_onehot_resetovrd.fsm[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_eyescanreset_1\,
      I2 => \^user_rxpcsreset_1\,
      I3 => \^user_rxpmareset_1\,
      I4 => \FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0\,
      I5 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      O => \FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \^user_rxbufreset_1\,
      I1 => \^user_rxcdrfreqreset_1\,
      I2 => \resetovrd.reset_reg_n_0_[7]\,
      I3 => rxresetdone_reg2,
      I4 => \^user_rxcdrreset_1\,
      I5 => user_rxdfelpmreset_1,
      O => \FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => resetovrd_start_reg2,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0\,
      I3 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      O => \FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[1]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^user_eyescanreset_1\,
      I1 => \^user_rxpcsreset_1\,
      I2 => \^user_rxpmareset_1\,
      I3 => \FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0\,
      O => \FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I1 => \resetovrd.reset_cnt_reg\(5),
      I2 => \resetovrd.reset_cnt_reg\(4),
      I3 => \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\,
      I4 => \resetovrd.reset_cnt_reg\(6),
      I5 => \resetovrd.reset_cnt_reg\(7),
      O => \FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(3),
      I1 => \resetovrd.reset_cnt_reg\(0),
      I2 => \resetovrd.reset_cnt_reg\(1),
      I3 => \resetovrd.reset_cnt_reg\(2),
      O => \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I2 => resetovrd_start_reg2,
      I3 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      O => \FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0\
    );
\FSM_onehot_resetovrd.fsm[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(7),
      I1 => \resetovrd.reset_cnt_reg\(6),
      I2 => \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\,
      I3 => \resetovrd.reset_cnt_reg\(4),
      I4 => \resetovrd.reset_cnt_reg\(5),
      O => \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\
    );
\FSM_onehot_resetovrd.fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_resetovrd.fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0\,
      Q => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => txelecidle_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\,
      I3 => p_1_in0_in,
      O => txcompliance_reg2_reg_1
    );
gt_rx_phy_status_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => gt_rx_phy_status_q_reg(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFBFFFFFFFBFFF"
    )
        port map (
      I0 => \gt_rxvalid_q_i_5__0_n_0\,
      I1 => gt_rxvalid_1,
      I2 => rate_idle_reg2,
      I3 => rst_idle_reg2,
      I4 => gt_rx_elec_idle_wire_filter(0),
      I5 => gt_rxvalid_q_reg,
      O => rate_idle_reg2_reg_0
    );
\gt_rxvalid_q_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(0),
      I2 => rxvalid_cnt_reg(1),
      I3 => rxvalid_cnt_reg(2),
      O => \gt_rxvalid_q_i_5__0_n_0\
    );
\gtp_channel.gtpe2_channel_i_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[1]\,
      O => user_resetovrd_1
    );
\gtp_channel.gtpe2_channel_i_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => SYNC_RXPHALIGNDONE_S,
      I3 => txphinitdone_reg1_reg_0,
      I4 => txphinitdone_reg1_reg_1,
      I5 => SYNC_RXPHALIGNDONE_M,
      O => rxsyncallin
    );
\gtp_channel.gtpe2_channel_i_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => txphaligndone_reg1_reg,
      I3 => txphinitdone_reg1_reg_0,
      I4 => txphinitdone_reg1_reg_1,
      I5 => txphaligndone_reg1_reg_0,
      O => SYNC_TXPHALIGNDONE
    );
\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => rst_cpllreset
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => rst_cpllreset
    );
\oobclk_div.oobclk_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__0_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__0_n_0\,
      Q => user_oobclk_1,
      R => rst_cpllreset
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pclk_sel_reg1_reg_0,
      Q => pclk_sel_reg1,
      R => rst_cpllreset
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => rst_cpllreset
    );
phy_rdy_n_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => reg_clock_locked,
      I2 => phy_rdy_n_int_reg,
      O => rst_idle_reg2_reg_0
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => Q(1),
      Q => rate_done_reg1,
      R => SR(0)
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => SR(0)
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => rate_gen3_reg1,
      R => SR(0)
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => SR(0)
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => Q(0),
      Q => rate_idle_reg1,
      R => SR(0)
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => SR(0)
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => rate_rxsync_reg1,
      R => SR(0)
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => SR(0)
    );
\resetdone_reg1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxresetdone_reg2,
      I1 => txresetdone_reg2,
      O => D(0)
    );
\resetovrd.reset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FB00F0"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I3 => rst_cpllreset,
      I4 => \^user_rxpmareset_1\,
      O => \resetovrd.reset[0]_i_1__0_n_0\
    );
\resetovrd.reset[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxpmareset_1\,
      O => \resetovrd.reset[1]_i_1__0_n_0\
    );
\resetovrd.reset[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxcdrreset_1\,
      O => \resetovrd.reset[2]_i_1__0_n_0\
    );
\resetovrd.reset[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxcdrfreqreset_1\,
      O => \resetovrd.reset[3]_i_1__0_n_0\
    );
\resetovrd.reset[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => user_rxdfelpmreset_1,
      O => \resetovrd.reset[4]_i_1__0_n_0\
    );
\resetovrd.reset[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_eyescanreset_1\,
      O => \resetovrd.reset[5]_i_1__0_n_0\
    );
\resetovrd.reset[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxpcsreset_1\,
      O => \resetovrd.reset[6]_i_1__0_n_0\
    );
\resetovrd.reset[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF4"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I3 => rst_cpllreset,
      O => \resetovrd.reset[7]_i_1__0_n_0\
    );
\resetovrd.reset[7]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[2]\,
      I1 => \^user_rxbufreset_1\,
      O => \resetovrd.reset[7]_i_2__0_n_0\
    );
\resetovrd.reset_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      O => \reset_cnt0__0\(0)
    );
\resetovrd.reset_cnt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      I1 => \resetovrd.reset_cnt_reg\(1),
      O => \resetovrd.reset_cnt[1]_i_1__0_n_0\
    );
\resetovrd.reset_cnt[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(0),
      I1 => \resetovrd.reset_cnt_reg\(1),
      I2 => \resetovrd.reset_cnt_reg\(2),
      O => \reset_cnt0__0\(2)
    );
\resetovrd.reset_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(2),
      I1 => \resetovrd.reset_cnt_reg\(1),
      I2 => \resetovrd.reset_cnt_reg\(0),
      I3 => \resetovrd.reset_cnt_reg\(3),
      O => \reset_cnt0__0\(3)
    );
\resetovrd.reset_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(4),
      I1 => \resetovrd.reset_cnt_reg\(2),
      I2 => \resetovrd.reset_cnt_reg\(1),
      I3 => \resetovrd.reset_cnt_reg\(0),
      I4 => \resetovrd.reset_cnt_reg\(3),
      O => \resetovrd.reset_cnt[4]_i_1__0_n_0\
    );
\resetovrd.reset_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(5),
      I1 => \resetovrd.reset_cnt_reg\(3),
      I2 => \resetovrd.reset_cnt_reg\(0),
      I3 => \resetovrd.reset_cnt_reg\(1),
      I4 => \resetovrd.reset_cnt_reg\(2),
      I5 => \resetovrd.reset_cnt_reg\(4),
      O => \reset_cnt0__0\(5)
    );
\resetovrd.reset_cnt[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(6),
      I1 => \resetovrd.reset_cnt_reg\(5),
      I2 => \resetovrd.reset_cnt_reg\(4),
      I3 => \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\,
      O => \reset_cnt0__0\(6)
    );
\resetovrd.reset_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F1FF"
    )
        port map (
      I0 => \FSM_onehot_resetovrd.fsm_reg_n_0_[0]\,
      I1 => \FSM_onehot_resetovrd.fsm_reg_n_0_[3]\,
      I2 => rst_cpllreset,
      I3 => \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0\,
      O => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \resetovrd.reset_cnt_reg\(7),
      I1 => \resetovrd.reset_cnt_reg\(6),
      I2 => \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0\,
      I3 => \resetovrd.reset_cnt_reg\(4),
      I4 => \resetovrd.reset_cnt_reg\(5),
      O => \reset_cnt0__0\(7)
    );
\resetovrd.reset_cnt_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(0),
      Q => \resetovrd.reset_cnt_reg\(0),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset_cnt[1]_i_1__0_n_0\,
      Q => \resetovrd.reset_cnt_reg\(1),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(2),
      Q => \resetovrd.reset_cnt_reg\(2),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(3),
      Q => \resetovrd.reset_cnt_reg\(3),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset_cnt[4]_i_1__0_n_0\,
      Q => \resetovrd.reset_cnt_reg\(4),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(5),
      Q => \resetovrd.reset_cnt_reg\(5),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(6),
      Q => \resetovrd.reset_cnt_reg\(6),
      S => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \reset_cnt0__0\(7),
      Q => \resetovrd.reset_cnt_reg\(7),
      R => \resetovrd.reset_cnt[7]_i_1__0_n_0\
    );
\resetovrd.reset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \resetovrd.reset[0]_i_1__0_n_0\,
      Q => \^user_rxpmareset_1\,
      R => '0'
    );
\resetovrd.reset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[1]_i_1__0_n_0\,
      Q => \^user_rxcdrreset_1\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[2]_i_1__0_n_0\,
      Q => \^user_rxcdrfreqreset_1\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[3]_i_1__0_n_0\,
      Q => user_rxdfelpmreset_1,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[4]_i_1__0_n_0\,
      Q => \^user_eyescanreset_1\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[5]_i_1__0_n_0\,
      Q => \^user_rxpcsreset_1\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[6]_i_1__0_n_0\,
      Q => \^user_rxbufreset_1\,
      R => rst_cpllreset
    );
\resetovrd.reset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => \resetovrd.reset[7]_i_1__0_n_0\,
      D => \resetovrd.reset[7]_i_2__0_n_0\,
      Q => \resetovrd.reset_reg_n_0_[7]\,
      R => rst_cpllreset
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => '0',
      Q => resetovrd_start_reg1,
      R => rst_cpllreset
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => rst_cpllreset
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rst_idle_reg1_reg_0(0),
      Q => rst_idle_reg1,
      R => SR(0)
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => SR(0)
    );
\rxcdrlock_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(0),
      I3 => rxcdrlock_cnt_reg(1),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__4\(0)
    );
\rxcdrlock_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(0),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(2),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__4\(1)
    );
\rxcdrlock_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BCCC0000"
    )
        port map (
      I0 => rxcdrlock_cnt_reg(3),
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_reg2,
      O => \p_0_in__4\(2)
    );
\rxcdrlock_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__4\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => rxcdrlock_cnt_reg(0),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => rxcdrlock_cnt_reg(1),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__4\(2),
      Q => rxcdrlock_cnt_reg(2),
      R => rst_cpllreset
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__4\(3),
      Q => rxcdrlock_cnt_reg(3),
      R => rst_cpllreset
    );
\rxcdrlock_reg1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => gt_rxcdrlock_1,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(2),
      O => SYNC_RXCDRLOCK
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxcdrlock_1,
      Q => rxcdrlock_reg1,
      R => rst_cpllreset
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rst_cpllreset
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => eq_rxeq_adapt_done_1,
      Q => rxeq_adapt_done_reg1,
      R => rst_cpllreset
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => rst_cpllreset
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxresetdone_1,
      Q => rxresetdone_reg1,
      R => rst_cpllreset
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => rst_cpllreset
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => RXSTATUS(0),
      Q => rxstatus_reg1,
      R => SR(0)
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => SR(0)
    );
\rxvalid_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(2),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__5\(0)
    );
\rxvalid_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"808000F000F00000"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(2),
      I2 => rxvalid_reg2,
      I3 => rxstatus_reg2,
      I4 => rxvalid_cnt_reg(1),
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__5\(1)
    );
\rxvalid_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000BFC00000"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_cnt_reg(0),
      I2 => rxvalid_cnt_reg(1),
      I3 => rxvalid_cnt_reg(2),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__5\(2)
    );
\rxvalid_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C440404040404040"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => rxvalid_reg2,
      I2 => rxvalid_cnt_reg(3),
      I3 => rxvalid_cnt_reg(0),
      I4 => rxvalid_cnt_reg(1),
      I5 => rxvalid_cnt_reg(2),
      O => \p_0_in__5\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__5\(0),
      Q => rxvalid_cnt_reg(0),
      R => SR(0)
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__5\(1),
      Q => rxvalid_cnt_reg(1),
      R => SR(0)
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__5\(2),
      Q => rxvalid_cnt_reg(2),
      R => SR(0)
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => \p_0_in__5\(3),
      Q => rxvalid_cnt_reg(3),
      R => SR(0)
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_rxvalid_1,
      Q => rxvalid_reg1,
      R => SR(0)
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => SR(0)
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txcompliance_reg1_reg_0(0),
      Q => txcompliance_reg1,
      R => rst_cpllreset
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => rst_cpllreset
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => pipe_tx1_elec_idle_gt,
      Q => txelecidle_reg1,
      R => rst_cpllreset
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => rst_cpllreset
    );
txphinitdone_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => txphinitdone_reg1_reg,
      I3 => txphinitdone_reg1_reg_0,
      I4 => txphinitdone_reg1_reg_1,
      I5 => txphinitdone_reg1_reg_2,
      O => SYNC_TXPHINITDONE
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => gt_txresetdone_1,
      Q => txresetdone_reg1,
      R => rst_cpllreset
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxvalid_cnt_reg[3]_0\,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_qpll_drp is
  port (
    QRST_DRP_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \di_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    qpll_drp_en : out STD_LOGIC;
    qpll_drp_we : out STD_LOGIC;
    rst_dclk_reset : in STD_LOGIC;
    QRST_DRP_START : in STD_LOGIC;
    CLK : in STD_LOGIC;
    qpll_drp_rdy : in STD_LOGIC;
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_qpll_drp : entity is "xdma_0_pcie2_ip_qpll_drp";
end xdma_0_xdma_0_pcie2_ip_qpll_drp;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_qpll_drp is
  signal \addr[0]_i_1_n_0\ : STD_LOGIC;
  signal \addr[1]_i_1_n_0\ : STD_LOGIC;
  signal \addr[2]_i_1_n_0\ : STD_LOGIC;
  signal \addr[5]_i_1_n_0\ : STD_LOGIC;
  signal \addr[7]_i_1_n_0\ : STD_LOGIC;
  signal \crscode_reg_n_0_[0]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[1]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[2]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[3]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[4]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[5]\ : STD_LOGIC;
  signal di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di[11]_i_2_n_0\ : STD_LOGIC;
  signal \di[12]_i_2_n_0\ : STD_LOGIC;
  signal \di[13]_i_2_n_0\ : STD_LOGIC;
  signal \di[14]_i_2_n_0\ : STD_LOGIC;
  signal \di[15]_i_2_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal done : STD_LOGIC;
  signal \fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_3_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i___0_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i___1_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i__n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal \gtp_common.gtpe2_common_i_i_4_n_0\ : STD_LOGIC;
  signal \gtp_common.gtpe2_common_i_i_5_n_0\ : STD_LOGIC;
  signal index : STD_LOGIC;
  signal \index[0]_i_1_n_0\ : STD_LOGIC;
  signal \index[0]_i_2_n_0\ : STD_LOGIC;
  signal \index[1]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_2_n_0\ : STD_LOGIC;
  signal \index[2]_i_3_n_0\ : STD_LOGIC;
  signal \index[2]_i_5_n_0\ : STD_LOGIC;
  signal \index_reg_n_0_[0]\ : STD_LOGIC;
  signal \index_reg_n_0_[1]\ : STD_LOGIC;
  signal \index_reg_n_0_[2]\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal ovrd_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of ovrd_reg1 : signal is "NO";
  attribute async_reg of ovrd_reg1 : signal is "true";
  signal ovrd_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of ovrd_reg2 : signal is "NO";
  attribute async_reg of ovrd_reg2 : signal is "true";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr[0]_i_1\ : label is "soft_lutpair1858";
  attribute SOFT_HLUTNM of \addr[1]_i_1\ : label is "soft_lutpair1857";
  attribute SOFT_HLUTNM of \addr[2]_i_1\ : label is "soft_lutpair1856";
  attribute SOFT_HLUTNM of \addr[7]_i_1\ : label is "soft_lutpair1857";
  attribute SOFT_HLUTNM of \di[13]_i_2\ : label is "soft_lutpair1853";
  attribute SOFT_HLUTNM of \di[14]_i_2\ : label is "soft_lutpair1853";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM of \fsm[1]_i_2\ : label is "soft_lutpair1855";
  attribute SOFT_HLUTNM of \fsm[1]_i_3\ : label is "soft_lutpair1856";
  attribute SOFT_HLUTNM of \fsm[2]_i_1__1\ : label is "soft_lutpair1855";
  attribute SOFT_HLUTNM of \fsm_inferred__1/i_\ : label is "soft_lutpair1854";
  attribute SOFT_HLUTNM of \fsm_inferred__1/i___0\ : label is "soft_lutpair1854";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \fsm_reg[0]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[1]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[2]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[3]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[4]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[5]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[6]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \gtp_common.gtpe2_common_i_i_2\ : label is "soft_lutpair1850";
  attribute SOFT_HLUTNM of \gtp_common.gtpe2_common_i_i_5\ : label is "soft_lutpair1852";
  attribute SOFT_HLUTNM of \index[0]_i_2\ : label is "soft_lutpair1858";
  attribute SOFT_HLUTNM of \index[2]_i_2\ : label is "soft_lutpair1850";
  attribute SOFT_HLUTNM of \index[2]_i_3\ : label is "soft_lutpair1852";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1\ : label is "soft_lutpair1851";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_1\ : label is "soft_lutpair1851";
  attribute ASYNC_REG_boolean of ovrd_reg1_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of ovrd_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of ovrd_reg2_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of ovrd_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
begin
\addr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => \addr[0]_i_1_n_0\
    );
\addr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      O => \addr[1]_i_1_n_0\
    );
\addr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4D"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      O => \addr[2]_i_1_n_0\
    );
\addr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[1]\,
      O => \addr[5]_i_1_n_0\
    );
\addr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => \addr[7]_i_1_n_0\
    );
\addr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[0]_i_1_n_0\,
      Q => Q(0),
      R => rst_dclk_reset
    );
\addr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[1]_i_1_n_0\,
      Q => Q(1),
      R => rst_dclk_reset
    );
\addr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[2]_i_1_n_0\,
      Q => Q(2),
      R => rst_dclk_reset
    );
\addr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[5]_i_1_n_0\,
      Q => Q(3),
      R => rst_dclk_reset
    );
\addr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[7]_i_1_n_0\,
      Q => Q(4),
      R => rst_dclk_reset
    );
\crscode[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(1),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(0)
    );
\crscode[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(2),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(1)
    );
\crscode[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(3),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(2)
    );
\crscode[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(4),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(3)
    );
\crscode[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(4)
    );
\crscode[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C080"
    )
        port map (
      I0 => ovrd_reg2,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[2]\,
      O => p_1_in
    );
\crscode[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(5)
    );
\crscode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(0),
      Q => \crscode_reg_n_0_[0]\,
      R => rst_dclk_reset
    );
\crscode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(1),
      Q => \crscode_reg_n_0_[1]\,
      R => rst_dclk_reset
    );
\crscode_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(2),
      Q => \crscode_reg_n_0_[2]\,
      R => rst_dclk_reset
    );
\crscode_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(3),
      Q => \crscode_reg_n_0_[3]\,
      R => rst_dclk_reset
    );
\crscode_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(4),
      Q => \crscode_reg_n_0_[4]\,
      R => rst_dclk_reset
    );
\crscode_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(5),
      Q => \crscode_reg_n_0_[5]\,
      R => rst_dclk_reset
    );
\di[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(0),
      O => di(0)
    );
\di[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CC5CCCC"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => do_reg2(10),
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[2]\,
      O => di(10)
    );
\di[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000090"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[1]\,
      I5 => \di[11]_i_2_n_0\,
      O => di(11)
    );
\di[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4022"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => ovrd_reg2,
      I3 => \index_reg_n_0_[2]\,
      I4 => do_reg2(11),
      O => \di[11]_i_2_n_0\
    );
\di[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AA00AAAAAAC3AA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => \di[12]_i_2_n_0\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[1]\,
      O => di(12)
    );
\di[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[1]\,
      O => \di[12]_i_2_n_0\
    );
\di[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAAAFFAAAAC3AA"
    )
        port map (
      I0 => do_reg2(13),
      I1 => \di[13]_i_2_n_0\,
      I2 => \crscode_reg_n_0_[3]\,
      I3 => \index_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[1]\,
      O => di(13)
    );
\di[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      O => \di[13]_i_2_n_0\
    );
\di[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0AAFAA3A"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di[14]_i_2_n_0\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[1]\,
      O => di(14)
    );
\di[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0001FFFE"
    )
        port map (
      I0 => \crscode_reg_n_0_[3]\,
      I1 => \crscode_reg_n_0_[1]\,
      I2 => \crscode_reg_n_0_[0]\,
      I3 => \crscode_reg_n_0_[2]\,
      I4 => \crscode_reg_n_0_[4]\,
      O => \di[14]_i_2_n_0\
    );
\di[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CC5CCCC"
    )
        port map (
      I0 => \di[15]_i_2_n_0\,
      I1 => do_reg2(15),
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[2]\,
      O => di(15)
    );
\di[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000001FFFFFFFE"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \crscode_reg_n_0_[3]\,
      I4 => \crscode_reg_n_0_[4]\,
      I5 => \crscode_reg_n_0_[5]\,
      O => \di[15]_i_2_n_0\
    );
\di[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(1),
      O => di(1)
    );
\di[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(2),
      O => di(2)
    );
\di[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(3),
      O => di(3)
    );
\di[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(4),
      O => di(4)
    );
\di[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAB"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[2]\,
      O => di(5)
    );
\di[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2BA8"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      O => di(6)
    );
\di[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(7),
      O => di(7)
    );
\di[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAB"
    )
        port map (
      I0 => do_reg2(8),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[2]\,
      O => di(8)
    );
\di[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => do_reg2(9),
      O => di(9)
    );
\di_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(0),
      Q => \di_reg[15]_0\(0),
      R => rst_dclk_reset
    );
\di_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(10),
      Q => \di_reg[15]_0\(10),
      R => rst_dclk_reset
    );
\di_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(11),
      Q => \di_reg[15]_0\(11),
      R => rst_dclk_reset
    );
\di_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(12),
      Q => \di_reg[15]_0\(12),
      R => rst_dclk_reset
    );
\di_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(13),
      Q => \di_reg[15]_0\(13),
      R => rst_dclk_reset
    );
\di_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(14),
      Q => \di_reg[15]_0\(14),
      R => rst_dclk_reset
    );
\di_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(15),
      Q => \di_reg[15]_0\(15),
      R => rst_dclk_reset
    );
\di_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(1),
      Q => \di_reg[15]_0\(1),
      R => rst_dclk_reset
    );
\di_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(2),
      Q => \di_reg[15]_0\(2),
      R => rst_dclk_reset
    );
\di_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(3),
      Q => \di_reg[15]_0\(3),
      R => rst_dclk_reset
    );
\di_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(4),
      Q => \di_reg[15]_0\(4),
      R => rst_dclk_reset
    );
\di_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(5),
      Q => \di_reg[15]_0\(5),
      R => rst_dclk_reset
    );
\di_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(6),
      Q => \di_reg[15]_0\(6),
      R => rst_dclk_reset
    );
\di_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(7),
      Q => \di_reg[15]_0\(7),
      R => rst_dclk_reset
    );
\di_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(8),
      Q => \di_reg[15]_0\(8),
      R => rst_dclk_reset
    );
\di_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(9),
      Q => \di_reg[15]_0\(9),
      R => rst_dclk_reset
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => do_reg1(0),
      R => rst_dclk_reset
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(10),
      Q => do_reg1(10),
      R => rst_dclk_reset
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(11),
      Q => do_reg1(11),
      R => rst_dclk_reset
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(12),
      Q => do_reg1(12),
      R => rst_dclk_reset
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(13),
      Q => do_reg1(13),
      R => rst_dclk_reset
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(14),
      Q => do_reg1(14),
      R => rst_dclk_reset
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(15),
      Q => do_reg1(15),
      R => rst_dclk_reset
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => do_reg1(1),
      R => rst_dclk_reset
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => do_reg1(2),
      R => rst_dclk_reset
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => do_reg1(3),
      R => rst_dclk_reset
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => do_reg1(4),
      R => rst_dclk_reset
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => do_reg1(5),
      R => rst_dclk_reset
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(6),
      Q => do_reg1(6),
      R => rst_dclk_reset
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(7),
      Q => do_reg1(7),
      R => rst_dclk_reset
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(8),
      Q => do_reg1(8),
      R => rst_dclk_reset
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(9),
      Q => do_reg1(9),
      R => rst_dclk_reset
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => rst_dclk_reset
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => rst_dclk_reset
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => rst_dclk_reset
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => rst_dclk_reset
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => rst_dclk_reset
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => rst_dclk_reset
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => rst_dclk_reset
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => rst_dclk_reset
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => rst_dclk_reset
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => rst_dclk_reset
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => rst_dclk_reset
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => rst_dclk_reset
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => rst_dclk_reset
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => rst_dclk_reset
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => rst_dclk_reset
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => rst_dclk_reset
    );
\done_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => start_reg2,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[0]\,
      I5 => \gtp_common.gtpe2_common_i_i_5_n_0\,
      O => done
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => done,
      Q => QRST_DRP_DONE(0),
      R => rst_dclk_reset
    );
\fsm[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5DFF5D5D"
    )
        port map (
      I0 => \fsm_inferred__1/i___1_n_0\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => start_reg2,
      I3 => \fsm[1]_i_3_n_0\,
      I4 => \fsm_reg_n_0_[6]\,
      O => \p_0_in__0\(0)
    );
\fsm[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAEAAAEAAAEAAA"
    )
        port map (
      I0 => \fsm[1]_i_2_n_0\,
      I1 => start_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_inferred__1/i___1_n_0\,
      I4 => \fsm_reg_n_0_[6]\,
      I5 => \fsm[1]_i_3_n_0\,
      O => \p_0_in__0\(1)
    );
\fsm[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      O => \fsm[1]_i_2_n_0\
    );
\fsm[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => \fsm[1]_i_3_n_0\
    );
\fsm[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      O => \p_0_in__0\(2)
    );
\fsm[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C8"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => rdy_reg2,
      O => \p_0_in__0\(3)
    );
\fsm[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_inferred__1/i___1_n_0\,
      O => \p_0_in__0\(4)
    );
\fsm[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C8"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => rdy_reg2,
      O => \p_0_in__0\(5)
    );
\fsm[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_inferred__1/i___1_n_0\,
      O => \p_0_in__0\(6)
    );
\fsm_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm_inferred__1/i__n_0\
    );
\fsm_inferred__1/i___0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm_inferred__1/i___0_n_0\
    );
\fsm_inferred__1/i___1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000116"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_inferred__1/i__n_0\,
      I4 => \fsm_inferred__1/i___0_n_0\,
      O => \fsm_inferred__1/i___1_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \fsm_reg_n_0_[0]\,
      S => rst_dclk_reset
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \fsm_reg_n_0_[1]\,
      R => rst_dclk_reset
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \fsm_reg_n_0_[2]\,
      R => rst_dclk_reset
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \fsm_reg_n_0_[3]\,
      R => rst_dclk_reset
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => \fsm_reg_n_0_[4]\,
      R => rst_dclk_reset
    );
\fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => \fsm_reg_n_0_[5]\,
      R => rst_dclk_reset
    );
\fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(6),
      Q => \fsm_reg_n_0_[6]\,
      R => rst_dclk_reset
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => rst_dclk_reset
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rst_dclk_reset
    );
\gtp_common.gtpe2_common_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000014"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \gtp_common.gtpe2_common_i_i_4_n_0\,
      O => qpll_drp_en
    );
\gtp_common.gtpe2_common_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => \gtp_common.gtpe2_common_i_i_5_n_0\,
      O => qpll_drp_we
    );
\gtp_common.gtpe2_common_i_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \gtp_common.gtpe2_common_i_i_4_n_0\
    );
\gtp_common.gtpe2_common_i_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \fsm_reg_n_0_[5]\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_reg_n_0_[2]\,
      O => \gtp_common.gtpe2_common_i_i_5_n_0\
    );
\index[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF20000000"
    )
        port map (
      I0 => \index[0]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \index[2]_i_3_n_0\,
      I4 => index,
      I5 => \index_reg_n_0_[0]\,
      O => \index[0]_i_1_n_0\
    );
\index[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[2]\,
      O => \index[0]_i_2_n_0\
    );
\index[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000FFFFC0000000"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index[2]_i_2_n_0\,
      I3 => \index[2]_i_3_n_0\,
      I4 => index,
      I5 => \index_reg_n_0_[1]\,
      O => \index[1]_i_1_n_0\
    );
\index[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5000FFFF80000000"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index[2]_i_2_n_0\,
      I3 => \index[2]_i_3_n_0\,
      I4 => index,
      I5 => \index_reg_n_0_[2]\,
      O => \index[2]_i_1_n_0\
    );
\index[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[1]\,
      O => \index[2]_i_2_n_0\
    );
\index[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[4]\,
      O => \index[2]_i_3_n_0\
    );
\index[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEED"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \index[2]_i_5_n_0\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      I4 => \fsm_reg_n_0_[5]\,
      I5 => \fsm_reg_n_0_[4]\,
      O => index
    );
\index[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_5_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[0]_i_1_n_0\,
      Q => \index_reg_n_0_[0]\,
      R => rst_dclk_reset
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[1]_i_1_n_0\,
      Q => \index_reg_n_0_[1]\,
      R => rst_dclk_reset
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[2]_i_1_n_0\,
      Q => \index_reg_n_0_[2]\,
      R => rst_dclk_reset
    );
\load_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00B00000"
    )
        port map (
      I0 => load_cnt(1),
      I1 => load_cnt(0),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \index[2]_i_3_n_0\,
      O => \load_cnt[0]_i_1_n_0\
    );
\load_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E00000"
    )
        port map (
      I0 => load_cnt(1),
      I1 => load_cnt(0),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \index[2]_i_3_n_0\,
      O => \load_cnt[1]_i_1_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1_n_0\,
      Q => load_cnt(0),
      R => rst_dclk_reset
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[1]_i_1_n_0\,
      Q => load_cnt(1),
      R => rst_dclk_reset
    );
ovrd_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => ovrd_reg1,
      R => rst_dclk_reset
    );
ovrd_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ovrd_reg1,
      Q => ovrd_reg2,
      R => rst_dclk_reset
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => qplllock_reg1,
      R => rst_dclk_reset
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => rst_dclk_reset
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => qpll_drp_rdy,
      Q => rdy_reg1,
      R => rst_dclk_reset
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => rst_dclk_reset
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => QRST_DRP_START,
      Q => start_reg1,
      R => rst_dclk_reset
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => rst_dclk_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_qpll_reset is
  port (
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reg1_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_DRP_DONE : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_qpll_reset : entity is "xdma_0_pcie2_ip_qpll_reset";
end xdma_0_xdma_0_pcie2_ip_qpll_reset;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_qpll_reset is
  signal \FSM_onehot_fsm[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cplllock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of cplllock_reg1 : signal is "true";
  signal cplllock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO";
  attribute async_reg of cplllock_reg2 : signal is "true";
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal qpllpd_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllpd_in_reg1 : signal is "NO";
  attribute async_reg of qpllpd_in_reg1 : signal is "true";
  signal qpllpd_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllpd_in_reg2 : signal is "NO";
  attribute async_reg of qpllpd_in_reg2 : signal is "true";
  signal qpllreset_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllreset_in_reg1 : signal is "NO";
  attribute async_reg of qpllreset_in_reg1 : signal is "true";
  signal qpllreset_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllreset_in_reg2 : signal is "NO";
  attribute async_reg of qpllreset_in_reg2 : signal is "true";
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO";
  attribute async_reg of rate_reg1 : signal is "true";
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO";
  attribute async_reg of rate_reg2 : signal is "true";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \qplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qplllock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qplllock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO";
begin
  Q(0) <= \^q\(0);
\FSM_onehot_fsm[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => qplllock_reg2,
      I2 => cplllock_reg2(0),
      I3 => cplllock_reg2(1),
      O => \FSM_onehot_fsm[0]_i_1__2_n_0\
    );
\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFFFFFF00000044"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => mmcm_lock_reg2,
      I3 => cplllock_reg2(1),
      I4 => cplllock_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[1]_i_1_n_0\
    );
\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF800080008000"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => cplllock_reg2(1),
      I2 => cplllock_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[2]_i_1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      S => SS(0)
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1_n_0\,
      Q => \^q\(0),
      R => SS(0)
    );
\cplllock_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => cplllock_reg1(0),
      S => SS(0)
    );
\cplllock_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => cplllock_reg1(1),
      S => SS(0)
    );
\cplllock_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => cplllock_reg1(0),
      Q => cplllock_reg2(0),
      S => SS(0)
    );
\cplllock_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => cplllock_reg1(1),
      Q => cplllock_reg2(1),
      S => SS(0)
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => QRST_DRP_DONE(0),
      Q => drp_done_reg1,
      R => SS(0)
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => SS(0)
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => SS(0)
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => SS(0)
    );
\qplllock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => qplllock_reg1,
      R => SS(0)
    );
\qplllock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => SS(0)
    );
\qpllpd_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => qpllpd_in_reg1(0),
      R => SS(0)
    );
\qpllpd_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => qpllpd_in_reg1(1),
      R => SS(0)
    );
\qpllpd_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => qpllpd_in_reg1(0),
      Q => qpllpd_in_reg2(0),
      R => SS(0)
    );
\qpllpd_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => qpllpd_in_reg1(1),
      Q => qpllpd_in_reg2(1),
      R => SS(0)
    );
\qpllreset_in_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => qpllreset_in_reg1(0),
      S => SS(0)
    );
\qpllreset_in_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => qpllreset_in_reg1(1),
      S => SS(0)
    );
\qpllreset_in_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => qpllreset_in_reg1(0),
      Q => qpllreset_in_reg2(0),
      S => SS(0)
    );
\qpllreset_in_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => qpllreset_in_reg1(1),
      Q => qpllreset_in_reg2(1),
      S => SS(0)
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => D(0),
      Q => rate_reg1(0),
      R => SS(0)
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => SS(0)
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => SS(0)
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => mmcm_lock_reg1_reg_0,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_rxeq_scan is
  port (
    adapt_done_reg_0 : out STD_LOGIC;
    new_txcoeff_done_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req : out STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    new_txcoeff_req_reg1_reg_0 : in STD_LOGIC;
    \lf_reg2_reg[5]_0\ : in STD_LOGIC;
    rxeq_preset_valid : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxeq_adapt_done_reg_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_1 : in STD_LOGIC;
    rxeq_adapt_done_reg : in STD_LOGIC;
    eq_rxeq_adapt_done_1 : in STD_LOGIC;
    \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_rxeq_scan : entity is "xdma_0_pcie2_ip_rxeq_scan";
end xdma_0_xdma_0_pcie2_ip_rxeq_scan;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_rxeq_scan is
  signal \FSM_onehot_fsm[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_10__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_11__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_12__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_9__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[6]_i_2__0_n_0\ : STD_LOGIC;
  signal adapt_done : STD_LOGIC;
  signal \adapt_done_cnt_i_1__0_n_0\ : STD_LOGIC;
  signal \adapt_done_cnt_i_2__0_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of fs_reg1 : signal is "true";
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO";
  attribute async_reg of fs_reg2 : signal is "true";
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO";
  attribute async_reg of lf_reg1 : signal is "true";
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO";
  attribute async_reg of lf_reg2 : signal is "true";
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg1 : signal is "true";
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg2 : signal is "true";
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO";
  attribute async_reg of preset_reg1 : signal is "true";
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO";
  attribute async_reg of preset_reg2 : signal is "true";
  signal preset_valid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO";
  attribute async_reg of preset_valid_reg1 : signal is "true";
  signal preset_valid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO";
  attribute async_reg of preset_valid_reg2 : signal is "true";
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO";
  attribute async_reg of txcoeff_reg1 : signal is "true";
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO";
  attribute async_reg of txcoeff_reg2 : signal is "true";
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO";
  attribute async_reg of txpreset_reg1 : signal is "true";
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO";
  attribute async_reg of txpreset_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2__0\ : label is "soft_lutpair1885";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_4__0\ : label is "soft_lutpair1884";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2__0\ : label is "soft_lutpair1886";
  attribute SOFT_HLUTNM of \converge_cnt[2]_i_1__0\ : label is "soft_lutpair1885";
  attribute SOFT_HLUTNM of \converge_cnt[3]_i_1__0\ : label is "soft_lutpair1884";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[11]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[15]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[19]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[3]_i_2__0\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[7]_i_2__0\ : label is 35;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_new_txcoeff_req_i_1__0\ : label is "soft_lutpair1886";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO";
begin
\FSM_onehot_fsm[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001FF01AAABFFFB"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => preset_valid_reg2,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__3_n_0\
    );
\FSM_onehot_fsm[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FF101010101010"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__0_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_2__0_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_2__0_n_0\,
      I3 => preset_valid_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[3]_i_1__3_n_0\
    );
\FSM_onehot_fsm[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04FF"
    )
        port map (
      I0 => adapt_done_cnt_reg_n_0,
      I1 => \out\(1),
      I2 => \out\(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[3]_i_2__0_n_0\
    );
\FSM_onehot_fsm[4]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[1]\,
      I2 => \converge_cnt_reg_n_0_[9]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_10__0_n_0\
    );
\FSM_onehot_fsm[4]_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      I1 => \converge_cnt_reg_n_0_[17]\,
      I2 => \converge_cnt_reg_n_0_[18]\,
      I3 => \converge_cnt_reg_n_0_[19]\,
      O => \FSM_onehot_fsm[4]_i_11__0_n_0\
    );
\FSM_onehot_fsm[4]_i_12__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[15]\,
      I3 => \converge_cnt_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[4]_i_12__0_n_0\
    );
\FSM_onehot_fsm[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFD0FFD0FFD0"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_2__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_3__0_n_0\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm[4]_i_4__0_n_0\,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_5__0_n_0\,
      I1 => \converge_cnt_reg_n_0_[20]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[10]\,
      I4 => \converge_cnt_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm[4]_i_6__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__0_n_0\
    );
\FSM_onehot_fsm[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_6__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_7__0_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_8__0_n_0\,
      I3 => \converge_cnt_reg_n_0_[10]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[4]_i_9__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_3__0_n_0\
    );
\FSM_onehot_fsm[4]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => adapt_done_cnt_reg_n_0,
      I1 => \out\(1),
      I2 => \out\(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_4__0_n_0\
    );
\FSM_onehot_fsm[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_10__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_9__0_n_0\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \converge_cnt_reg_n_0_[15]\,
      I4 => \converge_cnt_reg_n_0_[13]\,
      I5 => \converge_cnt_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_5__0_n_0\
    );
\FSM_onehot_fsm[4]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      I1 => \converge_cnt_reg_n_0_[5]\,
      I2 => \converge_cnt_reg_n_0_[7]\,
      I3 => \converge_cnt_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm[4]_i_11__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_6__0_n_0\
    );
\FSM_onehot_fsm[4]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      I1 => \converge_cnt_reg_n_0_[9]\,
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[11]\,
      I4 => \FSM_onehot_fsm[4]_i_12__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_7__0_n_0\
    );
\FSM_onehot_fsm[4]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      I1 => \converge_cnt_reg_n_0_[12]\,
      I2 => \converge_cnt_reg_n_0_[14]\,
      I3 => \converge_cnt_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[4]_i_8__0_n_0\
    );
\FSM_onehot_fsm[4]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \out\(1),
      I1 => \out\(0),
      O => \FSM_onehot_fsm[4]_i_9__0_n_0\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4040"
    )
        port map (
      I0 => \out\(1),
      I1 => \out\(0),
      I2 => Q(0),
      I3 => rxeqscan_preset_done,
      I4 => Q(1),
      O => D(0)
    );
\FSM_onehot_fsm_rx[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F444444444444444"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      I2 => \FSM_onehot_fsm_rx_reg[5]\(2),
      I3 => \FSM_onehot_fsm_rx_reg[5]\(1),
      I4 => \FSM_onehot_fsm_rx_reg[5]\(0),
      I5 => Q(2),
      O => D(1)
    );
\FSM_onehot_fsm_rx[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE0E0E0"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => Q(4),
      I3 => Q(1),
      I4 => rxeqscan_preset_done,
      I5 => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\,
      O => D(2)
    );
\FSM_onehot_fsm_rx[6]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      O => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\
    );
\adapt_done_cnt_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000AAAFFFF0800"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      I5 => \adapt_done_cnt_i_2__0_n_0\,
      O => \adapt_done_cnt_i_1__0_n_0\
    );
\adapt_done_cnt_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF0101"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => \adapt_done_cnt_i_2__0_n_0\
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \adapt_done_cnt_i_1__0_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => rst_cpllreset
    );
\adapt_done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8000000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => adapt_done_cnt_reg_n_0,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => rst_cpllreset
    );
\converge_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(11)
    );
\converge_cnt[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(15)
    );
\converge_cnt[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(19)
    );
\converge_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(21)
    );
\converge_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_3__0_n_0\
    );
\converge_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(7)
    );
\converge_cnt[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt_reg_n_0_[11]\,
      S(2) => \converge_cnt_reg_n_0_[10]\,
      S(1) => \converge_cnt_reg_n_0_[9]\,
      S(0) => \converge_cnt_reg_n_0_[8]\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[15]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt_reg_n_0_[15]\,
      S(2) => \converge_cnt_reg_n_0_[14]\,
      S(1) => \converge_cnt_reg_n_0_[13]\,
      S(0) => \converge_cnt_reg_n_0_[12]\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[19]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt_reg_n_0_[19]\,
      S(2) => \converge_cnt_reg_n_0_[18]\,
      S(1) => \converge_cnt_reg_n_0_[17]\,
      S(0) => \converge_cnt_reg_n_0_[16]\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[21]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__0_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3 downto 2) => B"00",
      S(1) => \converge_cnt_reg_n_0_[21]\,
      S(0) => \converge_cnt_reg_n_0_[20]\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt_reg_n_0_[3]\,
      S(2) => \converge_cnt_reg_n_0_[2]\,
      S(1) => \converge_cnt_reg_n_0_[1]\,
      S(0) => \converge_cnt[3]_i_3__0_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt_reg_n_0_[7]\,
      S(2) => \converge_cnt_reg_n_0_[6]\,
      S(1) => \converge_cnt_reg_n_0_[5]\,
      S(0) => \converge_cnt_reg_n_0_[4]\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => rst_cpllreset
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(0),
      Q => fs_reg1(0),
      R => rst_cpllreset
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(1),
      Q => fs_reg1(1),
      R => rst_cpllreset
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(2),
      Q => fs_reg1(2),
      R => rst_cpllreset
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(3),
      Q => fs_reg1(3),
      R => rst_cpllreset
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(4),
      Q => fs_reg1(4),
      R => rst_cpllreset
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(5),
      Q => fs_reg1(5),
      R => rst_cpllreset
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => rst_cpllreset
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => rst_cpllreset
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => rst_cpllreset
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => rst_cpllreset
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => rst_cpllreset
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => rst_cpllreset
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(0),
      Q => lf_reg1(0),
      R => rst_cpllreset
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(1),
      Q => lf_reg1(1),
      R => rst_cpllreset
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(2),
      Q => lf_reg1(2),
      R => rst_cpllreset
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(3),
      Q => lf_reg1(3),
      R => rst_cpllreset
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(4),
      Q => lf_reg1(4),
      R => rst_cpllreset
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(5),
      Q => lf_reg1(5),
      R => rst_cpllreset
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => rst_cpllreset
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => rst_cpllreset
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => rst_cpllreset
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => rst_cpllreset
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => rst_cpllreset
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => rst_cpllreset
    );
\new_txcoeff_done_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => rst_cpllreset
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1_reg_0,
      Q => new_txcoeff_req_reg1,
      R => rst_cpllreset
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => rst_cpllreset
    );
\preset_done_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => rst_cpllreset
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(0),
      Q => preset_reg1(0),
      R => rst_cpllreset
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(1),
      Q => preset_reg1(1),
      R => rst_cpllreset
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(2),
      Q => preset_reg1(2),
      R => rst_cpllreset
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => rst_cpllreset
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => rst_cpllreset
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => rst_cpllreset
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => rxeq_preset_valid,
      Q => preset_valid_reg1,
      R => rst_cpllreset
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => rst_cpllreset
    );
\rxeq_adapt_done_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A800FFFFA8000000"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => rxeq_adapt_done_reg_reg_1,
      I2 => rxeqscan_adapt_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg,
      I5 => eq_rxeq_adapt_done_1,
      O => new_txcoeff_done_reg_0
    );
\rxeq_adapt_done_reg_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF33AA00A800"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg_reg_0,
      I5 => rxeq_adapt_done_reg_reg_1,
      O => adapt_done_reg_0
    );
\rxeq_new_txcoeff_req_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Q(3),
      I1 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(0),
      Q => txcoeff_reg1(0),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(10),
      Q => txcoeff_reg1(10),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(11),
      Q => txcoeff_reg1(11),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(12),
      Q => txcoeff_reg1(12),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(13),
      Q => txcoeff_reg1(13),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(14),
      Q => txcoeff_reg1(14),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(15),
      Q => txcoeff_reg1(15),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(16),
      Q => txcoeff_reg1(16),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(17),
      Q => txcoeff_reg1(17),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(1),
      Q => txcoeff_reg1(1),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(2),
      Q => txcoeff_reg1(2),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(3),
      Q => txcoeff_reg1(3),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(4),
      Q => txcoeff_reg1(4),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(5),
      Q => txcoeff_reg1(5),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(6),
      Q => txcoeff_reg1(6),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(7),
      Q => txcoeff_reg1(7),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(8),
      Q => txcoeff_reg1(8),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(9),
      Q => txcoeff_reg1(9),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(0),
      Q => txpreset_reg1(0),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(1),
      Q => txpreset_reg1(1),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(2),
      Q => txpreset_reg1(2),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(3),
      Q => txpreset_reg1(3),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_rxeq_scan_37 is
  port (
    adapt_done_reg_0 : out STD_LOGIC;
    new_txcoeff_done_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req : out STD_LOGIC;
    rst_cpllreset : in STD_LOGIC;
    new_txcoeff_req_reg1_reg_0 : in STD_LOGIC;
    \fs_reg2_reg[5]_0\ : in STD_LOGIC;
    rxeq_preset_valid : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxeq_adapt_done_reg_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_1 : in STD_LOGIC;
    rxeq_adapt_done_reg : in STD_LOGIC;
    eq_rxeq_adapt_done_0 : in STD_LOGIC;
    \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_rxeq_scan_37 : entity is "xdma_0_pcie2_ip_rxeq_scan";
end xdma_0_xdma_0_pcie2_ip_rxeq_scan_37;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_rxeq_scan_37 is
  signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[6]_i_2_n_0\ : STD_LOGIC;
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt_i_1_n_0 : STD_LOGIC;
  signal adapt_done_cnt_i_2_n_0 : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of fs_reg1 : signal is "true";
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO";
  attribute async_reg of fs_reg2 : signal is "true";
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO";
  attribute async_reg of lf_reg1 : signal is "true";
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO";
  attribute async_reg of lf_reg2 : signal is "true";
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg1 : signal is "true";
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg2 : signal is "true";
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO";
  attribute async_reg of preset_reg1 : signal is "true";
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO";
  attribute async_reg of preset_reg2 : signal is "true";
  signal preset_valid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO";
  attribute async_reg of preset_valid_reg1 : signal is "true";
  signal preset_valid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO";
  attribute async_reg of preset_valid_reg2 : signal is "true";
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO";
  attribute async_reg of txcoeff_reg1 : signal is "true";
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO";
  attribute async_reg of txcoeff_reg2 : signal is "true";
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO";
  attribute async_reg of txpreset_reg1 : signal is "true";
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO";
  attribute async_reg of txpreset_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2\ : label is "soft_lutpair1838";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2\ : label is "soft_lutpair1839";
  attribute SOFT_HLUTNM of \converge_cnt[3]_i_1\ : label is "soft_lutpair1838";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[11]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[15]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[19]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[21]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[3]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \converge_cnt_reg[7]_i_2\ : label is 35;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of rxeq_new_txcoeff_req_i_1 : label is "soft_lutpair1839";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO";
begin
\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001FF01AAABFFFB"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => preset_valid_reg2,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[1]_i_1_n_0\
    );
\FSM_onehot_fsm[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__1_n_0\
    );
\FSM_onehot_fsm[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F444444"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_2_n_0\,
      I2 => preset_valid_reg2,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[3]_i_1__2_n_0\
    );
\FSM_onehot_fsm[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04FF"
    )
        port map (
      I0 => adapt_done_cnt_reg_n_0,
      I1 => \out\(1),
      I2 => \out\(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[3]_i_2_n_0\
    );
\FSM_onehot_fsm[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55750000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_2_n_0\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => new_txcoeff_done,
      O => \FSM_onehot_fsm[4]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \out\(1),
      I1 => \out\(0),
      O => \FSM_onehot_fsm[4]_i_10_n_0\
    );
\FSM_onehot_fsm[4]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      I1 => \converge_cnt_reg_n_0_[17]\,
      I2 => \converge_cnt_reg_n_0_[18]\,
      I3 => \converge_cnt_reg_n_0_[19]\,
      O => \FSM_onehot_fsm[4]_i_11_n_0\
    );
\FSM_onehot_fsm[4]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      I1 => \converge_cnt_reg_n_0_[10]\,
      I2 => \converge_cnt_reg_n_0_[2]\,
      I3 => \converge_cnt_reg_n_0_[12]\,
      O => \FSM_onehot_fsm[4]_i_12_n_0\
    );
\FSM_onehot_fsm[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEF0FEFE"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7_n_0\,
      O => \FSM_onehot_fsm[4]_i_2_n_0\
    );
\FSM_onehot_fsm[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      I1 => \converge_cnt_reg_n_0_[15]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm[4]_i_8_n_0\,
      O => \FSM_onehot_fsm[4]_i_3_n_0\
    );
\FSM_onehot_fsm[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[0]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \FSM_onehot_fsm[4]_i_9_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_10_n_0\,
      O => \FSM_onehot_fsm[4]_i_4_n_0\
    );
\FSM_onehot_fsm[4]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      I1 => \converge_cnt_reg_n_0_[5]\,
      I2 => \converge_cnt_reg_n_0_[7]\,
      I3 => \converge_cnt_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm[4]_i_11_n_0\,
      O => \FSM_onehot_fsm[4]_i_5_n_0\
    );
\FSM_onehot_fsm[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      I1 => \converge_cnt_reg_n_0_[9]\,
      I2 => \converge_cnt_reg_n_0_[20]\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm[4]_i_12_n_0\,
      O => \FSM_onehot_fsm[4]_i_6_n_0\
    );
\FSM_onehot_fsm[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[15]\,
      I3 => \converge_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm[4]_i_10_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_9_n_0\,
      O => \FSM_onehot_fsm[4]_i_7_n_0\
    );
\FSM_onehot_fsm[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      I1 => \converge_cnt_reg_n_0_[14]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      O => \FSM_onehot_fsm[4]_i_8_n_0\
    );
\FSM_onehot_fsm[4]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[11]\,
      O => \FSM_onehot_fsm[4]_i_9_n_0\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4040"
    )
        port map (
      I0 => \out\(1),
      I1 => \out\(0),
      I2 => Q(0),
      I3 => rxeqscan_preset_done,
      I4 => Q(1),
      O => D(0)
    );
\FSM_onehot_fsm_rx[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F444444444444444"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      I2 => \FSM_onehot_fsm_rx_reg[5]\(2),
      I3 => \FSM_onehot_fsm_rx_reg[5]\(1),
      I4 => \FSM_onehot_fsm_rx_reg[5]\(0),
      I5 => Q(2),
      O => D(1)
    );
\FSM_onehot_fsm_rx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE0E0E0"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => Q(4),
      I3 => Q(1),
      I4 => rxeqscan_preset_done,
      I5 => \FSM_onehot_fsm_rx[6]_i_2_n_0\,
      O => D(2)
    );
\FSM_onehot_fsm_rx[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      O => \FSM_onehot_fsm_rx[6]_i_2_n_0\
    );
adapt_done_cnt_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000AAAFFFF0800"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      I5 => adapt_done_cnt_i_2_n_0,
      O => adapt_done_cnt_i_1_n_0
    );
adapt_done_cnt_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF0101"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done_cnt_i_2_n_0
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done_cnt_i_1_n_0,
      Q => adapt_done_cnt_reg_n_0,
      R => rst_cpllreset
    );
adapt_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8000000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => adapt_done_cnt_reg_n_0,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => rst_cpllreset
    );
\converge_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(11)
    );
\converge_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(15)
    );
\converge_cnt[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(19)
    );
\converge_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(21)
    );
\converge_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_3_n_0\
    );
\converge_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(7)
    );
\converge_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(0),
      I3 => \out\(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt_reg_n_0_[11]\,
      S(2) => \converge_cnt_reg_n_0_[10]\,
      S(1) => \converge_cnt_reg_n_0_[9]\,
      S(0) => \converge_cnt_reg_n_0_[8]\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[15]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt_reg_n_0_[15]\,
      S(2) => \converge_cnt_reg_n_0_[14]\,
      S(1) => \converge_cnt_reg_n_0_[13]\,
      S(0) => \converge_cnt_reg_n_0_[12]\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[19]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt_reg_n_0_[19]\,
      S(2) => \converge_cnt_reg_n_0_[18]\,
      S(1) => \converge_cnt_reg_n_0_[17]\,
      S(0) => \converge_cnt_reg_n_0_[16]\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[21]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3 downto 2) => B"00",
      S(1) => \converge_cnt_reg_n_0_[21]\,
      S(0) => \converge_cnt_reg_n_0_[20]\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt_reg_n_0_[3]\,
      S(2) => \converge_cnt_reg_n_0_[2]\,
      S(1) => \converge_cnt_reg_n_0_[1]\,
      S(0) => \converge_cnt[3]_i_3_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt_reg_n_0_[7]\,
      S(2) => \converge_cnt_reg_n_0_[6]\,
      S(1) => \converge_cnt_reg_n_0_[5]\,
      S(0) => \converge_cnt_reg_n_0_[4]\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => rst_cpllreset
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(0),
      Q => fs_reg1(0),
      R => rst_cpllreset
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(1),
      Q => fs_reg1(1),
      R => rst_cpllreset
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(2),
      Q => fs_reg1(2),
      R => rst_cpllreset
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(3),
      Q => fs_reg1(3),
      R => rst_cpllreset
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(4),
      Q => fs_reg1(4),
      R => rst_cpllreset
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(5),
      Q => fs_reg1(5),
      R => rst_cpllreset
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => rst_cpllreset
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => rst_cpllreset
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => rst_cpllreset
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => rst_cpllreset
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => rst_cpllreset
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => rst_cpllreset
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(0),
      Q => lf_reg1(0),
      R => rst_cpllreset
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(1),
      Q => lf_reg1(1),
      R => rst_cpllreset
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(2),
      Q => lf_reg1(2),
      R => rst_cpllreset
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(3),
      Q => lf_reg1(3),
      R => rst_cpllreset
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(4),
      Q => lf_reg1(4),
      R => rst_cpllreset
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(5),
      Q => lf_reg1(5),
      R => rst_cpllreset
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => rst_cpllreset
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => rst_cpllreset
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => rst_cpllreset
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => rst_cpllreset
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => rst_cpllreset
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => rst_cpllreset
    );
new_txcoeff_done_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => rst_cpllreset
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1_reg_0,
      Q => new_txcoeff_req_reg1,
      R => rst_cpllreset
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => rst_cpllreset
    );
preset_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => rst_cpllreset
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(0),
      Q => preset_reg1(0),
      R => rst_cpllreset
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(1),
      Q => preset_reg1(1),
      R => rst_cpllreset
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(2),
      Q => preset_reg1(2),
      R => rst_cpllreset
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => rst_cpllreset
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => rst_cpllreset
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => rst_cpllreset
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => rxeq_preset_valid,
      Q => preset_valid_reg1,
      R => rst_cpllreset
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => rst_cpllreset
    );
rxeq_adapt_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A800FFFFA8000000"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => rxeq_adapt_done_reg_reg_1,
      I2 => rxeqscan_adapt_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg,
      I5 => eq_rxeq_adapt_done_0,
      O => new_txcoeff_done_reg_0
    );
rxeq_adapt_done_reg_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF33AA00A800"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg_reg_0,
      I5 => rxeq_adapt_done_reg_reg_1,
      O => adapt_done_reg_0
    );
rxeq_new_txcoeff_req_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Q(3),
      I1 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(0),
      Q => txcoeff_reg1(0),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(10),
      Q => txcoeff_reg1(10),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(11),
      Q => txcoeff_reg1(11),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(12),
      Q => txcoeff_reg1(12),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(13),
      Q => txcoeff_reg1(13),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(14),
      Q => txcoeff_reg1(14),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(15),
      Q => txcoeff_reg1(15),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(16),
      Q => txcoeff_reg1(16),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(17),
      Q => txcoeff_reg1(17),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(1),
      Q => txcoeff_reg1(1),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(2),
      Q => txcoeff_reg1(2),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(3),
      Q => txcoeff_reg1(3),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(4),
      Q => txcoeff_reg1(4),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(5),
      Q => txcoeff_reg1(5),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(6),
      Q => txcoeff_reg1(6),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(7),
      Q => txcoeff_reg1(7),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(8),
      Q => txcoeff_reg1(8),
      R => rst_cpllreset
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(9),
      Q => txcoeff_reg1(9),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => rst_cpllreset
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(0),
      Q => txpreset_reg1(0),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(1),
      Q => txpreset_reg1(1),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(2),
      Q => txpreset_reg1(2),
      R => rst_cpllreset
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(3),
      Q => txpreset_reg1(3),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => rst_cpllreset
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_tgt_cpl is
  port (
    D : out STD_LOGIC_VECTOR ( 16 downto 0 );
    state : out STD_LOGIC_VECTOR ( 0 to 0 );
    \tx_64.compl_data_reg[37]_0\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[1]_0\ : out STD_LOGIC;
    \tx_64.compl_len_reg[2]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[2]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[3]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[4]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[5]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[6]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[7]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[8]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[9]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[10]_0\ : out STD_LOGIC;
    \tx_64.compl_byte_reg[11]_0\ : out STD_LOGIC;
    \tx_64.compl_status_reg[0]_0\ : out STD_LOGIC;
    \tx_64.compl_status_reg[1]_0\ : out STD_LOGIC;
    \tx_64.compl_status_reg[2]_0\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[0]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[1]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[2]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[3]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[4]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[5]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[6]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[7]\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[1]_1\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[1]_2\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[1]_3\ : out STD_LOGIC;
    \cfg_function_number_d_reg[0]\ : out STD_LOGIC;
    \cfg_function_number_d_reg[1]\ : out STD_LOGIC;
    \cfg_function_number_d_reg[2]\ : out STD_LOGIC;
    \cfg_device_number_d_reg[0]\ : out STD_LOGIC;
    \cfg_device_number_d_reg[1]\ : out STD_LOGIC;
    \cfg_device_number_d_reg[2]\ : out STD_LOGIC;
    \cfg_device_number_d_reg[3]\ : out STD_LOGIC;
    \cfg_device_number_d_reg[4]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_0\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_1\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_2\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_3\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_4\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_5\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_6\ : out STD_LOGIC;
    \tx_64.compl_len_reg[7]_0\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_0\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_1\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_2\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_3\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_4\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_5\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_6\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_7\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_8\ : out STD_LOGIC;
    \Head_reg[8]\ : out STD_LOGIC;
    \Head_reg[9]\ : out STD_LOGIC;
    \Head_reg[10]\ : out STD_LOGIC;
    \Head_reg[11]\ : out STD_LOGIC;
    \Head_reg[12]\ : out STD_LOGIC;
    \Head_reg[13]\ : out STD_LOGIC;
    \Head_reg[14]\ : out STD_LOGIC;
    \Head_reg[15]\ : out STD_LOGIC;
    tready_thrtl_reg : out STD_LOGIC;
    \m_axis_cc\\.tready\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_9\ : out STD_LOGIC;
    \tx_64.compl_addr_reg[2]_0\ : out STD_LOGIC;
    \tx_64.compl_addr_reg[2]_1\ : out STD_LOGIC;
    \tx_64.compl_len_reg[0]_0\ : out STD_LOGIC;
    \tx_64.compl_len_reg[1]_0\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[24]_7\ : out STD_LOGIC;
    \aa256_tdata_ff_reg[25]\ : out STD_LOGIC;
    \tx_64.compl_status_reg[0]_1\ : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_10\ : out STD_LOGIC;
    s_axis_tx_tgt_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_axis_cc\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk_out : in STD_LOGIC;
    \s_axis_tx_tdata_reg[2]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[2]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[2]_1\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[29]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[44]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[44]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 21 downto 0 );
    \s_axis_tx_tdata_reg[34]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[56]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[30]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[25]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[25]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[27]\ : in STD_LOGIC;
    cfg_function_number_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \s_axis_tx_tdata_reg[48]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[48]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[49]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[50]\ : in STD_LOGIC;
    cfg_device_number_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \s_axis_tx_tdata_reg[51]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[52]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[53]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[54]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[55]\ : in STD_LOGIC;
    cfg_bus_number_o : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \s_axis_tx_tdata_reg[56]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[57]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[58]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[59]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[60]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[61]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[62]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[63]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[3]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[4]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[5]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[6]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[8]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[9]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[10]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[11]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[12]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[14]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[18]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[20]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[21]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[22]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[30]_0\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[7]\ : in STD_LOGIC;
    \s_axis_tx_tdata_reg[15]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \s_axis_tx_tdata_reg[15]_0\ : in STD_LOGIC;
    \m_axis_rq\\.tdata\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tready : in STD_LOGIC;
    \m_axis_cc\\.tlast\ : in STD_LOGIC;
    transfer_SM : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_tx_req_tvalid : in STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_11\ : in STD_LOGIC;
    \m_axis_cc\\.tvalid\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_tgt_cpl : entity is "xdma_0_tgt_cpl";
end xdma_0_xdma_0_tgt_cpl;

architecture STRUCTURE of xdma_0_xdma_0_tgt_cpl is
  signal \FSM_sequential_transfer_SM[1]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_transfer_SM[1]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_64.state[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_tx_64.state_reg[1]_0\ : STD_LOGIC;
  signal \^fsm_sequential_tx_64.state_reg[1]_2\ : STD_LOGIC;
  signal compl_addr : STD_LOGIC;
  signal compl_data : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal compl_rid : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal compl_tag : STD_LOGIC;
  signal in_packet_q : STD_LOGIC;
  signal in_packet_q_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_5_out : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \s_axis_tx_tdata[0]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[10]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[11]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[12]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[14]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[15]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[16]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[17]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[18]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[19]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[1]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[20]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[21]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[22]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[22]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[22]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[23]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[24]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[26]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[28]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[29]_i_7_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[30]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[31]_i_6_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[3]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[44]_i_2_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[4]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[55]_i_5_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[5]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[6]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[7]_i_4_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[8]_i_3_n_0\ : STD_LOGIC;
  signal \s_axis_tx_tdata[9]_i_3_n_0\ : STD_LOGIC;
  signal \^state\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \tx_64.compl_addr_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.compl_addr_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.compl_addr_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.compl_addr_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.compl_addr_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.compl_addr_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[32]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[33]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[34]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[35]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[36]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[37]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[38]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[39]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[40]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[41]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[42]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[43]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[44]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[45]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[46]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[47]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[48]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[49]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[50]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[51]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[52]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[53]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[54]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[55]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[56]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[57]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[58]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[59]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[60]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[61]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[62]\ : STD_LOGIC;
  signal \tx_64.compl_data_reg_n_0_[63]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.compl_tag_reg_n_0_[7]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_transfer_SM[1]_i_5\ : label is "soft_lutpair2070";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[0]\ : label is "TX_DW0_DW1:01,TX_DW2:10,TX_WAIT:11,TX_IDLE:00";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[1]\ : label is "TX_DW0_DW1:01,TX_DW2:10,TX_WAIT:11,TX_IDLE:00";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[22]_i_3\ : label is "soft_lutpair2070";
  attribute SOFT_HLUTNM of \tx_64.compl_data[32]_i_1\ : label is "soft_lutpair2071";
  attribute SOFT_HLUTNM of \tx_64.compl_data[33]_i_1\ : label is "soft_lutpair2071";
  attribute SOFT_HLUTNM of \tx_64.compl_data[34]_i_1\ : label is "soft_lutpair2072";
  attribute SOFT_HLUTNM of \tx_64.compl_data[35]_i_1\ : label is "soft_lutpair2072";
  attribute SOFT_HLUTNM of \tx_64.compl_data[36]_i_1\ : label is "soft_lutpair2073";
  attribute SOFT_HLUTNM of \tx_64.compl_data[37]_i_1\ : label is "soft_lutpair2073";
  attribute SOFT_HLUTNM of \tx_64.compl_data[38]_i_1\ : label is "soft_lutpair2074";
  attribute SOFT_HLUTNM of \tx_64.compl_data[39]_i_1\ : label is "soft_lutpair2074";
  attribute SOFT_HLUTNM of \tx_64.compl_data[40]_i_1\ : label is "soft_lutpair2075";
  attribute SOFT_HLUTNM of \tx_64.compl_data[41]_i_1\ : label is "soft_lutpair2075";
  attribute SOFT_HLUTNM of \tx_64.compl_data[42]_i_1\ : label is "soft_lutpair2076";
  attribute SOFT_HLUTNM of \tx_64.compl_data[43]_i_1\ : label is "soft_lutpair2076";
  attribute SOFT_HLUTNM of \tx_64.compl_data[44]_i_1\ : label is "soft_lutpair2077";
  attribute SOFT_HLUTNM of \tx_64.compl_data[45]_i_1\ : label is "soft_lutpair2077";
  attribute SOFT_HLUTNM of \tx_64.compl_data[46]_i_1\ : label is "soft_lutpair2078";
  attribute SOFT_HLUTNM of \tx_64.compl_data[47]_i_1\ : label is "soft_lutpair2078";
  attribute SOFT_HLUTNM of \tx_64.compl_data[48]_i_1\ : label is "soft_lutpair2079";
  attribute SOFT_HLUTNM of \tx_64.compl_data[49]_i_1\ : label is "soft_lutpair2079";
  attribute SOFT_HLUTNM of \tx_64.compl_data[50]_i_1\ : label is "soft_lutpair2080";
  attribute SOFT_HLUTNM of \tx_64.compl_data[51]_i_1\ : label is "soft_lutpair2080";
  attribute SOFT_HLUTNM of \tx_64.compl_data[52]_i_1\ : label is "soft_lutpair2081";
  attribute SOFT_HLUTNM of \tx_64.compl_data[53]_i_1\ : label is "soft_lutpair2081";
  attribute SOFT_HLUTNM of \tx_64.compl_data[54]_i_1\ : label is "soft_lutpair2082";
  attribute SOFT_HLUTNM of \tx_64.compl_data[55]_i_1\ : label is "soft_lutpair2082";
  attribute SOFT_HLUTNM of \tx_64.compl_data[56]_i_1\ : label is "soft_lutpair2083";
  attribute SOFT_HLUTNM of \tx_64.compl_data[57]_i_1\ : label is "soft_lutpair2083";
  attribute SOFT_HLUTNM of \tx_64.compl_data[58]_i_1\ : label is "soft_lutpair2084";
  attribute SOFT_HLUTNM of \tx_64.compl_data[59]_i_1\ : label is "soft_lutpair2084";
  attribute SOFT_HLUTNM of \tx_64.compl_data[60]_i_1\ : label is "soft_lutpair2085";
  attribute SOFT_HLUTNM of \tx_64.compl_data[61]_i_1\ : label is "soft_lutpair2085";
  attribute SOFT_HLUTNM of \tx_64.compl_data[62]_i_1\ : label is "soft_lutpair2086";
  attribute SOFT_HLUTNM of \tx_64.compl_data[63]_i_1\ : label is "soft_lutpair2086";
begin
  \FSM_sequential_tx_64.state_reg[1]_0\ <= \^fsm_sequential_tx_64.state_reg[1]_0\;
  \FSM_sequential_tx_64.state_reg[1]_2\ <= \^fsm_sequential_tx_64.state_reg[1]_2\;
  state(0) <= \^state\(0);
\FSM_sequential_transfer_SM[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAEAAAAAA"
    )
        port map (
      I0 => \FSM_sequential_transfer_SM[1]_i_6_n_0\,
      I1 => s_axis_tx_tready,
      I2 => SR(0),
      I3 => \m_axis_cc\\.tlast\,
      I4 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I5 => transfer_SM(1),
      O => tready_thrtl_reg
    );
\FSM_sequential_transfer_SM[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F088"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I1 => \tx_64.compl_tag_reg_n_0_[5]\,
      I2 => \FSM_sequential_transfer_SM[1]_i_7_n_0\,
      I3 => \^state\(0),
      I4 => SR(0),
      O => s_axis_tx_tgt_tdata(0)
    );
\FSM_sequential_transfer_SM[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      O => \FSM_sequential_tx_64.state_reg[0]_9\
    );
\FSM_sequential_transfer_SM[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF54"
    )
        port map (
      I0 => SR(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I2 => \^state\(0),
      I3 => s_axis_tx_req_tvalid,
      I4 => transfer_SM(1),
      I5 => transfer_SM(0),
      O => \FSM_sequential_transfer_SM[1]_i_6_n_0\
    );
\FSM_sequential_transfer_SM[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(21),
      I1 => p_0_in,
      I2 => \tx_64.compl_data_reg_n_0_[53]\,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I4 => \m_axis_cc\\.tdata\(29),
      O => \FSM_sequential_transfer_SM[1]_i_7_n_0\
    );
\FSM_sequential_tx_64.state[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFFAAAA11550F00"
    )
        port map (
      I0 => \FSM_sequential_tx_64.state_reg[0]_11\,
      I1 => \m_axis_cc\\.tlast\,
      I2 => in_packet_q,
      I3 => \m_axis_cc\\.tvalid\,
      I4 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I5 => \^state\(0),
      O => \FSM_sequential_tx_64.state[0]_i_1__0_n_0\
    );
\FSM_sequential_tx_64.state[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DF33DF00"
    )
        port map (
      I0 => \m_axis_cc\\.tlast\,
      I1 => \FSM_sequential_tx_64.state_reg[0]_11\,
      I2 => \m_axis_cc\\.tvalid\,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I4 => \^state\(0),
      O => \FSM_sequential_tx_64.state[1]_i_1__0_n_0\
    );
\FSM_sequential_tx_64.state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_tx_64.state[0]_i_1__0_n_0\,
      Q => \^state\(0),
      R => SR(0)
    );
\FSM_sequential_tx_64.state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_tx_64.state[1]_i_1__0_n_0\,
      Q => \^fsm_sequential_tx_64.state_reg[1]_2\,
      R => SR(0)
    );
in_packet_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40454444"
    )
        port map (
      I0 => SR(0),
      I1 => in_packet_q,
      I2 => \FSM_sequential_tx_64.state_reg[0]_11\,
      I3 => \m_axis_cc\\.tlast\,
      I4 => \m_axis_cc\\.tvalid\,
      O => in_packet_q_i_1_n_0
    );
in_packet_q_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => in_packet_q_i_1_n_0,
      Q => in_packet_q,
      R => '0'
    );
\s_axis_tx_tdata[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[0]_i_4_n_0\,
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => p_5_out(0),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I4 => \tx_64.compl_addr_reg_n_0_[0]\,
      O => \tx_64.compl_len_reg[0]_0\
    );
\s_axis_tx_tdata[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[56]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[0]_i_4_n_0\
    );
\s_axis_tx_tdata[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[10]\,
      I1 => \tx_64.compl_tag_reg_n_0_[2]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(10),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[10]_i_3_n_0\,
      O => D(7)
    );
\s_axis_tx_tdata[10]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(18),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[50]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[10]_i_3_n_0\
    );
\s_axis_tx_tdata[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[11]\,
      I1 => \tx_64.compl_tag_reg_n_0_[3]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(11),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[11]_i_3_n_0\,
      O => D(8)
    );
\s_axis_tx_tdata[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(19),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[51]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[11]_i_3_n_0\
    );
\s_axis_tx_tdata[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[12]\,
      I1 => \tx_64.compl_tag_reg_n_0_[4]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => \m_axis_cc\\.tdata\(28),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[12]_i_3_n_0\,
      O => D(9)
    );
\s_axis_tx_tdata[12]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(20),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[52]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[12]_i_3_n_0\
    );
\s_axis_tx_tdata[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[14]\,
      I1 => \tx_64.compl_tag_reg_n_0_[6]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(14),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[14]_i_3_n_0\,
      O => D(10)
    );
\s_axis_tx_tdata[14]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(22),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[54]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[14]_i_3_n_0\
    );
\s_axis_tx_tdata[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(23),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(9),
      I5 => \s_axis_tx_tdata[15]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_0\
    );
\s_axis_tx_tdata[15]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[55]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => \tx_64.compl_tag_reg_n_0_[7]\,
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[15]_i_5_n_0\
    );
\s_axis_tx_tdata[16]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(8),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(5),
      I5 => \s_axis_tx_tdata[16]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_1\
    );
\s_axis_tx_tdata[16]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[40]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(0),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[16]_i_5_n_0\
    );
\s_axis_tx_tdata[17]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(9),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(6),
      I5 => \s_axis_tx_tdata[17]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_2\
    );
\s_axis_tx_tdata[17]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[41]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(1),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[17]_i_5_n_0\
    );
\s_axis_tx_tdata[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[18]\,
      I1 => compl_rid(2),
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => \m_axis_cc\\.tdata\(30),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[18]_i_3_n_0\,
      O => D(11)
    );
\s_axis_tx_tdata[18]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(10),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[42]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[18]_i_3_n_0\
    );
\s_axis_tx_tdata[19]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(11),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(7),
      I5 => \s_axis_tx_tdata[19]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_3\
    );
\s_axis_tx_tdata[19]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[43]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(3),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[19]_i_5_n_0\
    );
\s_axis_tx_tdata[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[1]_i_4_n_0\,
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => p_5_out(1),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I4 => \tx_64.compl_addr_reg_n_0_[1]\,
      O => \tx_64.compl_len_reg[1]_0\
    );
\s_axis_tx_tdata[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(25),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[57]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[1]_i_4_n_0\
    );
\s_axis_tx_tdata[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[20]\,
      I1 => compl_rid(4),
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => \m_axis_cc\\.tdata\(25),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[20]_i_3_n_0\,
      O => D(12)
    );
\s_axis_tx_tdata[20]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(12),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[44]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[20]_i_3_n_0\
    );
\s_axis_tx_tdata[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[21]\,
      I1 => compl_rid(5),
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => \m_axis_cc\\.tdata\(26),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[21]_i_3_n_0\,
      O => D(13)
    );
\s_axis_tx_tdata[21]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(13),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[45]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[21]_i_3_n_0\
    );
\s_axis_tx_tdata[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[22]\,
      I1 => compl_rid(6),
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => \m_axis_cc\\.tdata\(27),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[22]_i_5_n_0\,
      O => D(14)
    );
\s_axis_tx_tdata[22]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I1 => SR(0),
      I2 => transfer_SM(0),
      I3 => transfer_SM(1),
      I4 => \^state\(0),
      O => \s_axis_tx_tdata[22]_i_3_n_0\
    );
\s_axis_tx_tdata[22]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \^state\(0),
      I1 => SR(0),
      I2 => transfer_SM(0),
      I3 => transfer_SM(1),
      I4 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      O => \s_axis_tx_tdata[22]_i_4_n_0\
    );
\s_axis_tx_tdata[22]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(14),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[46]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[22]_i_5_n_0\
    );
\s_axis_tx_tdata[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(15),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(8),
      I5 => \s_axis_tx_tdata[23]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_4\
    );
\s_axis_tx_tdata[23]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[47]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(7),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[23]_i_5_n_0\
    );
\s_axis_tx_tdata[24]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(0),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(1),
      I5 => \s_axis_tx_tdata[24]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_5\
    );
\s_axis_tx_tdata[24]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[32]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(8),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[24]_i_5_n_0\
    );
\s_axis_tx_tdata[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2A222A222A22"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]\,
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I2 => p_0_in,
      I3 => \tx_64.compl_data_reg_n_0_[33]\,
      I4 => \s_axis_tx_tdata_reg[25]\,
      I5 => \s_axis_tx_tdata_reg[25]_0\,
      O => \FSM_sequential_tx_64.state_reg[1]_1\
    );
\s_axis_tx_tdata[25]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]\,
      I1 => p_0_in,
      I2 => \m_axis_cc\\.tdata\(1),
      I3 => compl_rid(9),
      I4 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \tx_64.compl_addr_reg[2]_0\
    );
\s_axis_tx_tdata[26]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(2),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(2),
      I5 => \s_axis_tx_tdata[26]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_6\
    );
\s_axis_tx_tdata[26]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[34]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(10),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[26]_i_5_n_0\
    );
\s_axis_tx_tdata[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF2A222A222A22"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]\,
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I2 => p_0_in,
      I3 => \tx_64.compl_data_reg_n_0_[35]\,
      I4 => \s_axis_tx_tdata_reg[27]\,
      I5 => \s_axis_tx_tdata_reg[25]_0\,
      O => \FSM_sequential_tx_64.state_reg[1]_3\
    );
\s_axis_tx_tdata[27]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]\,
      I1 => p_0_in,
      I2 => \m_axis_cc\\.tdata\(3),
      I3 => compl_rid(11),
      I4 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \tx_64.compl_addr_reg[2]_1\
    );
\s_axis_tx_tdata[28]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(4),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(3),
      I5 => \s_axis_tx_tdata[28]_i_5_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_7\
    );
\s_axis_tx_tdata[28]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[36]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(12),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[28]_i_5_n_0\
    );
\s_axis_tx_tdata[29]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[29]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => \tx_64.compl_data_reg_n_0_[37]\,
      I3 => \^state\(0),
      I4 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I5 => \m_axis_cc\\.tdata\(5),
      O => \tx_64.compl_data_reg[37]_0\
    );
\s_axis_tx_tdata[29]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => \^state\(0),
      I1 => transfer_SM(1),
      I2 => transfer_SM(0),
      I3 => SR(0),
      I4 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I5 => compl_rid(13),
      O => \FSM_sequential_tx_64.state_reg[0]_10\
    );
\s_axis_tx_tdata[29]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010000000000000"
    )
        port map (
      I0 => p_0_in,
      I1 => transfer_SM(1),
      I2 => transfer_SM(0),
      I3 => SR(0),
      I4 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I5 => \^state\(0),
      O => \s_axis_tx_tdata[29]_i_7_n_0\
    );
\s_axis_tx_tdata[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAEAAFAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[2]\,
      I1 => \tx_64.compl_data_reg_n_0_[58]\,
      I2 => p_0_in,
      I3 => \s_axis_tx_tdata_reg[2]_0\,
      I4 => \^state\(0),
      I5 => \s_axis_tx_tdata_reg[2]_1\,
      O => D(0)
    );
\s_axis_tx_tdata[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(2),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(26),
      I4 => Q(21),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_len_reg[2]_0\
    );
\s_axis_tx_tdata[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAEFFAAAA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]_0\,
      I1 => \tx_64.compl_data_reg_n_0_[38]\,
      I2 => p_0_in,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I4 => \s_axis_tx_tdata_reg[30]\,
      I5 => \s_axis_tx_tdata[30]_i_4_n_0\,
      O => D(15)
    );
\s_axis_tx_tdata[30]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[30]\,
      I1 => p_0_in,
      I2 => \m_axis_cc\\.tdata\(6),
      I3 => compl_rid(14),
      I4 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[30]_i_4_n_0\
    );
\s_axis_tx_tdata[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF808080"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(7),
      I3 => \s_axis_tx_tdata_reg[15]_0\,
      I4 => \s_axis_tx_tdata_reg[15]\(4),
      I5 => \s_axis_tx_tdata[31]_i_6_n_0\,
      O => \FSM_sequential_tx_64.state_reg[0]_8\
    );
\s_axis_tx_tdata[31]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.compl_data_reg_n_0_[39]\,
      I1 => \s_axis_tx_tdata[29]_i_7_n_0\,
      I2 => compl_rid(15),
      I3 => \s_axis_tx_tdata[22]_i_3_n_0\,
      O => \s_axis_tx_tdata[31]_i_6_n_0\
    );
\s_axis_tx_tdata[32]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I2 => p_5_out(32),
      I3 => \s_axis_tx_tdata[22]_i_4_n_0\,
      O => \aa256_tdata_ff_reg[24]_7\
    );
\s_axis_tx_tdata[33]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(25),
      I1 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I2 => p_5_out(33),
      I3 => \s_axis_tx_tdata[22]_i_4_n_0\,
      O => \aa256_tdata_ff_reg[25]\
    );
\s_axis_tx_tdata[34]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(34),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(26),
      I4 => Q(0),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[2]_0\
    );
\s_axis_tx_tdata[35]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(35),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(27),
      I4 => Q(1),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[3]_0\
    );
\s_axis_tx_tdata[36]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(36),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(28),
      I4 => Q(2),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[4]_0\
    );
\s_axis_tx_tdata[37]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(37),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(29),
      I4 => Q(3),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[5]_0\
    );
\s_axis_tx_tdata[38]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(38),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(30),
      I4 => Q(4),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[6]_0\
    );
\s_axis_tx_tdata[39]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(39),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(31),
      I4 => Q(5),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[7]_0\
    );
\s_axis_tx_tdata[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[3]\,
      I1 => \tx_64.compl_addr_reg_n_0_[3]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(3),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[3]_i_3_n_0\,
      O => D(1)
    );
\s_axis_tx_tdata[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(27),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[59]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[3]_i_3_n_0\
    );
\s_axis_tx_tdata[40]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(40),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(16),
      I4 => Q(6),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[8]_0\
    );
\s_axis_tx_tdata[41]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(41),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(17),
      I4 => Q(7),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[9]_0\
    );
\s_axis_tx_tdata[42]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(42),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(18),
      I4 => Q(8),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[10]_0\
    );
\s_axis_tx_tdata[43]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(43),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(19),
      I4 => Q(9),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_byte_reg[11]_0\
    );
\s_axis_tx_tdata[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(52),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \m_axis_cc\\.tdata\(20),
      I3 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I4 => \s_axis_tx_tdata_reg[44]\,
      I5 => \s_axis_tx_tdata_reg[44]_0\,
      O => D(16)
    );
\s_axis_tx_tdata[44]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I1 => SR(0),
      I2 => transfer_SM(0),
      I3 => transfer_SM(1),
      I4 => p_0_in,
      O => \s_axis_tx_tdata[44]_i_2_n_0\
    );
\s_axis_tx_tdata[45]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(45),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(21),
      I4 => Q(10),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_status_reg[0]_0\
    );
\s_axis_tx_tdata[46]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(46),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(22),
      I4 => Q(11),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_status_reg[1]_0\
    );
\s_axis_tx_tdata[47]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I1 => SR(0),
      I2 => transfer_SM(0),
      I3 => transfer_SM(1),
      I4 => p_0_in,
      O => \^fsm_sequential_tx_64.state_reg[1]_0\
    );
\s_axis_tx_tdata[47]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I1 => p_5_out(47),
      I2 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I3 => \m_axis_cc\\.tdata\(23),
      I4 => Q(12),
      I5 => \s_axis_tx_tdata_reg[34]\,
      O => \tx_64.compl_status_reg[2]_0\
    );
\s_axis_tx_tdata[48]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(0),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(8),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[8]\
    );
\s_axis_tx_tdata[48]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_function_number_o(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(40),
      I4 => \s_axis_tx_tdata_reg[48]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_function_number_d_reg[0]\
    );
\s_axis_tx_tdata[49]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(1),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(9),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[9]\
    );
\s_axis_tx_tdata[49]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_function_number_o(1),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(41),
      I4 => \s_axis_tx_tdata_reg[49]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_function_number_d_reg[1]\
    );
\s_axis_tx_tdata[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[4]\,
      I1 => \tx_64.compl_addr_reg_n_0_[4]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(4),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[4]_i_3_n_0\,
      O => D(2)
    );
\s_axis_tx_tdata[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(28),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[60]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[4]_i_3_n_0\
    );
\s_axis_tx_tdata[50]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(2),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(10),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[10]\
    );
\s_axis_tx_tdata[50]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_function_number_o(2),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(42),
      I4 => \s_axis_tx_tdata_reg[50]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_function_number_d_reg[2]\
    );
\s_axis_tx_tdata[51]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(3),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(11),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[11]\
    );
\s_axis_tx_tdata[51]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_device_number_o(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(43),
      I4 => \s_axis_tx_tdata_reg[51]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_device_number_d_reg[0]\
    );
\s_axis_tx_tdata[52]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(4),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(12),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[12]\
    );
\s_axis_tx_tdata[52]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_device_number_o(1),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(44),
      I4 => \s_axis_tx_tdata_reg[52]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_device_number_d_reg[1]\
    );
\s_axis_tx_tdata[53]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(5),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(13),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[13]\
    );
\s_axis_tx_tdata[53]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_device_number_o(2),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(45),
      I4 => \s_axis_tx_tdata_reg[53]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_device_number_d_reg[2]\
    );
\s_axis_tx_tdata[54]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(6),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(14),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[14]\
    );
\s_axis_tx_tdata[54]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_device_number_o(3),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(46),
      I4 => \s_axis_tx_tdata_reg[54]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_device_number_d_reg[3]\
    );
\s_axis_tx_tdata[55]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8888888"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(7),
      I1 => \s_axis_tx_tdata_reg[15]_0\,
      I2 => \m_axis_cc\\.tdata\(15),
      I3 => \m_axis_cc\\.tdata\(24),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[44]_i_2_n_0\,
      O => \Head_reg[15]\
    );
\s_axis_tx_tdata[55]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[55]_i_5_n_0\,
      I1 => cfg_device_number_o(4),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(47),
      I4 => \s_axis_tx_tdata_reg[55]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \cfg_device_number_d_reg[4]\
    );
\s_axis_tx_tdata[55]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I1 => transfer_SM(1),
      I2 => transfer_SM(0),
      I3 => SR(0),
      I4 => \^state\(0),
      I5 => \m_axis_cc\\.tdata\(24),
      O => \s_axis_tx_tdata[55]_i_5_n_0\
    );
\s_axis_tx_tdata[56]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(32),
      I4 => Q(13),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[0]\
    );
\s_axis_tx_tdata[56]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(0),
      I3 => \m_axis_cc\\.tdata\(16),
      I4 => \s_axis_tx_tdata_reg[56]_0\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]\
    );
\s_axis_tx_tdata[57]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(1),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(33),
      I4 => Q(14),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[1]\
    );
\s_axis_tx_tdata[57]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(1),
      I3 => \m_axis_cc\\.tdata\(17),
      I4 => \s_axis_tx_tdata_reg[57]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_0\
    );
\s_axis_tx_tdata[58]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(2),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(34),
      I4 => Q(15),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[2]\
    );
\s_axis_tx_tdata[58]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(2),
      I3 => \m_axis_cc\\.tdata\(18),
      I4 => \s_axis_tx_tdata_reg[58]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_1\
    );
\s_axis_tx_tdata[59]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(3),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(35),
      I4 => Q(16),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[3]\
    );
\s_axis_tx_tdata[59]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(3),
      I3 => \m_axis_cc\\.tdata\(19),
      I4 => \s_axis_tx_tdata_reg[59]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_2\
    );
\s_axis_tx_tdata[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[5]\,
      I1 => \tx_64.compl_addr_reg_n_0_[5]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(5),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[5]_i_3_n_0\,
      O => D(3)
    );
\s_axis_tx_tdata[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(29),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[61]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[5]_i_3_n_0\
    );
\s_axis_tx_tdata[60]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(4),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(36),
      I4 => Q(17),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[4]\
    );
\s_axis_tx_tdata[60]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(4),
      I3 => \m_axis_cc\\.tdata\(20),
      I4 => \s_axis_tx_tdata_reg[60]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_3\
    );
\s_axis_tx_tdata[61]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(5),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(37),
      I4 => Q(18),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[5]\
    );
\s_axis_tx_tdata[61]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(5),
      I3 => \m_axis_cc\\.tdata\(21),
      I4 => \s_axis_tx_tdata_reg[61]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_4\
    );
\s_axis_tx_tdata[62]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(6),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(38),
      I4 => Q(19),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[6]\
    );
\s_axis_tx_tdata[62]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(6),
      I3 => \m_axis_cc\\.tdata\(22),
      I4 => \s_axis_tx_tdata_reg[62]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_5\
    );
\s_axis_tx_tdata[63]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \s_axis_tx_tdata[44]_i_2_n_0\,
      I1 => \m_axis_cc\\.tdata\(7),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I3 => \m_axis_cc\\.tdata\(39),
      I4 => Q(20),
      I5 => \s_axis_tx_tdata_reg[56]\,
      O => \aa256_tdata_ff_reg[7]\
    );
\s_axis_tx_tdata[63]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC840C840C840"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(24),
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => cfg_bus_number_o(7),
      I3 => \m_axis_cc\\.tdata\(23),
      I4 => \s_axis_tx_tdata_reg[63]\,
      I5 => \s_axis_tx_tdata_reg[48]_0\,
      O => \aa256_tdata_ff_reg[24]_6\
    );
\s_axis_tx_tdata[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[6]\,
      I1 => \tx_64.compl_addr_reg_n_0_[6]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(6),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[6]_i_3_n_0\,
      O => D(4)
    );
\s_axis_tx_tdata[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(30),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[62]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[6]_i_3_n_0\
    );
\s_axis_tx_tdata[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata[7]_i_4_n_0\,
      I1 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I2 => p_5_out(7),
      I3 => \s_axis_tx_tdata_reg[7]\,
      I4 => \s_axis_tx_tdata_reg[15]\(0),
      O => \tx_64.compl_len_reg[7]_0\
    );
\s_axis_tx_tdata[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(31),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[63]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[7]_i_4_n_0\
    );
\s_axis_tx_tdata[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[8]\,
      I1 => \tx_64.compl_tag_reg_n_0_[0]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(8),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[8]_i_3_n_0\,
      O => D(5)
    );
\s_axis_tx_tdata[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(16),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[48]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[8]_i_3_n_0\
    );
\s_axis_tx_tdata[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => \s_axis_tx_tdata_reg[9]\,
      I1 => \tx_64.compl_tag_reg_n_0_[1]\,
      I2 => \s_axis_tx_tdata[22]_i_3_n_0\,
      I3 => p_5_out(9),
      I4 => \s_axis_tx_tdata[22]_i_4_n_0\,
      I5 => \s_axis_tx_tdata[9]_i_3_n_0\,
      O => D(6)
    );
\s_axis_tx_tdata[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \m_axis_cc\\.tdata\(17),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\,
      I2 => \^state\(0),
      I3 => \tx_64.compl_data_reg_n_0_[49]\,
      I4 => \s_axis_tx_tdata[29]_i_7_n_0\,
      O => \s_axis_tx_tdata[9]_i_3_n_0\
    );
\s_axis_tx_tkeep[7]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_5_out(45),
      I1 => p_5_out(46),
      I2 => p_5_out(47),
      I3 => \s_axis_tx_tdata_reg[2]_0\,
      O => \tx_64.compl_status_reg[0]_1\
    );
\tx_64.compl_addr[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => in_packet_q,
      I1 => \m_axis_cc\\.tvalid\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I3 => \^state\(0),
      O => compl_addr
    );
\tx_64.compl_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(0),
      Q => \tx_64.compl_addr_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.compl_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(1),
      Q => \tx_64.compl_addr_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.compl_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(2),
      Q => p_0_in,
      R => SR(0)
    );
\tx_64.compl_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(3),
      Q => \tx_64.compl_addr_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.compl_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(4),
      Q => \tx_64.compl_addr_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.compl_addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(5),
      Q => \tx_64.compl_addr_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.compl_addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(6),
      Q => \tx_64.compl_addr_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.compl_at_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(8),
      Q => p_5_out(10),
      R => SR(0)
    );
\tx_64.compl_at_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(9),
      Q => p_5_out(11),
      R => SR(0)
    );
\tx_64.compl_byte_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(16),
      Q => p_5_out(32),
      R => SR(0)
    );
\tx_64.compl_byte_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(26),
      Q => p_5_out(42),
      R => SR(0)
    );
\tx_64.compl_byte_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(27),
      Q => p_5_out(43),
      R => SR(0)
    );
\tx_64.compl_byte_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(17),
      Q => p_5_out(33),
      R => SR(0)
    );
\tx_64.compl_byte_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(18),
      Q => p_5_out(34),
      R => SR(0)
    );
\tx_64.compl_byte_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(19),
      Q => p_5_out(35),
      R => SR(0)
    );
\tx_64.compl_byte_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(20),
      Q => p_5_out(36),
      R => SR(0)
    );
\tx_64.compl_byte_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(21),
      Q => p_5_out(37),
      R => SR(0)
    );
\tx_64.compl_byte_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(22),
      Q => p_5_out(38),
      R => SR(0)
    );
\tx_64.compl_byte_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(23),
      Q => p_5_out(39),
      R => SR(0)
    );
\tx_64.compl_byte_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(24),
      Q => p_5_out(40),
      R => SR(0)
    );
\tx_64.compl_byte_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(25),
      Q => p_5_out(41),
      R => SR(0)
    );
\tx_64.compl_data[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(32),
      O => compl_data(32)
    );
\tx_64.compl_data[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(33),
      O => compl_data(33)
    );
\tx_64.compl_data[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(34),
      O => compl_data(34)
    );
\tx_64.compl_data[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(35),
      O => compl_data(35)
    );
\tx_64.compl_data[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(36),
      O => compl_data(36)
    );
\tx_64.compl_data[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(37),
      O => compl_data(37)
    );
\tx_64.compl_data[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(38),
      O => compl_data(38)
    );
\tx_64.compl_data[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(39),
      O => compl_data(39)
    );
\tx_64.compl_data[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(40),
      O => compl_data(40)
    );
\tx_64.compl_data[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(41),
      O => compl_data(41)
    );
\tx_64.compl_data[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(42),
      O => compl_data(42)
    );
\tx_64.compl_data[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(43),
      O => compl_data(43)
    );
\tx_64.compl_data[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(44),
      O => compl_data(44)
    );
\tx_64.compl_data[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(45),
      O => compl_data(45)
    );
\tx_64.compl_data[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(46),
      O => compl_data(46)
    );
\tx_64.compl_data[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(47),
      O => compl_data(47)
    );
\tx_64.compl_data[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(48),
      O => compl_data(48)
    );
\tx_64.compl_data[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(49),
      O => compl_data(49)
    );
\tx_64.compl_data[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(50),
      O => compl_data(50)
    );
\tx_64.compl_data[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(51),
      O => compl_data(51)
    );
\tx_64.compl_data[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(52),
      O => compl_data(52)
    );
\tx_64.compl_data[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(53),
      O => compl_data(53)
    );
\tx_64.compl_data[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(54),
      O => compl_data(54)
    );
\tx_64.compl_data[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(55),
      O => compl_data(55)
    );
\tx_64.compl_data[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(56),
      O => compl_data(56)
    );
\tx_64.compl_data[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(57),
      O => compl_data(57)
    );
\tx_64.compl_data[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(58),
      O => compl_data(58)
    );
\tx_64.compl_data[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(59),
      O => compl_data(59)
    );
\tx_64.compl_data[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(60),
      O => compl_data(60)
    );
\tx_64.compl_data[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(61),
      O => compl_data(61)
    );
\tx_64.compl_data[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(62),
      O => compl_data(62)
    );
\tx_64.compl_data[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D0"
    )
        port map (
      I0 => p_0_in,
      I1 => \^state\(0),
      I2 => \m_axis_cc\\.tdata\(63),
      O => compl_data(63)
    );
\tx_64.compl_data_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(32),
      Q => \tx_64.compl_data_reg_n_0_[32]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(33),
      Q => \tx_64.compl_data_reg_n_0_[33]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(34),
      Q => \tx_64.compl_data_reg_n_0_[34]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(35),
      Q => \tx_64.compl_data_reg_n_0_[35]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(36),
      Q => \tx_64.compl_data_reg_n_0_[36]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(37),
      Q => \tx_64.compl_data_reg_n_0_[37]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(38),
      Q => \tx_64.compl_data_reg_n_0_[38]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(39),
      Q => \tx_64.compl_data_reg_n_0_[39]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(40),
      Q => \tx_64.compl_data_reg_n_0_[40]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(41),
      Q => \tx_64.compl_data_reg_n_0_[41]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(42),
      Q => \tx_64.compl_data_reg_n_0_[42]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(43),
      Q => \tx_64.compl_data_reg_n_0_[43]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(44),
      Q => \tx_64.compl_data_reg_n_0_[44]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(45),
      Q => \tx_64.compl_data_reg_n_0_[45]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(46),
      Q => \tx_64.compl_data_reg_n_0_[46]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(47),
      Q => \tx_64.compl_data_reg_n_0_[47]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(48),
      Q => \tx_64.compl_data_reg_n_0_[48]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(49),
      Q => \tx_64.compl_data_reg_n_0_[49]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(50),
      Q => \tx_64.compl_data_reg_n_0_[50]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(51),
      Q => \tx_64.compl_data_reg_n_0_[51]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(52),
      Q => \tx_64.compl_data_reg_n_0_[52]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(53),
      Q => \tx_64.compl_data_reg_n_0_[53]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(54),
      Q => \tx_64.compl_data_reg_n_0_[54]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(55),
      Q => \tx_64.compl_data_reg_n_0_[55]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(56),
      Q => \tx_64.compl_data_reg_n_0_[56]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(57),
      Q => \tx_64.compl_data_reg_n_0_[57]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(58),
      Q => \tx_64.compl_data_reg_n_0_[58]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(59),
      Q => \tx_64.compl_data_reg_n_0_[59]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(60),
      Q => \tx_64.compl_data_reg_n_0_[60]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(61),
      Q => \tx_64.compl_data_reg_n_0_[61]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(62),
      Q => \tx_64.compl_data_reg_n_0_[62]\,
      R => SR(0)
    );
\tx_64.compl_data_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \^fsm_sequential_tx_64.state_reg[1]_2\,
      D => compl_data(63),
      Q => \tx_64.compl_data_reg_n_0_[63]\,
      R => SR(0)
    );
\tx_64.compl_ep_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(46),
      Q => p_5_out(14),
      R => SR(0)
    );
\tx_64.compl_len_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(32),
      Q => p_5_out(0),
      R => SR(0)
    );
\tx_64.compl_len_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(33),
      Q => p_5_out(1),
      R => SR(0)
    );
\tx_64.compl_len_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(34),
      Q => p_5_out(2),
      R => SR(0)
    );
\tx_64.compl_len_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(35),
      Q => p_5_out(3),
      R => SR(0)
    );
\tx_64.compl_len_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(36),
      Q => p_5_out(4),
      R => SR(0)
    );
\tx_64.compl_len_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(37),
      Q => p_5_out(5),
      R => SR(0)
    );
\tx_64.compl_len_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(38),
      Q => p_5_out(6),
      R => SR(0)
    );
\tx_64.compl_len_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(39),
      Q => p_5_out(7),
      R => SR(0)
    );
\tx_64.compl_len_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(40),
      Q => p_5_out(8),
      R => SR(0)
    );
\tx_64.compl_len_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(41),
      Q => p_5_out(9),
      R => SR(0)
    );
\tx_64.compl_rid_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(48),
      Q => compl_rid(0),
      R => SR(0)
    );
\tx_64.compl_rid_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(58),
      Q => compl_rid(10),
      R => SR(0)
    );
\tx_64.compl_rid_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(59),
      Q => compl_rid(11),
      R => SR(0)
    );
\tx_64.compl_rid_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(60),
      Q => compl_rid(12),
      R => SR(0)
    );
\tx_64.compl_rid_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(61),
      Q => compl_rid(13),
      R => SR(0)
    );
\tx_64.compl_rid_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(62),
      Q => compl_rid(14),
      R => SR(0)
    );
\tx_64.compl_rid_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(63),
      Q => compl_rid(15),
      R => SR(0)
    );
\tx_64.compl_rid_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(49),
      Q => compl_rid(1),
      R => SR(0)
    );
\tx_64.compl_rid_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(50),
      Q => compl_rid(2),
      R => SR(0)
    );
\tx_64.compl_rid_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(51),
      Q => compl_rid(3),
      R => SR(0)
    );
\tx_64.compl_rid_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(52),
      Q => compl_rid(4),
      R => SR(0)
    );
\tx_64.compl_rid_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(53),
      Q => compl_rid(5),
      R => SR(0)
    );
\tx_64.compl_rid_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(54),
      Q => compl_rid(6),
      R => SR(0)
    );
\tx_64.compl_rid_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(55),
      Q => compl_rid(7),
      R => SR(0)
    );
\tx_64.compl_rid_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(56),
      Q => compl_rid(8),
      R => SR(0)
    );
\tx_64.compl_rid_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(57),
      Q => compl_rid(9),
      R => SR(0)
    );
\tx_64.compl_status_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(43),
      Q => p_5_out(45),
      R => SR(0)
    );
\tx_64.compl_status_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(44),
      Q => p_5_out(46),
      R => SR(0)
    );
\tx_64.compl_status_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_addr,
      D => \m_axis_cc\\.tdata\(45),
      Q => p_5_out(47),
      R => SR(0)
    );
\tx_64.compl_tag[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      O => compl_tag
    );
\tx_64.compl_tag_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(0),
      Q => \tx_64.compl_tag_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(1),
      Q => \tx_64.compl_tag_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(2),
      Q => \tx_64.compl_tag_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(3),
      Q => \tx_64.compl_tag_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(4),
      Q => \tx_64.compl_tag_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(5),
      Q => \tx_64.compl_tag_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(6),
      Q => \tx_64.compl_tag_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.compl_tag_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => compl_tag,
      D => \m_axis_cc\\.tdata\(7),
      Q => \tx_64.compl_tag_reg_n_0_[7]\,
      R => SR(0)
    );
udma_wrapper_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F1FFF1F1F1F1F1F1"
    )
        port map (
      I0 => \^state\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_2\,
      I2 => SR(0),
      I3 => transfer_SM(1),
      I4 => transfer_SM(0),
      I5 => s_axis_tx_tready,
      O => \m_axis_cc\\.tready\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_tgt_req is
  port (
    req_mesg : out STD_LOGIC;
    in_packet_q : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_tready : out STD_LOGIC;
    \FSM_sequential_tx_64.state_reg[0]_0\ : out STD_LOGIC;
    in_packet_q_reg_0 : out STD_LOGIC;
    \s_axis_cq\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_cq\\.tuser\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \s_axis_cq\\.tvalid\ : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_out : in STD_LOGIC;
    req_OBFF : in STD_LOGIC;
    req_LTR : in STD_LOGIC;
    req_ATS : in STD_LOGIC;
    req_VDM : in STD_LOGIC;
    \tx_64.req_rid_reg[15]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \tx_64.req_tag_reg[0]_0\ : in STD_LOGIC;
    \sop__0\ : in STD_LOGIC;
    \s_axis_cq\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_tlast : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \tx_64.req_msg_code_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \tx_64.req_bar_id_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_tgt_req : entity is "xdma_0_tgt_req";
end xdma_0_xdma_0_tgt_req;

architecture STRUCTURE of xdma_0_xdma_0_tgt_req is
  signal \^fsm_sequential_tx_64.state_reg[0]_0\ : STD_LOGIC;
  signal \^fsm_sequential_tx_64.state_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal in130 : STD_LOGIC;
  signal \^in_packet_q\ : STD_LOGIC;
  signal \in_packet_q_i_1__2_n_0\ : STD_LOGIC;
  signal in_packet_q_i_2_n_0 : STD_LOGIC;
  signal in_packet_q_i_3_n_0 : STD_LOGIC;
  signal in_packet_q_i_4_n_0 : STD_LOGIC;
  signal \^m_axis_tready\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in22_in : STD_LOGIC;
  signal req_4dw : STD_LOGIC;
  signal \req_addr1__0\ : STD_LOGIC;
  signal req_at : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal req_attr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_data : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal req_fmt : STD_LOGIC_VECTOR ( 1 to 1 );
  signal req_len : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \^req_mesg\ : STD_LOGIC;
  signal req_rid : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal req_tag : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal req_tc : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_type : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_wr : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal state : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal tgt_brdg_fifo_inst_i_2_n_0 : STD_LOGIC;
  signal \tx_64.req_4dw_i_1__0_n_0\ : STD_LOGIC;
  signal \tx_64.req_addr[2]_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_at_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_at_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_attr_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_attr_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_attr_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_bar_id_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_bar_id_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_bar_id_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_data[31]_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[16]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[17]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[18]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[19]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[20]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[21]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[22]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[23]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[24]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[25]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[26]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[27]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[28]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[29]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[30]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[31]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.req_data_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_64.req_fbe_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_fbe_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_fbe_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_fbe_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.req_len_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_64.req_mesg_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_msg_code_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[10]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[11]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[12]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[13]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[14]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[15]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_64.req_rid_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_64.req_tag_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_64.req_tc_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_tc_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_tc_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_type_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_64.req_type_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_64.req_type_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_64.req_wr_i_1_n_0\ : STD_LOGIC;
  signal \tx_64.req_wr_reg_n_0\ : STD_LOGIC;
  signal udma_wrapper_i_170_n_0 : STD_LOGIC;
  signal udma_wrapper_i_171_n_0 : STD_LOGIC;
  signal udma_wrapper_i_172_n_0 : STD_LOGIC;
  signal udma_wrapper_i_173_n_0 : STD_LOGIC;
  signal udma_wrapper_i_174_n_0 : STD_LOGIC;
  signal udma_wrapper_i_175_n_0 : STD_LOGIC;
  signal udma_wrapper_i_176_n_0 : STD_LOGIC;
  signal udma_wrapper_i_177_n_0 : STD_LOGIC;
  signal udma_wrapper_i_178_n_0 : STD_LOGIC;
  signal udma_wrapper_i_179_n_0 : STD_LOGIC;
  signal udma_wrapper_i_180_n_0 : STD_LOGIC;
  signal udma_wrapper_i_181_n_0 : STD_LOGIC;
  signal udma_wrapper_i_182_n_0 : STD_LOGIC;
  signal udma_wrapper_i_183_n_0 : STD_LOGIC;
  signal udma_wrapper_i_184_n_0 : STD_LOGIC;
  signal udma_wrapper_i_185_n_0 : STD_LOGIC;
  signal udma_wrapper_i_186_n_0 : STD_LOGIC;
  signal udma_wrapper_i_187_n_0 : STD_LOGIC;
  signal udma_wrapper_i_188_n_0 : STD_LOGIC;
  signal udma_wrapper_i_189_n_0 : STD_LOGIC;
  signal udma_wrapper_i_190_n_0 : STD_LOGIC;
  signal udma_wrapper_i_191_n_0 : STD_LOGIC;
  signal udma_wrapper_i_192_n_0 : STD_LOGIC;
  signal udma_wrapper_i_193_n_0 : STD_LOGIC;
  signal udma_wrapper_i_194_n_0 : STD_LOGIC;
  signal udma_wrapper_i_195_n_0 : STD_LOGIC;
  signal udma_wrapper_i_196_n_0 : STD_LOGIC;
  signal udma_wrapper_i_197_n_0 : STD_LOGIC;
  signal udma_wrapper_i_198_n_0 : STD_LOGIC;
  signal udma_wrapper_i_199_n_0 : STD_LOGIC;
  signal udma_wrapper_i_200_n_0 : STD_LOGIC;
  signal udma_wrapper_i_201_n_0 : STD_LOGIC;
  signal udma_wrapper_i_202_n_0 : STD_LOGIC;
  signal udma_wrapper_i_203_n_0 : STD_LOGIC;
  signal udma_wrapper_i_204_n_0 : STD_LOGIC;
  signal udma_wrapper_i_205_n_0 : STD_LOGIC;
  signal udma_wrapper_i_206_n_0 : STD_LOGIC;
  signal udma_wrapper_i_207_n_0 : STD_LOGIC;
  signal udma_wrapper_i_208_n_0 : STD_LOGIC;
  signal udma_wrapper_i_209_n_0 : STD_LOGIC;
  signal udma_wrapper_i_210_n_0 : STD_LOGIC;
  signal udma_wrapper_i_211_n_0 : STD_LOGIC;
  signal udma_wrapper_i_212_n_0 : STD_LOGIC;
  signal udma_wrapper_i_213_n_0 : STD_LOGIC;
  signal udma_wrapper_i_214_n_0 : STD_LOGIC;
  signal udma_wrapper_i_215_n_0 : STD_LOGIC;
  signal udma_wrapper_i_216_n_0 : STD_LOGIC;
  signal udma_wrapper_i_217_n_0 : STD_LOGIC;
  signal udma_wrapper_i_218_n_0 : STD_LOGIC;
  signal udma_wrapper_i_219_n_0 : STD_LOGIC;
  signal udma_wrapper_i_220_n_0 : STD_LOGIC;
  signal udma_wrapper_i_221_n_0 : STD_LOGIC;
  signal udma_wrapper_i_222_n_0 : STD_LOGIC;
  signal udma_wrapper_i_223_n_0 : STD_LOGIC;
  signal udma_wrapper_i_224_n_0 : STD_LOGIC;
  signal udma_wrapper_i_225_n_0 : STD_LOGIC;
  signal udma_wrapper_i_226_n_0 : STD_LOGIC;
  signal udma_wrapper_i_227_n_0 : STD_LOGIC;
  signal udma_wrapper_i_228_n_0 : STD_LOGIC;
  signal udma_wrapper_i_229_n_0 : STD_LOGIC;
  signal udma_wrapper_i_230_n_0 : STD_LOGIC;
  signal udma_wrapper_i_231_n_0 : STD_LOGIC;
  signal udma_wrapper_i_232_n_0 : STD_LOGIC;
  signal udma_wrapper_i_233_n_0 : STD_LOGIC;
  signal udma_wrapper_i_234_n_0 : STD_LOGIC;
  signal udma_wrapper_i_235_n_0 : STD_LOGIC;
  signal udma_wrapper_i_236_n_0 : STD_LOGIC;
  signal udma_wrapper_i_246_n_0 : STD_LOGIC;
  signal udma_wrapper_i_247_n_0 : STD_LOGIC;
  signal udma_wrapper_i_248_n_0 : STD_LOGIC;
  signal udma_wrapper_i_249_n_0 : STD_LOGIC;
  signal udma_wrapper_i_250_n_0 : STD_LOGIC;
  signal udma_wrapper_i_251_n_0 : STD_LOGIC;
  signal udma_wrapper_i_252_n_0 : STD_LOGIC;
  signal udma_wrapper_i_262_n_0 : STD_LOGIC;
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[0]\ : label is "RX_DW2:10,RX_WAIT:11,RX_IDLE:00,RX_DW0_DW1:01";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_64.state_reg[1]\ : label is "RX_DW2:10,RX_WAIT:11,RX_IDLE:00,RX_DW0_DW1:01";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of in_packet_q_i_4 : label is "soft_lutpair2115";
  attribute SOFT_HLUTNM of tgt_brdg_fifo_inst_i_2 : label is "soft_lutpair2117";
  attribute SOFT_HLUTNM of \tx_64.req_4dw_i_1__0\ : label is "soft_lutpair2116";
  attribute SOFT_HLUTNM of \tx_64.req_ATS_i_3\ : label is "soft_lutpair2091";
  attribute SOFT_HLUTNM of \tx_64.req_addr[2]_i_2\ : label is "soft_lutpair2117";
  attribute SOFT_HLUTNM of \tx_64.req_at[0]_i_1\ : label is "soft_lutpair2109";
  attribute SOFT_HLUTNM of \tx_64.req_at[1]_i_1__0\ : label is "soft_lutpair2109";
  attribute SOFT_HLUTNM of \tx_64.req_attr[0]_i_1\ : label is "soft_lutpair2110";
  attribute SOFT_HLUTNM of \tx_64.req_attr[1]_i_1\ : label is "soft_lutpair2110";
  attribute SOFT_HLUTNM of \tx_64.req_attr[2]_i_1\ : label is "soft_lutpair2111";
  attribute SOFT_HLUTNM of \tx_64.req_fmt[1]_i_1\ : label is "soft_lutpair2114";
  attribute SOFT_HLUTNM of \tx_64.req_len[0]_i_1\ : label is "soft_lutpair2104";
  attribute SOFT_HLUTNM of \tx_64.req_len[1]_i_1\ : label is "soft_lutpair2104";
  attribute SOFT_HLUTNM of \tx_64.req_len[2]_i_1\ : label is "soft_lutpair2105";
  attribute SOFT_HLUTNM of \tx_64.req_len[3]_i_1\ : label is "soft_lutpair2105";
  attribute SOFT_HLUTNM of \tx_64.req_len[4]_i_1\ : label is "soft_lutpair2106";
  attribute SOFT_HLUTNM of \tx_64.req_len[5]_i_1\ : label is "soft_lutpair2106";
  attribute SOFT_HLUTNM of \tx_64.req_len[6]_i_1\ : label is "soft_lutpair2107";
  attribute SOFT_HLUTNM of \tx_64.req_len[7]_i_1\ : label is "soft_lutpair2107";
  attribute SOFT_HLUTNM of \tx_64.req_len[8]_i_1\ : label is "soft_lutpair2108";
  attribute SOFT_HLUTNM of \tx_64.req_len[9]_i_1__0\ : label is "soft_lutpair2108";
  attribute SOFT_HLUTNM of \tx_64.req_mesg_i_2\ : label is "soft_lutpair2091";
  attribute SOFT_HLUTNM of \tx_64.req_rid[0]_i_1\ : label is "soft_lutpair2096";
  attribute SOFT_HLUTNM of \tx_64.req_rid[10]_i_1\ : label is "soft_lutpair2101";
  attribute SOFT_HLUTNM of \tx_64.req_rid[11]_i_1\ : label is "soft_lutpair2101";
  attribute SOFT_HLUTNM of \tx_64.req_rid[12]_i_1\ : label is "soft_lutpair2102";
  attribute SOFT_HLUTNM of \tx_64.req_rid[13]_i_1\ : label is "soft_lutpair2102";
  attribute SOFT_HLUTNM of \tx_64.req_rid[14]_i_1\ : label is "soft_lutpair2103";
  attribute SOFT_HLUTNM of \tx_64.req_rid[15]_i_1\ : label is "soft_lutpair2103";
  attribute SOFT_HLUTNM of \tx_64.req_rid[1]_i_1\ : label is "soft_lutpair2096";
  attribute SOFT_HLUTNM of \tx_64.req_rid[2]_i_1\ : label is "soft_lutpair2097";
  attribute SOFT_HLUTNM of \tx_64.req_rid[3]_i_1\ : label is "soft_lutpair2097";
  attribute SOFT_HLUTNM of \tx_64.req_rid[4]_i_1\ : label is "soft_lutpair2098";
  attribute SOFT_HLUTNM of \tx_64.req_rid[5]_i_1\ : label is "soft_lutpair2098";
  attribute SOFT_HLUTNM of \tx_64.req_rid[6]_i_1\ : label is "soft_lutpair2099";
  attribute SOFT_HLUTNM of \tx_64.req_rid[7]_i_1\ : label is "soft_lutpair2099";
  attribute SOFT_HLUTNM of \tx_64.req_rid[8]_i_1\ : label is "soft_lutpair2100";
  attribute SOFT_HLUTNM of \tx_64.req_rid[9]_i_1\ : label is "soft_lutpair2100";
  attribute SOFT_HLUTNM of \tx_64.req_tag[0]_i_1\ : label is "soft_lutpair2092";
  attribute SOFT_HLUTNM of \tx_64.req_tag[1]_i_1\ : label is "soft_lutpair2092";
  attribute SOFT_HLUTNM of \tx_64.req_tag[2]_i_1\ : label is "soft_lutpair2093";
  attribute SOFT_HLUTNM of \tx_64.req_tag[3]_i_1\ : label is "soft_lutpair2093";
  attribute SOFT_HLUTNM of \tx_64.req_tag[4]_i_1\ : label is "soft_lutpair2094";
  attribute SOFT_HLUTNM of \tx_64.req_tag[5]_i_1\ : label is "soft_lutpair2094";
  attribute SOFT_HLUTNM of \tx_64.req_tag[6]_i_1\ : label is "soft_lutpair2095";
  attribute SOFT_HLUTNM of \tx_64.req_tag[7]_i_1\ : label is "soft_lutpair2095";
  attribute SOFT_HLUTNM of \tx_64.req_tc[0]_i_1\ : label is "soft_lutpair2111";
  attribute SOFT_HLUTNM of \tx_64.req_tc[1]_i_1\ : label is "soft_lutpair2112";
  attribute SOFT_HLUTNM of \tx_64.req_tc[2]_i_1\ : label is "soft_lutpair2112";
  attribute SOFT_HLUTNM of \tx_64.req_type[0]_i_1\ : label is "soft_lutpair2113";
  attribute SOFT_HLUTNM of \tx_64.req_type[1]_i_1\ : label is "soft_lutpair2113";
  attribute SOFT_HLUTNM of \tx_64.req_type[2]_i_1\ : label is "soft_lutpair2114";
  attribute SOFT_HLUTNM of \tx_64.req_wr_i_1\ : label is "soft_lutpair2116";
  attribute SOFT_HLUTNM of udma_wrapper_i_138 : label is "soft_lutpair2088";
  attribute SOFT_HLUTNM of udma_wrapper_i_144 : label is "soft_lutpair2090";
  attribute SOFT_HLUTNM of udma_wrapper_i_221 : label is "soft_lutpair2088";
  attribute SOFT_HLUTNM of udma_wrapper_i_234 : label is "soft_lutpair2089";
  attribute SOFT_HLUTNM of udma_wrapper_i_235 : label is "soft_lutpair2087";
  attribute SOFT_HLUTNM of udma_wrapper_i_246 : label is "soft_lutpair2115";
  attribute SOFT_HLUTNM of udma_wrapper_i_247 : label is "soft_lutpair2089";
  attribute SOFT_HLUTNM of udma_wrapper_i_248 : label is "soft_lutpair2090";
  attribute SOFT_HLUTNM of udma_wrapper_i_250 : label is "soft_lutpair2087";
begin
  \FSM_sequential_tx_64.state_reg[0]_0\ <= \^fsm_sequential_tx_64.state_reg[0]_0\;
  \FSM_sequential_tx_64.state_reg[1]_0\(0) <= \^fsm_sequential_tx_64.state_reg[1]_0\(0);
  in_packet_q <= \^in_packet_q\;
  m_axis_tready <= \^m_axis_tready\;
  req_mesg <= \^req_mesg\;
\FSM_sequential_tx_64.state[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF570F00F0F0FFF0"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[0]_0\,
      I1 => tgt_brdg_fifo_inst_i_2_n_0,
      I2 => state(0),
      I3 => \sop__0\,
      I4 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I5 => \s_axis_cq\\.tready\(0),
      O => \state__0\(0)
    );
\FSM_sequential_tx_64.state[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6C646464ECECECEC"
    )
        port map (
      I0 => \s_axis_cq\\.tready\(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => state(0),
      I3 => p_0_in22_in,
      I4 => in130,
      I5 => \^fsm_sequential_tx_64.state_reg[0]_0\,
      O => \state__0\(1)
    );
\FSM_sequential_tx_64.state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \state__0\(0),
      Q => state(0),
      R => SR(0)
    );
\FSM_sequential_tx_64.state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \state__0\(1),
      Q => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      R => SR(0)
    );
\in_packet_q_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAAAAAAAAAAAAA"
    )
        port map (
      I0 => in_packet_q_i_2_n_0,
      I1 => in130,
      I2 => p_0_in22_in,
      I3 => \tx_64.req_wr_reg_n_0\,
      I4 => udma_wrapper_i_180_n_0,
      I5 => in_packet_q_i_3_n_0,
      O => \in_packet_q_i_1__2_n_0\
    );
in_packet_q_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222200002FFF0000"
    )
        port map (
      I0 => in_packet_q_i_4_n_0,
      I1 => \s_axis_cq\\.tready\(0),
      I2 => m_axis_tlast,
      I3 => \tx_64.req_tag_reg[0]_0\,
      I4 => in_packet_q_i_3_n_0,
      I5 => SR(0),
      O => in_packet_q_i_2_n_0
    );
in_packet_q_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \tx_64.req_tag_reg[0]_0\,
      I1 => \^m_axis_tready\,
      I2 => \^in_packet_q\,
      O => in_packet_q_i_3_n_0
    );
in_packet_q_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => SR(0),
      I2 => state(0),
      O => in_packet_q_i_4_n_0
    );
in_packet_q_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \in_packet_q_i_1__2_n_0\,
      Q => \^in_packet_q\,
      R => '0'
    );
tgt_brdg_fifo_inst_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBBFB1111"
    )
        port map (
      I0 => state(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => tgt_brdg_fifo_inst_i_2_n_0,
      I3 => \tx_64.req_wr_reg_n_0\,
      I4 => \s_axis_cq\\.tready\(0),
      I5 => SR(0),
      O => \^m_axis_tready\
    );
tgt_brdg_fifo_inst_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => p_0_in22_in,
      I1 => in130,
      O => tgt_brdg_fifo_inst_i_2_n_0
    );
\tx_64.req_4dw_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(29),
      I1 => req_wr,
      I2 => req_4dw,
      O => \tx_64.req_4dw_i_1__0_n_0\
    );
\tx_64.req_4dw_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \tx_64.req_4dw_i_1__0_n_0\,
      Q => req_4dw,
      R => SR(0)
    );
\tx_64.req_ATS_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \^in_packet_q\,
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => in_packet_q_reg_0
    );
\tx_64.req_ATS_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_ATS,
      Q => sel0(2),
      R => SR(0)
    );
\tx_64.req_LTR_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_LTR,
      Q => sel0(1),
      R => SR(0)
    );
\tx_64.req_OBFF_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_OBFF,
      Q => sel0(0),
      R => SR(0)
    );
\tx_64.req_VDM_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_VDM,
      Q => sel0(3),
      R => SR(0)
    );
\tx_64.req_addr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BB8888B8888888"
    )
        port map (
      I0 => p_0_in,
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => \tx_64.req_rid_reg[15]_0\(34),
      I3 => \req_addr1__0\,
      I4 => state(0),
      I5 => \tx_64.req_rid_reg[15]_0\(2),
      O => \tx_64.req_addr[2]_i_1_n_0\
    );
\tx_64.req_addr[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => req_4dw,
      I1 => in130,
      I2 => p_0_in22_in,
      O => \req_addr1__0\
    );
\tx_64.req_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \tx_64.req_addr[2]_i_1_n_0\,
      Q => p_0_in,
      R => SR(0)
    );
\tx_64.req_at[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(10),
      O => req_at(0)
    );
\tx_64.req_at[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(11),
      O => req_at(1)
    );
\tx_64.req_at_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_at(0),
      Q => \tx_64.req_at_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_at_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_at(1),
      Q => \tx_64.req_at_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_attr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(12),
      O => req_attr(0)
    );
\tx_64.req_attr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(13),
      O => req_attr(1)
    );
\tx_64.req_attr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(18),
      O => req_attr(2)
    );
\tx_64.req_attr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_attr(0),
      Q => \tx_64.req_attr_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_attr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_attr(1),
      Q => \tx_64.req_attr_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_attr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_attr(2),
      Q => \tx_64.req_attr_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_bar_id_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_bar_id_reg[2]_0\(0),
      Q => \tx_64.req_bar_id_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_bar_id_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_bar_id_reg[2]_0\(1),
      Q => \tx_64.req_bar_id_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_bar_id_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_bar_id_reg[2]_0\(2),
      Q => \tx_64.req_bar_id_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_data[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(0),
      I1 => \tx_64.req_rid_reg[15]_0\(32),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(0)
    );
\tx_64.req_data[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(10),
      I1 => \tx_64.req_rid_reg[15]_0\(42),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(10)
    );
\tx_64.req_data[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(11),
      I1 => \tx_64.req_rid_reg[15]_0\(43),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(11)
    );
\tx_64.req_data[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(12),
      I1 => \tx_64.req_rid_reg[15]_0\(44),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(12)
    );
\tx_64.req_data[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(13),
      I1 => \tx_64.req_rid_reg[15]_0\(45),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(13)
    );
\tx_64.req_data[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(14),
      I1 => \tx_64.req_rid_reg[15]_0\(46),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(14)
    );
\tx_64.req_data[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(15),
      I1 => \tx_64.req_rid_reg[15]_0\(47),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(15)
    );
\tx_64.req_data[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(16),
      I1 => \tx_64.req_rid_reg[15]_0\(48),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(16)
    );
\tx_64.req_data[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(17),
      I1 => \tx_64.req_rid_reg[15]_0\(49),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(17)
    );
\tx_64.req_data[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(18),
      I1 => \tx_64.req_rid_reg[15]_0\(50),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(18)
    );
\tx_64.req_data[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(19),
      I1 => \tx_64.req_rid_reg[15]_0\(51),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(19)
    );
\tx_64.req_data[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(1),
      I1 => \tx_64.req_rid_reg[15]_0\(33),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(1)
    );
\tx_64.req_data[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(20),
      I1 => \tx_64.req_rid_reg[15]_0\(52),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(20)
    );
\tx_64.req_data[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(21),
      I1 => \tx_64.req_rid_reg[15]_0\(53),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(21)
    );
\tx_64.req_data[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(22),
      I1 => \tx_64.req_rid_reg[15]_0\(54),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(22)
    );
\tx_64.req_data[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(23),
      I1 => \tx_64.req_rid_reg[15]_0\(55),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(23)
    );
\tx_64.req_data[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(24),
      I1 => \tx_64.req_rid_reg[15]_0\(56),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(24)
    );
\tx_64.req_data[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(25),
      I1 => \tx_64.req_rid_reg[15]_0\(57),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(25)
    );
\tx_64.req_data[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(26),
      I1 => \tx_64.req_rid_reg[15]_0\(58),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(26)
    );
\tx_64.req_data[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(27),
      I1 => \tx_64.req_rid_reg[15]_0\(59),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(27)
    );
\tx_64.req_data[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(28),
      I1 => \tx_64.req_rid_reg[15]_0\(60),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(28)
    );
\tx_64.req_data[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(29),
      I1 => \tx_64.req_rid_reg[15]_0\(61),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(29)
    );
\tx_64.req_data[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(2),
      I1 => \tx_64.req_rid_reg[15]_0\(34),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(2)
    );
\tx_64.req_data[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(30),
      I1 => \tx_64.req_rid_reg[15]_0\(62),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(30)
    );
\tx_64.req_data[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FFEA00"
    )
        port map (
      I0 => req_4dw,
      I1 => in130,
      I2 => p_0_in22_in,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I4 => state(0),
      O => \tx_64.req_data[31]_i_1_n_0\
    );
\tx_64.req_data[31]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(31),
      I1 => \tx_64.req_rid_reg[15]_0\(63),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(31)
    );
\tx_64.req_data[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(3),
      I1 => \tx_64.req_rid_reg[15]_0\(35),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(3)
    );
\tx_64.req_data[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(4),
      I1 => \tx_64.req_rid_reg[15]_0\(36),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(4)
    );
\tx_64.req_data[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(5),
      I1 => \tx_64.req_rid_reg[15]_0\(37),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(5)
    );
\tx_64.req_data[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(6),
      I1 => \tx_64.req_rid_reg[15]_0\(38),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(6)
    );
\tx_64.req_data[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(7),
      I1 => \tx_64.req_rid_reg[15]_0\(39),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(7)
    );
\tx_64.req_data[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(8),
      I1 => \tx_64.req_rid_reg[15]_0\(40),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(8)
    );
\tx_64.req_data[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000CCC"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(9),
      I1 => \tx_64.req_rid_reg[15]_0\(41),
      I2 => p_0_in22_in,
      I3 => in130,
      I4 => req_4dw,
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_data(9)
    );
\tx_64.req_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(0),
      Q => \tx_64.req_data_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(10),
      Q => \tx_64.req_data_reg_n_0_[10]\,
      R => SR(0)
    );
\tx_64.req_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(11),
      Q => \tx_64.req_data_reg_n_0_[11]\,
      R => SR(0)
    );
\tx_64.req_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(12),
      Q => \tx_64.req_data_reg_n_0_[12]\,
      R => SR(0)
    );
\tx_64.req_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(13),
      Q => \tx_64.req_data_reg_n_0_[13]\,
      R => SR(0)
    );
\tx_64.req_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(14),
      Q => \tx_64.req_data_reg_n_0_[14]\,
      R => SR(0)
    );
\tx_64.req_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(15),
      Q => \tx_64.req_data_reg_n_0_[15]\,
      R => SR(0)
    );
\tx_64.req_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(16),
      Q => \tx_64.req_data_reg_n_0_[16]\,
      R => SR(0)
    );
\tx_64.req_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(17),
      Q => \tx_64.req_data_reg_n_0_[17]\,
      R => SR(0)
    );
\tx_64.req_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(18),
      Q => \tx_64.req_data_reg_n_0_[18]\,
      R => SR(0)
    );
\tx_64.req_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(19),
      Q => \tx_64.req_data_reg_n_0_[19]\,
      R => SR(0)
    );
\tx_64.req_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(1),
      Q => \tx_64.req_data_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(20),
      Q => \tx_64.req_data_reg_n_0_[20]\,
      R => SR(0)
    );
\tx_64.req_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(21),
      Q => \tx_64.req_data_reg_n_0_[21]\,
      R => SR(0)
    );
\tx_64.req_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(22),
      Q => \tx_64.req_data_reg_n_0_[22]\,
      R => SR(0)
    );
\tx_64.req_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(23),
      Q => \tx_64.req_data_reg_n_0_[23]\,
      R => SR(0)
    );
\tx_64.req_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(24),
      Q => \tx_64.req_data_reg_n_0_[24]\,
      R => SR(0)
    );
\tx_64.req_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(25),
      Q => \tx_64.req_data_reg_n_0_[25]\,
      R => SR(0)
    );
\tx_64.req_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(26),
      Q => \tx_64.req_data_reg_n_0_[26]\,
      R => SR(0)
    );
\tx_64.req_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(27),
      Q => \tx_64.req_data_reg_n_0_[27]\,
      R => SR(0)
    );
\tx_64.req_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(28),
      Q => \tx_64.req_data_reg_n_0_[28]\,
      R => SR(0)
    );
\tx_64.req_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(29),
      Q => \tx_64.req_data_reg_n_0_[29]\,
      R => SR(0)
    );
\tx_64.req_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(2),
      Q => \tx_64.req_data_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(30),
      Q => \tx_64.req_data_reg_n_0_[30]\,
      R => SR(0)
    );
\tx_64.req_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(31),
      Q => \tx_64.req_data_reg_n_0_[31]\,
      R => SR(0)
    );
\tx_64.req_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(3),
      Q => \tx_64.req_data_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(4),
      Q => \tx_64.req_data_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(5),
      Q => \tx_64.req_data_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(6),
      Q => \tx_64.req_data_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(7),
      Q => \tx_64.req_data_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(8),
      Q => \tx_64.req_data_reg_n_0_[8]\,
      R => SR(0)
    );
\tx_64.req_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_data[31]_i_1_n_0\,
      D => req_data(9),
      Q => \tx_64.req_data_reg_n_0_[9]\,
      R => SR(0)
    );
\tx_64.req_fbe_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => D(0),
      Q => \tx_64.req_fbe_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_fbe_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => D(1),
      Q => \tx_64.req_fbe_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_fbe_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => D(2),
      Q => \tx_64.req_fbe_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_fbe_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => D(3),
      Q => \tx_64.req_fbe_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_fmt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(30),
      O => req_fmt(1)
    );
\tx_64.req_fmt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_fmt(1),
      Q => p_0_in22_in,
      R => SR(0)
    );
\tx_64.req_len[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(0),
      O => req_len(0)
    );
\tx_64.req_len[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(1),
      O => req_len(1)
    );
\tx_64.req_len[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(2),
      O => req_len(2)
    );
\tx_64.req_len[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(3),
      O => req_len(3)
    );
\tx_64.req_len[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(4),
      O => req_len(4)
    );
\tx_64.req_len[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(5),
      O => req_len(5)
    );
\tx_64.req_len[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(6),
      O => req_len(6)
    );
\tx_64.req_len[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(7),
      O => req_len(7)
    );
\tx_64.req_len[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(8),
      O => req_len(8)
    );
\tx_64.req_len[9]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(9),
      O => req_len(9)
    );
\tx_64.req_len_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(0),
      Q => \tx_64.req_len_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_len_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(1),
      Q => \tx_64.req_len_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_len_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(2),
      Q => \tx_64.req_len_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_len_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(3),
      Q => \tx_64.req_len_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_len_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(4),
      Q => \tx_64.req_len_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_len_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(5),
      Q => \tx_64.req_len_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_len_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(6),
      Q => \tx_64.req_len_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_len_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(7),
      Q => \tx_64.req_len_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_len_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(8),
      Q => \tx_64.req_len_reg_n_0_[8]\,
      R => SR(0)
    );
\tx_64.req_len_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_len(9),
      Q => \tx_64.req_len_reg_n_0_[9]\,
      R => SR(0)
    );
\tx_64.req_mesg_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"808000008000FFFF"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[0]_0\,
      I1 => \s_axis_cq\\.tready\(0),
      I2 => \sop__0\,
      I3 => tgt_brdg_fifo_inst_i_2_n_0,
      I4 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I5 => state(0),
      O => \tx_64.req_mesg_i_1_n_0\
    );
\tx_64.req_mesg_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(28),
      O => \^req_mesg\
    );
\tx_64.req_mesg_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \^req_mesg\,
      Q => in130,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(0),
      Q => \tx_64.req_msg_code_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(1),
      Q => \tx_64.req_msg_code_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(2),
      Q => \tx_64.req_msg_code_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(3),
      Q => \tx_64.req_msg_code_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(4),
      Q => \tx_64.req_msg_code_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(5),
      Q => \tx_64.req_msg_code_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(6),
      Q => \tx_64.req_msg_code_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_msg_code_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => \tx_64.req_msg_code_reg[7]_0\(7),
      Q => \tx_64.req_msg_code_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_rid[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(48),
      O => req_rid(0)
    );
\tx_64.req_rid[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(58),
      O => req_rid(10)
    );
\tx_64.req_rid[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(59),
      O => req_rid(11)
    );
\tx_64.req_rid[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(60),
      O => req_rid(12)
    );
\tx_64.req_rid[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(61),
      O => req_rid(13)
    );
\tx_64.req_rid[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(62),
      O => req_rid(14)
    );
\tx_64.req_rid[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(63),
      O => req_rid(15)
    );
\tx_64.req_rid[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(49),
      O => req_rid(1)
    );
\tx_64.req_rid[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(50),
      O => req_rid(2)
    );
\tx_64.req_rid[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(51),
      O => req_rid(3)
    );
\tx_64.req_rid[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(52),
      O => req_rid(4)
    );
\tx_64.req_rid[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(53),
      O => req_rid(5)
    );
\tx_64.req_rid[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(54),
      O => req_rid(6)
    );
\tx_64.req_rid[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(55),
      O => req_rid(7)
    );
\tx_64.req_rid[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(56),
      O => req_rid(8)
    );
\tx_64.req_rid[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(57),
      O => req_rid(9)
    );
\tx_64.req_rid_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(0),
      Q => \tx_64.req_rid_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(10),
      Q => \tx_64.req_rid_reg_n_0_[10]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(11),
      Q => \tx_64.req_rid_reg_n_0_[11]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(12),
      Q => \tx_64.req_rid_reg_n_0_[12]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(13),
      Q => \tx_64.req_rid_reg_n_0_[13]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(14),
      Q => \tx_64.req_rid_reg_n_0_[14]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(15),
      Q => \tx_64.req_rid_reg_n_0_[15]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(1),
      Q => \tx_64.req_rid_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(2),
      Q => \tx_64.req_rid_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(3),
      Q => \tx_64.req_rid_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(4),
      Q => \tx_64.req_rid_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(5),
      Q => \tx_64.req_rid_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(6),
      Q => \tx_64.req_rid_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(7),
      Q => \tx_64.req_rid_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(8),
      Q => \tx_64.req_rid_reg_n_0_[8]\,
      R => SR(0)
    );
\tx_64.req_rid_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_rid(9),
      Q => \tx_64.req_rid_reg_n_0_[9]\,
      R => SR(0)
    );
\tx_64.req_tag[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(40),
      O => req_tag(0)
    );
\tx_64.req_tag[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(41),
      O => req_tag(1)
    );
\tx_64.req_tag[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(42),
      O => req_tag(2)
    );
\tx_64.req_tag[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(43),
      O => req_tag(3)
    );
\tx_64.req_tag[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(44),
      O => req_tag(4)
    );
\tx_64.req_tag[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(45),
      O => req_tag(5)
    );
\tx_64.req_tag[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(46),
      O => req_tag(6)
    );
\tx_64.req_tag[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(47),
      O => req_tag(7)
    );
\tx_64.req_tag_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(0),
      Q => \tx_64.req_tag_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(1),
      Q => \tx_64.req_tag_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(2),
      Q => \tx_64.req_tag_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(3),
      Q => \tx_64.req_tag_reg_n_0_[3]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(4),
      Q => \tx_64.req_tag_reg_n_0_[4]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(5),
      Q => \tx_64.req_tag_reg_n_0_[5]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(6),
      Q => \tx_64.req_tag_reg_n_0_[6]\,
      R => SR(0)
    );
\tx_64.req_tag_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tag(7),
      Q => \tx_64.req_tag_reg_n_0_[7]\,
      R => SR(0)
    );
\tx_64.req_tc[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(20),
      O => req_tc(0)
    );
\tx_64.req_tc[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(21),
      O => req_tc(1)
    );
\tx_64.req_tc[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(22),
      O => req_tc(2)
    );
\tx_64.req_tc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tc(0),
      Q => \tx_64.req_tc_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_tc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tc(1),
      Q => \tx_64.req_tc_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_tc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_tc(2),
      Q => \tx_64.req_tc_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_type[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(24),
      O => req_type(0)
    );
\tx_64.req_type[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(25),
      O => req_type(1)
    );
\tx_64.req_type[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => \tx_64.req_tag_reg[0]_0\,
      I2 => \^in_packet_q\,
      I3 => \tx_64.req_rid_reg[15]_0\(26),
      O => req_type(2)
    );
\tx_64.req_type_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_type(0),
      Q => \tx_64.req_type_reg_n_0_[0]\,
      R => SR(0)
    );
\tx_64.req_type_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_type(1),
      Q => \tx_64.req_type_reg_n_0_[1]\,
      R => SR(0)
    );
\tx_64.req_type_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \tx_64.req_mesg_i_1_n_0\,
      D => req_type(2),
      Q => \tx_64.req_type_reg_n_0_[2]\,
      R => SR(0)
    );
\tx_64.req_wr_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(30),
      I1 => req_wr,
      I2 => \tx_64.req_wr_reg_n_0\,
      O => \tx_64.req_wr_i_1_n_0\
    );
\tx_64.req_wr_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"880080000000FF00"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[0]_0\,
      I1 => \s_axis_cq\\.tready\(0),
      I2 => tgt_brdg_fifo_inst_i_2_n_0,
      I3 => \sop__0\,
      I4 => state(0),
      I5 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => req_wr
    );
\tx_64.req_wr_reg\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \tx_64.req_wr_i_1_n_0\,
      Q => \tx_64.req_wr_reg_n_0\,
      R => SR(0)
    );
udma_wrapper_i_100: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(37),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[29]\,
      I4 => udma_wrapper_i_193_n_0,
      O => \s_axis_cq\\.tdata\(37)
    );
udma_wrapper_i_101: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(36),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[28]\,
      I4 => udma_wrapper_i_194_n_0,
      O => \s_axis_cq\\.tdata\(36)
    );
udma_wrapper_i_102: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(35),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[27]\,
      I4 => udma_wrapper_i_195_n_0,
      O => \s_axis_cq\\.tdata\(35)
    );
udma_wrapper_i_103: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(34),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[26]\,
      I4 => udma_wrapper_i_196_n_0,
      O => \s_axis_cq\\.tdata\(34)
    );
udma_wrapper_i_104: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(33),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[25]\,
      I4 => udma_wrapper_i_197_n_0,
      O => \s_axis_cq\\.tdata\(33)
    );
udma_wrapper_i_105: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(32),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[24]\,
      I4 => udma_wrapper_i_198_n_0,
      O => \s_axis_cq\\.tdata\(32)
    );
udma_wrapper_i_106: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_199_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(15),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[15]\,
      O => \s_axis_cq\\.tdata\(31)
    );
udma_wrapper_i_107: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_201_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(14),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[14]\,
      O => \s_axis_cq\\.tdata\(30)
    );
udma_wrapper_i_108: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_202_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(13),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[13]\,
      O => \s_axis_cq\\.tdata\(29)
    );
udma_wrapper_i_109: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_203_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(12),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[12]\,
      O => \s_axis_cq\\.tdata\(28)
    );
udma_wrapper_i_110: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_204_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(11),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[11]\,
      O => \s_axis_cq\\.tdata\(27)
    );
udma_wrapper_i_111: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_205_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(10),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[10]\,
      O => \s_axis_cq\\.tdata\(26)
    );
udma_wrapper_i_112: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_206_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(9),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[9]\,
      O => \s_axis_cq\\.tdata\(25)
    );
udma_wrapper_i_113: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_207_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(8),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[8]\,
      O => \s_axis_cq\\.tdata\(24)
    );
udma_wrapper_i_114: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_208_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(7),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[7]\,
      O => \s_axis_cq\\.tdata\(23)
    );
udma_wrapper_i_115: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_209_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(6),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[6]\,
      O => \s_axis_cq\\.tdata\(22)
    );
udma_wrapper_i_116: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_210_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(5),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[5]\,
      O => \s_axis_cq\\.tdata\(21)
    );
udma_wrapper_i_117: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_211_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(4),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[4]\,
      O => \s_axis_cq\\.tdata\(20)
    );
udma_wrapper_i_118: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_212_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(3),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[3]\,
      O => \s_axis_cq\\.tdata\(19)
    );
udma_wrapper_i_119: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_213_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(2),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[2]\,
      O => \s_axis_cq\\.tdata\(18)
    );
udma_wrapper_i_120: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_214_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(1),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[1]\,
      O => \s_axis_cq\\.tdata\(17)
    );
udma_wrapper_i_121: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_215_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(0),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_rid_reg_n_0_[0]\,
      O => \s_axis_cq\\.tdata\(16)
    );
udma_wrapper_i_122: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_216_n_0,
      I1 => udma_wrapper_i_217_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(15),
      I3 => udma_wrapper_i_170_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(47),
      O => \s_axis_cq\\.tdata\(15)
    );
udma_wrapper_i_123: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_218_n_0,
      I1 => udma_wrapper_i_217_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(14),
      I3 => udma_wrapper_i_200_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(30),
      O => \s_axis_cq\\.tdata\(14)
    );
udma_wrapper_i_124: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_219_n_0,
      I1 => udma_wrapper_i_217_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(13),
      I3 => udma_wrapper_i_200_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(29),
      O => \s_axis_cq\\.tdata\(13)
    );
udma_wrapper_i_125: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAFFEAEAEAEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_220_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(28),
      I3 => sel0(3),
      I4 => sel0(2),
      I5 => udma_wrapper_i_221_n_0,
      O => \s_axis_cq\\.tdata\(12)
    );
udma_wrapper_i_126: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
        port map (
      I0 => \tx_64.req_rid_reg[15]_0\(43),
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(11),
      I3 => udma_wrapper_i_217_n_0,
      I4 => udma_wrapper_i_222_n_0,
      I5 => udma_wrapper_i_223_n_0,
      O => \s_axis_cq\\.tdata\(11)
    );
udma_wrapper_i_127: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_224_n_0,
      I1 => udma_wrapper_i_217_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(10),
      I3 => udma_wrapper_i_170_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(42),
      O => \s_axis_cq\\.tdata\(10)
    );
udma_wrapper_i_128: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_225_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(25),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[9]\,
      O => \s_axis_cq\\.tdata\(9)
    );
udma_wrapper_i_129: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_226_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(24),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[8]\,
      O => \s_axis_cq\\.tdata\(8)
    );
udma_wrapper_i_130: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_227_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(23),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[7]\,
      O => \s_axis_cq\\.tdata\(7)
    );
udma_wrapper_i_131: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_228_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(22),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[6]\,
      O => \s_axis_cq\\.tdata\(6)
    );
udma_wrapper_i_132: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_229_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(21),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[5]\,
      O => \s_axis_cq\\.tdata\(5)
    );
udma_wrapper_i_133: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_230_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(20),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[4]\,
      O => \s_axis_cq\\.tdata\(4)
    );
udma_wrapper_i_134: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_231_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(19),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[3]\,
      O => \s_axis_cq\\.tdata\(3)
    );
udma_wrapper_i_135: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_232_n_0,
      I1 => udma_wrapper_i_200_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(18),
      I3 => udma_wrapper_i_180_n_0,
      I4 => \tx_64.req_len_reg_n_0_[2]\,
      O => \s_axis_cq\\.tdata\(2)
    );
udma_wrapper_i_136: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEAAAEAAAEAAA"
    )
        port map (
      I0 => udma_wrapper_i_233_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(1),
      I2 => udma_wrapper_i_234_n_0,
      I3 => udma_wrapper_i_235_n_0,
      I4 => udma_wrapper_i_200_n_0,
      I5 => \tx_64.req_rid_reg[15]_0\(17),
      O => \s_axis_cq\\.tdata\(1)
    );
udma_wrapper_i_137: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEAAAEAAAEAAA"
    )
        port map (
      I0 => udma_wrapper_i_236_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(0),
      I2 => udma_wrapper_i_234_n_0,
      I3 => udma_wrapper_i_235_n_0,
      I4 => udma_wrapper_i_200_n_0,
      I5 => \tx_64.req_rid_reg[15]_0\(16),
      O => \s_axis_cq\\.tdata\(0)
    );
udma_wrapper_i_138: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200000"
    )
        port map (
      I0 => in130,
      I1 => SR(0),
      I2 => state(0),
      I3 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I4 => \tx_64.req_wr_reg_n_0\,
      O => \s_axis_cq\\.tuser\(4)
    );
udma_wrapper_i_139: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C000000AAA0"
    )
        port map (
      I0 => \tx_64.req_fbe_reg_n_0_[3]\,
      I1 => \tx_64.req_wr_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => SR(0),
      I5 => in130,
      O => \s_axis_cq\\.tuser\(3)
    );
udma_wrapper_i_140: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C000000AAA0"
    )
        port map (
      I0 => \tx_64.req_fbe_reg_n_0_[2]\,
      I1 => \tx_64.req_wr_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => SR(0),
      I5 => in130,
      O => \s_axis_cq\\.tuser\(2)
    );
udma_wrapper_i_141: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C000000AAA0"
    )
        port map (
      I0 => \tx_64.req_fbe_reg_n_0_[1]\,
      I1 => \tx_64.req_wr_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => SR(0),
      I5 => in130,
      O => \s_axis_cq\\.tuser\(1)
    );
udma_wrapper_i_142: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000C000000AAA0"
    )
        port map (
      I0 => \tx_64.req_fbe_reg_n_0_[0]\,
      I1 => \tx_64.req_wr_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => SR(0),
      I5 => in130,
      O => \s_axis_cq\\.tuser\(0)
    );
udma_wrapper_i_143: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A000B000F000B0"
    )
        port map (
      I0 => state(0),
      I1 => \tx_64.req_wr_reg_n_0\,
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => SR(0),
      I4 => in130,
      I5 => p_0_in22_in,
      O => \^fsm_sequential_tx_64.state_reg[0]_0\
    );
udma_wrapper_i_144: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => state(0),
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => in130,
      O => \s_axis_cq\\.tvalid\
    );
udma_wrapper_i_170: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08A808A8080808A8"
    )
        port map (
      I0 => udma_wrapper_i_246_n_0,
      I1 => req_4dw,
      I2 => in130,
      I3 => udma_wrapper_i_247_n_0,
      I4 => sel0(0),
      I5 => sel0(1),
      O => udma_wrapper_i_170_n_0
    );
udma_wrapper_i_171: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => state(0),
      I2 => SR(0),
      I3 => p_0_in,
      I4 => in130,
      O => udma_wrapper_i_171_n_0
    );
udma_wrapper_i_172: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8A8AAA8"
    )
        port map (
      I0 => udma_wrapper_i_235_n_0,
      I1 => sel0(2),
      I2 => sel0(3),
      I3 => sel0(0),
      I4 => sel0(1),
      O => udma_wrapper_i_172_n_0
    );
udma_wrapper_i_173: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_attr_reg_n_0_[2]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(30),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_173_n_0
    );
udma_wrapper_i_174: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_attr_reg_n_0_[1]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(29),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_174_n_0
    );
udma_wrapper_i_175: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_attr_reg_n_0_[0]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(28),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_175_n_0
    );
udma_wrapper_i_176: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tc_reg_n_0_[2]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(27),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_176_n_0
    );
udma_wrapper_i_177: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tc_reg_n_0_[1]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(26),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_177_n_0
    );
udma_wrapper_i_178: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tc_reg_n_0_[0]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(25),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_178_n_0
    );
udma_wrapper_i_179: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(18),
      I2 => udma_wrapper_i_248_n_0,
      I3 => \tx_64.req_bar_id_reg_n_0_[2]\,
      I4 => \tx_64.req_rid_reg[15]_0\(50),
      I5 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_179_n_0
    );
udma_wrapper_i_180: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => SR(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => state(0),
      O => udma_wrapper_i_180_n_0
    );
udma_wrapper_i_181: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(17),
      I2 => udma_wrapper_i_248_n_0,
      I3 => \tx_64.req_bar_id_reg_n_0_[1]\,
      I4 => \tx_64.req_rid_reg[15]_0\(49),
      I5 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_181_n_0
    );
udma_wrapper_i_182: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(16),
      I2 => udma_wrapper_i_248_n_0,
      I3 => \tx_64.req_bar_id_reg_n_0_[0]\,
      I4 => \tx_64.req_rid_reg[15]_0\(48),
      I5 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_182_n_0
    );
udma_wrapper_i_183: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[7]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(47),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_183_n_0
    );
udma_wrapper_i_184: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[6]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(46),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_184_n_0
    );
udma_wrapper_i_185: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[5]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(45),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_185_n_0
    );
udma_wrapper_i_186: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[4]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(44),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_186_n_0
    );
udma_wrapper_i_187: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[3]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(43),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_187_n_0
    );
udma_wrapper_i_188: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[2]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(42),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_188_n_0
    );
udma_wrapper_i_189: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[1]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(41),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_189_n_0
    );
udma_wrapper_i_190: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF808080"
    )
        port map (
      I0 => \tx_64.req_msg_code_reg_n_0_[0]\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(40),
      I4 => udma_wrapper_i_172_n_0,
      O => udma_wrapper_i_190_n_0
    );
udma_wrapper_i_191: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[7]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(7),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_191_n_0
    );
udma_wrapper_i_192: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[6]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(6),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_192_n_0
    );
udma_wrapper_i_193: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[5]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(5),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_193_n_0
    );
udma_wrapper_i_194: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[4]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(4),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_194_n_0
    );
udma_wrapper_i_195: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[3]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(3),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_195_n_0
    );
udma_wrapper_i_196: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[2]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(2),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_196_n_0
    );
udma_wrapper_i_197: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[1]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(1),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_197_n_0
    );
udma_wrapper_i_198: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
        port map (
      I0 => \tx_64.req_tag_reg_n_0_[0]\,
      I1 => SR(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I3 => state(0),
      I4 => \tx_64.req_rid_reg[15]_0\(0),
      I5 => udma_wrapper_i_170_n_0,
      O => udma_wrapper_i_198_n_0
    );
udma_wrapper_i_199: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(31),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(63),
      I4 => \tx_64.req_data_reg_n_0_[7]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_199_n_0
    );
udma_wrapper_i_200: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => sel0(3),
      I1 => in130,
      I2 => SR(0),
      I3 => state(0),
      I4 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => udma_wrapper_i_200_n_0
    );
udma_wrapper_i_201: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(30),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(62),
      I4 => \tx_64.req_data_reg_n_0_[6]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_201_n_0
    );
udma_wrapper_i_202: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(29),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(61),
      I4 => \tx_64.req_data_reg_n_0_[5]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_202_n_0
    );
udma_wrapper_i_203: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(28),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(60),
      I4 => \tx_64.req_data_reg_n_0_[4]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_203_n_0
    );
udma_wrapper_i_204: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(27),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(59),
      I4 => \tx_64.req_data_reg_n_0_[3]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_204_n_0
    );
udma_wrapper_i_205: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(26),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(58),
      I4 => \tx_64.req_data_reg_n_0_[2]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_205_n_0
    );
udma_wrapper_i_206: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(25),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(57),
      I4 => \tx_64.req_data_reg_n_0_[1]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_206_n_0
    );
udma_wrapper_i_207: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(24),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(56),
      I4 => \tx_64.req_data_reg_n_0_[0]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_207_n_0
    );
udma_wrapper_i_208: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(23),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(55),
      I4 => \tx_64.req_data_reg_n_0_[15]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_208_n_0
    );
udma_wrapper_i_209: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(22),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(54),
      I4 => \tx_64.req_data_reg_n_0_[14]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_209_n_0
    );
udma_wrapper_i_210: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(21),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(53),
      I4 => \tx_64.req_data_reg_n_0_[13]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_210_n_0
    );
udma_wrapper_i_211: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(20),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(52),
      I4 => \tx_64.req_data_reg_n_0_[12]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_211_n_0
    );
udma_wrapper_i_212: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(19),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(51),
      I4 => \tx_64.req_data_reg_n_0_[11]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_212_n_0
    );
udma_wrapper_i_213: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(18),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(50),
      I4 => \tx_64.req_data_reg_n_0_[10]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_213_n_0
    );
udma_wrapper_i_214: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(17),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(49),
      I4 => \tx_64.req_data_reg_n_0_[9]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_214_n_0
    );
udma_wrapper_i_215: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(16),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(48),
      I4 => \tx_64.req_data_reg_n_0_[8]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_215_n_0
    );
udma_wrapper_i_216: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.req_data_reg_n_0_[23]\,
      I1 => udma_wrapper_i_249_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(31),
      I3 => udma_wrapper_i_200_n_0,
      O => udma_wrapper_i_216_n_0
    );
udma_wrapper_i_217: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000D10000"
    )
        port map (
      I0 => req_4dw,
      I1 => in130,
      I2 => udma_wrapper_i_234_n_0,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I4 => state(0),
      I5 => SR(0),
      O => udma_wrapper_i_217_n_0
    );
udma_wrapper_i_218: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_180_n_0,
      I1 => in130,
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(46),
      I4 => \tx_64.req_data_reg_n_0_[22]\,
      I5 => udma_wrapper_i_250_n_0,
      O => udma_wrapper_i_218_n_0
    );
udma_wrapper_i_219: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_180_n_0,
      I1 => in130,
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(45),
      I4 => \tx_64.req_data_reg_n_0_[21]\,
      I5 => udma_wrapper_i_250_n_0,
      O => udma_wrapper_i_219_n_0
    );
udma_wrapper_i_220: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(12),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(44),
      I4 => \tx_64.req_data_reg_n_0_[20]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_220_n_0
    );
udma_wrapper_i_221: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => state(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => SR(0),
      I3 => in130,
      O => udma_wrapper_i_221_n_0
    );
udma_wrapper_i_222: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF080808"
    )
        port map (
      I0 => \tx_64.req_wr_reg_n_0\,
      I1 => udma_wrapper_i_180_n_0,
      I2 => in130,
      I3 => \tx_64.req_rid_reg[15]_0\(27),
      I4 => udma_wrapper_i_200_n_0,
      O => udma_wrapper_i_222_n_0
    );
udma_wrapper_i_223: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \tx_64.req_data_reg_n_0_[19]\,
      I1 => udma_wrapper_i_249_n_0,
      I2 => sel0(3),
      I3 => udma_wrapper_i_180_n_0,
      I4 => in130,
      O => udma_wrapper_i_223_n_0
    );
udma_wrapper_i_224: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \tx_64.req_data_reg_n_0_[18]\,
      I1 => udma_wrapper_i_249_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(26),
      I3 => udma_wrapper_i_200_n_0,
      O => udma_wrapper_i_224_n_0
    );
udma_wrapper_i_225: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(9),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(41),
      I4 => \tx_64.req_data_reg_n_0_[17]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_225_n_0
    );
udma_wrapper_i_226: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(8),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(40),
      I4 => \tx_64.req_data_reg_n_0_[16]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_226_n_0
    );
udma_wrapper_i_227: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(7),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(39),
      I4 => \tx_64.req_data_reg_n_0_[31]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_227_n_0
    );
udma_wrapper_i_228: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(6),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(38),
      I4 => \tx_64.req_data_reg_n_0_[30]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_228_n_0
    );
udma_wrapper_i_229: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(5),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(37),
      I4 => \tx_64.req_data_reg_n_0_[29]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_229_n_0
    );
udma_wrapper_i_230: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(4),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(36),
      I4 => \tx_64.req_data_reg_n_0_[28]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_230_n_0
    );
udma_wrapper_i_231: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(3),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(35),
      I4 => \tx_64.req_data_reg_n_0_[27]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_231_n_0
    );
udma_wrapper_i_232: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_217_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(2),
      I2 => udma_wrapper_i_170_n_0,
      I3 => \tx_64.req_rid_reg[15]_0\(34),
      I4 => \tx_64.req_data_reg_n_0_[26]\,
      I5 => udma_wrapper_i_249_n_0,
      O => udma_wrapper_i_232_n_0
    );
udma_wrapper_i_233: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBAAABAAABAAA"
    )
        port map (
      I0 => udma_wrapper_i_251_n_0,
      I1 => in130,
      I2 => \tx_64.req_at_reg_n_0_[1]\,
      I3 => udma_wrapper_i_246_n_0,
      I4 => udma_wrapper_i_180_n_0,
      I5 => \tx_64.req_len_reg_n_0_[1]\,
      O => udma_wrapper_i_233_n_0
    );
udma_wrapper_i_234: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2322"
    )
        port map (
      I0 => sel0(2),
      I1 => sel0(3),
      I2 => sel0(1),
      I3 => sel0(0),
      O => udma_wrapper_i_234_n_0
    );
udma_wrapper_i_235: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => state(0),
      I2 => SR(0),
      I3 => in130,
      O => udma_wrapper_i_235_n_0
    );
udma_wrapper_i_236: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBAAABAAABAAA"
    )
        port map (
      I0 => udma_wrapper_i_252_n_0,
      I1 => in130,
      I2 => \tx_64.req_at_reg_n_0_[0]\,
      I3 => udma_wrapper_i_246_n_0,
      I4 => udma_wrapper_i_180_n_0,
      I5 => \tx_64.req_len_reg_n_0_[0]\,
      O => udma_wrapper_i_236_n_0
    );
udma_wrapper_i_246: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => SR(0),
      I1 => state(0),
      I2 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      O => udma_wrapper_i_246_n_0
    );
udma_wrapper_i_247: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => sel0(2),
      I1 => sel0(3),
      O => udma_wrapper_i_247_n_0
    );
udma_wrapper_i_248: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => state(0),
      I1 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I2 => SR(0),
      I3 => in130,
      O => udma_wrapper_i_248_n_0
    );
udma_wrapper_i_249: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08080008"
    )
        port map (
      I0 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I1 => state(0),
      I2 => SR(0),
      I3 => p_0_in,
      I4 => in130,
      O => udma_wrapper_i_249_n_0
    );
udma_wrapper_i_250: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F400"
    )
        port map (
      I0 => p_0_in,
      I1 => state(0),
      I2 => in130,
      I3 => \^fsm_sequential_tx_64.state_reg[1]_0\(0),
      I4 => SR(0),
      O => udma_wrapper_i_250_n_0
    );
udma_wrapper_i_251: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8888888888888"
    )
        port map (
      I0 => \tx_64.req_data_reg_n_0_[25]\,
      I1 => udma_wrapper_i_249_n_0,
      I2 => udma_wrapper_i_235_n_0,
      I3 => udma_wrapper_i_247_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(33),
      I5 => udma_wrapper_i_262_n_0,
      O => udma_wrapper_i_251_n_0
    );
udma_wrapper_i_252: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F8888888888888"
    )
        port map (
      I0 => \tx_64.req_data_reg_n_0_[24]\,
      I1 => udma_wrapper_i_249_n_0,
      I2 => udma_wrapper_i_235_n_0,
      I3 => udma_wrapper_i_247_n_0,
      I4 => \tx_64.req_rid_reg[15]_0\(32),
      I5 => udma_wrapper_i_262_n_0,
      O => udma_wrapper_i_252_n_0
    );
udma_wrapper_i_262: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => sel0(1),
      I1 => sel0(0),
      O => udma_wrapper_i_262_n_0
    );
udma_wrapper_i_74: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(31),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[7]\,
      I4 => \tx_64.req_rid_reg[15]_0\(63),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(63)
    );
udma_wrapper_i_75: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(62),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[6]\,
      I4 => udma_wrapper_i_173_n_0,
      O => \s_axis_cq\\.tdata\(62)
    );
udma_wrapper_i_76: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(61),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[5]\,
      I4 => udma_wrapper_i_174_n_0,
      O => \s_axis_cq\\.tdata\(61)
    );
udma_wrapper_i_77: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(60),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[4]\,
      I4 => udma_wrapper_i_175_n_0,
      O => \s_axis_cq\\.tdata\(60)
    );
udma_wrapper_i_78: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(59),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[3]\,
      I4 => udma_wrapper_i_176_n_0,
      O => \s_axis_cq\\.tdata\(59)
    );
udma_wrapper_i_79: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(58),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[2]\,
      I4 => udma_wrapper_i_177_n_0,
      O => \s_axis_cq\\.tdata\(58)
    );
udma_wrapper_i_80: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(57),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[1]\,
      I4 => udma_wrapper_i_178_n_0,
      O => \s_axis_cq\\.tdata\(57)
    );
udma_wrapper_i_81: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(24),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[0]\,
      I4 => \tx_64.req_rid_reg[15]_0\(56),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(56)
    );
udma_wrapper_i_82: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(23),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[15]\,
      I4 => \tx_64.req_rid_reg[15]_0\(55),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(55)
    );
udma_wrapper_i_83: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(22),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[14]\,
      I4 => \tx_64.req_rid_reg[15]_0\(54),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(54)
    );
udma_wrapper_i_84: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(21),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[13]\,
      I4 => \tx_64.req_rid_reg[15]_0\(53),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(53)
    );
udma_wrapper_i_85: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(20),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[12]\,
      I4 => \tx_64.req_rid_reg[15]_0\(52),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(52)
    );
udma_wrapper_i_86: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => udma_wrapper_i_170_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(19),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[11]\,
      I4 => \tx_64.req_rid_reg[15]_0\(51),
      I5 => udma_wrapper_i_172_n_0,
      O => \s_axis_cq\\.tdata\(51)
    );
udma_wrapper_i_87: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_179_n_0,
      I1 => udma_wrapper_i_171_n_0,
      I2 => \tx_64.req_data_reg_n_0_[10]\,
      I3 => in130,
      I4 => udma_wrapper_i_180_n_0,
      I5 => \tx_64.req_type_reg_n_0_[2]\,
      O => \s_axis_cq\\.tdata\(50)
    );
udma_wrapper_i_88: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_181_n_0,
      I1 => udma_wrapper_i_171_n_0,
      I2 => \tx_64.req_data_reg_n_0_[9]\,
      I3 => in130,
      I4 => udma_wrapper_i_180_n_0,
      I5 => \tx_64.req_type_reg_n_0_[1]\,
      O => \s_axis_cq\\.tdata\(49)
    );
udma_wrapper_i_89: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_182_n_0,
      I1 => udma_wrapper_i_171_n_0,
      I2 => \tx_64.req_data_reg_n_0_[8]\,
      I3 => in130,
      I4 => udma_wrapper_i_180_n_0,
      I5 => \tx_64.req_type_reg_n_0_[0]\,
      O => \s_axis_cq\\.tdata\(48)
    );
udma_wrapper_i_90: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_183_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(15),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[23]\,
      O => \s_axis_cq\\.tdata\(47)
    );
udma_wrapper_i_91: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_184_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(14),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[22]\,
      O => \s_axis_cq\\.tdata\(46)
    );
udma_wrapper_i_92: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_185_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(13),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[21]\,
      O => \s_axis_cq\\.tdata\(45)
    );
udma_wrapper_i_93: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_186_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(12),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[20]\,
      O => \s_axis_cq\\.tdata\(44)
    );
udma_wrapper_i_94: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_187_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(11),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[19]\,
      O => \s_axis_cq\\.tdata\(43)
    );
udma_wrapper_i_95: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_188_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(10),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[18]\,
      O => \s_axis_cq\\.tdata\(42)
    );
udma_wrapper_i_96: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_189_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(9),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[17]\,
      O => \s_axis_cq\\.tdata\(41)
    );
udma_wrapper_i_97: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => udma_wrapper_i_190_n_0,
      I1 => udma_wrapper_i_170_n_0,
      I2 => \tx_64.req_rid_reg[15]_0\(8),
      I3 => udma_wrapper_i_171_n_0,
      I4 => \tx_64.req_data_reg_n_0_[16]\,
      O => \s_axis_cq\\.tdata\(40)
    );
udma_wrapper_i_98: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(39),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[31]\,
      I4 => udma_wrapper_i_191_n_0,
      O => \s_axis_cq\\.tdata\(39)
    );
udma_wrapper_i_99: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => udma_wrapper_i_172_n_0,
      I1 => \tx_64.req_rid_reg[15]_0\(38),
      I2 => udma_wrapper_i_171_n_0,
      I3 => \tx_64.req_data_reg_n_0_[30]\,
      I4 => udma_wrapper_i_192_n_0,
      O => \s_axis_cq\\.tdata\(38)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_tx_mux is
  port (
    s_axis_tx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tlast : out STD_LOGIC;
    s_axis_tx_tvalid : out STD_LOGIC;
    \FSM_sequential_transfer_SM_reg[1]_0\ : out STD_LOGIC;
    \FSM_sequential_transfer_SM_reg[1]_1\ : out STD_LOGIC;
    transfer_SM : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pcie_dma_in\\.pcie_rq_seq_num0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pcie_dma_in\\.pcie_rq_seq_num_vld0\ : out STD_LOGIC;
    tready_thrtl_reg : out STD_LOGIC;
    s_axis_tx_req_tready : out STD_LOGIC;
    user_reset_out_reg : out STD_LOGIC;
    \Head_reg[11]\ : out STD_LOGIC;
    user_reset_out_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_tx_tkeep_reg[7]_0\ : in STD_LOGIC;
    user_clk_out : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_req_tvalid : in STD_LOGIC;
    s_axis_tx_tready : in STD_LOGIC;
    s_axis_tx_tgt_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_transfer_SM_reg[1]_2\ : in STD_LOGIC;
    \FSM_sequential_transfer_SM_reg[1]_3\ : in STD_LOGIC;
    \pcie_rq_seq_ret_wr_ff_reg[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    state : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tlast_reg_0 : in STD_LOGIC;
    \m_axis_rq\\.tdata\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_req_tlast : in STD_LOGIC;
    \m_axis_cc\\.tlast\ : in STD_LOGIC;
    \s_axis_tx_tdata[33]_i_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_transfer_SM_reg[1]_4\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_tx_mux : entity is "xdma_0_tx_mux";
end xdma_0_xdma_0_tx_mux;

architecture STRUCTURE of xdma_0_xdma_0_tx_mux is
  signal \FSM_sequential_transfer_SM[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_transfer_SM[1]_i_1_n_0\ : STD_LOGIC;
  signal \^fsm_sequential_transfer_sm_reg[1]_0\ : STD_LOGIC;
  signal \^fsm_sequential_transfer_sm_reg[1]_1\ : STD_LOGIC;
  signal \s_axis_tx_tdata[63]_i_1_n_0\ : STD_LOGIC;
  signal s_axis_tx_tlast_i_1_n_0 : STD_LOGIC;
  signal \^s_axis_tx_tvalid\ : STD_LOGIC;
  signal s_axis_tx_tvalid_i_1_n_0 : STD_LOGIC;
  signal s_axis_tx_tvalid_i_3_n_0 : STD_LOGIC;
  signal \^transfer_sm\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \transfer_SM__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_transfer_SM_reg[0]\ : label is "SM_IDLE:00,SM_TGT:01,SM_REQ:11,SM_MSIX:10";
  attribute FSM_ENCODED_STATES of \FSM_sequential_transfer_SM_reg[1]\ : label is "SM_IDLE:00,SM_TGT:01,SM_REQ:11,SM_MSIX:10";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[1]_i_2\ : label is "soft_lutpair2120";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[2]_i_3\ : label is "soft_lutpair2123";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[30]_i_3\ : label is "soft_lutpair2122";
  attribute SOFT_HLUTNM of \s_axis_tx_tdata[63]_i_8\ : label is "soft_lutpair2123";
  attribute SOFT_HLUTNM of \s_axis_tx_tkeep[7]_i_3\ : label is "soft_lutpair2122";
  attribute SOFT_HLUTNM of s_axis_tx_tvalid_i_3 : label is "soft_lutpair2121";
  attribute SOFT_HLUTNM of udma_wrapper_i_148 : label is "soft_lutpair2118";
  attribute SOFT_HLUTNM of udma_wrapper_i_149 : label is "soft_lutpair2118";
  attribute SOFT_HLUTNM of udma_wrapper_i_150 : label is "soft_lutpair2119";
  attribute SOFT_HLUTNM of udma_wrapper_i_151 : label is "soft_lutpair2120";
  attribute SOFT_HLUTNM of udma_wrapper_i_152 : label is "soft_lutpair2121";
  attribute SOFT_HLUTNM of udma_wrapper_i_153 : label is "soft_lutpair2119";
begin
  \FSM_sequential_transfer_SM_reg[1]_0\ <= \^fsm_sequential_transfer_sm_reg[1]_0\;
  \FSM_sequential_transfer_SM_reg[1]_1\ <= \^fsm_sequential_transfer_sm_reg[1]_1\;
  s_axis_tx_tvalid <= \^s_axis_tx_tvalid\;
  transfer_SM(1 downto 0) <= \^transfer_sm\(1 downto 0);
\FSM_sequential_transfer_SM[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15550A0A"
    )
        port map (
      I0 => \FSM_sequential_transfer_SM_reg[1]_4\,
      I1 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I2 => \^transfer_sm\(1),
      I3 => s_axis_tx_tready,
      I4 => \^transfer_sm\(0),
      O => \FSM_sequential_transfer_SM[0]_i_1_n_0\
    );
\FSM_sequential_transfer_SM[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AB88BB88BB88BB88"
    )
        port map (
      I0 => \transfer_SM__0\(1),
      I1 => \FSM_sequential_transfer_SM_reg[1]_4\,
      I2 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I3 => \^transfer_sm\(1),
      I4 => s_axis_tx_tready,
      I5 => \^transfer_sm\(0),
      O => \FSM_sequential_transfer_SM[1]_i_1_n_0\
    );
\FSM_sequential_transfer_SM[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1010001010101010"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => \^transfer_sm\(0),
      I2 => s_axis_tx_req_tvalid,
      I3 => s_axis_tx_tgt_tdata(0),
      I4 => SR(0),
      I5 => \FSM_sequential_transfer_SM_reg[1]_2\,
      O => \transfer_SM__0\(1)
    );
\FSM_sequential_transfer_SM_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_transfer_SM[0]_i_1_n_0\,
      Q => \^transfer_sm\(0),
      R => SR(0)
    );
\FSM_sequential_transfer_SM_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => \FSM_sequential_transfer_SM[1]_i_1_n_0\,
      Q => \^transfer_sm\(1),
      R => SR(0)
    );
\FSM_sequential_tx_64.state[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F7"
    )
        port map (
      I0 => s_axis_tx_tready,
      I1 => \^transfer_sm\(0),
      I2 => \^transfer_sm\(1),
      O => tready_thrtl_reg
    );
\s_axis_tx_tdata[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => \^transfer_sm\(0),
      I2 => SR(0),
      I3 => s_axis_tx_tlast_reg_0,
      O => \^fsm_sequential_transfer_sm_reg[1]_0\
    );
\s_axis_tx_tdata[30]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => \^transfer_sm\(0),
      I2 => SR(0),
      I3 => state(0),
      O => \^fsm_sequential_transfer_sm_reg[1]_1\
    );
\s_axis_tx_tdata[30]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \m_axis_rq\\.tdata\(0),
      I1 => \m_axis_rq\\.tdata\(1),
      I2 => \m_axis_rq\\.tdata\(3),
      I3 => \m_axis_rq\\.tdata\(2),
      O => \Head_reg[11]\
    );
\s_axis_tx_tdata[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_axis_tx_tready,
      I1 => SR(0),
      O => \s_axis_tx_tdata[63]_i_1_n_0\
    );
\s_axis_tx_tdata[63]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => SR(0),
      I1 => \^transfer_sm\(0),
      I2 => \^transfer_sm\(1),
      I3 => \s_axis_tx_tdata[33]_i_3\(0),
      O => user_reset_out_reg_0
    );
\s_axis_tx_tdata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\s_axis_tx_tdata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(10),
      Q => Q(10),
      R => '0'
    );
\s_axis_tx_tdata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(11),
      Q => Q(11),
      R => '0'
    );
\s_axis_tx_tdata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(12),
      Q => Q(12),
      R => '0'
    );
\s_axis_tx_tdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(13),
      Q => Q(13),
      R => '0'
    );
\s_axis_tx_tdata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(14),
      Q => Q(14),
      R => '0'
    );
\s_axis_tx_tdata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(15),
      Q => Q(15),
      R => '0'
    );
\s_axis_tx_tdata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(16),
      Q => Q(16),
      R => '0'
    );
\s_axis_tx_tdata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(17),
      Q => Q(17),
      R => '0'
    );
\s_axis_tx_tdata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(18),
      Q => Q(18),
      R => '0'
    );
\s_axis_tx_tdata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(19),
      Q => Q(19),
      R => '0'
    );
\s_axis_tx_tdata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\s_axis_tx_tdata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(20),
      Q => Q(20),
      R => '0'
    );
\s_axis_tx_tdata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(21),
      Q => Q(21),
      R => '0'
    );
\s_axis_tx_tdata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(22),
      Q => Q(22),
      R => '0'
    );
\s_axis_tx_tdata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(23),
      Q => Q(23),
      R => '0'
    );
\s_axis_tx_tdata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(24),
      Q => Q(24),
      R => '0'
    );
\s_axis_tx_tdata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(25),
      Q => Q(25),
      R => '0'
    );
\s_axis_tx_tdata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(26),
      Q => Q(26),
      R => '0'
    );
\s_axis_tx_tdata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(27),
      Q => Q(27),
      R => '0'
    );
\s_axis_tx_tdata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(28),
      Q => Q(28),
      R => '0'
    );
\s_axis_tx_tdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(29),
      Q => Q(29),
      R => '0'
    );
\s_axis_tx_tdata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\s_axis_tx_tdata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(30),
      Q => Q(30),
      R => '0'
    );
\s_axis_tx_tdata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(31),
      Q => Q(31),
      R => '0'
    );
\s_axis_tx_tdata_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(32),
      Q => Q(32),
      R => '0'
    );
\s_axis_tx_tdata_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(33),
      Q => Q(33),
      R => '0'
    );
\s_axis_tx_tdata_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(34),
      Q => Q(34),
      R => '0'
    );
\s_axis_tx_tdata_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(35),
      Q => Q(35),
      R => '0'
    );
\s_axis_tx_tdata_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(36),
      Q => Q(36),
      R => '0'
    );
\s_axis_tx_tdata_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(37),
      Q => Q(37),
      R => '0'
    );
\s_axis_tx_tdata_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(38),
      Q => Q(38),
      R => '0'
    );
\s_axis_tx_tdata_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(39),
      Q => Q(39),
      R => '0'
    );
\s_axis_tx_tdata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\s_axis_tx_tdata_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(40),
      Q => Q(40),
      R => '0'
    );
\s_axis_tx_tdata_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(41),
      Q => Q(41),
      R => '0'
    );
\s_axis_tx_tdata_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(42),
      Q => Q(42),
      R => '0'
    );
\s_axis_tx_tdata_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(43),
      Q => Q(43),
      R => '0'
    );
\s_axis_tx_tdata_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(44),
      Q => Q(44),
      R => '0'
    );
\s_axis_tx_tdata_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(45),
      Q => Q(45),
      R => '0'
    );
\s_axis_tx_tdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(46),
      Q => Q(46),
      R => '0'
    );
\s_axis_tx_tdata_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(47),
      Q => Q(47),
      R => '0'
    );
\s_axis_tx_tdata_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(48),
      Q => Q(48),
      R => '0'
    );
\s_axis_tx_tdata_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(49),
      Q => Q(49),
      R => '0'
    );
\s_axis_tx_tdata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(4),
      Q => Q(4),
      R => '0'
    );
\s_axis_tx_tdata_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(50),
      Q => Q(50),
      R => '0'
    );
\s_axis_tx_tdata_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(51),
      Q => Q(51),
      R => '0'
    );
\s_axis_tx_tdata_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(52),
      Q => Q(52),
      R => '0'
    );
\s_axis_tx_tdata_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(53),
      Q => Q(53),
      R => '0'
    );
\s_axis_tx_tdata_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(54),
      Q => Q(54),
      R => '0'
    );
\s_axis_tx_tdata_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(55),
      Q => Q(55),
      R => '0'
    );
\s_axis_tx_tdata_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(56),
      Q => Q(56),
      R => '0'
    );
\s_axis_tx_tdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(57),
      Q => Q(57),
      R => '0'
    );
\s_axis_tx_tdata_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(58),
      Q => Q(58),
      R => '0'
    );
\s_axis_tx_tdata_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(59),
      Q => Q(59),
      R => '0'
    );
\s_axis_tx_tdata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(5),
      Q => Q(5),
      R => '0'
    );
\s_axis_tx_tdata_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(60),
      Q => Q(60),
      R => '0'
    );
\s_axis_tx_tdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(61),
      Q => Q(61),
      R => '0'
    );
\s_axis_tx_tdata_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(62),
      Q => Q(62),
      R => '0'
    );
\s_axis_tx_tdata_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(63),
      Q => Q(63),
      R => '0'
    );
\s_axis_tx_tdata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(6),
      Q => Q(6),
      R => '0'
    );
\s_axis_tx_tdata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(7),
      Q => Q(7),
      R => '0'
    );
\s_axis_tx_tdata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(8),
      Q => Q(8),
      R => '0'
    );
\s_axis_tx_tdata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => D(9),
      Q => Q(9),
      R => '0'
    );
\s_axis_tx_tkeep[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => SR(0),
      I1 => \^transfer_sm\(0),
      I2 => \^transfer_sm\(1),
      O => user_reset_out_reg
    );
\s_axis_tx_tkeep_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => \s_axis_tx_tkeep_reg[7]_0\,
      Q => s_axis_tx_tkeep(0),
      R => '0'
    );
s_axis_tx_tlast_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AC00A000"
    )
        port map (
      I0 => s_axis_tx_req_tlast,
      I1 => \m_axis_cc\\.tlast\,
      I2 => \^transfer_sm\(1),
      I3 => \^transfer_sm\(0),
      I4 => s_axis_tx_tlast_reg_0,
      O => s_axis_tx_tlast_i_1_n_0
    );
s_axis_tx_tlast_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => \s_axis_tx_tdata[63]_i_1_n_0\,
      D => s_axis_tx_tlast_i_1_n_0,
      Q => s_axis_tx_tlast,
      R => '0'
    );
s_axis_tx_tvalid_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFFFFFEEE0000"
    )
        port map (
      I0 => \^fsm_sequential_transfer_sm_reg[1]_0\,
      I1 => \^fsm_sequential_transfer_sm_reg[1]_1\,
      I2 => s_axis_tx_req_tvalid,
      I3 => s_axis_tx_tvalid_i_3_n_0,
      I4 => s_axis_tx_tready,
      I5 => \^s_axis_tx_tvalid\,
      O => s_axis_tx_tvalid_i_1_n_0
    );
s_axis_tx_tvalid_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^transfer_sm\(0),
      I1 => \^transfer_sm\(1),
      O => s_axis_tx_tvalid_i_3_n_0
    );
s_axis_tx_tvalid_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => s_axis_tx_tvalid_i_1_n_0,
      Q => \^s_axis_tx_tvalid\,
      R => SR(0)
    );
udma_wrapper_i_148: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I1 => \^transfer_sm\(0),
      I2 => s_axis_tx_tready,
      I3 => \^transfer_sm\(1),
      O => \pcie_dma_in\\.pcie_rq_seq_num_vld0\
    );
udma_wrapper_i_149: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => s_axis_tx_tready,
      I2 => \^transfer_sm\(0),
      I3 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I4 => \pcie_rq_seq_ret_wr_ff_reg[8]\(3),
      O => \pcie_dma_in\\.pcie_rq_seq_num0\(3)
    );
udma_wrapper_i_150: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => s_axis_tx_tready,
      I2 => \^transfer_sm\(0),
      I3 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I4 => \pcie_rq_seq_ret_wr_ff_reg[8]\(2),
      O => \pcie_dma_in\\.pcie_rq_seq_num0\(2)
    );
udma_wrapper_i_151: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => s_axis_tx_tready,
      I2 => \^transfer_sm\(0),
      I3 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I4 => \pcie_rq_seq_ret_wr_ff_reg[8]\(1),
      O => \pcie_dma_in\\.pcie_rq_seq_num0\(1)
    );
udma_wrapper_i_152: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => s_axis_tx_tready,
      I2 => \^transfer_sm\(0),
      I3 => \FSM_sequential_transfer_SM_reg[1]_3\,
      I4 => \pcie_rq_seq_ret_wr_ff_reg[8]\(0),
      O => \pcie_dma_in\\.pcie_rq_seq_num0\(0)
    );
udma_wrapper_i_153: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^transfer_sm\(1),
      I1 => s_axis_tx_tready,
      I2 => \^transfer_sm\(0),
      O => s_axis_tx_req_tready
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFO is
  port (
    D : out STD_LOGIC_VECTOR ( 63 downto 0 );
    wtlp_dat_vld_ff : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 63 downto 0 );
    wtlp_dat_ren : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \WrPtr_reg[0]_0\ : in STD_LOGIC;
    wtlp_wpl_wen_504 : in STD_LOGIC;
    \MemArray_reg[61]\ : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFO : entity is "xdma_v4_1_8_GenericFIFO";
end xdma_0_xdma_v4_1_8_GenericFIFO;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFO is
  signal MemArray_reg_0_7_0_5_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_12_17_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_18_23_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_24_29_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_30_35_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_36_41_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_42_47_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_48_53_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_54_59_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_60_65_n_5 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_0 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_3 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_6_11_n_5 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \MemArray[0]_i_1\ : label is "soft_lutpair1677";
  attribute SOFT_HLUTNM of \MemArray[10]_i_1\ : label is "soft_lutpair1682";
  attribute SOFT_HLUTNM of \MemArray[11]_i_1\ : label is "soft_lutpair1697";
  attribute SOFT_HLUTNM of \MemArray[12]_i_1\ : label is "soft_lutpair1676";
  attribute SOFT_HLUTNM of \MemArray[13]_i_1\ : label is "soft_lutpair1696";
  attribute SOFT_HLUTNM of \MemArray[14]_i_1\ : label is "soft_lutpair1671";
  attribute SOFT_HLUTNM of \MemArray[15]_i_1\ : label is "soft_lutpair1687";
  attribute SOFT_HLUTNM of \MemArray[16]_i_1\ : label is "soft_lutpair1681";
  attribute SOFT_HLUTNM of \MemArray[17]_i_1\ : label is "soft_lutpair1696";
  attribute SOFT_HLUTNM of \MemArray[18]_i_1\ : label is "soft_lutpair1676";
  attribute SOFT_HLUTNM of \MemArray[19]_i_1\ : label is "soft_lutpair1695";
  attribute SOFT_HLUTNM of \MemArray[1]_i_1\ : label is "soft_lutpair1698";
  attribute SOFT_HLUTNM of \MemArray[20]_i_1\ : label is "soft_lutpair1670";
  attribute SOFT_HLUTNM of \MemArray[21]_i_1\ : label is "soft_lutpair1686";
  attribute SOFT_HLUTNM of \MemArray[22]_i_1\ : label is "soft_lutpair1681";
  attribute SOFT_HLUTNM of \MemArray[23]_i_1\ : label is "soft_lutpair1695";
  attribute SOFT_HLUTNM of \MemArray[24]_i_1\ : label is "soft_lutpair1675";
  attribute SOFT_HLUTNM of \MemArray[25]_i_1\ : label is "soft_lutpair1694";
  attribute SOFT_HLUTNM of \MemArray[26]_i_1\ : label is "soft_lutpair1670";
  attribute SOFT_HLUTNM of \MemArray[27]_i_1\ : label is "soft_lutpair1686";
  attribute SOFT_HLUTNM of \MemArray[28]_i_1\ : label is "soft_lutpair1680";
  attribute SOFT_HLUTNM of \MemArray[29]_i_1\ : label is "soft_lutpair1694";
  attribute SOFT_HLUTNM of \MemArray[2]_i_1\ : label is "soft_lutpair1672";
  attribute SOFT_HLUTNM of \MemArray[30]_i_1\ : label is "soft_lutpair1675";
  attribute SOFT_HLUTNM of \MemArray[31]_i_1\ : label is "soft_lutpair1693";
  attribute SOFT_HLUTNM of \MemArray[32]_i_1\ : label is "soft_lutpair1669";
  attribute SOFT_HLUTNM of \MemArray[33]_i_1\ : label is "soft_lutpair1685";
  attribute SOFT_HLUTNM of \MemArray[34]_i_1\ : label is "soft_lutpair1680";
  attribute SOFT_HLUTNM of \MemArray[35]_i_1\ : label is "soft_lutpair1693";
  attribute SOFT_HLUTNM of \MemArray[36]_i_1\ : label is "soft_lutpair1674";
  attribute SOFT_HLUTNM of \MemArray[37]_i_1\ : label is "soft_lutpair1692";
  attribute SOFT_HLUTNM of \MemArray[38]_i_1\ : label is "soft_lutpair1669";
  attribute SOFT_HLUTNM of \MemArray[39]_i_1\ : label is "soft_lutpair1685";
  attribute SOFT_HLUTNM of \MemArray[3]_i_1\ : label is "soft_lutpair1688";
  attribute SOFT_HLUTNM of \MemArray[40]_i_1\ : label is "soft_lutpair1679";
  attribute SOFT_HLUTNM of \MemArray[41]_i_1\ : label is "soft_lutpair1692";
  attribute SOFT_HLUTNM of \MemArray[42]_i_1\ : label is "soft_lutpair1674";
  attribute SOFT_HLUTNM of \MemArray[43]_i_1\ : label is "soft_lutpair1691";
  attribute SOFT_HLUTNM of \MemArray[44]_i_1\ : label is "soft_lutpair1668";
  attribute SOFT_HLUTNM of \MemArray[45]_i_1\ : label is "soft_lutpair1684";
  attribute SOFT_HLUTNM of \MemArray[46]_i_1\ : label is "soft_lutpair1679";
  attribute SOFT_HLUTNM of \MemArray[47]_i_1\ : label is "soft_lutpair1691";
  attribute SOFT_HLUTNM of \MemArray[48]_i_1\ : label is "soft_lutpair1673";
  attribute SOFT_HLUTNM of \MemArray[49]_i_1\ : label is "soft_lutpair1690";
  attribute SOFT_HLUTNM of \MemArray[4]_i_1\ : label is "soft_lutpair1682";
  attribute SOFT_HLUTNM of \MemArray[50]_i_1\ : label is "soft_lutpair1668";
  attribute SOFT_HLUTNM of \MemArray[51]_i_1\ : label is "soft_lutpair1684";
  attribute SOFT_HLUTNM of \MemArray[52]_i_1\ : label is "soft_lutpair1678";
  attribute SOFT_HLUTNM of \MemArray[53]_i_1\ : label is "soft_lutpair1690";
  attribute SOFT_HLUTNM of \MemArray[54]_i_1\ : label is "soft_lutpair1673";
  attribute SOFT_HLUTNM of \MemArray[55]_i_1\ : label is "soft_lutpair1689";
  attribute SOFT_HLUTNM of \MemArray[56]_i_1\ : label is "soft_lutpair1667";
  attribute SOFT_HLUTNM of \MemArray[57]_i_1\ : label is "soft_lutpair1683";
  attribute SOFT_HLUTNM of \MemArray[58]_i_1\ : label is "soft_lutpair1678";
  attribute SOFT_HLUTNM of \MemArray[59]_i_1\ : label is "soft_lutpair1689";
  attribute SOFT_HLUTNM of \MemArray[5]_i_1\ : label is "soft_lutpair1698";
  attribute SOFT_HLUTNM of \MemArray[60]_i_1\ : label is "soft_lutpair1672";
  attribute SOFT_HLUTNM of \MemArray[61]_i_1\ : label is "soft_lutpair1688";
  attribute SOFT_HLUTNM of \MemArray[62]_i_1\ : label is "soft_lutpair1667";
  attribute SOFT_HLUTNM of \MemArray[63]_i_1\ : label is "soft_lutpair1683";
  attribute SOFT_HLUTNM of \MemArray[6]_i_1\ : label is "soft_lutpair1677";
  attribute SOFT_HLUTNM of \MemArray[7]_i_1\ : label is "soft_lutpair1697";
  attribute SOFT_HLUTNM of \MemArray[8]_i_1\ : label is "soft_lutpair1671";
  attribute SOFT_HLUTNM of \MemArray[9]_i_1\ : label is "soft_lutpair1687";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_7_0_5 : label is 576;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_7_0_5 : label is 7;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_7_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_12_17 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_12_17 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_7_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_18_23 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_18_23 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_7_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_24_29 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_24_29 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_7_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_30_35 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_30_35 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_7_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_36_41 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_36_41 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_7_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_42_47 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_42_47 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_7_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_48_53 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_48_53 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_7_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_54_59 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_54_59 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_7_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_60_65 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_60_65 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_7_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_6_11 : label is 576;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_6_11 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_7_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1\ : label is "soft_lutpair1665";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_1\ : label is "soft_lutpair1665";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1\ : label is "soft_lutpair1666";
  attribute SOFT_HLUTNM of \WrPtr[2]_i_1\ : label is "soft_lutpair1666";
begin
\MemArray[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(0),
      O => D(0)
    );
\MemArray[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(10),
      O => D(10)
    );
\MemArray[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(11),
      O => D(11)
    );
\MemArray[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(12),
      O => D(12)
    );
\MemArray[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(13),
      O => D(13)
    );
\MemArray[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(14),
      O => D(14)
    );
\MemArray[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(15),
      O => D(15)
    );
\MemArray[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(16),
      O => D(16)
    );
\MemArray[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_12_17_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(17),
      O => D(17)
    );
\MemArray[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(18),
      O => D(18)
    );
\MemArray[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(19),
      O => D(19)
    );
\MemArray[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(1),
      O => D(1)
    );
\MemArray[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(20),
      O => D(20)
    );
\MemArray[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(21),
      O => D(21)
    );
\MemArray[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(22),
      O => D(22)
    );
\MemArray[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_18_23_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(23),
      O => D(23)
    );
\MemArray[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(24),
      O => D(24)
    );
\MemArray[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(25),
      O => D(25)
    );
\MemArray[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(26),
      O => D(26)
    );
\MemArray[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(27),
      O => D(27)
    );
\MemArray[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(28),
      O => D(28)
    );
\MemArray[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_24_29_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(29),
      O => D(29)
    );
\MemArray[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(2),
      O => D(2)
    );
\MemArray[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(30),
      O => D(30)
    );
\MemArray[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(31),
      O => D(31)
    );
\MemArray[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(32),
      O => D(32)
    );
\MemArray[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(33),
      O => D(33)
    );
\MemArray[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(34),
      O => D(34)
    );
\MemArray[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_30_35_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(35),
      O => D(35)
    );
\MemArray[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(36),
      O => D(36)
    );
\MemArray[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(37),
      O => D(37)
    );
\MemArray[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(38),
      O => D(38)
    );
\MemArray[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(39),
      O => D(39)
    );
\MemArray[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(3),
      O => D(3)
    );
\MemArray[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(40),
      O => D(40)
    );
\MemArray[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_36_41_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(41),
      O => D(41)
    );
\MemArray[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(42),
      O => D(42)
    );
\MemArray[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(43),
      O => D(43)
    );
\MemArray[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(44),
      O => D(44)
    );
\MemArray[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(45),
      O => D(45)
    );
\MemArray[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(46),
      O => D(46)
    );
\MemArray[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_42_47_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(47),
      O => D(47)
    );
\MemArray[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(48),
      O => D(48)
    );
\MemArray[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(49),
      O => D(49)
    );
\MemArray[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(4),
      O => D(4)
    );
\MemArray[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(50),
      O => D(50)
    );
\MemArray[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(51),
      O => D(51)
    );
\MemArray[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(52),
      O => D(52)
    );
\MemArray[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_48_53_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(53),
      O => D(53)
    );
\MemArray[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(54),
      O => D(54)
    );
\MemArray[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(55),
      O => D(55)
    );
\MemArray[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(56),
      O => D(56)
    );
\MemArray[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(57),
      O => D(57)
    );
\MemArray[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_5,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(58),
      O => D(58)
    );
\MemArray[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_54_59_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(59),
      O => D(59)
    );
\MemArray[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_0_5_n_4,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(5),
      O => D(5)
    );
\MemArray[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_60_65_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(60),
      O => D(60)
    );
\MemArray[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_60_65_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(61),
      O => D(61)
    );
\MemArray[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_60_65_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(62),
      O => D(62)
    );
\MemArray[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_60_65_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(63),
      O => D(63)
    );
\MemArray[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_1,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(6),
      O => D(6)
    );
\MemArray[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_0,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(7),
      O => D(7)
    );
\MemArray[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_3,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(8),
      O => D(8)
    );
\MemArray[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => MemArray_reg_0_7_6_11_n_2,
      I1 => wtlp_dat_vld_ff(0),
      I2 => Q(9),
      O => D(9)
    );
MemArray_reg_0_7_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(1 downto 0),
      DIB(1 downto 0) => \MemArray_reg[61]\(3 downto 2),
      DIC(1 downto 0) => \MemArray_reg[61]\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_0_5_n_0,
      DOA(0) => MemArray_reg_0_7_0_5_n_1,
      DOB(1) => MemArray_reg_0_7_0_5_n_2,
      DOB(0) => MemArray_reg_0_7_0_5_n_3,
      DOC(1) => MemArray_reg_0_7_0_5_n_4,
      DOC(0) => MemArray_reg_0_7_0_5_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(13 downto 12),
      DIB(1 downto 0) => \MemArray_reg[61]\(15 downto 14),
      DIC(1 downto 0) => \MemArray_reg[61]\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_12_17_n_0,
      DOA(0) => MemArray_reg_0_7_12_17_n_1,
      DOB(1) => MemArray_reg_0_7_12_17_n_2,
      DOB(0) => MemArray_reg_0_7_12_17_n_3,
      DOC(1) => MemArray_reg_0_7_12_17_n_4,
      DOC(0) => MemArray_reg_0_7_12_17_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(19 downto 18),
      DIB(1 downto 0) => \MemArray_reg[61]\(21 downto 20),
      DIC(1 downto 0) => \MemArray_reg[61]\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_18_23_n_0,
      DOA(0) => MemArray_reg_0_7_18_23_n_1,
      DOB(1) => MemArray_reg_0_7_18_23_n_2,
      DOB(0) => MemArray_reg_0_7_18_23_n_3,
      DOC(1) => MemArray_reg_0_7_18_23_n_4,
      DOC(0) => MemArray_reg_0_7_18_23_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(25 downto 24),
      DIB(1 downto 0) => \MemArray_reg[61]\(27 downto 26),
      DIC(1 downto 0) => \MemArray_reg[61]\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_24_29_n_0,
      DOA(0) => MemArray_reg_0_7_24_29_n_1,
      DOB(1) => MemArray_reg_0_7_24_29_n_2,
      DOB(0) => MemArray_reg_0_7_24_29_n_3,
      DOC(1) => MemArray_reg_0_7_24_29_n_4,
      DOC(0) => MemArray_reg_0_7_24_29_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(31 downto 30),
      DIB(1 downto 0) => \MemArray_reg[61]\(33 downto 32),
      DIC(1 downto 0) => \MemArray_reg[61]\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_30_35_n_0,
      DOA(0) => MemArray_reg_0_7_30_35_n_1,
      DOB(1) => MemArray_reg_0_7_30_35_n_2,
      DOB(0) => MemArray_reg_0_7_30_35_n_3,
      DOC(1) => MemArray_reg_0_7_30_35_n_4,
      DOC(0) => MemArray_reg_0_7_30_35_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(37 downto 36),
      DIB(1 downto 0) => \MemArray_reg[61]\(39 downto 38),
      DIC(1 downto 0) => \MemArray_reg[61]\(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_36_41_n_0,
      DOA(0) => MemArray_reg_0_7_36_41_n_1,
      DOB(1) => MemArray_reg_0_7_36_41_n_2,
      DOB(0) => MemArray_reg_0_7_36_41_n_3,
      DOC(1) => MemArray_reg_0_7_36_41_n_4,
      DOC(0) => MemArray_reg_0_7_36_41_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(43 downto 42),
      DIB(1 downto 0) => \MemArray_reg[61]\(45 downto 44),
      DIC(1 downto 0) => \MemArray_reg[61]\(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_42_47_n_0,
      DOA(0) => MemArray_reg_0_7_42_47_n_1,
      DOB(1) => MemArray_reg_0_7_42_47_n_2,
      DOB(0) => MemArray_reg_0_7_42_47_n_3,
      DOC(1) => MemArray_reg_0_7_42_47_n_4,
      DOC(0) => MemArray_reg_0_7_42_47_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(49 downto 48),
      DIB(1 downto 0) => \MemArray_reg[61]\(51 downto 50),
      DIC(1 downto 0) => \MemArray_reg[61]\(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_48_53_n_0,
      DOA(0) => MemArray_reg_0_7_48_53_n_1,
      DOB(1) => MemArray_reg_0_7_48_53_n_2,
      DOB(0) => MemArray_reg_0_7_48_53_n_3,
      DOC(1) => MemArray_reg_0_7_48_53_n_4,
      DOC(0) => MemArray_reg_0_7_48_53_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(55 downto 54),
      DIB(1 downto 0) => \MemArray_reg[61]\(57 downto 56),
      DIC(1 downto 0) => \MemArray_reg[61]\(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_54_59_n_0,
      DOA(0) => MemArray_reg_0_7_54_59_n_1,
      DOB(1) => MemArray_reg_0_7_54_59_n_2,
      DOB(0) => MemArray_reg_0_7_54_59_n_3,
      DOC(1) => MemArray_reg_0_7_54_59_n_4,
      DOC(0) => MemArray_reg_0_7_54_59_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(61 downto 60),
      DIB(1 downto 0) => \MemArray_reg[61]\(63 downto 62),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_60_65_n_0,
      DOA(0) => MemArray_reg_0_7_60_65_n_1,
      DOB(1) => MemArray_reg_0_7_60_65_n_2,
      DOB(0) => MemArray_reg_0_7_60_65_n_3,
      DOC(1) => MemArray_reg_0_7_60_65_n_4,
      DOC(0) => MemArray_reg_0_7_60_65_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
MemArray_reg_0_7_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => \MemArray_reg[61]\(7 downto 6),
      DIB(1 downto 0) => \MemArray_reg[61]\(9 downto 8),
      DIC(1 downto 0) => \MemArray_reg[61]\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_7_6_11_n_0,
      DOA(0) => MemArray_reg_0_7_6_11_n_1,
      DOB(1) => MemArray_reg_0_7_6_11_n_2,
      DOB(0) => MemArray_reg_0_7_6_11_n_3,
      DOC(1) => MemArray_reg_0_7_6_11_n_4,
      DOC(0) => MemArray_reg_0_7_6_11_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_wpl_wen_504
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RdPtr(0),
      I1 => wtlp_dat_ren,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RdPtr(0),
      I1 => wtlp_dat_ren,
      I2 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => wtlp_dat_ren,
      I1 => RdPtr(0),
      I2 => RdPtr(1),
      I3 => RdPtr(2),
      O => \RdPtr__0\(2)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => SR(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => RdPtr(2),
      R => SR(0)
    );
\WrPtr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \WrPtr_reg[0]_0\,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \WrPtr_reg[0]_0\,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => WrPtr(0),
      I2 => WrPtr(1),
      I3 => WrPtr(2),
      O => \WrPtr__0\(2)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => SR(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => WrPtr(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFOAsync is
  port (
    empty_ff : out STD_LOGIC;
    almost_full_ff_reg_0 : out STD_LOGIC;
    \Head_reg[18]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 79 downto 0 );
    \FifoCntrRd_reg[1]_0\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rreq_lbe : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \rreq_head_info_ff_reg[1][len][3]_i_1_0\ : out STD_LOGIC;
    \rreq_head_info_ff_reg[1][fbe][2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Head_reg[18]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[30]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[29]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[30]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    A : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \FifoCntrRd_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrWr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \RdPtr_reg[0]_0\ : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \WrPtr_reg[0]_0\ : out STD_LOGIC;
    I13 : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rreq_head_ld_shf_0 : in STD_LOGIC;
    \Head_reg[121]_0\ : in STD_LOGIC;
    \Head_reg[121]_1\ : in STD_LOGIC;
    Head0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[121]_2\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][lbe][3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rreq_head_info_ff_reg[0][fbe][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    tag_sel_ff0 : in STD_LOGIC;
    \FifoCntrWr_reg[2]_0\ : in STD_LOGIC;
    payloadOut : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RdPtr_reg[0]_1\ : in STD_LOGIC;
    empty_ff_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    H2C_RRQ_RDY_IN0 : in STD_LOGIC;
    \Head_reg[119]_0\ : in STD_LOGIC_VECTOR ( 91 downto 0 );
    \FifoCntrWr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFOAsync : entity is "xdma_v4_1_8_GenericFIFOAsync";
end xdma_0_xdma_v4_1_8_GenericFIFOAsync;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFOAsync is
  signal \^a\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \FifoCntrRd[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \^fifocntrrd_reg[1]_0\ : STD_LOGIC;
  signal \^fifocntrrd_reg[1]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \FifoCntrWr[0]_i_1__13_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__10_n_0\ : STD_LOGIC;
  signal \^fifocntrwr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \Head[121]_i_1__1_n_0\ : STD_LOGIC;
  signal \^head_reg[30]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^i13\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \RdPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \^rdptr_reg[0]_0\ : STD_LOGIC;
  signal \WrPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \^wrptr_reg[0]_0\ : STD_LOGIC;
  signal \almost_full_ff_i_1__3_n_0\ : STD_LOGIC;
  signal \^almost_full_ff_reg_0\ : STD_LOGIC;
  signal arb_rrq_pay : STD_LOGIC_VECTOR ( 30 downto 18 );
  signal \empty_ff_i_1__13_n_0\ : STD_LOGIC;
  signal \^out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 121 to 121 );
  signal \rreq_head_info_ff[1][fbe][2]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][fbe][3]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][fbe][3]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][len][3]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][len][3]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][len][3]_i_5_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_10_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_5_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_6_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_7_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_8_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[1][rcb][4]_i_9_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_1_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_3_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_3_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][10]_i_3_n_3\ : STD_LOGIC;
  signal \^rreq_head_info_ff_reg[1][len][3]_i_1_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_1_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_1_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_1_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_2_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_2_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][3]_i_2_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_1_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_1_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_1_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_2_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_2_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][len][7]_i_2_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_3\ : STD_LOGIC;
  signal \^rreq_lbe\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_rreq_head_info_ff_reg[1][len][10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_rreq_head_info_ff_reg[1][len][10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_rreq_head_info_ff_reg[1][len][10]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rreq_head_info_ff_reg[1][len][10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_rreq_head_info_ff_reg[1][len][3]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__12\ : label is "soft_lutpair1435";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__2\ : label is "soft_lutpair1435";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__13\ : label is "soft_lutpair1436";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__10\ : label is "soft_lutpair1436";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_2__4\ : label is "soft_lutpair1430";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_3__1\ : label is "soft_lutpair1430";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \RdPtr_reg[1]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[1]\ : label is "128";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][fbe][2]_i_1\ : label is "soft_lutpair1433";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][lbe][3]_i_1\ : label is "soft_lutpair1431";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][fbe][0]_i_1\ : label is "soft_lutpair1437";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][fbe][1]_i_1\ : label is "soft_lutpair1437";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][fbe][2]_i_1\ : label is "soft_lutpair1433";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][fbe][2]_i_2\ : label is "soft_lutpair1434";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][fbe][3]_i_1\ : label is "soft_lutpair1434";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][lbe][1]_i_1\ : label is "soft_lutpair1432";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][lbe][2]_i_1\ : label is "soft_lutpair1432";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][lbe][3]_i_1\ : label is "soft_lutpair1431";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[0][rcb][7]_i_4\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[0][rcb][7]_i_5\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][10]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][10]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][3]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][3]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][7]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][len][7]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][rcb][4]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \rreq_head_info_ff_reg[1][rcb][4]_i_4\ : label is 35;
begin
  A(10 downto 0) <= \^a\(10 downto 0);
  \FifoCntrRd_reg[1]_0\ <= \^fifocntrrd_reg[1]_0\;
  \FifoCntrRd_reg[1]_1\(1 downto 0) <= \^fifocntrrd_reg[1]_1\(1 downto 0);
  \FifoCntrWr_reg[1]_0\(1 downto 0) <= \^fifocntrwr_reg[1]_0\(1 downto 0);
  \Head_reg[30]_0\(10 downto 0) <= \^head_reg[30]_0\(10 downto 0);
  I13(0) <= \^i13\(0);
  Q(79 downto 0) <= \^q\(79 downto 0);
  \RdPtr_reg[0]_0\ <= \^rdptr_reg[0]_0\;
  \WrPtr_reg[0]_0\ <= \^wrptr_reg[0]_0\;
  almost_full_ff_reg_0 <= \^almost_full_ff_reg_0\;
  \out\(0) <= \^out\(0);
  \rreq_head_info_ff_reg[1][len][3]_i_1_0\ <= \^rreq_head_info_ff_reg[1][len][3]_i_1_0\;
  rreq_lbe(3 downto 0) <= \^rreq_lbe\(3 downto 0);
\FifoCntrRd[0]_i_1__12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_1\(0),
      O => \FifoCntrRd[0]_i_1__12_n_0\
    );
\FifoCntrRd[2]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"666AAAA9"
    )
        port map (
      I0 => FifoCntrRd(2),
      I1 => \^fifocntrrd_reg[1]_1\(1),
      I2 => payloadOut(0),
      I3 => \FifoCntrWr_reg[2]_0\,
      I4 => \^fifocntrrd_reg[1]_1\(0),
      O => \FifoCntrRd[2]_i_2__2_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd[0]_i_1__12_n_0\,
      Q => \^fifocntrrd_reg[1]_1\(0),
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd_reg[1]_2\(0),
      Q => \^fifocntrrd_reg[1]_1\(1),
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd[2]_i_2__2_n_0\,
      Q => FifoCntrRd(2),
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[0]_i_1__13_n_0\
    );
\FifoCntrWr[2]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"666AAAA9"
    )
        port map (
      I0 => FifoCntrWr(2),
      I1 => \^fifocntrwr_reg[1]_0\(1),
      I2 => payloadOut(0),
      I3 => \FifoCntrWr_reg[2]_0\,
      I4 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[2]_i_1__10_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[0]_i_1__13_n_0\,
      Q => \^fifocntrwr_reg[1]_0\(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr_reg[1]_1\(0),
      Q => \^fifocntrwr_reg[1]_0\(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[2]_i_1__10_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
\Head[121]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF01"
    )
        port map (
      I0 => FifoCntrRd(2),
      I1 => \^fifocntrrd_reg[1]_1\(1),
      I2 => \^fifocntrrd_reg[1]_1\(0),
      I3 => tag_sel_ff0,
      I4 => \^fifocntrrd_reg[1]_0\,
      O => \Head[121]_i_1__1_n_0\
    );
\Head[121]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00220033F0F0F0F0"
    )
        port map (
      I0 => \Head_reg[121]_0\,
      I1 => \Head_reg[121]_1\,
      I2 => Head0(0),
      I3 => \^almost_full_ff_reg_0\,
      I4 => \Head_reg[121]_2\,
      I5 => \^fifocntrrd_reg[1]_0\,
      O => p_0_in1_in(121)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(72),
      Q => \^q\(59),
      R => SR(0)
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(73),
      Q => \^q\(60),
      R => SR(0)
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(74),
      Q => \^q\(61),
      R => SR(0)
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(75),
      Q => \^q\(62),
      R => SR(0)
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(76),
      Q => \^q\(63),
      R => SR(0)
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(77),
      Q => \^q\(64),
      R => SR(0)
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(78),
      Q => \^q\(65),
      R => SR(0)
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(79),
      Q => \^q\(66),
      R => SR(0)
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(80),
      Q => \^q\(67),
      R => SR(0)
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(81),
      Q => \^q\(68),
      R => SR(0)
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(2),
      Q => \^q\(2),
      R => SR(0)
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(82),
      Q => \^q\(69),
      R => SR(0)
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(83),
      Q => \^q\(70),
      R => SR(0)
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(84),
      Q => \^q\(71),
      R => SR(0)
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(85),
      Q => \^q\(72),
      R => SR(0)
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(86),
      Q => \^q\(73),
      R => SR(0)
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(87),
      Q => \^q\(74),
      R => SR(0)
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(88),
      Q => \^q\(75),
      R => SR(0)
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(89),
      Q => \^q\(76),
      R => SR(0)
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(90),
      Q => \^q\(77),
      R => SR(0)
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(91),
      Q => \^q\(78),
      R => SR(0)
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(3),
      Q => \^q\(3),
      R => SR(0)
    );
\Head_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => p_0_in1_in(121),
      Q => \^q\(79),
      R => SR(0)
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(4),
      Q => \^q\(4),
      R => SR(0)
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(5),
      Q => \^q\(5),
      R => SR(0)
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(6),
      Q => \^q\(6),
      R => SR(0)
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(7),
      Q => \^q\(7),
      R => SR(0)
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(8),
      Q => \^q\(8),
      R => SR(0)
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(9),
      Q => arb_rrq_pay(18),
      R => SR(0)
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(10),
      Q => arb_rrq_pay(19),
      R => SR(0)
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(11),
      Q => arb_rrq_pay(20),
      R => SR(0)
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(12),
      Q => arb_rrq_pay(21),
      R => SR(0)
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(13),
      Q => arb_rrq_pay(22),
      R => SR(0)
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(14),
      Q => arb_rrq_pay(23),
      R => SR(0)
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(15),
      Q => arb_rrq_pay(24),
      R => SR(0)
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(16),
      Q => arb_rrq_pay(25),
      R => SR(0)
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(17),
      Q => arb_rrq_pay(26),
      R => SR(0)
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(18),
      Q => arb_rrq_pay(27),
      R => SR(0)
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(19),
      Q => arb_rrq_pay(28),
      R => SR(0)
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(20),
      Q => arb_rrq_pay(29),
      R => SR(0)
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(21),
      Q => arb_rrq_pay(30),
      R => SR(0)
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(22),
      Q => \^q\(9),
      R => SR(0)
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(23),
      Q => \^q\(10),
      R => SR(0)
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(24),
      Q => \^q\(11),
      R => SR(0)
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(25),
      Q => \^q\(12),
      R => SR(0)
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(26),
      Q => \^q\(13),
      R => SR(0)
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(27),
      Q => \^q\(14),
      R => SR(0)
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(28),
      Q => \^q\(15),
      R => SR(0)
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(29),
      Q => \^q\(16),
      R => SR(0)
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(30),
      Q => \^q\(17),
      R => SR(0)
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(31),
      Q => \^q\(18),
      R => SR(0)
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(32),
      Q => \^q\(19),
      R => SR(0)
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(33),
      Q => \^q\(20),
      R => SR(0)
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(34),
      Q => \^q\(21),
      R => SR(0)
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(35),
      Q => \^q\(22),
      R => SR(0)
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(36),
      Q => \^q\(23),
      R => SR(0)
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(37),
      Q => \^q\(24),
      R => SR(0)
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(38),
      Q => \^q\(25),
      R => SR(0)
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(39),
      Q => \^q\(26),
      R => SR(0)
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(40),
      Q => \^q\(27),
      R => SR(0)
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(41),
      Q => \^q\(28),
      R => SR(0)
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(42),
      Q => \^q\(29),
      R => SR(0)
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(43),
      Q => \^q\(30),
      R => SR(0)
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(44),
      Q => \^q\(31),
      R => SR(0)
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(45),
      Q => \^q\(32),
      R => SR(0)
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(46),
      Q => \^q\(33),
      R => SR(0)
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(47),
      Q => \^q\(34),
      R => SR(0)
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(48),
      Q => \^q\(35),
      R => SR(0)
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(49),
      Q => \^q\(36),
      R => SR(0)
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(50),
      Q => \^q\(37),
      R => SR(0)
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(51),
      Q => \^q\(38),
      R => SR(0)
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(52),
      Q => \^q\(39),
      R => SR(0)
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(53),
      Q => \^q\(40),
      R => SR(0)
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(54),
      Q => \^q\(41),
      R => SR(0)
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(55),
      Q => \^q\(42),
      R => SR(0)
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(56),
      Q => \^q\(43),
      R => SR(0)
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(57),
      Q => \^q\(44),
      R => SR(0)
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(58),
      Q => \^q\(45),
      R => SR(0)
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(59),
      Q => \^q\(46),
      R => SR(0)
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(60),
      Q => \^q\(47),
      R => SR(0)
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(61),
      Q => \^q\(48),
      R => SR(0)
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(62),
      Q => \^q\(49),
      R => SR(0)
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(63),
      Q => \^q\(50),
      R => SR(0)
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(64),
      Q => \^q\(51),
      R => SR(0)
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(65),
      Q => \^q\(52),
      R => SR(0)
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(66),
      Q => \^q\(53),
      R => SR(0)
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(67),
      Q => \^q\(54),
      R => SR(0)
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(68),
      Q => \^q\(55),
      R => SR(0)
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(69),
      Q => \^q\(56),
      R => SR(0)
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(70),
      Q => \^q\(57),
      R => SR(0)
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(71),
      Q => \^q\(58),
      R => SR(0)
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[121]_i_1__1_n_0\,
      D => \Head_reg[119]_0\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555777F55554440"
    )
        port map (
      I0 => \^rdptr_reg[0]_0\,
      I1 => tag_sel_ff0,
      I2 => \^fifocntrrd_reg[1]_1\(1),
      I3 => FifoCntrRd(2),
      I4 => \^fifocntrrd_reg[1]_0\,
      I5 => \^rdptr_reg[0]_0\,
      O => \RdPtr[0]_i_1_n_0\
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"66666FFF66666000"
    )
        port map (
      I0 => \^rdptr_reg[0]_0\,
      I1 => \^out\(0),
      I2 => tag_sel_ff0,
      I3 => \RdPtr[1]_i_2__4_n_0\,
      I4 => \^fifocntrrd_reg[1]_0\,
      I5 => \^out\(0),
      O => \RdPtr[1]_i_1_n_0\
    );
\RdPtr[1]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_1\(1),
      I1 => FifoCntrRd(2),
      O => \RdPtr[1]_i_2__4_n_0\
    );
\RdPtr[1]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100000"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_1\(1),
      I1 => FifoCntrRd(2),
      I2 => \FifoCntrWr_reg[2]_0\,
      I3 => payloadOut(0),
      I4 => \RdPtr_reg[0]_1\,
      O => \^fifocntrrd_reg[1]_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1_n_0\,
      Q => \^rdptr_reg[0]_0\,
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1_n_0\,
      Q => \^out\(0),
      R => SR(0)
    );
\WrPtr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5754"
    )
        port map (
      I0 => \^wrptr_reg[0]_0\,
      I1 => H2C_RRQ_RDY_IN0,
      I2 => payloadOut(0),
      I3 => \^wrptr_reg[0]_0\,
      O => \WrPtr[0]_i_1_n_0\
    );
\WrPtr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"666F6660"
    )
        port map (
      I0 => \^wrptr_reg[0]_0\,
      I1 => \^i13\(0),
      I2 => H2C_RRQ_RDY_IN0,
      I3 => payloadOut(0),
      I4 => \^i13\(0),
      O => \WrPtr[1]_i_1_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1_n_0\,
      Q => \^wrptr_reg[0]_0\,
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1_n_0\,
      Q => \^i13\(0),
      R => SR(0)
    );
\almost_full_ff_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      I1 => \^fifocntrwr_reg[1]_0\(1),
      I2 => FifoCntrWr(2),
      O => \almost_full_ff_i_1__3_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__3_n_0\,
      Q => \^almost_full_ff_reg_0\,
      R => SR(0)
    );
\empty_ff_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"57555757"
    )
        port map (
      I0 => empty_ff_reg_0(0),
      I1 => \^fifocntrrd_reg[1]_1\(1),
      I2 => FifoCntrRd(2),
      I3 => tag_sel_ff0,
      I4 => \^fifocntrrd_reg[1]_1\(0),
      O => \empty_ff_i_1__13_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__13_n_0\,
      Q => empty_ff,
      R => '0'
    );
\rreq_head_info_ff[0][fbe][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBB88B"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][fbe][2]\(0),
      I1 => rreq_head_ld_shf_0,
      I2 => arb_rrq_pay(18),
      I3 => \^q\(15),
      I4 => \rreq_head_info_ff[1][fbe][2]_i_2_n_0\,
      I5 => \^q\(16),
      O => \rreq_head_info_ff_reg[1][fbe][2]\(0)
    );
\rreq_head_info_ff[0][fbe][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88B8B8B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][fbe][2]\(1),
      I1 => rreq_head_ld_shf_0,
      I2 => \rreq_head_info_ff[1][fbe][2]_i_2_n_0\,
      I3 => \^q\(15),
      I4 => \^q\(16),
      O => \rreq_head_info_ff_reg[1][fbe][2]\(1)
    );
\rreq_head_info_ff[0][lbe][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B88888B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][lbe][3]\(0),
      I1 => rreq_head_ld_shf_0,
      I2 => \^rreq_lbe\(2),
      I3 => \^q\(15),
      I4 => arb_rrq_pay(18),
      O => D(0)
    );
\rreq_head_info_ff[0][len][3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000E77E"
    )
        port map (
      I0 => arb_rrq_pay(18),
      I1 => \^q\(15),
      I2 => \^q\(16),
      I3 => arb_rrq_pay(19),
      I4 => rreq_head_ld_shf_0,
      O => \Head_reg[18]_0\
    );
\rreq_head_info_ff[1][fbe][0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(16),
      I1 => \^q\(15),
      O => \Head_reg[18]_1\(0)
    );
\rreq_head_info_ff[1][fbe][1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00F9"
    )
        port map (
      I0 => arb_rrq_pay(18),
      I1 => \^q\(15),
      I2 => \rreq_head_info_ff[1][fbe][2]_i_2_n_0\,
      I3 => \^q\(16),
      O => \Head_reg[18]_1\(1)
    );
\rreq_head_info_ff[1][fbe][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \^q\(15),
      I1 => \^q\(16),
      I2 => \rreq_head_info_ff[1][fbe][2]_i_2_n_0\,
      O => \Head_reg[18]_1\(2)
    );
\rreq_head_info_ff[1][fbe][2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"57FDFD57"
    )
        port map (
      I0 => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\,
      I1 => arb_rrq_pay(18),
      I2 => \^q\(15),
      I3 => \^q\(16),
      I4 => arb_rrq_pay(19),
      O => \rreq_head_info_ff[1][fbe][2]_i_2_n_0\
    );
\rreq_head_info_ff[1][fbe][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1881FFFF"
    )
        port map (
      I0 => arb_rrq_pay(18),
      I1 => \^q\(15),
      I2 => arb_rrq_pay(19),
      I3 => \^q\(16),
      I4 => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\,
      O => \Head_reg[18]_1\(3)
    );
\rreq_head_info_ff[1][fbe][3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \rreq_head_info_ff[1][fbe][3]_i_3_n_0\,
      I1 => \rreq_head_info_ff[1][fbe][3]_i_4_n_0\,
      I2 => \^head_reg[30]_0\(0),
      I3 => \^head_reg[30]_0\(1),
      I4 => \^head_reg[30]_0\(2),
      O => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\
    );
\rreq_head_info_ff[1][fbe][3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^head_reg[30]_0\(6),
      I1 => \^head_reg[30]_0\(5),
      I2 => \^head_reg[30]_0\(4),
      I3 => \^head_reg[30]_0\(3),
      O => \rreq_head_info_ff[1][fbe][3]_i_3_n_0\
    );
\rreq_head_info_ff[1][fbe][3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^head_reg[30]_0\(10),
      I1 => \^head_reg[30]_0\(9),
      I2 => \^head_reg[30]_0\(8),
      I3 => \^head_reg[30]_0\(7),
      O => \rreq_head_info_ff[1][fbe][3]_i_4_n_0\
    );
\rreq_head_info_ff[1][lbe][0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\,
      O => \^rreq_lbe\(0)
    );
\rreq_head_info_ff[1][lbe][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F66F"
    )
        port map (
      I0 => arb_rrq_pay(19),
      I1 => \^q\(16),
      I2 => \^q\(15),
      I3 => arb_rrq_pay(18),
      I4 => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\,
      O => \^rreq_lbe\(1)
    );
\rreq_head_info_ff[1][lbe][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01545401"
    )
        port map (
      I0 => \^rreq_head_info_ff_reg[1][len][3]_i_1_0\,
      I1 => arb_rrq_pay(18),
      I2 => \^q\(15),
      I3 => \^q\(16),
      I4 => arb_rrq_pay(19),
      O => \^rreq_lbe\(2)
    );
\rreq_head_info_ff[1][lbe][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^rreq_lbe\(2),
      I1 => \^q\(15),
      I2 => arb_rrq_pay(18),
      O => \^rreq_lbe\(3)
    );
\rreq_head_info_ff[1][len][3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"56959556"
    )
        port map (
      I0 => \^a\(0),
      I1 => arb_rrq_pay(18),
      I2 => \^q\(15),
      I3 => \^q\(16),
      I4 => arb_rrq_pay(19),
      O => \rreq_head_info_ff[1][len][3]_i_3_n_0\
    );
\rreq_head_info_ff[1][len][3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(19),
      I1 => \^q\(16),
      O => \rreq_head_info_ff[1][len][3]_i_4_n_0\
    );
\rreq_head_info_ff[1][len][3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(18),
      I1 => \^q\(15),
      O => \rreq_head_info_ff[1][len][3]_i_5_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(18),
      I1 => \^q\(15),
      O => \rreq_head_info_ff[1][rcb][4]_i_10_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(23),
      I1 => \^q\(20),
      O => \rreq_head_info_ff[1][rcb][4]_i_5_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(22),
      I1 => \^q\(19),
      O => \rreq_head_info_ff[1][rcb][4]_i_6_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(21),
      I1 => \^q\(18),
      O => \rreq_head_info_ff[1][rcb][4]_i_7_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(20),
      I1 => \^q\(17),
      O => \rreq_head_info_ff[1][rcb][4]_i_8_n_0\
    );
\rreq_head_info_ff[1][rcb][4]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_rrq_pay(19),
      I1 => \^q\(16),
      O => \rreq_head_info_ff[1][rcb][4]_i_9_n_0\
    );
\rreq_head_info_ff_reg[0][rcb][7]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0\,
      CO(3) => \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0\,
      CO(2) => \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_1\,
      CO(1) => \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_2\,
      CO(0) => \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Head_reg[29]_0\(3 downto 0),
      S(3 downto 0) => arb_rrq_pay(29 downto 26)
    );
\rreq_head_info_ff_reg[0][rcb][7]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0\,
      CO(3 downto 0) => \NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_O_UNCONNECTED\(3 downto 1),
      O(0) => \Head_reg[30]_1\(0),
      S(3 downto 1) => B"000",
      S(0) => arb_rrq_pay(30)
    );
\rreq_head_info_ff_reg[1][len][10]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][len][7]_i_1_n_0\,
      CO(3 downto 2) => \NLW_rreq_head_info_ff_reg[1][len][10]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \rreq_head_info_ff_reg[1][len][10]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][10]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_rreq_head_info_ff_reg[1][len][10]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => \^head_reg[30]_0\(10 downto 8),
      S(3) => '0',
      S(2 downto 0) => \^a\(10 downto 8)
    );
\rreq_head_info_ff_reg[1][len][10]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][len][10]_i_3_n_0\,
      CO(3 downto 0) => \NLW_rreq_head_info_ff_reg[1][len][10]_i_2_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_rreq_head_info_ff_reg[1][len][10]_i_2_O_UNCONNECTED\(3 downto 1),
      O(0) => \^a\(10),
      S(3 downto 1) => B"000",
      S(0) => arb_rrq_pay(30)
    );
\rreq_head_info_ff_reg[1][len][10]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][len][7]_i_2_n_0\,
      CO(3) => \rreq_head_info_ff_reg[1][len][10]_i_3_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][len][10]_i_3_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][len][10]_i_3_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][10]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \^a\(9 downto 6),
      S(3 downto 0) => arb_rrq_pay(29 downto 26)
    );
\rreq_head_info_ff_reg[1][len][3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_info_ff_reg[1][len][3]_i_1_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][len][3]_i_1_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][len][3]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][3]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \^a\(0),
      O(3 downto 0) => \^head_reg[30]_0\(3 downto 0),
      S(3 downto 1) => \^a\(3 downto 1),
      S(0) => \rreq_head_info_ff[1][len][3]_i_3_n_0\
    );
\rreq_head_info_ff_reg[1][len][3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_info_ff_reg[1][len][3]_i_2_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][len][3]_i_2_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][len][3]_i_2_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][3]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => arb_rrq_pay(19 downto 18),
      O(3 downto 2) => \^a\(1 downto 0),
      O(1 downto 0) => \NLW_rreq_head_info_ff_reg[1][len][3]_i_2_O_UNCONNECTED\(1 downto 0),
      S(3 downto 2) => arb_rrq_pay(21 downto 20),
      S(1) => \rreq_head_info_ff[1][len][3]_i_4_n_0\,
      S(0) => \rreq_head_info_ff[1][len][3]_i_5_n_0\
    );
\rreq_head_info_ff_reg[1][len][7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][len][3]_i_1_n_0\,
      CO(3) => \rreq_head_info_ff_reg[1][len][7]_i_1_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][len][7]_i_1_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][len][7]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][7]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \^head_reg[30]_0\(7 downto 4),
      S(3 downto 0) => \^a\(7 downto 4)
    );
\rreq_head_info_ff_reg[1][len][7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][len][3]_i_2_n_0\,
      CO(3) => \rreq_head_info_ff_reg[1][len][7]_i_2_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][len][7]_i_2_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][len][7]_i_2_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][len][7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \^a\(5 downto 2),
      S(3 downto 0) => arb_rrq_pay(25 downto 22)
    );
\rreq_head_info_ff_reg[1][rcb][4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0\,
      CO(3) => \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => arb_rrq_pay(23 downto 22),
      O(3 downto 0) => \Head_reg[23]_0\(3 downto 0),
      S(3 downto 2) => arb_rrq_pay(25 downto 24),
      S(1) => \rreq_head_info_ff[1][rcb][4]_i_5_n_0\,
      S(0) => \rreq_head_info_ff[1][rcb][4]_i_6_n_0\
    );
\rreq_head_info_ff_reg[1][rcb][4]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0\,
      CO(2) => \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_1\,
      CO(1) => \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_2\,
      CO(0) => \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => arb_rrq_pay(21 downto 18),
      O(3 downto 0) => O(3 downto 0),
      S(3) => \rreq_head_info_ff[1][rcb][4]_i_7_n_0\,
      S(2) => \rreq_head_info_ff[1][rcb][4]_i_8_n_0\,
      S(1) => \rreq_head_info_ff[1][rcb][4]_i_9_n_0\,
      S(0) => \rreq_head_info_ff[1][rcb][4]_i_10_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFOAsync_54 is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    almost_full_ff_reg_0 : out STD_LOGIC;
    \Head_reg[21]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 66 downto 0 );
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[29]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    user_clk : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \WrPtr_reg[0]_0\ : in STD_LOGIC;
    DataOut : in STD_LOGIC_VECTOR ( 75 downto 0 );
    arb_rrq_rdy : in STD_LOGIC;
    \Head_reg[19]_0\ : in STD_LOGIC;
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \RdPtr_reg[0]_0\ : in STD_LOGIC;
    payloadOut : in STD_LOGIC_VECTOR ( 75 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFOAsync_54 : entity is "xdma_v4_1_8_GenericFIFOAsync";
end xdma_0_xdma_v4_1_8_GenericFIFOAsync_54;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFOAsync_54 is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__12_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__11_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__5_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__14_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__13_n_0\ : STD_LOGIC;
  signal Head0_0 : STD_LOGIC_VECTOR ( 119 downto 18 );
  signal \Head1__2\ : STD_LOGIC;
  signal \Head[119]_i_1__4_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_1 : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 66 downto 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal RdPtr_reg0 : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1__16_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__16_n_0\ : STD_LOGIC;
  signal \almost_full_ff_i_1__1_n_0\ : STD_LOGIC;
  signal \^almost_full_ff_reg_0\ : STD_LOGIC;
  signal \empty_ff_i_1__7_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_11_n_0 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_11_n_1 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_11_n_2 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_11_n_3 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_11_n_4 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_7_n_1 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_7_n_2 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_7_n_3 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_8_n_1 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_8_n_2 : STD_LOGIC;
  signal m_axi_arlenissueq_reg_0_15_0_5_i_8_n_3 : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 119 downto 18 );
  signal tlpbytelength : STD_LOGIC_VECTOR ( 11 downto 3 );
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__12\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__5\ : label is "soft_lutpair486";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__14\ : label is "soft_lutpair487";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__13\ : label is "soft_lutpair487";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 488;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_113 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_113 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_113 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_114_119 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_114_119 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_114_119 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_3_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 488;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \RdPtr_reg[1]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[1]\ : label is "128";
begin
  Q(66 downto 0) <= \^q\(66 downto 0);
  almost_full_ff_reg_0 <= \^almost_full_ff_reg_0\;
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
\FifoCntrRd[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__6_n_0\
    );
\FifoCntrRd[1]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C396"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(1),
      I3 => \^almost_full_ff_reg_0\,
      O => \FifoCntrRd[1]_i_1__12_n_0\
    );
\FifoCntrRd[2]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"11E1"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => arb_rrq_rdy,
      I3 => \^empty_ff_reg_0\,
      O => \FifoCntrRd[2]_i_1__11_n_0\
    );
\FifoCntrRd[2]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FC03BD42"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \^almost_full_ff_reg_0\,
      O => \FifoCntrRd[2]_i_2__5_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrRd[0]_i_1__6_n_0\,
      Q => FifoCntrRd(0),
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrRd[1]_i_1__12_n_0\,
      Q => FifoCntrRd(1),
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrRd[2]_i_2__5_n_0\,
      Q => FifoCntrRd(2),
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__5_n_0\
    );
\FifoCntrWr[1]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C396"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(1),
      I3 => \^almost_full_ff_reg_0\,
      O => \FifoCntrWr[1]_i_1__14_n_0\
    );
\FifoCntrWr[2]_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FC03BD42"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(1),
      I3 => FifoCntrWr(2),
      I4 => \^almost_full_ff_reg_0\,
      O => \FifoCntrWr[2]_i_1__13_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrWr[0]_i_1__5_n_0\,
      Q => FifoCntrWr(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrWr[1]_i_1__14_n_0\,
      Q => FifoCntrWr(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__11_n_0\,
      D => \FifoCntrWr[2]_i_1__13_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
\Head[100]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(56),
      I3 => Head0_0(100),
      I4 => \Head1__2\,
      O => p_0_in1_in(100)
    );
\Head[101]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(57),
      I3 => Head0_0(101),
      I4 => \Head1__2\,
      O => p_0_in1_in(101)
    );
\Head[102]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(58),
      I3 => Head0_0(102),
      I4 => \Head1__2\,
      O => p_0_in1_in(102)
    );
\Head[103]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(59),
      I3 => Head0_0(103),
      I4 => \Head1__2\,
      O => p_0_in1_in(103)
    );
\Head[104]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(60),
      I3 => Head0_0(104),
      I4 => \Head1__2\,
      O => p_0_in1_in(104)
    );
\Head[105]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(61),
      I3 => Head0_0(105),
      I4 => \Head1__2\,
      O => p_0_in1_in(105)
    );
\Head[106]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(62),
      I3 => Head0_0(106),
      I4 => \Head1__2\,
      O => p_0_in1_in(106)
    );
\Head[107]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(63),
      I3 => Head0_0(107),
      I4 => \Head1__2\,
      O => p_0_in1_in(107)
    );
\Head[108]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(64),
      I3 => Head0_0(108),
      I4 => \Head1__2\,
      O => p_0_in1_in(108)
    );
\Head[109]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(65),
      I3 => Head0_0(109),
      I4 => \Head1__2\,
      O => p_0_in1_in(109)
    );
\Head[110]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(66),
      I3 => Head0_0(110),
      I4 => \Head1__2\,
      O => p_0_in1_in(110)
    );
\Head[111]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(67),
      I3 => Head0_0(111),
      I4 => \Head1__2\,
      O => p_0_in1_in(111)
    );
\Head[112]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(68),
      I3 => Head0_0(112),
      I4 => \Head1__2\,
      O => p_0_in1_in(112)
    );
\Head[113]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(69),
      I3 => Head0_0(113),
      I4 => \Head1__2\,
      O => p_0_in1_in(113)
    );
\Head[114]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(70),
      I3 => Head0_0(114),
      I4 => \Head1__2\,
      O => p_0_in1_in(114)
    );
\Head[115]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(71),
      I3 => Head0_0(115),
      I4 => \Head1__2\,
      O => p_0_in1_in(115)
    );
\Head[116]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(72),
      I3 => Head0_0(116),
      I4 => \Head1__2\,
      O => p_0_in1_in(116)
    );
\Head[117]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(73),
      I3 => Head0_0(117),
      I4 => \Head1__2\,
      O => p_0_in1_in(117)
    );
\Head[118]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(74),
      I3 => Head0_0(118),
      I4 => \Head1__2\,
      O => p_0_in1_in(118)
    );
\Head[119]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEAEAEAEAEFF"
    )
        port map (
      I0 => \Head1__2\,
      I1 => arb_rrq_rdy,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => FifoCntrRd(0),
      O => \Head[119]_i_1__4_n_0\
    );
\Head[119]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(75),
      I3 => Head0_0(119),
      I4 => \Head1__2\,
      O => p_0_in1_in(119)
    );
\Head[18]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(0),
      I3 => Head0_0(18),
      I4 => \Head1__2\,
      O => p_0_in1_in(18)
    );
\Head[19]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(1),
      I3 => Head0_0(19),
      I4 => \Head1__2\,
      O => p_0_in1_in(19)
    );
\Head[20]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(2),
      I3 => Head0_0(20),
      I4 => \Head1__2\,
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(3),
      I3 => Head0_0(21),
      I4 => \Head1__2\,
      O => p_0_in1_in(21)
    );
\Head[22]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(4),
      I3 => Head0_0(22),
      I4 => \Head1__2\,
      O => p_0_in1_in(22)
    );
\Head[23]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(5),
      I3 => Head0_0(23),
      I4 => \Head1__2\,
      O => p_0_in1_in(23)
    );
\Head[24]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(6),
      I3 => Head0_0(24),
      I4 => \Head1__2\,
      O => p_0_in1_in(24)
    );
\Head[25]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(7),
      I3 => Head0_0(25),
      I4 => \Head1__2\,
      O => p_0_in1_in(25)
    );
\Head[26]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(8),
      I3 => Head0_0(26),
      I4 => \Head1__2\,
      O => p_0_in1_in(26)
    );
\Head[27]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(9),
      I3 => Head0_0(27),
      I4 => \Head1__2\,
      O => p_0_in1_in(27)
    );
\Head[28]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(10),
      I3 => Head0_0(28),
      I4 => \Head1__2\,
      O => p_0_in1_in(28)
    );
\Head[29]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(11),
      I3 => Head0_0(29),
      I4 => \Head1__2\,
      O => p_0_in1_in(29)
    );
\Head[56]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(12),
      I3 => Head0_0(56),
      I4 => \Head1__2\,
      O => p_0_in1_in(56)
    );
\Head[57]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(13),
      I3 => Head0_0(57),
      I4 => \Head1__2\,
      O => p_0_in1_in(57)
    );
\Head[58]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(14),
      I3 => Head0_0(58),
      I4 => \Head1__2\,
      O => p_0_in1_in(58)
    );
\Head[59]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(15),
      I3 => Head0_0(59),
      I4 => \Head1__2\,
      O => p_0_in1_in(59)
    );
\Head[60]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(16),
      I3 => Head0_0(60),
      I4 => \Head1__2\,
      O => p_0_in1_in(60)
    );
\Head[61]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(17),
      I3 => Head0_0(61),
      I4 => \Head1__2\,
      O => p_0_in1_in(61)
    );
\Head[62]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(18),
      I3 => Head0_0(62),
      I4 => \Head1__2\,
      O => p_0_in1_in(62)
    );
\Head[63]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(19),
      I3 => Head0_0(63),
      I4 => \Head1__2\,
      O => p_0_in1_in(63)
    );
\Head[64]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(20),
      I3 => Head0_0(64),
      I4 => \Head1__2\,
      O => p_0_in1_in(64)
    );
\Head[65]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(21),
      I3 => Head0_0(65),
      I4 => \Head1__2\,
      O => p_0_in1_in(65)
    );
\Head[66]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(22),
      I3 => Head0_0(66),
      I4 => \Head1__2\,
      O => p_0_in1_in(66)
    );
\Head[67]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(23),
      I3 => Head0_0(67),
      I4 => \Head1__2\,
      O => p_0_in1_in(67)
    );
\Head[68]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(24),
      I3 => Head0_0(68),
      I4 => \Head1__2\,
      O => p_0_in1_in(68)
    );
\Head[69]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(25),
      I3 => Head0_0(69),
      I4 => \Head1__2\,
      O => p_0_in1_in(69)
    );
\Head[70]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(26),
      I3 => Head0_0(70),
      I4 => \Head1__2\,
      O => p_0_in1_in(70)
    );
\Head[71]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(27),
      I3 => Head0_0(71),
      I4 => \Head1__2\,
      O => p_0_in1_in(71)
    );
\Head[72]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(28),
      I3 => Head0_0(72),
      I4 => \Head1__2\,
      O => p_0_in1_in(72)
    );
\Head[73]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(29),
      I3 => Head0_0(73),
      I4 => \Head1__2\,
      O => p_0_in1_in(73)
    );
\Head[74]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(30),
      I3 => Head0_0(74),
      I4 => \Head1__2\,
      O => p_0_in1_in(74)
    );
\Head[75]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(31),
      I3 => Head0_0(75),
      I4 => \Head1__2\,
      O => p_0_in1_in(75)
    );
\Head[76]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(32),
      I3 => Head0_0(76),
      I4 => \Head1__2\,
      O => p_0_in1_in(76)
    );
\Head[77]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(33),
      I3 => Head0_0(77),
      I4 => \Head1__2\,
      O => p_0_in1_in(77)
    );
\Head[78]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(34),
      I3 => Head0_0(78),
      I4 => \Head1__2\,
      O => p_0_in1_in(78)
    );
\Head[79]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(35),
      I3 => Head0_0(79),
      I4 => \Head1__2\,
      O => p_0_in1_in(79)
    );
\Head[80]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(36),
      I3 => Head0_0(80),
      I4 => \Head1__2\,
      O => p_0_in1_in(80)
    );
\Head[81]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(37),
      I3 => Head0_0(81),
      I4 => \Head1__2\,
      O => p_0_in1_in(81)
    );
\Head[82]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(38),
      I3 => Head0_0(82),
      I4 => \Head1__2\,
      O => p_0_in1_in(82)
    );
\Head[83]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(39),
      I3 => Head0_0(83),
      I4 => \Head1__2\,
      O => p_0_in1_in(83)
    );
\Head[84]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(40),
      I3 => Head0_0(84),
      I4 => \Head1__2\,
      O => p_0_in1_in(84)
    );
\Head[85]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(41),
      I3 => Head0_0(85),
      I4 => \Head1__2\,
      O => p_0_in1_in(85)
    );
\Head[86]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(42),
      I3 => Head0_0(86),
      I4 => \Head1__2\,
      O => p_0_in1_in(86)
    );
\Head[87]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(43),
      I3 => Head0_0(87),
      I4 => \Head1__2\,
      O => p_0_in1_in(87)
    );
\Head[88]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(44),
      I3 => Head0_0(88),
      I4 => \Head1__2\,
      O => p_0_in1_in(88)
    );
\Head[89]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(45),
      I3 => Head0_0(89),
      I4 => \Head1__2\,
      O => p_0_in1_in(89)
    );
\Head[90]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(46),
      I3 => Head0_0(90),
      I4 => \Head1__2\,
      O => p_0_in1_in(90)
    );
\Head[91]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(47),
      I3 => Head0_0(91),
      I4 => \Head1__2\,
      O => p_0_in1_in(91)
    );
\Head[92]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(48),
      I3 => Head0_0(92),
      I4 => \Head1__2\,
      O => p_0_in1_in(92)
    );
\Head[93]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(49),
      I3 => Head0_0(93),
      I4 => \Head1__2\,
      O => p_0_in1_in(93)
    );
\Head[94]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(50),
      I3 => Head0_0(94),
      I4 => \Head1__2\,
      O => p_0_in1_in(94)
    );
\Head[95]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(51),
      I3 => Head0_0(95),
      I4 => \Head1__2\,
      O => p_0_in1_in(95)
    );
\Head[96]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(52),
      I3 => Head0_0(96),
      I4 => \Head1__2\,
      O => p_0_in1_in(96)
    );
\Head[97]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(53),
      I3 => Head0_0(97),
      I4 => \Head1__2\,
      O => p_0_in1_in(97)
    );
\Head[98]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(54),
      I3 => Head0_0(98),
      I4 => \Head1__2\,
      O => p_0_in1_in(98)
    );
\Head[99]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => DataOut(55),
      I3 => Head0_0(99),
      I4 => \Head1__2\,
      O => p_0_in1_in(99)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(100),
      Q => \^q\(47),
      R => SR(0)
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(101),
      Q => \^q\(48),
      R => SR(0)
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(102),
      Q => \^q\(49),
      R => SR(0)
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(103),
      Q => \^q\(50),
      R => SR(0)
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(104),
      Q => \^q\(51),
      R => SR(0)
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(105),
      Q => \^q\(52),
      R => SR(0)
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(106),
      Q => \^q\(53),
      R => SR(0)
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(107),
      Q => \^q\(54),
      R => SR(0)
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(108),
      Q => \^q\(55),
      R => SR(0)
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(109),
      Q => \^q\(56),
      R => SR(0)
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(110),
      Q => \^q\(57),
      R => SR(0)
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(111),
      Q => \^q\(58),
      R => SR(0)
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(112),
      Q => \^q\(59),
      R => SR(0)
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(113),
      Q => \^q\(60),
      R => SR(0)
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(114),
      Q => \^q\(61),
      R => SR(0)
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(115),
      Q => \^q\(62),
      R => SR(0)
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(116),
      Q => \^q\(63),
      R => SR(0)
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(117),
      Q => \^q\(64),
      R => SR(0)
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(118),
      Q => \^q\(65),
      R => SR(0)
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(119),
      Q => \^q\(66),
      R => SR(0)
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(18),
      Q => \^q\(0),
      R => SR(0)
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(19),
      Q => \^q\(1),
      R => SR(0)
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(20),
      Q => \^q\(2),
      R => SR(0)
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(21),
      Q => tlpbytelength(3),
      R => SR(0)
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(22),
      Q => tlpbytelength(4),
      R => SR(0)
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(23),
      Q => tlpbytelength(5),
      R => SR(0)
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(24),
      Q => tlpbytelength(6),
      R => SR(0)
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(25),
      Q => tlpbytelength(7),
      R => SR(0)
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(26),
      Q => tlpbytelength(8),
      R => SR(0)
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(27),
      Q => tlpbytelength(9),
      R => SR(0)
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(28),
      Q => tlpbytelength(10),
      R => SR(0)
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(29),
      Q => tlpbytelength(11),
      R => SR(0)
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(56),
      Q => \^q\(3),
      R => SR(0)
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(57),
      Q => \^q\(4),
      R => SR(0)
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(58),
      Q => \^q\(5),
      R => SR(0)
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(59),
      Q => \^q\(6),
      R => SR(0)
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(60),
      Q => \^q\(7),
      R => SR(0)
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(61),
      Q => \^q\(8),
      R => SR(0)
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(62),
      Q => \^q\(9),
      R => SR(0)
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(63),
      Q => \^q\(10),
      R => SR(0)
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(64),
      Q => \^q\(11),
      R => SR(0)
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(65),
      Q => \^q\(12),
      R => SR(0)
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(66),
      Q => \^q\(13),
      R => SR(0)
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(67),
      Q => \^q\(14),
      R => SR(0)
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(68),
      Q => \^q\(15),
      R => SR(0)
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(69),
      Q => \^q\(16),
      R => SR(0)
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(70),
      Q => \^q\(17),
      R => SR(0)
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(71),
      Q => \^q\(18),
      R => SR(0)
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(72),
      Q => \^q\(19),
      R => SR(0)
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(73),
      Q => \^q\(20),
      R => SR(0)
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(74),
      Q => \^q\(21),
      R => SR(0)
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(75),
      Q => \^q\(22),
      R => SR(0)
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(76),
      Q => \^q\(23),
      R => SR(0)
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(77),
      Q => \^q\(24),
      R => SR(0)
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(78),
      Q => \^q\(25),
      R => SR(0)
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(79),
      Q => \^q\(26),
      R => SR(0)
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(80),
      Q => \^q\(27),
      R => SR(0)
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(81),
      Q => \^q\(28),
      R => SR(0)
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(82),
      Q => \^q\(29),
      R => SR(0)
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(83),
      Q => \^q\(30),
      R => SR(0)
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(84),
      Q => \^q\(31),
      R => SR(0)
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(85),
      Q => \^q\(32),
      R => SR(0)
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(86),
      Q => \^q\(33),
      R => SR(0)
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(87),
      Q => \^q\(34),
      R => SR(0)
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(88),
      Q => \^q\(35),
      R => SR(0)
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(89),
      Q => \^q\(36),
      R => SR(0)
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(90),
      Q => \^q\(37),
      R => SR(0)
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(91),
      Q => \^q\(38),
      R => SR(0)
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(92),
      Q => \^q\(39),
      R => SR(0)
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(93),
      Q => \^q\(40),
      R => SR(0)
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(94),
      Q => \^q\(41),
      R => SR(0)
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(95),
      Q => \^q\(42),
      R => SR(0)
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(96),
      Q => \^q\(43),
      R => SR(0)
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(97),
      Q => \^q\(44),
      R => SR(0)
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(98),
      Q => \^q\(45),
      R => SR(0)
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__4_n_0\,
      D => p_0_in1_in(99),
      Q => \^q\(46),
      R => SR(0)
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(59 downto 58),
      DIB(1 downto 0) => payloadOut(61 downto 60),
      DIC(1 downto 0) => payloadOut(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(103 downto 102),
      DOB(1 downto 0) => Head0_0(105 downto 104),
      DOC(1 downto 0) => Head0_0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(65 downto 64),
      DIB(1 downto 0) => payloadOut(67 downto 66),
      DIC(1 downto 0) => payloadOut(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(109 downto 108),
      DOB(1 downto 0) => Head0_0(111 downto 110),
      DOC(1 downto 0) => Head0_0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(71 downto 70),
      DIB(1 downto 0) => payloadOut(73 downto 72),
      DIC(1 downto 0) => payloadOut(75 downto 74),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(115 downto 114),
      DOB(1 downto 0) => Head0_0(117 downto 116),
      DOC(1 downto 0) => Head0_0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(1 downto 0),
      DIB(1 downto 0) => payloadOut(3 downto 2),
      DIC(1 downto 0) => payloadOut(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(19 downto 18),
      DOB(1 downto 0) => Head0_0(21 downto 20),
      DOC(1 downto 0) => Head0_0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(7 downto 6),
      DIB(1 downto 0) => payloadOut(9 downto 8),
      DIC(1 downto 0) => payloadOut(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(25 downto 24),
      DOB(1 downto 0) => Head0_0(27 downto 26),
      DOC(1 downto 0) => Head0_0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => payloadOut(13 downto 12),
      DIC(1 downto 0) => payloadOut(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_54_59_n_0,
      DOA(0) => MemArray_reg_0_3_54_59_n_1,
      DOB(1 downto 0) => Head0_0(57 downto 56),
      DOC(1 downto 0) => Head0_0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(17 downto 16),
      DIB(1 downto 0) => payloadOut(19 downto 18),
      DIC(1 downto 0) => payloadOut(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(61 downto 60),
      DOB(1 downto 0) => Head0_0(63 downto 62),
      DOC(1 downto 0) => Head0_0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(23 downto 22),
      DIB(1 downto 0) => payloadOut(25 downto 24),
      DIC(1 downto 0) => payloadOut(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(67 downto 66),
      DOB(1 downto 0) => Head0_0(69 downto 68),
      DOC(1 downto 0) => Head0_0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(29 downto 28),
      DIB(1 downto 0) => payloadOut(31 downto 30),
      DIC(1 downto 0) => payloadOut(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(73 downto 72),
      DOB(1 downto 0) => Head0_0(75 downto 74),
      DOC(1 downto 0) => Head0_0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(35 downto 34),
      DIB(1 downto 0) => payloadOut(37 downto 36),
      DIC(1 downto 0) => payloadOut(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(79 downto 78),
      DOB(1 downto 0) => Head0_0(81 downto 80),
      DOC(1 downto 0) => Head0_0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(41 downto 40),
      DIB(1 downto 0) => payloadOut(43 downto 42),
      DIC(1 downto 0) => payloadOut(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(85 downto 84),
      DOB(1 downto 0) => Head0_0(87 downto 86),
      DOC(1 downto 0) => Head0_0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(47 downto 46),
      DIB(1 downto 0) => payloadOut(49 downto 48),
      DIC(1 downto 0) => payloadOut(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(91 downto 90),
      DOB(1 downto 0) => Head0_0(93 downto 92),
      DOC(1 downto 0) => Head0_0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadOut(53 downto 52),
      DIB(1 downto 0) => payloadOut(55 downto 54),
      DIC(1 downto 0) => payloadOut(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(97 downto 96),
      DOB(1 downto 0) => Head0_0(99 downto 98),
      DOC(1 downto 0) => Head0_0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \Head_reg[19]_0\
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557777755544444"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \Head1__2\,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \RdPtr_reg[0]_0\,
      I5 => RdPtr(0),
      O => \RdPtr[0]_i_1_n_0\
    );
\RdPtr[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0103010100000000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => \^empty_ff_reg_0\,
      I4 => arb_rrq_rdy,
      I5 => \Head_reg[19]_0\,
      O => \Head1__2\
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => RdPtr(0),
      I1 => RdPtr(1),
      I2 => RdPtr_reg0,
      I3 => RdPtr(1),
      O => \RdPtr[1]_i_1_n_0\
    );
\RdPtr[1]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAFEAA"
    )
        port map (
      I0 => \Head1__2\,
      I1 => FifoCntrRd(1),
      I2 => FifoCntrRd(2),
      I3 => arb_rrq_rdy,
      I4 => \^empty_ff_reg_0\,
      O => RdPtr_reg0
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1_n_0\,
      Q => RdPtr(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB01"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => WrPtr(0),
      I2 => \^almost_full_ff_reg_0\,
      I3 => WrPtr(0),
      O => \WrPtr[0]_i_1__16_n_0\
    );
\WrPtr[1]_i_1__16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBE0014"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => WrPtr(0),
      I2 => WrPtr(1),
      I3 => \^almost_full_ff_reg_0\,
      I4 => WrPtr(1),
      O => \WrPtr[1]_i_1__16_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__16_n_0\,
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__16_n_0\,
      Q => WrPtr(1),
      R => SR(0)
    );
\almost_full_ff_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => FifoCntrWr(1),
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(2),
      O => \almost_full_ff_i_1__1_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__1_n_0\,
      Q => \^almost_full_ff_reg_0\,
      R => SR(0)
    );
\empty_ff_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555DFF"
    )
        port map (
      I0 => empty_ff_reg_1(0),
      I1 => arb_rrq_rdy,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(0),
      I4 => FifoCntrRd(1),
      I5 => FifoCntrRd(2),
      O => \empty_ff_i_1__7_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__7_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
m_axi_arlenissueq_reg_0_15_0_5_i_11: unisim.vcomponents.CARRY4
     port map (
      CI => m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0,
      CO(3) => m_axi_arlenissueq_reg_0_15_0_5_i_11_n_0,
      CO(2) => m_axi_arlenissueq_reg_0_15_0_5_i_11_n_1,
      CO(1) => m_axi_arlenissueq_reg_0_15_0_5_i_11_n_2,
      CO(0) => m_axi_arlenissueq_reg_0_15_0_5_i_11_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => m_axi_arlenissueq_reg_0_15_0_5_i_11_n_4,
      O(2 downto 0) => \Head_reg[29]_0\(2 downto 0),
      S(3 downto 0) => tlpbytelength(11 downto 8)
    );
m_axi_arlenissueq_reg_0_15_0_5_i_7: unisim.vcomponents.CARRY4
     port map (
      CI => m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0,
      CO(3) => m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0,
      CO(2) => m_axi_arlenissueq_reg_0_15_0_5_i_7_n_1,
      CO(1) => m_axi_arlenissueq_reg_0_15_0_5_i_7_n_2,
      CO(0) => m_axi_arlenissueq_reg_0_15_0_5_i_7_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => tlpbytelength(5 downto 4),
      O(3 downto 0) => O(3 downto 0),
      S(3 downto 0) => tlpbytelength(7 downto 4)
    );
m_axi_arlenissueq_reg_0_15_0_5_i_8: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0,
      CO(2) => m_axi_arlenissueq_reg_0_15_0_5_i_8_n_1,
      CO(1) => m_axi_arlenissueq_reg_0_15_0_5_i_8_n_2,
      CO(0) => m_axi_arlenissueq_reg_0_15_0_5_i_8_n_3,
      CYINIT => '0',
      DI(3) => tlpbytelength(3),
      DI(2 downto 0) => \^q\(2 downto 0),
      O(3 downto 0) => \Head_reg[21]_0\(3 downto 0),
      S(3) => tlpbytelength(3),
      S(2 downto 0) => S(2 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0\ is
  port (
    almost_full_ff_reg_0 : out STD_LOGIC;
    empty_ff : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 75 downto 0 );
    \Head_reg[14]_0\ : out STD_LOGIC;
    \FifoCntrRd_reg[1]_0\ : out STD_LOGIC;
    \WrPtr_reg[0]_0\ : out STD_LOGIC;
    I22 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[48]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \Head_reg[19]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \Head_reg[14]_1\ : out STD_LOGIC;
    \Head_reg[14]_2\ : out STD_LOGIC;
    \Head_reg[14]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    O : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \Head_reg[10]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \Head_reg[20]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wrq_aabt_noinc : out STD_LOGIC;
    \Head_reg[21]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \RdPtr_reg[0]_0\ : out STD_LOGIC;
    \RdPtr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_0 : in STD_LOGIC;
    \WrPtr_reg[0]_1\ : in STD_LOGIC;
    \Head_reg[112]_0\ : in STD_LOGIC;
    \Head_reg[112]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    C2H_WRQ_RDY_IN0 : in STD_LOGIC;
    \RdPtr_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[111]_0\ : in STD_LOGIC_VECTOR ( 88 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0\ : entity is "xdma_v4_1_8_GenericFIFOAsync";
end \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__11_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__13_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \^fifocntrrd_reg[1]_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__15_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__14_n_0\ : STD_LOGIC;
  signal \Head[112]_i_1__5_n_0\ : STD_LOGIC;
  signal \^head_reg[10]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^head_reg[14]_0\ : STD_LOGIC;
  signal \^head_reg[14]_1\ : STD_LOGIC;
  signal \^head_reg[20]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^i22\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 75 downto 0 );
  signal \RdPtr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \^rdptr_reg[0]_0\ : STD_LOGIC;
  signal \^rdptr_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \WrPtr[0]_i_1__17_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__17_n_0\ : STD_LOGIC;
  signal \^wrptr_reg[0]_0\ : STD_LOGIC;
  signal \almost_full_ff_i_1__4_n_0\ : STD_LOGIC;
  signal \^almost_full_ff_reg_0\ : STD_LOGIC;
  signal arb_wrq_pay : STD_LOGIC_VECTOR ( 21 downto 2 );
  signal \dma_pcie_rq/data1\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \dma_pcie_rq/wrq_aabt_whole_len1\ : STD_LOGIC_VECTOR ( 13 to 13 );
  signal \dma_pcie_rq/wrq_dwlen_whole\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \empty_ff_i_1__14_n_0\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 112 to 112 );
  signal \wrq_aabt_len_ff[2]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff[2]_i_4_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff[2]_i_5_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[9]_i_4_n_0\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[9]_i_4_n_1\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[9]_i_4_n_2\ : STD_LOGIC;
  signal \wrq_aabt_len_ff_reg[9]_i_4_n_3\ : STD_LOGIC;
  signal wrq_aabt_noinc_ff_i_3_n_0 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_i_4_n_0 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_i_5_n_0 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_0 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_1 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_2 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_3 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_4 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_5 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_6 : STD_LOGIC;
  signal wrq_aabt_noinc_ff_reg_i_2_n_7 : STD_LOGIC;
  signal \wrq_btlen_ff[1]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff[1]_i_4_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff[5]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff[8]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff[8]_i_5_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff[8]_i_6_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[1]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[1]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[1]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[5]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[5]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[5]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_btlen_ff_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff[3]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff[3]_i_4_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff[3]_i_5_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_4_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_4_n_1\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_4_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[10]_i_4_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_1_n_1\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_1_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_1_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_1_n_7\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \wrq_dwlen_ff_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \wrq_fbe_ff[3]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_fbe_ff[3]_i_4_n_0\ : STD_LOGIC;
  signal \NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wrq_aabt_len_ff_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wrq_btlen_ff_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_wrq_btlen_ff_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_wrq_dwlen_ff_reg[10]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_wrq_dwlen_ff_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_wrq_dwlen_ff_reg[10]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wrq_dwlen_ff_reg[10]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_wrq_dwlen_ff_reg[3]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__11\ : label is "soft_lutpair1443";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__13\ : label is "soft_lutpair1443";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__14\ : label is "soft_lutpair1444";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__15\ : label is "soft_lutpair1444";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_2__5\ : label is "soft_lutpair1442";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \RdPtr_reg[1]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[1]\ : label is "128";
  attribute SOFT_HLUTNM of \empty_ff_i_1__14\ : label is "soft_lutpair1442";
  attribute SOFT_HLUTNM of wrq_0len_ff_i_1 : label is "soft_lutpair1441";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[0]_i_1\ : label is "soft_lutpair1441";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[2]_i_1\ : label is "soft_lutpair1448";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[3]_i_1\ : label is "soft_lutpair1440";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[4]_i_1\ : label is "soft_lutpair1440";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[6]_i_1\ : label is "soft_lutpair1448";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[7]_i_1\ : label is "soft_lutpair1446";
  attribute SOFT_HLUTNM of \wrq_btlen_ff[8]_i_1\ : label is "soft_lutpair1446";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \wrq_btlen_ff_reg[1]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_btlen_ff_reg[5]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_btlen_ff_reg[8]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \wrq_dwlen_ff[0]_i_1\ : label is "soft_lutpair1445";
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[10]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[10]_i_3\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[10]_i_4\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[3]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[3]_i_2\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[7]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \wrq_dwlen_ff_reg[7]_i_2\ : label is 35;
  attribute SOFT_HLUTNM of \wrq_fbe_ff[1]_i_1\ : label is "soft_lutpair1439";
  attribute SOFT_HLUTNM of \wrq_fbe_ff[2]_i_1\ : label is "soft_lutpair1438";
  attribute SOFT_HLUTNM of \wrq_fbe_ff[3]_i_1\ : label is "soft_lutpair1438";
  attribute SOFT_HLUTNM of \wrq_fbe_ff[3]_i_3\ : label is "soft_lutpair1445";
  attribute SOFT_HLUTNM of \wrq_lbe_ff[1]_i_1\ : label is "soft_lutpair1447";
  attribute SOFT_HLUTNM of \wrq_lbe_ff[2]_i_1\ : label is "soft_lutpair1447";
  attribute SOFT_HLUTNM of \wrq_lbe_ff[3]_i_2\ : label is "soft_lutpair1439";
begin
  \FifoCntrRd_reg[1]_0\ <= \^fifocntrrd_reg[1]_0\;
  \Head_reg[10]_0\(2 downto 0) <= \^head_reg[10]_0\(2 downto 0);
  \Head_reg[14]_0\ <= \^head_reg[14]_0\;
  \Head_reg[14]_1\ <= \^head_reg[14]_1\;
  \Head_reg[20]_0\(3 downto 0) <= \^head_reg[20]_0\(3 downto 0);
  I22(0) <= \^i22\(0);
  O(2 downto 0) <= \^o\(2 downto 0);
  Q(75 downto 0) <= \^q\(75 downto 0);
  \RdPtr_reg[0]_0\ <= \^rdptr_reg[0]_0\;
  \RdPtr_reg[1]_0\(0) <= \^rdptr_reg[1]_0\(0);
  \WrPtr_reg[0]_0\ <= \^wrptr_reg[0]_0\;
  almost_full_ff_reg_0 <= \^almost_full_ff_reg_0\;
\FifoCntrRd[0]_i_1__11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__11_n_0\
    );
\FifoCntrRd[1]_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EC1313EC"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[112]_0\,
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(0),
      O => \FifoCntrRd[1]_i_1__13_n_0\
    );
\FifoCntrRd[2]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCC9C3CC3C3C6CC"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => \Head_reg[112]_0\,
      I4 => \^almost_full_ff_reg_0\,
      I5 => FifoCntrRd(0),
      O => \FifoCntrRd[2]_i_2__6_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd[0]_i_1__11_n_0\,
      Q => FifoCntrRd(0),
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd[1]_i_1__13_n_0\,
      Q => FifoCntrRd(1),
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrRd[2]_i_2__6_n_0\,
      Q => FifoCntrRd(2),
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__14_n_0\
    );
\FifoCntrWr[1]_i_1__15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EC1313EC"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[112]_0\,
      I3 => FifoCntrWr(0),
      I4 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__15_n_0\
    );
\FifoCntrWr[2]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCC9C3CC3C3C6CC"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => FifoCntrWr(2),
      I2 => FifoCntrWr(1),
      I3 => \Head_reg[112]_0\,
      I4 => \^almost_full_ff_reg_0\,
      I5 => FifoCntrWr(0),
      O => \FifoCntrWr[2]_i_1__14_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[0]_i_1__14_n_0\,
      Q => FifoCntrWr(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[1]_i_1__15_n_0\,
      Q => FifoCntrWr(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[2]_i_1__14_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
\Head[112]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDDDDDF"
    )
        port map (
      I0 => empty_ff_reg_0,
      I1 => \^fifocntrrd_reg[1]_0\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(2),
      O => \Head[112]_i_1__5_n_0\
    );
\Head[112]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"03AA"
    )
        port map (
      I0 => \Head_reg[112]_1\(0),
      I1 => \Head_reg[112]_0\,
      I2 => \^almost_full_ff_reg_0\,
      I3 => \^fifocntrrd_reg[1]_0\,
      O => p_0_in1_in(112)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(77),
      Q => \^q\(63),
      R => SR(0)
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(78),
      Q => \^q\(64),
      R => SR(0)
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(79),
      Q => \^q\(65),
      R => SR(0)
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(80),
      Q => \^q\(66),
      R => SR(0)
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(81),
      Q => \^q\(67),
      R => SR(0)
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(82),
      Q => \^q\(68),
      R => SR(0)
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(83),
      Q => \^q\(69),
      R => SR(0)
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(84),
      Q => \^q\(70),
      R => SR(0)
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(85),
      Q => \^q\(71),
      R => SR(0)
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(86),
      Q => \^q\(72),
      R => SR(0)
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(7),
      Q => arb_wrq_pay(10),
      R => SR(0)
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(87),
      Q => \^q\(73),
      R => SR(0)
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(88),
      Q => \^q\(74),
      R => SR(0)
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => p_0_in1_in(112),
      Q => \^q\(75),
      R => SR(0)
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(8),
      Q => arb_wrq_pay(11),
      R => SR(0)
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(9),
      Q => arb_wrq_pay(12),
      R => SR(0)
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(10),
      Q => arb_wrq_pay(13),
      R => SR(0)
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(11),
      Q => arb_wrq_pay(14),
      R => SR(0)
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(12),
      Q => arb_wrq_pay(15),
      R => SR(0)
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(13),
      Q => arb_wrq_pay(16),
      R => SR(0)
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(14),
      Q => arb_wrq_pay(17),
      R => SR(0)
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(15),
      Q => arb_wrq_pay(18),
      R => SR(0)
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(16),
      Q => arb_wrq_pay(19),
      R => SR(0)
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(17),
      Q => arb_wrq_pay(20),
      R => SR(0)
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(18),
      Q => arb_wrq_pay(21),
      R => SR(0)
    );
\Head_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(1),
      Q => arb_wrq_pay(2),
      R => SR(0)
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(19),
      Q => \^q\(5),
      R => SR(0)
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(20),
      Q => \^q\(6),
      R => SR(0)
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(21),
      Q => \^q\(7),
      R => SR(0)
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(2),
      Q => \^q\(1),
      R => SR(0)
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(22),
      Q => \^q\(8),
      R => SR(0)
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(23),
      Q => \^q\(9),
      R => SR(0)
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(24),
      Q => \^q\(10),
      R => SR(0)
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(25),
      Q => \^q\(11),
      R => SR(0)
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(26),
      Q => \^q\(12),
      R => SR(0)
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(3),
      Q => \^q\(2),
      R => SR(0)
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(27),
      Q => \^q\(13),
      R => SR(0)
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(28),
      Q => \^q\(14),
      R => SR(0)
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(29),
      Q => \^q\(15),
      R => SR(0)
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(30),
      Q => \^q\(16),
      R => SR(0)
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(31),
      Q => \^q\(17),
      R => SR(0)
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(32),
      Q => \^q\(18),
      R => SR(0)
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(33),
      Q => \^q\(19),
      R => SR(0)
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(34),
      Q => \^q\(20),
      R => SR(0)
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(35),
      Q => \^q\(21),
      R => SR(0)
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(36),
      Q => \^q\(22),
      R => SR(0)
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(4),
      Q => \^q\(3),
      R => SR(0)
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(37),
      Q => \^q\(23),
      R => SR(0)
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(38),
      Q => \^q\(24),
      R => SR(0)
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(39),
      Q => \^q\(25),
      R => SR(0)
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(40),
      Q => \^q\(26),
      R => SR(0)
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(41),
      Q => \^q\(27),
      R => SR(0)
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(42),
      Q => \^q\(28),
      R => SR(0)
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(43),
      Q => \^q\(29),
      R => SR(0)
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(44),
      Q => \^q\(30),
      R => SR(0)
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(45),
      Q => \^q\(31),
      R => SR(0)
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(46),
      Q => \^q\(32),
      R => SR(0)
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(47),
      Q => \^q\(33),
      R => SR(0)
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(48),
      Q => \^q\(34),
      R => SR(0)
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(49),
      Q => \^q\(35),
      R => SR(0)
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(50),
      Q => \^q\(36),
      R => SR(0)
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(51),
      Q => \^q\(37),
      R => SR(0)
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(52),
      Q => \^q\(38),
      R => SR(0)
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(53),
      Q => \^q\(39),
      R => SR(0)
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(54),
      Q => \^q\(40),
      R => SR(0)
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(55),
      Q => \^q\(41),
      R => SR(0)
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(56),
      Q => \^q\(42),
      R => SR(0)
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(57),
      Q => \^q\(43),
      R => SR(0)
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(58),
      Q => \^q\(44),
      R => SR(0)
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(59),
      Q => \^q\(45),
      R => SR(0)
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(60),
      Q => \^q\(46),
      R => SR(0)
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(61),
      Q => \^q\(47),
      R => SR(0)
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(62),
      Q => \^q\(48),
      R => SR(0)
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(63),
      Q => \^q\(49),
      R => SR(0)
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(64),
      Q => \^q\(50),
      R => SR(0)
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(65),
      Q => \^q\(51),
      R => SR(0)
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(66),
      Q => \^q\(52),
      R => SR(0)
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(5),
      Q => \^q\(4),
      R => SR(0)
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(67),
      Q => \^q\(53),
      R => SR(0)
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(68),
      Q => \^q\(54),
      R => SR(0)
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(69),
      Q => \^q\(55),
      R => SR(0)
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(70),
      Q => \^q\(56),
      R => SR(0)
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(71),
      Q => \^q\(57),
      R => SR(0)
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(72),
      Q => \^q\(58),
      R => SR(0)
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(73),
      Q => \^q\(59),
      R => SR(0)
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(74),
      Q => \^q\(60),
      R => SR(0)
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(75),
      Q => \^q\(61),
      R => SR(0)
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(76),
      Q => \^q\(62),
      R => SR(0)
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[112]_i_1__5_n_0\,
      D => \Head_reg[111]_0\(6),
      Q => arb_wrq_pay(9),
      R => SR(0)
    );
\RdPtr[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555DDDF55551110"
    )
        port map (
      I0 => \^rdptr_reg[0]_0\,
      I1 => empty_ff_reg_0,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \^fifocntrrd_reg[1]_0\,
      I5 => \^rdptr_reg[0]_0\,
      O => \RdPtr[0]_i_1__0_n_0\
    );
\RdPtr[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6666F6FF66660600"
    )
        port map (
      I0 => \^rdptr_reg[0]_0\,
      I1 => \^rdptr_reg[1]_0\(0),
      I2 => empty_ff_reg_0,
      I3 => \RdPtr[1]_i_2__5_n_0\,
      I4 => \^fifocntrrd_reg[1]_0\,
      I5 => \^rdptr_reg[1]_0\(0),
      O => \RdPtr[1]_i_1__0_n_0\
    );
\RdPtr[1]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(2),
      O => \RdPtr[1]_i_2__5_n_0\
    );
\RdPtr[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000111011101110"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(2),
      I2 => C2H_WRQ_RDY_IN0,
      I3 => \RdPtr_reg[0]_1\(0),
      I4 => FifoCntrRd(0),
      I5 => empty_ff_reg_0,
      O => \^fifocntrrd_reg[1]_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__0_n_0\,
      Q => \^rdptr_reg[0]_0\,
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__0_n_0\,
      Q => \^rdptr_reg[1]_0\(0),
      R => SR(0)
    );
\WrPtr[0]_i_1__17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBF30103"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => \^wrptr_reg[0]_0\,
      I2 => \^almost_full_ff_reg_0\,
      I3 => \Head_reg[112]_0\,
      I4 => \^wrptr_reg[0]_0\,
      O => \WrPtr[0]_i_1__17_n_0\
    );
\WrPtr[1]_i_1__17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBEFF3C0014003C"
    )
        port map (
      I0 => \WrPtr_reg[0]_1\,
      I1 => \^wrptr_reg[0]_0\,
      I2 => \^i22\(0),
      I3 => \^almost_full_ff_reg_0\,
      I4 => \Head_reg[112]_0\,
      I5 => \^i22\(0),
      O => \WrPtr[1]_i_1__17_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__17_n_0\,
      Q => \^wrptr_reg[0]_0\,
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__17_n_0\,
      Q => \^i22\(0),
      R => SR(0)
    );
\almost_full_ff_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => FifoCntrWr(2),
      O => \almost_full_ff_i_1__4_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__4_n_0\,
      Q => \^almost_full_ff_reg_0\,
      R => SR(0)
    );
\empty_ff_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55575757"
    )
        port map (
      I0 => empty_ff_reg_1(0),
      I1 => FifoCntrRd(1),
      I2 => FifoCntrRd(2),
      I3 => empty_ff_reg_0,
      I4 => FifoCntrRd(0),
      O => \empty_ff_i_1__14_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__14_n_0\,
      Q => empty_ff,
      R => '0'
    );
wrq_0len_ff_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[14]_1\,
      O => \Head_reg[14]_2\
    );
\wrq_aabt_len_ff[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_wrq_pay(11),
      I1 => \^q\(3),
      O => \wrq_aabt_len_ff[2]_i_3_n_0\
    );
\wrq_aabt_len_ff[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_wrq_pay(10),
      I1 => \^q\(2),
      O => \wrq_aabt_len_ff[2]_i_4_n_0\
    );
\wrq_aabt_len_ff[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(1),
      O => \wrq_aabt_len_ff[2]_i_5_n_0\
    );
\wrq_aabt_len_ff_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wrq_aabt_len_ff_reg[2]_i_2_n_0\,
      CO(2) => \wrq_aabt_len_ff_reg[2]_i_2_n_1\,
      CO(1) => \wrq_aabt_len_ff_reg[2]_i_2_n_2\,
      CO(0) => \wrq_aabt_len_ff_reg[2]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => arb_wrq_pay(12 downto 9),
      O(3 downto 0) => \Head_reg[21]_0\(3 downto 0),
      S(3) => arb_wrq_pay(12),
      S(2) => \wrq_aabt_len_ff[2]_i_3_n_0\,
      S(1) => \wrq_aabt_len_ff[2]_i_4_n_0\,
      S(0) => \wrq_aabt_len_ff[2]_i_5_n_0\
    );
\wrq_aabt_len_ff_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_aabt_len_ff_reg[2]_i_2_n_0\,
      CO(3) => \wrq_aabt_len_ff_reg[7]_i_2_n_0\,
      CO(2) => \wrq_aabt_len_ff_reg[7]_i_2_n_1\,
      CO(1) => \wrq_aabt_len_ff_reg[7]_i_2_n_2\,
      CO(0) => \wrq_aabt_len_ff_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => arb_wrq_pay(14 downto 13),
      O(3 downto 0) => \Head_reg[21]_0\(7 downto 4),
      S(3 downto 0) => arb_wrq_pay(16 downto 13)
    );
\wrq_aabt_len_ff_reg[9]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_aabt_len_ff_reg[7]_i_2_n_0\,
      CO(3) => \wrq_aabt_len_ff_reg[9]_i_4_n_0\,
      CO(2) => \wrq_aabt_len_ff_reg[9]_i_4_n_1\,
      CO(1) => \wrq_aabt_len_ff_reg[9]_i_4_n_2\,
      CO(0) => \wrq_aabt_len_ff_reg[9]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \Head_reg[21]_0\(11 downto 8),
      S(3 downto 0) => arb_wrq_pay(20 downto 17)
    );
\wrq_aabt_len_ff_reg[9]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_aabt_len_ff_reg[9]_i_4_n_0\,
      CO(3 downto 2) => \NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \dma_pcie_rq/wrq_aabt_whole_len1\(13),
      CO(0) => \NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wrq_aabt_len_ff_reg[9]_i_6_O_UNCONNECTED\(3 downto 1),
      O(0) => \Head_reg[21]_0\(12),
      S(3 downto 1) => B"001",
      S(0) => arb_wrq_pay(21)
    );
wrq_aabt_noinc_ff_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03030302"
    )
        port map (
      I0 => wrq_aabt_noinc_ff_reg_i_2_n_5,
      I1 => arb_wrq_pay(2),
      I2 => \^q\(0),
      I3 => wrq_aabt_noinc_ff_reg_i_2_n_6,
      I4 => wrq_aabt_noinc_ff_reg_i_2_n_7,
      O => wrq_aabt_noinc
    );
wrq_aabt_noinc_ff_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(3),
      I1 => arb_wrq_pay(11),
      O => wrq_aabt_noinc_ff_i_3_n_0
    );
wrq_aabt_noinc_ff_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(2),
      I1 => arb_wrq_pay(10),
      O => wrq_aabt_noinc_ff_i_4_n_0
    );
wrq_aabt_noinc_ff_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(1),
      I1 => arb_wrq_pay(9),
      O => wrq_aabt_noinc_ff_i_5_n_0
    );
wrq_aabt_noinc_ff_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => wrq_aabt_noinc_ff_reg_i_2_n_0,
      CO(2) => wrq_aabt_noinc_ff_reg_i_2_n_1,
      CO(1) => wrq_aabt_noinc_ff_reg_i_2_n_2,
      CO(0) => wrq_aabt_noinc_ff_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => \^q\(3 downto 1),
      O(3) => wrq_aabt_noinc_ff_reg_i_2_n_4,
      O(2) => wrq_aabt_noinc_ff_reg_i_2_n_5,
      O(1) => wrq_aabt_noinc_ff_reg_i_2_n_6,
      O(0) => wrq_aabt_noinc_ff_reg_i_2_n_7,
      S(3) => arb_wrq_pay(12),
      S(2) => wrq_aabt_noinc_ff_i_3_n_0,
      S(1) => wrq_aabt_noinc_ff_i_4_n_0,
      S(0) => wrq_aabt_noinc_ff_i_5_n_0
    );
\wrq_btlen_ff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55FF56FF"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(3),
      I1 => \dma_pcie_rq/data1\(0),
      I2 => \dma_pcie_rq/data1\(1),
      I3 => \^head_reg[14]_1\,
      I4 => \dma_pcie_rq/data1\(2),
      O => \Head_reg[19]_0\(0)
    );
\wrq_btlen_ff[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557AAA800000000"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(3),
      I1 => \dma_pcie_rq/data1\(2),
      I2 => \dma_pcie_rq/data1\(1),
      I3 => \dma_pcie_rq/data1\(0),
      I4 => \dma_pcie_rq/data1\(4),
      I5 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(1)
    );
\wrq_btlen_ff[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(11),
      I1 => arb_wrq_pay(10),
      O => \wrq_btlen_ff[1]_i_3_n_0\
    );
\wrq_btlen_ff[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(10),
      I1 => arb_wrq_pay(9),
      O => \wrq_btlen_ff[1]_i_4_n_0\
    );
\wrq_btlen_ff[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \wrq_btlen_ff[5]_i_3_n_0\,
      I1 => \dma_pcie_rq/data1\(5),
      I2 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(2)
    );
\wrq_btlen_ff[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D200"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(5),
      I1 => \wrq_btlen_ff[5]_i_3_n_0\,
      I2 => \dma_pcie_rq/data1\(6),
      I3 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(3)
    );
\wrq_btlen_ff[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BF400000"
    )
        port map (
      I0 => \wrq_btlen_ff[5]_i_3_n_0\,
      I1 => \dma_pcie_rq/data1\(5),
      I2 => \dma_pcie_rq/data1\(6),
      I3 => \dma_pcie_rq/data1\(7),
      I4 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(4)
    );
\wrq_btlen_ff[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FF080000000000"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(6),
      I1 => \dma_pcie_rq/data1\(5),
      I2 => \wrq_btlen_ff[5]_i_3_n_0\,
      I3 => \dma_pcie_rq/data1\(7),
      I4 => \dma_pcie_rq/data1\(8),
      I5 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(5)
    );
\wrq_btlen_ff[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FFFFFFFFFFFF"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(3),
      I1 => \dma_pcie_rq/data1\(2),
      I2 => \dma_pcie_rq/data1\(1),
      I3 => \dma_pcie_rq/data1\(0),
      I4 => \dma_pcie_rq/data1\(4),
      I5 => \^head_reg[14]_1\,
      O => \wrq_btlen_ff[5]_i_3_n_0\
    );
\wrq_btlen_ff[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \wrq_btlen_ff[8]_i_3_n_0\,
      I1 => \dma_pcie_rq/data1\(9),
      I2 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(6)
    );
\wrq_btlen_ff[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D200"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(9),
      I1 => \wrq_btlen_ff[8]_i_3_n_0\,
      I2 => \dma_pcie_rq/data1\(10),
      I3 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(7)
    );
\wrq_btlen_ff[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(9),
      I1 => \wrq_btlen_ff[8]_i_3_n_0\,
      I2 => \dma_pcie_rq/data1\(10),
      I3 => \^head_reg[14]_1\,
      O => \Head_reg[19]_0\(8)
    );
\wrq_btlen_ff[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \dma_pcie_rq/data1\(6),
      I1 => \dma_pcie_rq/data1\(5),
      I2 => \wrq_btlen_ff[5]_i_3_n_0\,
      I3 => \dma_pcie_rq/data1\(7),
      I4 => \dma_pcie_rq/data1\(8),
      I5 => \^head_reg[14]_1\,
      O => \wrq_btlen_ff[8]_i_3_n_0\
    );
\wrq_btlen_ff[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \wrq_btlen_ff[8]_i_5_n_0\,
      I1 => arb_wrq_pay(14),
      I2 => arb_wrq_pay(21),
      I3 => arb_wrq_pay(13),
      I4 => arb_wrq_pay(12),
      I5 => \wrq_btlen_ff[8]_i_6_n_0\,
      O => \^head_reg[14]_1\
    );
\wrq_btlen_ff[8]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => arb_wrq_pay(15),
      I1 => arb_wrq_pay(17),
      I2 => arb_wrq_pay(20),
      I3 => arb_wrq_pay(16),
      O => \wrq_btlen_ff[8]_i_5_n_0\
    );
\wrq_btlen_ff[8]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => arb_wrq_pay(18),
      I2 => arb_wrq_pay(19),
      I3 => arb_wrq_pay(11),
      I4 => arb_wrq_pay(10),
      O => \wrq_btlen_ff[8]_i_6_n_0\
    );
\wrq_btlen_ff_reg[1]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wrq_btlen_ff_reg[1]_i_2_n_0\,
      CO(2) => \wrq_btlen_ff_reg[1]_i_2_n_1\,
      CO(1) => \wrq_btlen_ff_reg[1]_i_2_n_2\,
      CO(0) => \wrq_btlen_ff_reg[1]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => \^q\(11 downto 10),
      O(3 downto 0) => \dma_pcie_rq/data1\(3 downto 0),
      S(3 downto 2) => arb_wrq_pay(12 downto 11),
      S(1) => \wrq_btlen_ff[1]_i_3_n_0\,
      S(0) => \wrq_btlen_ff[1]_i_4_n_0\
    );
\wrq_btlen_ff_reg[5]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_btlen_ff_reg[1]_i_2_n_0\,
      CO(3) => \wrq_btlen_ff_reg[5]_i_2_n_0\,
      CO(2) => \wrq_btlen_ff_reg[5]_i_2_n_1\,
      CO(1) => \wrq_btlen_ff_reg[5]_i_2_n_2\,
      CO(0) => \wrq_btlen_ff_reg[5]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => arb_wrq_pay(13),
      O(3 downto 0) => \dma_pcie_rq/data1\(7 downto 4),
      S(3 downto 0) => arb_wrq_pay(16 downto 13)
    );
\wrq_btlen_ff_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_btlen_ff_reg[5]_i_2_n_0\,
      CO(3 downto 2) => \NLW_wrq_btlen_ff_reg[8]_i_2_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \wrq_btlen_ff_reg[8]_i_2_n_2\,
      CO(0) => \wrq_btlen_ff_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_wrq_btlen_ff_reg[8]_i_2_O_UNCONNECTED\(3),
      O(2 downto 0) => \dma_pcie_rq/data1\(10 downto 8),
      S(3) => '0',
      S(2 downto 0) => arb_wrq_pay(19 downto 17)
    );
\wrq_dwlen_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \wrq_dwlen_ff_reg[3]_i_1_n_7\,
      I1 => \^head_reg[14]_1\,
      O => \Head_reg[14]_3\(0)
    );
\wrq_dwlen_ff[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1881E77E"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      I2 => \^q\(11),
      I3 => arb_wrq_pay(10),
      I4 => \dma_pcie_rq/wrq_dwlen_whole\(0),
      O => \wrq_dwlen_ff[3]_i_3_n_0\
    );
\wrq_dwlen_ff[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_wrq_pay(10),
      I1 => \^q\(11),
      O => \wrq_dwlen_ff[3]_i_4_n_0\
    );
\wrq_dwlen_ff[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      O => \wrq_dwlen_ff[3]_i_5_n_0\
    );
\wrq_dwlen_ff_reg[10]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_dwlen_ff_reg[7]_i_1_n_0\,
      CO(3 downto 2) => \NLW_wrq_dwlen_ff_reg[10]_i_2_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \wrq_dwlen_ff_reg[10]_i_2_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[10]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_wrq_dwlen_ff_reg[10]_i_2_O_UNCONNECTED\(3),
      O(2 downto 0) => \^o\(2 downto 0),
      S(3) => '0',
      S(2 downto 0) => \dma_pcie_rq/wrq_dwlen_whole\(10 downto 8)
    );
\wrq_dwlen_ff_reg[10]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_dwlen_ff_reg[10]_i_4_n_0\,
      CO(3 downto 0) => \NLW_wrq_dwlen_ff_reg[10]_i_3_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wrq_dwlen_ff_reg[10]_i_3_O_UNCONNECTED\(3 downto 1),
      O(0) => \dma_pcie_rq/wrq_dwlen_whole\(10),
      S(3 downto 1) => B"000",
      S(0) => arb_wrq_pay(21)
    );
\wrq_dwlen_ff_reg[10]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_dwlen_ff_reg[7]_i_2_n_0\,
      CO(3) => \wrq_dwlen_ff_reg[10]_i_4_n_0\,
      CO(2) => \wrq_dwlen_ff_reg[10]_i_4_n_1\,
      CO(1) => \wrq_dwlen_ff_reg[10]_i_4_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[10]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \dma_pcie_rq/wrq_dwlen_whole\(9 downto 6),
      S(3 downto 0) => arb_wrq_pay(20 downto 17)
    );
\wrq_dwlen_ff_reg[3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wrq_dwlen_ff_reg[3]_i_1_n_0\,
      CO(2) => \wrq_dwlen_ff_reg[3]_i_1_n_1\,
      CO(1) => \wrq_dwlen_ff_reg[3]_i_1_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[3]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \dma_pcie_rq/wrq_dwlen_whole\(0),
      O(3 downto 1) => \^head_reg[10]_0\(2 downto 0),
      O(0) => \wrq_dwlen_ff_reg[3]_i_1_n_7\,
      S(3 downto 1) => \dma_pcie_rq/wrq_dwlen_whole\(3 downto 1),
      S(0) => \wrq_dwlen_ff[3]_i_3_n_0\
    );
\wrq_dwlen_ff_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wrq_dwlen_ff_reg[3]_i_2_n_0\,
      CO(2) => \wrq_dwlen_ff_reg[3]_i_2_n_1\,
      CO(1) => \wrq_dwlen_ff_reg[3]_i_2_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => arb_wrq_pay(10 downto 9),
      O(3 downto 2) => \dma_pcie_rq/wrq_dwlen_whole\(1 downto 0),
      O(1 downto 0) => \NLW_wrq_dwlen_ff_reg[3]_i_2_O_UNCONNECTED\(1 downto 0),
      S(3 downto 2) => arb_wrq_pay(12 downto 11),
      S(1) => \wrq_dwlen_ff[3]_i_4_n_0\,
      S(0) => \wrq_dwlen_ff[3]_i_5_n_0\
    );
\wrq_dwlen_ff_reg[7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_dwlen_ff_reg[3]_i_1_n_0\,
      CO(3) => \wrq_dwlen_ff_reg[7]_i_1_n_0\,
      CO(2) => \wrq_dwlen_ff_reg[7]_i_1_n_1\,
      CO(1) => \wrq_dwlen_ff_reg[7]_i_1_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[7]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \^head_reg[20]_0\(3 downto 0),
      S(3 downto 0) => \dma_pcie_rq/wrq_dwlen_whole\(7 downto 4)
    );
\wrq_dwlen_ff_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wrq_dwlen_ff_reg[3]_i_2_n_0\,
      CO(3) => \wrq_dwlen_ff_reg[7]_i_2_n_0\,
      CO(2) => \wrq_dwlen_ff_reg[7]_i_2_n_1\,
      CO(1) => \wrq_dwlen_ff_reg[7]_i_2_n_2\,
      CO(0) => \wrq_dwlen_ff_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \dma_pcie_rq/wrq_dwlen_whole\(5 downto 2),
      S(3 downto 0) => arb_wrq_pay(16 downto 13)
    );
\wrq_fbe_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(11),
      I1 => \^q\(10),
      O => D(0)
    );
\wrq_fbe_ff[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F090F0F"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      I2 => \^q\(11),
      I3 => arb_wrq_pay(10),
      I4 => \^head_reg[14]_0\,
      O => D(1)
    );
\wrq_fbe_ff[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1E213F3F"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      I2 => \^q\(11),
      I3 => arb_wrq_pay(10),
      I4 => \^head_reg[14]_0\,
      O => D(2)
    );
\wrq_fbe_ff[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1881FFFF"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      I2 => arb_wrq_pay(10),
      I3 => \^q\(11),
      I4 => \^head_reg[14]_0\,
      O => D(3)
    );
\wrq_fbe_ff[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000001FFFFFFFF"
    )
        port map (
      I0 => \wrq_fbe_ff[3]_i_3_n_0\,
      I1 => \wrq_fbe_ff[3]_i_4_n_0\,
      I2 => \^o\(2),
      I3 => \^head_reg[10]_0\(0),
      I4 => \^head_reg[10]_0\(1),
      I5 => \^head_reg[14]_1\,
      O => \^head_reg[14]_0\
    );
\wrq_fbe_ff[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \wrq_dwlen_ff_reg[3]_i_1_n_7\,
      I1 => \^o\(1),
      I2 => \^o\(0),
      I3 => \^head_reg[20]_0\(3),
      O => \wrq_fbe_ff[3]_i_3_n_0\
    );
\wrq_fbe_ff[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^head_reg[20]_0\(2),
      I1 => \^head_reg[20]_0\(1),
      I2 => \^head_reg[20]_0\(0),
      I3 => \^head_reg[10]_0\(2),
      O => \wrq_fbe_ff[3]_i_4_n_0\
    );
\wrq_lbe_ff[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F66F"
    )
        port map (
      I0 => \^q\(11),
      I1 => arb_wrq_pay(10),
      I2 => \^q\(10),
      I3 => arb_wrq_pay(9),
      O => \Head_reg[48]_0\(0)
    );
\wrq_lbe_ff[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => arb_wrq_pay(9),
      I1 => \^q\(10),
      I2 => \^q\(11),
      I3 => arb_wrq_pay(10),
      O => \Head_reg[48]_0\(1)
    );
\wrq_lbe_ff[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6009"
    )
        port map (
      I0 => \^q\(11),
      I1 => arb_wrq_pay(10),
      I2 => \^q\(10),
      I3 => arb_wrq_pay(9),
      O => \Head_reg[48]_0\(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0_53\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    almost_full_ff_reg_0 : out STD_LOGIC;
    \Head_reg[8]_0\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 86 downto 0 );
    DIA : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DIB : out STD_LOGIC_VECTOR ( 1 downto 0 );
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[14]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[20]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    arb_wrq_vld : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[0]_0\ : in STD_LOGIC;
    \Head_reg[110]_0\ : in STD_LOGIC_VECTOR ( 86 downto 0 );
    \Head_reg[110]_1\ : in STD_LOGIC;
    \FifoCntrWr_reg[0]_0\ : in STD_LOGIC;
    \FifoCntrWr_reg[0]_1\ : in STD_LOGIC;
    \Head1__2\ : in STD_LOGIC;
    Head0 : in STD_LOGIC_VECTOR ( 22 downto 0 );
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_15_in : in STD_LOGIC;
    I69 : in STD_LOGIC_VECTOR ( 91 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0_53\ : entity is "xdma_v4_1_8_GenericFIFOAsync";
end \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0_53\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized0_53\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__7_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__14_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__14_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__7_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__16_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__15_n_0\ : STD_LOGIC;
  signal \Head1__2_0\ : STD_LOGIC;
  signal \Head[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \Head[100]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[101]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[102]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[103]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[104]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[105]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[106]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[107]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[108]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[109]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[10]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[110]_i_1__6_n_0\ : STD_LOGIC;
  signal \Head[110]_i_2_n_0\ : STD_LOGIC;
  signal \Head[11]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[12]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[13]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[14]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[15]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[16]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[17]_i_1__8_n_0\ : STD_LOGIC;
  signal \Head[18]_i_1__11_n_0\ : STD_LOGIC;
  signal \Head[19]_i_1__11_n_0\ : STD_LOGIC;
  signal \Head[20]_i_1__12_n_0\ : STD_LOGIC;
  signal \Head[21]_i_1__12_n_0\ : STD_LOGIC;
  signal \Head[37]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[38]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[39]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \Head[40]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[41]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[47]_i_1__8_n_0\ : STD_LOGIC;
  signal \Head[48]_i_1__7_n_0\ : STD_LOGIC;
  signal \Head[49]_i_1__7_n_0\ : STD_LOGIC;
  signal \Head[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \Head[50]_i_1__7_n_0\ : STD_LOGIC;
  signal \Head[51]_i_1__7_n_0\ : STD_LOGIC;
  signal \Head[52]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[53]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[54]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[55]_i_1__5_n_0\ : STD_LOGIC;
  signal \Head[56]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[57]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[58]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[59]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \Head[60]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[61]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[62]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[63]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[64]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[65]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[66]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[67]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[68]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[69]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[70]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[71]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[72]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[73]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[74]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[75]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[76]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[77]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[78]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[79]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[80]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[81]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[82]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[83]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[84]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[85]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[86]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[87]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[88]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[89]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[8]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[90]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[91]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[92]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[93]_i_1__10_n_0\ : STD_LOGIC;
  signal \Head[94]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[95]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[96]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[97]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[98]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[99]_i_1__9_n_0\ : STD_LOGIC;
  signal \Head[9]_i_1__9_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_102_107_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_108_112_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_108_112_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_108_112_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_108_112_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_18_23_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_36_41_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_42_47_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_42_47_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_42_47_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_48_53_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_54_59_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_60_65_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_66_71_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_72_77_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_78_83_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_84_89_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_90_95_n_5 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_1 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_2 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_3 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_96_101_n_5 : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 86 downto 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_3__0_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1__18_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__18_n_0\ : STD_LOGIC;
  signal \almost_full_ff_i_1__2_n_0\ : STD_LOGIC;
  signal \^almost_full_ff_reg_0\ : STD_LOGIC;
  signal \axi4mm_axi_mm_master_wr/p_0_in1_in\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \empty_ff_i_1__8_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_11_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_11_n_1 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_11_n_2 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_11_n_3 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_11_n_4 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_13_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_14_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_15_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_7_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_7_n_1 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_7_n_2 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_7_n_3 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_8_n_0 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_8_n_1 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_8_n_2 : STD_LOGIC;
  signal m_axi_awlenq_reg_0_15_0_5_i_8_n_3 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_5_n_0 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_5_n_1 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_5_n_2 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_5_n_3 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0 : STD_LOGIC;
  signal m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0 : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_112_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_112_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__14\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__7\ : label is "soft_lutpair489";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__16\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__15\ : label is "soft_lutpair490";
  attribute SOFT_HLUTNM of \Head[10]_i_1__5\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \Head[11]_i_1__5\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \Head[12]_i_1__5\ : label is "soft_lutpair492";
  attribute SOFT_HLUTNM of \Head[13]_i_1__5\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \Head[14]_i_1__5\ : label is "soft_lutpair493";
  attribute SOFT_HLUTNM of \Head[15]_i_1__5\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \Head[16]_i_1__4\ : label is "soft_lutpair494";
  attribute SOFT_HLUTNM of \Head[17]_i_1__4\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \Head[18]_i_1__5\ : label is "soft_lutpair495";
  attribute SOFT_HLUTNM of \Head[19]_i_1__5\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \Head[1]_i_1__3\ : label is "soft_lutpair491";
  attribute SOFT_HLUTNM of \Head[20]_i_1__6\ : label is "soft_lutpair496";
  attribute SOFT_HLUTNM of \Head[21]_i_1__6\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \Head[23]_i_1__4\ : label is "soft_lutpair497";
  attribute SOFT_HLUTNM of \Head[24]_i_1__4\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \Head[25]_i_1__4\ : label is "soft_lutpair498";
  attribute SOFT_HLUTNM of \Head[26]_i_1__4\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \Head[27]_i_1__4\ : label is "soft_lutpair499";
  attribute SOFT_HLUTNM of \Head[28]_i_1__4\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \Head[29]_i_1__4\ : label is "soft_lutpair500";
  attribute SOFT_HLUTNM of \Head[30]_i_1__3\ : label is "soft_lutpair501";
  attribute SOFT_HLUTNM of \Head[31]_i_1__3\ : label is "soft_lutpair501";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 452;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_112 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_112 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_112 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_112 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_112 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_112 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_112 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_112 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_112 : label is 112;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_36_41 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_36_41 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_36_41 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_42_47 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_42_47 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_42_47 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_48_53 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_48_53 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_48_53 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 452;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \RdPtr[1]_i_3__0\ : label is "soft_lutpair488";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \RdPtr_reg[1]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[1]\ : label is "128";
  attribute SOFT_HLUTNM of \empty_ff_i_1__8\ : label is "soft_lutpair488";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of m_axi_waddrlastq_reg_0_15_0_5_i_5 : label is 35;
begin
  Q(86 downto 0) <= \^q\(86 downto 0);
  almost_full_ff_reg_0 <= \^almost_full_ff_reg_0\;
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
\FifoCntrRd[0]_i_1__7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__7_n_0\
    );
\FifoCntrRd[1]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C396"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(1),
      I3 => \^almost_full_ff_reg_0\,
      O => \FifoCntrRd[1]_i_1__14_n_0\
    );
\FifoCntrRd[2]_i_1__14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \FifoCntrWr_reg[0]_1\,
      O => \FifoCntrRd[2]_i_1__14_n_0\
    );
\FifoCntrRd[2]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FC03BD42"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \^almost_full_ff_reg_0\,
      O => \FifoCntrRd[2]_i_2__7_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrRd[0]_i_1__7_n_0\,
      Q => FifoCntrRd(0),
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrRd[1]_i_1__14_n_0\,
      Q => FifoCntrRd(1),
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrRd[2]_i_2__7_n_0\,
      Q => FifoCntrRd(2),
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__6_n_0\
    );
\FifoCntrWr[1]_i_1__16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C396"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(1),
      I3 => \^almost_full_ff_reg_0\,
      O => \FifoCntrWr[1]_i_1__16_n_0\
    );
\FifoCntrWr[2]_i_1__15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FC03BD42"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(1),
      I3 => FifoCntrWr(2),
      I4 => \^almost_full_ff_reg_0\,
      O => \FifoCntrWr[2]_i_1__15_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrWr[0]_i_1__6_n_0\,
      Q => FifoCntrWr(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrWr[1]_i_1__16_n_0\,
      Q => FifoCntrWr(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__14_n_0\,
      D => \FifoCntrWr[2]_i_1__15_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
\Head[0]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(0),
      I3 => MemArray_reg_0_3_0_5_n_1,
      I4 => \Head1__2_0\,
      O => \Head[0]_i_1__8_n_0\
    );
\Head[100]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(76),
      I3 => MemArray_reg_0_3_96_101_n_5,
      I4 => \Head1__2_0\,
      O => \Head[100]_i_1__9_n_0\
    );
\Head[101]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(77),
      I3 => MemArray_reg_0_3_96_101_n_4,
      I4 => \Head1__2_0\,
      O => \Head[101]_i_1__9_n_0\
    );
\Head[102]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(78),
      I3 => MemArray_reg_0_3_102_107_n_1,
      I4 => \Head1__2_0\,
      O => \Head[102]_i_1__9_n_0\
    );
\Head[103]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(79),
      I3 => MemArray_reg_0_3_102_107_n_0,
      I4 => \Head1__2_0\,
      O => \Head[103]_i_1__9_n_0\
    );
\Head[104]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(80),
      I3 => MemArray_reg_0_3_102_107_n_3,
      I4 => \Head1__2_0\,
      O => \Head[104]_i_1__9_n_0\
    );
\Head[105]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(81),
      I3 => MemArray_reg_0_3_102_107_n_2,
      I4 => \Head1__2_0\,
      O => \Head[105]_i_1__9_n_0\
    );
\Head[106]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(82),
      I3 => MemArray_reg_0_3_102_107_n_5,
      I4 => \Head1__2_0\,
      O => \Head[106]_i_1__9_n_0\
    );
\Head[107]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(83),
      I3 => MemArray_reg_0_3_102_107_n_4,
      I4 => \Head1__2_0\,
      O => \Head[107]_i_1__9_n_0\
    );
\Head[108]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(84),
      I3 => MemArray_reg_0_3_108_112_n_1,
      I4 => \Head1__2_0\,
      O => \Head[108]_i_1__9_n_0\
    );
\Head[109]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(85),
      I3 => MemArray_reg_0_3_108_112_n_0,
      I4 => \Head1__2_0\,
      O => \Head[109]_i_1__9_n_0\
    );
\Head[10]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(6),
      I3 => MemArray_reg_0_3_6_11_n_5,
      I4 => \Head1__2_0\,
      O => \Head[10]_i_1__10_n_0\
    );
\Head[10]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(5),
      I1 => \Head1__2\,
      I2 => Head0(1),
      O => \Head_reg[8]_0\(1)
    );
\Head[110]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEF"
    )
        port map (
      I0 => \Head1__2_0\,
      I1 => \FifoCntrWr_reg[0]_1\,
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(0),
      O => \Head[110]_i_1__6_n_0\
    );
\Head[110]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[110]_1\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(86),
      I3 => MemArray_reg_0_3_108_112_n_3,
      I4 => \Head1__2_0\,
      O => \Head[110]_i_2_n_0\
    );
\Head[11]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(7),
      I3 => MemArray_reg_0_3_6_11_n_4,
      I4 => \Head1__2_0\,
      O => \Head[11]_i_1__10_n_0\
    );
\Head[11]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(6),
      I1 => \Head1__2\,
      I2 => Head0(2),
      O => \Head_reg[8]_0\(2)
    );
\Head[12]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(8),
      I3 => MemArray_reg_0_3_12_17_n_1,
      I4 => \Head1__2_0\,
      O => \Head[12]_i_1__10_n_0\
    );
\Head[12]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(7),
      I1 => \Head1__2\,
      I2 => Head0(3),
      O => \Head_reg[8]_0\(3)
    );
\Head[13]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(9),
      I3 => MemArray_reg_0_3_12_17_n_0,
      I4 => \Head1__2_0\,
      O => \Head[13]_i_1__10_n_0\
    );
\Head[13]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(8),
      I1 => \Head1__2\,
      I2 => Head0(4),
      O => \Head_reg[8]_0\(4)
    );
\Head[14]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(10),
      I3 => MemArray_reg_0_3_12_17_n_3,
      I4 => \Head1__2_0\,
      O => \Head[14]_i_1__10_n_0\
    );
\Head[14]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(9),
      I1 => \Head1__2\,
      I2 => Head0(5),
      O => \Head_reg[8]_0\(5)
    );
\Head[15]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(11),
      I3 => MemArray_reg_0_3_12_17_n_2,
      I4 => \Head1__2_0\,
      O => \Head[15]_i_1__10_n_0\
    );
\Head[15]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(10),
      I1 => \Head1__2\,
      I2 => Head0(6),
      O => \Head_reg[8]_0\(6)
    );
\Head[16]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(11),
      I1 => \Head1__2\,
      I2 => Head0(7),
      O => \Head_reg[8]_0\(7)
    );
\Head[16]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(12),
      I3 => MemArray_reg_0_3_12_17_n_5,
      I4 => \Head1__2_0\,
      O => \Head[16]_i_1__9_n_0\
    );
\Head[17]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(12),
      I1 => \Head1__2\,
      I2 => Head0(8),
      O => \Head_reg[8]_0\(8)
    );
\Head[17]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(13),
      I3 => MemArray_reg_0_3_12_17_n_4,
      I4 => \Head1__2_0\,
      O => \Head[17]_i_1__8_n_0\
    );
\Head[18]_i_1__11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(14),
      I3 => MemArray_reg_0_3_18_23_n_1,
      I4 => \Head1__2_0\,
      O => \Head[18]_i_1__11_n_0\
    );
\Head[18]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(13),
      I1 => \Head1__2\,
      I2 => Head0(9),
      O => \Head_reg[8]_0\(9)
    );
\Head[19]_i_1__11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(15),
      I3 => MemArray_reg_0_3_18_23_n_0,
      I4 => \Head1__2_0\,
      O => \Head[19]_i_1__11_n_0\
    );
\Head[19]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(14),
      I1 => \Head1__2\,
      I2 => Head0(10),
      O => \Head_reg[8]_0\(10)
    );
\Head[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \Head1__2\,
      I2 => Head0(0),
      O => \Head_reg[8]_0\(0)
    );
\Head[20]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(16),
      I3 => MemArray_reg_0_3_18_23_n_3,
      I4 => \Head1__2_0\,
      O => \Head[20]_i_1__12_n_0\
    );
\Head[20]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(15),
      I1 => \Head1__2\,
      I2 => Head0(11),
      O => \Head_reg[8]_0\(11)
    );
\Head[21]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(17),
      I3 => MemArray_reg_0_3_18_23_n_2,
      I4 => \Head1__2_0\,
      O => \Head[21]_i_1__12_n_0\
    );
\Head[21]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(16),
      I1 => \Head1__2\,
      I2 => Head0(12),
      O => \Head_reg[8]_0\(12)
    );
\Head[23]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(23),
      I1 => \Head1__2\,
      I2 => Head0(13),
      O => \Head_reg[8]_0\(13)
    );
\Head[24]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(24),
      I1 => \Head1__2\,
      I2 => Head0(14),
      O => \Head_reg[8]_0\(14)
    );
\Head[25]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(25),
      I1 => \Head1__2\,
      I2 => Head0(15),
      O => \Head_reg[8]_0\(15)
    );
\Head[26]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(26),
      I1 => \Head1__2\,
      I2 => Head0(16),
      O => \Head_reg[8]_0\(16)
    );
\Head[27]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(27),
      I1 => \Head1__2\,
      I2 => Head0(17),
      O => \Head_reg[8]_0\(17)
    );
\Head[28]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(28),
      I1 => \Head1__2\,
      I2 => Head0(18),
      O => \Head_reg[8]_0\(18)
    );
\Head[29]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(1),
      I1 => \Head1__2\,
      I2 => Head0(19),
      O => \Head_reg[8]_0\(19)
    );
\Head[30]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(2),
      I1 => \Head1__2\,
      I2 => Head0(20),
      O => \Head_reg[8]_0\(20)
    );
\Head[31]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(3),
      I1 => \Head1__2\,
      I2 => Head0(21),
      O => \Head_reg[8]_0\(21)
    );
\Head[34]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^q\(4),
      I1 => \Head1__2\,
      I2 => Head0(22),
      O => \Head_reg[8]_0\(22)
    );
\Head[37]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(18),
      I3 => MemArray_reg_0_3_36_41_n_0,
      I4 => \Head1__2_0\,
      O => \Head[37]_i_1__5_n_0\
    );
\Head[38]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(19),
      I3 => MemArray_reg_0_3_36_41_n_3,
      I4 => \Head1__2_0\,
      O => \Head[38]_i_1__5_n_0\
    );
\Head[39]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(20),
      I3 => MemArray_reg_0_3_36_41_n_2,
      I4 => \Head1__2_0\,
      O => \Head[39]_i_1__5_n_0\
    );
\Head[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(1),
      I3 => MemArray_reg_0_3_0_5_n_2,
      I4 => \Head1__2_0\,
      O => \Head[3]_i_1__6_n_0\
    );
\Head[40]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(21),
      I3 => MemArray_reg_0_3_36_41_n_5,
      I4 => \Head1__2_0\,
      O => \Head[40]_i_1__5_n_0\
    );
\Head[41]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(22),
      I3 => MemArray_reg_0_3_36_41_n_4,
      I4 => \Head1__2_0\,
      O => \Head[41]_i_1__5_n_0\
    );
\Head[47]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(23),
      I3 => MemArray_reg_0_3_42_47_n_4,
      I4 => \Head1__2_0\,
      O => \Head[47]_i_1__8_n_0\
    );
\Head[48]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(24),
      I3 => MemArray_reg_0_3_48_53_n_1,
      I4 => \Head1__2_0\,
      O => \Head[48]_i_1__7_n_0\
    );
\Head[49]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(25),
      I3 => MemArray_reg_0_3_48_53_n_0,
      I4 => \Head1__2_0\,
      O => \Head[49]_i_1__7_n_0\
    );
\Head[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(2),
      I3 => MemArray_reg_0_3_0_5_n_5,
      I4 => \Head1__2_0\,
      O => \Head[4]_i_1__6_n_0\
    );
\Head[50]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(26),
      I3 => MemArray_reg_0_3_48_53_n_3,
      I4 => \Head1__2_0\,
      O => \Head[50]_i_1__7_n_0\
    );
\Head[51]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(27),
      I3 => MemArray_reg_0_3_48_53_n_2,
      I4 => \Head1__2_0\,
      O => \Head[51]_i_1__7_n_0\
    );
\Head[52]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(28),
      I3 => MemArray_reg_0_3_48_53_n_5,
      I4 => \Head1__2_0\,
      O => \Head[52]_i_1__5_n_0\
    );
\Head[53]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(29),
      I3 => MemArray_reg_0_3_48_53_n_4,
      I4 => \Head1__2_0\,
      O => \Head[53]_i_1__5_n_0\
    );
\Head[54]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(30),
      I3 => MemArray_reg_0_3_54_59_n_1,
      I4 => \Head1__2_0\,
      O => \Head[54]_i_1__5_n_0\
    );
\Head[55]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(31),
      I3 => MemArray_reg_0_3_54_59_n_0,
      I4 => \Head1__2_0\,
      O => \Head[55]_i_1__5_n_0\
    );
\Head[56]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(32),
      I3 => MemArray_reg_0_3_54_59_n_3,
      I4 => \Head1__2_0\,
      O => \Head[56]_i_1__9_n_0\
    );
\Head[57]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(33),
      I3 => MemArray_reg_0_3_54_59_n_2,
      I4 => \Head1__2_0\,
      O => \Head[57]_i_1__9_n_0\
    );
\Head[58]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(34),
      I3 => MemArray_reg_0_3_54_59_n_5,
      I4 => \Head1__2_0\,
      O => \Head[58]_i_1__9_n_0\
    );
\Head[59]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(35),
      I3 => MemArray_reg_0_3_54_59_n_4,
      I4 => \Head1__2_0\,
      O => \Head[59]_i_1__9_n_0\
    );
\Head[5]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(3),
      I3 => MemArray_reg_0_3_0_5_n_4,
      I4 => \Head1__2_0\,
      O => \Head[5]_i_1__6_n_0\
    );
\Head[60]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(36),
      I3 => MemArray_reg_0_3_60_65_n_1,
      I4 => \Head1__2_0\,
      O => \Head[60]_i_1__10_n_0\
    );
\Head[61]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(37),
      I3 => MemArray_reg_0_3_60_65_n_0,
      I4 => \Head1__2_0\,
      O => \Head[61]_i_1__10_n_0\
    );
\Head[62]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(38),
      I3 => MemArray_reg_0_3_60_65_n_3,
      I4 => \Head1__2_0\,
      O => \Head[62]_i_1__10_n_0\
    );
\Head[63]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(39),
      I3 => MemArray_reg_0_3_60_65_n_2,
      I4 => \Head1__2_0\,
      O => \Head[63]_i_1__10_n_0\
    );
\Head[64]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(40),
      I3 => MemArray_reg_0_3_60_65_n_5,
      I4 => \Head1__2_0\,
      O => \Head[64]_i_1__9_n_0\
    );
\Head[65]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(41),
      I3 => MemArray_reg_0_3_60_65_n_4,
      I4 => \Head1__2_0\,
      O => \Head[65]_i_1__9_n_0\
    );
\Head[66]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(42),
      I3 => MemArray_reg_0_3_66_71_n_1,
      I4 => \Head1__2_0\,
      O => \Head[66]_i_1__10_n_0\
    );
\Head[67]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(43),
      I3 => MemArray_reg_0_3_66_71_n_0,
      I4 => \Head1__2_0\,
      O => \Head[67]_i_1__10_n_0\
    );
\Head[68]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(44),
      I3 => MemArray_reg_0_3_66_71_n_3,
      I4 => \Head1__2_0\,
      O => \Head[68]_i_1__10_n_0\
    );
\Head[69]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(45),
      I3 => MemArray_reg_0_3_66_71_n_2,
      I4 => \Head1__2_0\,
      O => \Head[69]_i_1__10_n_0\
    );
\Head[70]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(46),
      I3 => MemArray_reg_0_3_66_71_n_5,
      I4 => \Head1__2_0\,
      O => \Head[70]_i_1__10_n_0\
    );
\Head[71]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(47),
      I3 => MemArray_reg_0_3_66_71_n_4,
      I4 => \Head1__2_0\,
      O => \Head[71]_i_1__10_n_0\
    );
\Head[72]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(48),
      I3 => MemArray_reg_0_3_72_77_n_1,
      I4 => \Head1__2_0\,
      O => \Head[72]_i_1__10_n_0\
    );
\Head[73]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(49),
      I3 => MemArray_reg_0_3_72_77_n_0,
      I4 => \Head1__2_0\,
      O => \Head[73]_i_1__10_n_0\
    );
\Head[74]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(50),
      I3 => MemArray_reg_0_3_72_77_n_3,
      I4 => \Head1__2_0\,
      O => \Head[74]_i_1__9_n_0\
    );
\Head[75]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(51),
      I3 => MemArray_reg_0_3_72_77_n_2,
      I4 => \Head1__2_0\,
      O => \Head[75]_i_1__9_n_0\
    );
\Head[76]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(52),
      I3 => MemArray_reg_0_3_72_77_n_5,
      I4 => \Head1__2_0\,
      O => \Head[76]_i_1__9_n_0\
    );
\Head[77]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(53),
      I3 => MemArray_reg_0_3_72_77_n_4,
      I4 => \Head1__2_0\,
      O => \Head[77]_i_1__9_n_0\
    );
\Head[78]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(54),
      I3 => MemArray_reg_0_3_78_83_n_1,
      I4 => \Head1__2_0\,
      O => \Head[78]_i_1__9_n_0\
    );
\Head[79]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(55),
      I3 => MemArray_reg_0_3_78_83_n_0,
      I4 => \Head1__2_0\,
      O => \Head[79]_i_1__9_n_0\
    );
\Head[80]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(56),
      I3 => MemArray_reg_0_3_78_83_n_3,
      I4 => \Head1__2_0\,
      O => \Head[80]_i_1__9_n_0\
    );
\Head[81]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(57),
      I3 => MemArray_reg_0_3_78_83_n_2,
      I4 => \Head1__2_0\,
      O => \Head[81]_i_1__9_n_0\
    );
\Head[82]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(58),
      I3 => MemArray_reg_0_3_78_83_n_5,
      I4 => \Head1__2_0\,
      O => \Head[82]_i_1__9_n_0\
    );
\Head[83]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(59),
      I3 => MemArray_reg_0_3_78_83_n_4,
      I4 => \Head1__2_0\,
      O => \Head[83]_i_1__9_n_0\
    );
\Head[84]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(60),
      I3 => MemArray_reg_0_3_84_89_n_1,
      I4 => \Head1__2_0\,
      O => \Head[84]_i_1__9_n_0\
    );
\Head[85]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(61),
      I3 => MemArray_reg_0_3_84_89_n_0,
      I4 => \Head1__2_0\,
      O => \Head[85]_i_1__9_n_0\
    );
\Head[86]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(62),
      I3 => MemArray_reg_0_3_84_89_n_3,
      I4 => \Head1__2_0\,
      O => \Head[86]_i_1__9_n_0\
    );
\Head[87]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(63),
      I3 => MemArray_reg_0_3_84_89_n_2,
      I4 => \Head1__2_0\,
      O => \Head[87]_i_1__9_n_0\
    );
\Head[88]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(64),
      I3 => MemArray_reg_0_3_84_89_n_5,
      I4 => \Head1__2_0\,
      O => \Head[88]_i_1__9_n_0\
    );
\Head[89]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(65),
      I3 => MemArray_reg_0_3_84_89_n_4,
      I4 => \Head1__2_0\,
      O => \Head[89]_i_1__9_n_0\
    );
\Head[8]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(4),
      I3 => MemArray_reg_0_3_6_11_n_3,
      I4 => \Head1__2_0\,
      O => \Head[8]_i_1__9_n_0\
    );
\Head[90]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(66),
      I3 => MemArray_reg_0_3_90_95_n_1,
      I4 => \Head1__2_0\,
      O => \Head[90]_i_1__10_n_0\
    );
\Head[91]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(67),
      I3 => MemArray_reg_0_3_90_95_n_0,
      I4 => \Head1__2_0\,
      O => \Head[91]_i_1__10_n_0\
    );
\Head[92]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(68),
      I3 => MemArray_reg_0_3_90_95_n_3,
      I4 => \Head1__2_0\,
      O => \Head[92]_i_1__10_n_0\
    );
\Head[93]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(69),
      I3 => MemArray_reg_0_3_90_95_n_2,
      I4 => \Head1__2_0\,
      O => \Head[93]_i_1__10_n_0\
    );
\Head[94]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(70),
      I3 => MemArray_reg_0_3_90_95_n_5,
      I4 => \Head1__2_0\,
      O => \Head[94]_i_1__9_n_0\
    );
\Head[95]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(71),
      I3 => MemArray_reg_0_3_90_95_n_4,
      I4 => \Head1__2_0\,
      O => \Head[95]_i_1__9_n_0\
    );
\Head[96]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(72),
      I3 => MemArray_reg_0_3_96_101_n_1,
      I4 => \Head1__2_0\,
      O => \Head[96]_i_1__9_n_0\
    );
\Head[97]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(73),
      I3 => MemArray_reg_0_3_96_101_n_0,
      I4 => \Head1__2_0\,
      O => \Head[97]_i_1__9_n_0\
    );
\Head[98]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(74),
      I3 => MemArray_reg_0_3_96_101_n_3,
      I4 => \Head1__2_0\,
      O => \Head[98]_i_1__9_n_0\
    );
\Head[99]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(75),
      I3 => MemArray_reg_0_3_96_101_n_2,
      I4 => \Head1__2_0\,
      O => \Head[99]_i_1__9_n_0\
    );
\Head[9]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1010FF00"
    )
        port map (
      I0 => \Head_reg[0]_0\,
      I1 => \^almost_full_ff_reg_0\,
      I2 => \Head_reg[110]_0\(5),
      I3 => MemArray_reg_0_3_6_11_n_2,
      I4 => \Head1__2_0\,
      O => \Head[9]_i_1__9_n_0\
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[0]_i_1__8_n_0\,
      Q => \^q\(0),
      R => SR(0)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[100]_i_1__9_n_0\,
      Q => \^q\(76),
      R => SR(0)
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[101]_i_1__9_n_0\,
      Q => \^q\(77),
      R => SR(0)
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[102]_i_1__9_n_0\,
      Q => \^q\(78),
      R => SR(0)
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[103]_i_1__9_n_0\,
      Q => \^q\(79),
      R => SR(0)
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[104]_i_1__9_n_0\,
      Q => \^q\(80),
      R => SR(0)
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[105]_i_1__9_n_0\,
      Q => \^q\(81),
      R => SR(0)
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[106]_i_1__9_n_0\,
      Q => \^q\(82),
      R => SR(0)
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[107]_i_1__9_n_0\,
      Q => \^q\(83),
      R => SR(0)
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[108]_i_1__9_n_0\,
      Q => \^q\(84),
      R => SR(0)
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[109]_i_1__9_n_0\,
      Q => \^q\(85),
      R => SR(0)
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[10]_i_1__10_n_0\,
      Q => \^q\(6),
      R => SR(0)
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[110]_i_2_n_0\,
      Q => \^q\(86),
      R => SR(0)
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[11]_i_1__10_n_0\,
      Q => \^q\(7),
      R => SR(0)
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[12]_i_1__10_n_0\,
      Q => \^q\(8),
      R => SR(0)
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[13]_i_1__10_n_0\,
      Q => \^q\(9),
      R => SR(0)
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[14]_i_1__10_n_0\,
      Q => \^q\(10),
      R => SR(0)
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[15]_i_1__10_n_0\,
      Q => \^q\(11),
      R => SR(0)
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[16]_i_1__9_n_0\,
      Q => \^q\(12),
      R => SR(0)
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[17]_i_1__8_n_0\,
      Q => \^q\(13),
      R => SR(0)
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[18]_i_1__11_n_0\,
      Q => \^q\(14),
      R => SR(0)
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[19]_i_1__11_n_0\,
      Q => \^q\(15),
      R => SR(0)
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[20]_i_1__12_n_0\,
      Q => \^q\(16),
      R => SR(0)
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[21]_i_1__12_n_0\,
      Q => \^q\(17),
      R => SR(0)
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[37]_i_1__5_n_0\,
      Q => \^q\(18),
      R => SR(0)
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[38]_i_1__5_n_0\,
      Q => \^q\(19),
      R => SR(0)
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[39]_i_1__5_n_0\,
      Q => \^q\(20),
      R => SR(0)
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[3]_i_1__6_n_0\,
      Q => \^q\(1),
      R => SR(0)
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[40]_i_1__5_n_0\,
      Q => \^q\(21),
      R => SR(0)
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[41]_i_1__5_n_0\,
      Q => \^q\(22),
      R => SR(0)
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[47]_i_1__8_n_0\,
      Q => \^q\(23),
      R => SR(0)
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[48]_i_1__7_n_0\,
      Q => \^q\(24),
      R => SR(0)
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[49]_i_1__7_n_0\,
      Q => \^q\(25),
      R => SR(0)
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[4]_i_1__6_n_0\,
      Q => \^q\(2),
      R => SR(0)
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[50]_i_1__7_n_0\,
      Q => \^q\(26),
      R => SR(0)
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[51]_i_1__7_n_0\,
      Q => \^q\(27),
      R => SR(0)
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[52]_i_1__5_n_0\,
      Q => \^q\(28),
      R => SR(0)
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[53]_i_1__5_n_0\,
      Q => \^q\(29),
      R => SR(0)
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[54]_i_1__5_n_0\,
      Q => \^q\(30),
      R => SR(0)
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[55]_i_1__5_n_0\,
      Q => \^q\(31),
      R => SR(0)
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[56]_i_1__9_n_0\,
      Q => \^q\(32),
      R => SR(0)
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[57]_i_1__9_n_0\,
      Q => \^q\(33),
      R => SR(0)
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[58]_i_1__9_n_0\,
      Q => \^q\(34),
      R => SR(0)
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[59]_i_1__9_n_0\,
      Q => \^q\(35),
      R => SR(0)
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[5]_i_1__6_n_0\,
      Q => \^q\(3),
      R => SR(0)
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[60]_i_1__10_n_0\,
      Q => \^q\(36),
      R => SR(0)
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[61]_i_1__10_n_0\,
      Q => \^q\(37),
      R => SR(0)
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[62]_i_1__10_n_0\,
      Q => \^q\(38),
      R => SR(0)
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[63]_i_1__10_n_0\,
      Q => \^q\(39),
      R => SR(0)
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[64]_i_1__9_n_0\,
      Q => \^q\(40),
      R => SR(0)
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[65]_i_1__9_n_0\,
      Q => \^q\(41),
      R => SR(0)
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[66]_i_1__10_n_0\,
      Q => \^q\(42),
      R => SR(0)
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[67]_i_1__10_n_0\,
      Q => \^q\(43),
      R => SR(0)
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[68]_i_1__10_n_0\,
      Q => \^q\(44),
      R => SR(0)
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[69]_i_1__10_n_0\,
      Q => \^q\(45),
      R => SR(0)
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[70]_i_1__10_n_0\,
      Q => \^q\(46),
      R => SR(0)
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[71]_i_1__10_n_0\,
      Q => \^q\(47),
      R => SR(0)
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[72]_i_1__10_n_0\,
      Q => \^q\(48),
      R => SR(0)
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[73]_i_1__10_n_0\,
      Q => \^q\(49),
      R => SR(0)
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[74]_i_1__9_n_0\,
      Q => \^q\(50),
      R => SR(0)
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[75]_i_1__9_n_0\,
      Q => \^q\(51),
      R => SR(0)
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[76]_i_1__9_n_0\,
      Q => \^q\(52),
      R => SR(0)
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[77]_i_1__9_n_0\,
      Q => \^q\(53),
      R => SR(0)
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[78]_i_1__9_n_0\,
      Q => \^q\(54),
      R => SR(0)
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[79]_i_1__9_n_0\,
      Q => \^q\(55),
      R => SR(0)
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[80]_i_1__9_n_0\,
      Q => \^q\(56),
      R => SR(0)
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[81]_i_1__9_n_0\,
      Q => \^q\(57),
      R => SR(0)
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[82]_i_1__9_n_0\,
      Q => \^q\(58),
      R => SR(0)
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[83]_i_1__9_n_0\,
      Q => \^q\(59),
      R => SR(0)
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[84]_i_1__9_n_0\,
      Q => \^q\(60),
      R => SR(0)
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[85]_i_1__9_n_0\,
      Q => \^q\(61),
      R => SR(0)
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[86]_i_1__9_n_0\,
      Q => \^q\(62),
      R => SR(0)
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[87]_i_1__9_n_0\,
      Q => \^q\(63),
      R => SR(0)
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[88]_i_1__9_n_0\,
      Q => \^q\(64),
      R => SR(0)
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[89]_i_1__9_n_0\,
      Q => \^q\(65),
      R => SR(0)
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[8]_i_1__9_n_0\,
      Q => \^q\(4),
      R => SR(0)
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[90]_i_1__10_n_0\,
      Q => \^q\(66),
      R => SR(0)
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[91]_i_1__10_n_0\,
      Q => \^q\(67),
      R => SR(0)
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[92]_i_1__10_n_0\,
      Q => \^q\(68),
      R => SR(0)
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[93]_i_1__10_n_0\,
      Q => \^q\(69),
      R => SR(0)
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[94]_i_1__9_n_0\,
      Q => \^q\(70),
      R => SR(0)
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[95]_i_1__9_n_0\,
      Q => \^q\(71),
      R => SR(0)
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[96]_i_1__9_n_0\,
      Q => \^q\(72),
      R => SR(0)
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[97]_i_1__9_n_0\,
      Q => \^q\(73),
      R => SR(0)
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[98]_i_1__9_n_0\,
      Q => \^q\(74),
      R => SR(0)
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[99]_i_1__9_n_0\,
      Q => \^q\(75),
      R => SR(0)
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[110]_i_1__6_n_0\,
      D => \Head[9]_i_1__9_n_0\,
      Q => \^q\(5),
      R => SR(0)
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(1 downto 0),
      DIB(1 downto 0) => I69(3 downto 2),
      DIC(1 downto 0) => I69(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_0_5_n_0,
      DOA(0) => MemArray_reg_0_3_0_5_n_1,
      DOB(1) => MemArray_reg_0_3_0_5_n_2,
      DOB(0) => MemArray_reg_0_3_0_5_n_3,
      DOC(1) => MemArray_reg_0_3_0_5_n_4,
      DOC(0) => MemArray_reg_0_3_0_5_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(83 downto 82),
      DIB(1 downto 0) => I69(85 downto 84),
      DIC(1 downto 0) => I69(87 downto 86),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_102_107_n_0,
      DOA(0) => MemArray_reg_0_3_102_107_n_1,
      DOB(1) => MemArray_reg_0_3_102_107_n_2,
      DOB(0) => MemArray_reg_0_3_102_107_n_3,
      DOC(1) => MemArray_reg_0_3_102_107_n_4,
      DOC(0) => MemArray_reg_0_3_102_107_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_108_112: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(89 downto 88),
      DIB(1 downto 0) => I69(91 downto 90),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_108_112_n_0,
      DOA(0) => MemArray_reg_0_3_108_112_n_1,
      DOB(1) => MemArray_reg_0_3_108_112_n_2,
      DOB(0) => MemArray_reg_0_3_108_112_n_3,
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_108_112_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_112_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(11 downto 10),
      DIB(1 downto 0) => I69(13 downto 12),
      DIC(1 downto 0) => I69(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_12_17_n_0,
      DOA(0) => MemArray_reg_0_3_12_17_n_1,
      DOB(1) => MemArray_reg_0_3_12_17_n_2,
      DOB(0) => MemArray_reg_0_3_12_17_n_3,
      DOC(1) => MemArray_reg_0_3_12_17_n_4,
      DOC(0) => MemArray_reg_0_3_12_17_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(17 downto 16),
      DIB(1 downto 0) => I69(19 downto 18),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_18_23_n_0,
      DOA(0) => MemArray_reg_0_3_18_23_n_1,
      DOB(1) => MemArray_reg_0_3_18_23_n_2,
      DOB(0) => MemArray_reg_0_3_18_23_n_3,
      DOC(1) => MemArray_reg_0_3_18_23_n_4,
      DOC(0) => MemArray_reg_0_3_18_23_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(21 downto 20),
      DIB(1 downto 0) => I69(23 downto 22),
      DIC(1 downto 0) => I69(25 downto 24),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_36_41_n_0,
      DOA(0) => MemArray_reg_0_3_36_41_n_1,
      DOB(1) => MemArray_reg_0_3_36_41_n_2,
      DOB(0) => MemArray_reg_0_3_36_41_n_3,
      DOC(1) => MemArray_reg_0_3_36_41_n_4,
      DOC(0) => MemArray_reg_0_3_36_41_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => I69(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED(1 downto 0),
      DOB(1) => MemArray_reg_0_3_42_47_n_2,
      DOB(0) => NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED(0),
      DOC(1) => MemArray_reg_0_3_42_47_n_4,
      DOC(0) => MemArray_reg_0_3_42_47_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(29 downto 28),
      DIB(1 downto 0) => I69(31 downto 30),
      DIC(1 downto 0) => I69(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_48_53_n_0,
      DOA(0) => MemArray_reg_0_3_48_53_n_1,
      DOB(1) => MemArray_reg_0_3_48_53_n_2,
      DOB(0) => MemArray_reg_0_3_48_53_n_3,
      DOC(1) => MemArray_reg_0_3_48_53_n_4,
      DOC(0) => MemArray_reg_0_3_48_53_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(35 downto 34),
      DIB(1 downto 0) => I69(37 downto 36),
      DIC(1 downto 0) => I69(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_54_59_n_0,
      DOA(0) => MemArray_reg_0_3_54_59_n_1,
      DOB(1) => MemArray_reg_0_3_54_59_n_2,
      DOB(0) => MemArray_reg_0_3_54_59_n_3,
      DOC(1) => MemArray_reg_0_3_54_59_n_4,
      DOC(0) => MemArray_reg_0_3_54_59_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(41 downto 40),
      DIB(1 downto 0) => I69(43 downto 42),
      DIC(1 downto 0) => I69(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_60_65_n_0,
      DOA(0) => MemArray_reg_0_3_60_65_n_1,
      DOB(1) => MemArray_reg_0_3_60_65_n_2,
      DOB(0) => MemArray_reg_0_3_60_65_n_3,
      DOC(1) => MemArray_reg_0_3_60_65_n_4,
      DOC(0) => MemArray_reg_0_3_60_65_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(47 downto 46),
      DIB(1 downto 0) => I69(49 downto 48),
      DIC(1 downto 0) => I69(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_66_71_n_0,
      DOA(0) => MemArray_reg_0_3_66_71_n_1,
      DOB(1) => MemArray_reg_0_3_66_71_n_2,
      DOB(0) => MemArray_reg_0_3_66_71_n_3,
      DOC(1) => MemArray_reg_0_3_66_71_n_4,
      DOC(0) => MemArray_reg_0_3_66_71_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => I69(7 downto 6),
      DIC(1 downto 0) => I69(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED(1 downto 0),
      DOB(1) => MemArray_reg_0_3_6_11_n_2,
      DOB(0) => MemArray_reg_0_3_6_11_n_3,
      DOC(1) => MemArray_reg_0_3_6_11_n_4,
      DOC(0) => MemArray_reg_0_3_6_11_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(53 downto 52),
      DIB(1 downto 0) => I69(55 downto 54),
      DIC(1 downto 0) => I69(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_72_77_n_0,
      DOA(0) => MemArray_reg_0_3_72_77_n_1,
      DOB(1) => MemArray_reg_0_3_72_77_n_2,
      DOB(0) => MemArray_reg_0_3_72_77_n_3,
      DOC(1) => MemArray_reg_0_3_72_77_n_4,
      DOC(0) => MemArray_reg_0_3_72_77_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(59 downto 58),
      DIB(1 downto 0) => I69(61 downto 60),
      DIC(1 downto 0) => I69(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_78_83_n_0,
      DOA(0) => MemArray_reg_0_3_78_83_n_1,
      DOB(1) => MemArray_reg_0_3_78_83_n_2,
      DOB(0) => MemArray_reg_0_3_78_83_n_3,
      DOC(1) => MemArray_reg_0_3_78_83_n_4,
      DOC(0) => MemArray_reg_0_3_78_83_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(65 downto 64),
      DIB(1 downto 0) => I69(67 downto 66),
      DIC(1 downto 0) => I69(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_84_89_n_0,
      DOA(0) => MemArray_reg_0_3_84_89_n_1,
      DOB(1) => MemArray_reg_0_3_84_89_n_2,
      DOB(0) => MemArray_reg_0_3_84_89_n_3,
      DOC(1) => MemArray_reg_0_3_84_89_n_4,
      DOC(0) => MemArray_reg_0_3_84_89_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(71 downto 70),
      DIB(1 downto 0) => I69(73 downto 72),
      DIC(1 downto 0) => I69(75 downto 74),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_90_95_n_0,
      DOA(0) => MemArray_reg_0_3_90_95_n_1,
      DOB(1) => MemArray_reg_0_3_90_95_n_2,
      DOB(0) => MemArray_reg_0_3_90_95_n_3,
      DOC(1) => MemArray_reg_0_3_90_95_n_4,
      DOC(0) => MemArray_reg_0_3_90_95_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I69(77 downto 76),
      DIB(1 downto 0) => I69(79 downto 78),
      DIC(1 downto 0) => I69(81 downto 80),
      DID(1 downto 0) => B"00",
      DOA(1) => MemArray_reg_0_3_96_101_n_0,
      DOA(0) => MemArray_reg_0_3_96_101_n_1,
      DOB(1) => MemArray_reg_0_3_96_101_n_2,
      DOB(0) => MemArray_reg_0_3_96_101_n_3,
      DOC(1) => MemArray_reg_0_3_96_101_n_4,
      DOC(0) => MemArray_reg_0_3_96_101_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => p_15_in
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557777755544444"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \Head1__2_0\,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \FifoCntrWr_reg[0]_1\,
      I5 => RdPtr(0),
      O => \RdPtr[0]_i_1_n_0\
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"666F6F6F66606060"
    )
        port map (
      I0 => RdPtr(0),
      I1 => RdPtr(1),
      I2 => \Head1__2_0\,
      I3 => \RdPtr[1]_i_3__0_n_0\,
      I4 => \FifoCntrWr_reg[0]_1\,
      I5 => RdPtr(1),
      O => \RdPtr[1]_i_1_n_0\
    );
\RdPtr[1]_i_2__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000050001"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => \FifoCntrWr_reg[0]_1\,
      I5 => \^almost_full_ff_reg_0\,
      O => \Head1__2_0\
    );
\RdPtr[1]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(2),
      O => \RdPtr[1]_i_3__0_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1_n_0\,
      Q => RdPtr(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB01"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => WrPtr(0),
      I2 => \^almost_full_ff_reg_0\,
      I3 => WrPtr(0),
      O => \WrPtr[0]_i_1__18_n_0\
    );
\WrPtr[1]_i_1__18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBE0014"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => WrPtr(0),
      I2 => WrPtr(1),
      I3 => \^almost_full_ff_reg_0\,
      I4 => WrPtr(1),
      O => \WrPtr[1]_i_1__18_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__18_n_0\,
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__18_n_0\,
      Q => WrPtr(1),
      R => SR(0)
    );
\almost_full_ff_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => FifoCntrWr(1),
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(2),
      O => \almost_full_ff_i_1__2_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__2_n_0\,
      Q => \^almost_full_ff_reg_0\,
      R => SR(0)
    );
\empty_ff_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555555DF"
    )
        port map (
      I0 => empty_ff_reg_1(0),
      I1 => \FifoCntrWr_reg[0]_1\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(2),
      O => \empty_ff_i_1__8_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__8_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
m_axi_awaddrq_reg_0_15_0_5_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      O => arb_wrq_vld
    );
m_axi_awlenq_reg_0_15_0_5_i_11: unisim.vcomponents.CARRY4
     port map (
      CI => m_axi_awlenq_reg_0_15_0_5_i_8_n_0,
      CO(3) => m_axi_awlenq_reg_0_15_0_5_i_11_n_0,
      CO(2) => m_axi_awlenq_reg_0_15_0_5_i_11_n_1,
      CO(1) => m_axi_awlenq_reg_0_15_0_5_i_11_n_2,
      CO(0) => m_axi_awlenq_reg_0_15_0_5_i_11_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => m_axi_awlenq_reg_0_15_0_5_i_11_n_4,
      O(2 downto 0) => \Head_reg[20]_0\(2 downto 0),
      S(3 downto 0) => \^q\(16 downto 13)
    );
m_axi_awlenq_reg_0_15_0_5_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(7),
      I1 => \^q\(25),
      O => m_axi_awlenq_reg_0_15_0_5_i_13_n_0
    );
m_axi_awlenq_reg_0_15_0_5_i_14: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(6),
      I1 => \^q\(24),
      O => m_axi_awlenq_reg_0_15_0_5_i_14_n_0
    );
m_axi_awlenq_reg_0_15_0_5_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(23),
      O => m_axi_awlenq_reg_0_15_0_5_i_15_n_0
    );
m_axi_awlenq_reg_0_15_0_5_i_7: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => m_axi_awlenq_reg_0_15_0_5_i_7_n_0,
      CO(2) => m_axi_awlenq_reg_0_15_0_5_i_7_n_1,
      CO(1) => m_axi_awlenq_reg_0_15_0_5_i_7_n_2,
      CO(0) => m_axi_awlenq_reg_0_15_0_5_i_7_n_3,
      CYINIT => '0',
      DI(3 downto 0) => \^q\(8 downto 5),
      O(3 downto 0) => O(3 downto 0),
      S(3) => \^q\(8),
      S(2) => m_axi_awlenq_reg_0_15_0_5_i_13_n_0,
      S(1) => m_axi_awlenq_reg_0_15_0_5_i_14_n_0,
      S(0) => m_axi_awlenq_reg_0_15_0_5_i_15_n_0
    );
m_axi_awlenq_reg_0_15_0_5_i_8: unisim.vcomponents.CARRY4
     port map (
      CI => m_axi_awlenq_reg_0_15_0_5_i_7_n_0,
      CO(3) => m_axi_awlenq_reg_0_15_0_5_i_8_n_0,
      CO(2) => m_axi_awlenq_reg_0_15_0_5_i_8_n_1,
      CO(1) => m_axi_awlenq_reg_0_15_0_5_i_8_n_2,
      CO(0) => m_axi_awlenq_reg_0_15_0_5_i_8_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => \^q\(10 downto 9),
      O(3 downto 0) => \Head_reg[14]_0\(3 downto 0),
      S(3 downto 0) => \^q\(12 downto 9)
    );
m_axi_waddrlastq_reg_0_15_0_5_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(1),
      I1 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(0),
      O => DIA(1)
    );
m_axi_waddrlastq_reg_0_15_0_5_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(0),
      O => DIA(0)
    );
m_axi_waddrlastq_reg_0_15_0_5_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(2),
      I1 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(0),
      I2 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(1),
      O => DIB(1)
    );
m_axi_waddrlastq_reg_0_15_0_5_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(2),
      I1 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(0),
      I2 => \axi4mm_axi_mm_master_wr/p_0_in1_in\(1),
      O => DIB(0)
    );
m_axi_waddrlastq_reg_0_15_0_5_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => m_axi_waddrlastq_reg_0_15_0_5_i_5_n_0,
      CO(2) => m_axi_waddrlastq_reg_0_15_0_5_i_5_n_1,
      CO(1) => m_axi_waddrlastq_reg_0_15_0_5_i_5_n_2,
      CO(0) => m_axi_waddrlastq_reg_0_15_0_5_i_5_n_3,
      CYINIT => '0',
      DI(3 downto 0) => \^q\(26 downto 23),
      O(3 downto 0) => \axi4mm_axi_mm_master_wr/p_0_in1_in\(3 downto 0),
      S(3) => m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0,
      S(2) => m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0,
      S(1) => m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0,
      S(0) => m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0
    );
m_axi_waddrlastq_reg_0_15_0_5_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(26),
      I1 => \^q\(8),
      O => m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0
    );
m_axi_waddrlastq_reg_0_15_0_5_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(25),
      I1 => \^q\(7),
      O => m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0
    );
m_axi_waddrlastq_reg_0_15_0_5_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(24),
      I1 => \^q\(6),
      O => m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0
    );
m_axi_waddrlastq_reg_0_15_0_5_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(23),
      I1 => \^q\(5),
      O => m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized1\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    almost_full_ff : out STD_LOGIC;
    \wb_req_pnd_vec_ff_reg[1]\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wb_req_pnd_vec_ff_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    wbrq_gnt : out STD_LOGIC_VECTOR ( 0 to 0 );
    wb_win_vld : out STD_LOGIC;
    \Head_reg[32]_0\ : out STD_LOGIC_VECTOR ( 26 downto 0 );
    user_clk : in STD_LOGIC;
    FifoCntrRd : in STD_LOGIC;
    \WrPtr_reg[0]_0\ : in STD_LOGIC;
    \WrPtr_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wb_req_pnd_vec_ff_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wcp_rid_ff_0 : in STD_LOGIC;
    wcp_vld_ff : in STD_LOGIC;
    \c2h_xdma_wbrq_req[0][dat]\ : in STD_LOGIC_VECTOR ( 24 downto 0 );
    \h2c_xdma_wbrq_req[0][dat]\ : in STD_LOGIC_VECTOR ( 24 downto 0 );
    wb_dat_fl : in STD_LOGIC;
    wb_info_fl : in STD_LOGIC;
    c2h_xdma_wbrq_vld : in STD_LOGIC;
    \WrPtr_reg[0]_2\ : in STD_LOGIC;
    h2c_xdma_wbrq_vld : in STD_LOGIC;
    arbhist_ff : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized1\ : entity is "xdma_v4_1_8_GenericFIFOAsync";
end \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized1\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOAsync__parameterized1\ is
  signal \FifoCntrRd[0]_i_1__13_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__11_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__9_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__3_n_0\ : STD_LOGIC;
  signal FifoCntrRd_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__15_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__12_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__12_n_0\ : STD_LOGIC;
  signal Head0 : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal \Head[32]_i_1__3_n_0\ : STD_LOGIC;
  signal \Head[32]_i_3_n_0\ : STD_LOGIC;
  signal \MemArray_reg_0_3_0_5_i_1__2_n_0\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_2__7_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1_n_0\ : STD_LOGIC;
  signal \^almost_full_ff\ : STD_LOGIC;
  signal \almost_full_ff_i_1__6_n_0\ : STD_LOGIC;
  signal \empty_ff_i_1__15_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__7_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal payloadmuxed : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^wb_req_pnd_vec_ff_reg[1]\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_32_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_3_30_32_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_32_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__11\ : label is "soft_lutpair1389";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__3\ : label is "soft_lutpair1389";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__12\ : label is "soft_lutpair1388";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__12\ : label is "soft_lutpair1388";
  attribute SOFT_HLUTNM of \Head[30]_i_1__6\ : label is "soft_lutpair1390";
  attribute SOFT_HLUTNM of \Head[32]_i_2\ : label is "soft_lutpair1390";
  attribute SOFT_HLUTNM of \Head[32]_i_3\ : label is "soft_lutpair1387";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 132;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "axidma_wb_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 132;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "axidma_wb_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 132;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "axidma_wb_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_32 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_32 : label is 132;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_32 : label is "axidma_wb_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_32 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_32 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_32 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_32 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_32 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_32 : label is 32;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 132;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "axidma_wb_arb/Fifowhead.fifoInfo/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[1]_i_2__7\ : label is "soft_lutpair1387";
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \RdPtr_reg[1]\ : label is "128";
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__14\ : label is "soft_lutpair1391";
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__15\ : label is "soft_lutpair1391";
  attribute MAX_FANOUT of \WrPtr_reg[0]\ : label is "128";
  attribute MAX_FANOUT of \WrPtr_reg[1]\ : label is "128";
begin
  almost_full_ff <= \^almost_full_ff\;
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  \wb_req_pnd_vec_ff_reg[1]\ <= \^wb_req_pnd_vec_ff_reg[1]\;
\FifoCntrRd[0]_i_1__13\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd_0(0),
      O => \FifoCntrRd[0]_i_1__13_n_0\
    );
\FifoCntrRd[1]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"956A"
    )
        port map (
      I0 => FifoCntrRd_0(0),
      I1 => \^wb_req_pnd_vec_ff_reg[1]\,
      I2 => \WrPtr_reg[0]_0\,
      I3 => FifoCntrRd_0(1),
      O => \FifoCntrRd[1]_i_1__11_n_0\
    );
\FifoCntrRd[2]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77777778"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^wb_req_pnd_vec_ff_reg[1]\,
      I2 => wb_dat_fl,
      I3 => wb_info_fl,
      I4 => \^empty_ff_reg_0\,
      O => \FifoCntrRd[2]_i_1__9_n_0\
    );
\FifoCntrRd[2]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"95AAAA6A"
    )
        port map (
      I0 => FifoCntrRd_0(2),
      I1 => \^wb_req_pnd_vec_ff_reg[1]\,
      I2 => \WrPtr_reg[0]_0\,
      I3 => FifoCntrRd_0(1),
      I4 => FifoCntrRd_0(0),
      O => \FifoCntrRd[2]_i_2__3_n_0\
    );
\FifoCntrRd[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFBFFFBFBFBFBFB"
    )
        port map (
      I0 => \wb_req_pnd_vec_ff_reg[1]_1\(1),
      I1 => c2h_xdma_wbrq_vld,
      I2 => \^almost_full_ff\,
      I3 => \WrPtr_reg[0]_2\,
      I4 => \wb_req_pnd_vec_ff_reg[1]_1\(0),
      I5 => h2c_xdma_wbrq_vld,
      O => \^wb_req_pnd_vec_ff_reg[1]\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrRd[0]_i_1__13_n_0\,
      Q => FifoCntrRd_0(0),
      R => FifoCntrRd
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrRd[1]_i_1__11_n_0\,
      Q => FifoCntrRd_0(1),
      R => FifoCntrRd
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrRd[2]_i_2__3_n_0\,
      Q => FifoCntrRd_0(2),
      R => FifoCntrRd
    );
\FifoCntrWr[0]_i_1__15\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__15_n_0\
    );
\FifoCntrWr[1]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \WrPtr_reg[0]_0\,
      I1 => \^wb_req_pnd_vec_ff_reg[1]\,
      I2 => FifoCntrWr(1),
      I3 => FifoCntrWr(0),
      O => \FifoCntrWr[1]_i_1__12_n_0\
    );
\FifoCntrWr[2]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A96A6A6A"
    )
        port map (
      I0 => FifoCntrWr(2),
      I1 => FifoCntrWr(1),
      I2 => FifoCntrWr(0),
      I3 => \WrPtr_reg[0]_0\,
      I4 => \^wb_req_pnd_vec_ff_reg[1]\,
      O => \FifoCntrWr[2]_i_1__12_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrWr[0]_i_1__15_n_0\,
      Q => FifoCntrWr(0),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrWr[1]_i_1__12_n_0\,
      Q => FifoCntrWr(1),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__9_n_0\,
      D => \FifoCntrWr[2]_i_1__12_n_0\,
      Q => FifoCntrWr(2),
      R => FifoCntrRd
    );
\Head[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(0),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(0),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(0),
      O => p_0_in1_in(0)
    );
\Head[10]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(10),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(10),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(10),
      O => p_0_in1_in(10)
    );
\Head[11]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(11),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(11),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(11),
      O => p_0_in1_in(11)
    );
\Head[12]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(12),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(12),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(12),
      O => p_0_in1_in(12)
    );
\Head[13]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(13),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(13),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(13),
      O => p_0_in1_in(13)
    );
\Head[14]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(14),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(14),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(14),
      O => p_0_in1_in(14)
    );
\Head[15]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(15),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(15),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(15),
      O => p_0_in1_in(15)
    );
\Head[16]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(16),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(16),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(16),
      O => p_0_in1_in(16)
    );
\Head[17]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(17),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(17),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(17),
      O => p_0_in1_in(17)
    );
\Head[18]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(18),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(18),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(18),
      O => p_0_in1_in(18)
    );
\Head[19]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(19),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(19),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(19),
      O => p_0_in1_in(19)
    );
\Head[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(1),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(1),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(1),
      O => p_0_in1_in(1)
    );
\Head[20]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(20),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(20),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(20),
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(21),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(21),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(21),
      O => p_0_in1_in(21)
    );
\Head[22]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(22),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(22),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(22),
      O => p_0_in1_in(22)
    );
\Head[23]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(23),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(23),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(23),
      O => p_0_in1_in(23)
    );
\Head[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(2),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(2),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(2),
      O => p_0_in1_in(2)
    );
\Head[30]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Head[32]_i_3_n_0\,
      I1 => Head0(30),
      O => p_0_in1_in(30)
    );
\Head[31]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(31),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(24),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(24),
      O => p_0_in1_in(31)
    );
\Head[32]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01010101010101FF"
    )
        port map (
      I0 => FifoCntrRd_0(0),
      I1 => FifoCntrRd_0(1),
      I2 => FifoCntrRd_0(2),
      I3 => \^empty_ff_reg_0\,
      I4 => wb_info_fl,
      I5 => wb_dat_fl,
      O => \Head[32]_i_1__3_n_0\
    );
\Head[32]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => Head0(32),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      O => p_0_in1_in(32)
    );
\Head[32]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEFE"
    )
        port map (
      I0 => \RdPtr[0]_i_2__0_n_0\,
      I1 => FifoCntrRd_0(2),
      I2 => FifoCntrRd_0(1),
      I3 => \WrPtr_reg[0]_0\,
      I4 => \^wb_req_pnd_vec_ff_reg[1]\,
      O => \Head[32]_i_3_n_0\
    );
\Head[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(3),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(3),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(3),
      O => p_0_in1_in(3)
    );
\Head[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(4),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(4),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(4),
      O => p_0_in1_in(4)
    );
\Head[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(5),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(5),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(5),
      O => p_0_in1_in(5)
    );
\Head[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(6),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(6),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(6),
      O => p_0_in1_in(6)
    );
\Head[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(7),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(7),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(7),
      O => p_0_in1_in(7)
    );
\Head[8]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(8),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(8),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(8),
      O => p_0_in1_in(8)
    );
\Head[9]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B88BBBB8B888B88"
    )
        port map (
      I0 => Head0(9),
      I1 => \Head[32]_i_3_n_0\,
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \c2h_xdma_wbrq_req[0][dat]\(9),
      I4 => \WrPtr_reg[0]_0\,
      I5 => \h2c_xdma_wbrq_req[0][dat]\(9),
      O => p_0_in1_in(9)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(0),
      Q => \Head_reg[32]_0\(0),
      R => FifoCntrRd
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(10),
      Q => \Head_reg[32]_0\(10),
      R => FifoCntrRd
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(11),
      Q => \Head_reg[32]_0\(11),
      R => FifoCntrRd
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(12),
      Q => \Head_reg[32]_0\(12),
      R => FifoCntrRd
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(13),
      Q => \Head_reg[32]_0\(13),
      R => FifoCntrRd
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(14),
      Q => \Head_reg[32]_0\(14),
      R => FifoCntrRd
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(15),
      Q => \Head_reg[32]_0\(15),
      R => FifoCntrRd
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(16),
      Q => \Head_reg[32]_0\(16),
      R => FifoCntrRd
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(17),
      Q => \Head_reg[32]_0\(17),
      R => FifoCntrRd
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(18),
      Q => \Head_reg[32]_0\(18),
      R => FifoCntrRd
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(19),
      Q => \Head_reg[32]_0\(19),
      R => FifoCntrRd
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(1),
      Q => \Head_reg[32]_0\(1),
      R => FifoCntrRd
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(20),
      Q => \Head_reg[32]_0\(20),
      R => FifoCntrRd
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(21),
      Q => \Head_reg[32]_0\(21),
      R => FifoCntrRd
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(22),
      Q => \Head_reg[32]_0\(22),
      R => FifoCntrRd
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(23),
      Q => \Head_reg[32]_0\(23),
      R => FifoCntrRd
    );
\Head_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(2),
      Q => \Head_reg[32]_0\(2),
      R => FifoCntrRd
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(30),
      Q => \Head_reg[32]_0\(24),
      R => FifoCntrRd
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(31),
      Q => \Head_reg[32]_0\(25),
      R => FifoCntrRd
    );
\Head_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(32),
      Q => \Head_reg[32]_0\(26),
      R => FifoCntrRd
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(3),
      Q => \Head_reg[32]_0\(3),
      R => FifoCntrRd
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(4),
      Q => \Head_reg[32]_0\(4),
      R => FifoCntrRd
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(5),
      Q => \Head_reg[32]_0\(5),
      R => FifoCntrRd
    );
\Head_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(6),
      Q => \Head_reg[32]_0\(6),
      R => FifoCntrRd
    );
\Head_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(7),
      Q => \Head_reg[32]_0\(7),
      R => FifoCntrRd
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(8),
      Q => \Head_reg[32]_0\(8),
      R => FifoCntrRd
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[32]_i_1__3_n_0\,
      D => p_0_in1_in(9),
      Q => \Head_reg[32]_0\(9),
      R => FifoCntrRd
    );
MemArray_reg_0_3_0_0_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      O => wb_win_vld
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadmuxed(1 downto 0),
      DIB(1 downto 0) => payloadmuxed(3 downto 2),
      DIC(1 downto 0) => payloadmuxed(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(1 downto 0),
      DOB(1 downto 0) => Head0(3 downto 2),
      DOC(1 downto 0) => Head0(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
\MemArray_reg_0_3_0_5_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \WrPtr_reg[0]_0\,
      O => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
\MemArray_reg_0_3_0_5_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(1),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(1),
      O => payloadmuxed(1)
    );
\MemArray_reg_0_3_0_5_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(0),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(0),
      O => payloadmuxed(0)
    );
\MemArray_reg_0_3_0_5_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(3),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(3),
      O => payloadmuxed(3)
    );
\MemArray_reg_0_3_0_5_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(2),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(2),
      O => payloadmuxed(2)
    );
\MemArray_reg_0_3_0_5_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(5),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(5),
      O => payloadmuxed(5)
    );
\MemArray_reg_0_3_0_5_i_7__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(4),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(4),
      O => payloadmuxed(4)
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadmuxed(13 downto 12),
      DIB(1 downto 0) => payloadmuxed(15 downto 14),
      DIC(1 downto 0) => payloadmuxed(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => Head0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
\MemArray_reg_0_3_12_17_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(13),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(13),
      O => payloadmuxed(13)
    );
\MemArray_reg_0_3_12_17_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(12),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(12),
      O => payloadmuxed(12)
    );
\MemArray_reg_0_3_12_17_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(15),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(15),
      O => payloadmuxed(15)
    );
\MemArray_reg_0_3_12_17_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(14),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(14),
      O => payloadmuxed(14)
    );
\MemArray_reg_0_3_12_17_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(17),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(17),
      O => payloadmuxed(17)
    );
\MemArray_reg_0_3_12_17_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(16),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(16),
      O => payloadmuxed(16)
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadmuxed(19 downto 18),
      DIB(1 downto 0) => payloadmuxed(21 downto 20),
      DIC(1 downto 0) => payloadmuxed(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
MemArray_reg_0_3_18_23_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(19),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(19),
      O => payloadmuxed(19)
    );
MemArray_reg_0_3_18_23_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(18),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(18),
      O => payloadmuxed(18)
    );
\MemArray_reg_0_3_18_23_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(21),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(21),
      O => payloadmuxed(21)
    );
\MemArray_reg_0_3_18_23_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(20),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(20),
      O => payloadmuxed(20)
    );
\MemArray_reg_0_3_18_23_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(23),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(23),
      O => payloadmuxed(23)
    );
\MemArray_reg_0_3_18_23_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(22),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(22),
      O => payloadmuxed(22)
    );
MemArray_reg_0_3_30_32: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1) => payloadmuxed(31),
      DIA(0) => '0',
      DIB(1) => '0',
      DIB(0) => \Head_reg[31]_0\(0),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(31 downto 30),
      DOB(1) => NLW_MemArray_reg_0_3_30_32_DOB_UNCONNECTED(1),
      DOB(0) => Head0(32),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_30_32_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_32_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
MemArray_reg_0_3_30_32_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(24),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(24),
      O => payloadmuxed(31)
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => payloadmuxed(7 downto 6),
      DIB(1 downto 0) => payloadmuxed(9 downto 8),
      DIC(1 downto 0) => payloadmuxed(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(7 downto 6),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \MemArray_reg_0_3_0_5_i_1__2_n_0\
    );
\MemArray_reg_0_3_6_11_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(7),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(7),
      O => payloadmuxed(7)
    );
\MemArray_reg_0_3_6_11_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(6),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(6),
      O => payloadmuxed(6)
    );
\MemArray_reg_0_3_6_11_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(9),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(9),
      O => payloadmuxed(9)
    );
\MemArray_reg_0_3_6_11_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(8),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(8),
      O => payloadmuxed(8)
    );
\MemArray_reg_0_3_6_11_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(11),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(11),
      O => payloadmuxed(11)
    );
\MemArray_reg_0_3_6_11_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \c2h_xdma_wbrq_req[0][dat]\(10),
      I2 => \WrPtr_reg[0]_0\,
      I3 => \h2c_xdma_wbrq_req[0][dat]\(10),
      O => payloadmuxed(10)
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDDDF11111110"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \RdPtr[0]_i_2__0_n_0\,
      I2 => FifoCntrRd_0(2),
      I3 => FifoCntrRd_0(1),
      I4 => \MemArray_reg_0_3_0_5_i_1__2_n_0\,
      I5 => RdPtr(0),
      O => \RdPtr[0]_i_1_n_0\
    );
\RdPtr[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFEFEFEFE00"
    )
        port map (
      I0 => wb_dat_fl,
      I1 => wb_info_fl,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd_0(2),
      I4 => FifoCntrRd_0(1),
      I5 => FifoCntrRd_0(0),
      O => \RdPtr[0]_i_2__0_n_0\
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6F60"
    )
        port map (
      I0 => RdPtr(0),
      I1 => RdPtr(1),
      I2 => \RdPtr[1]_i_2__7_n_0\,
      I3 => RdPtr(1),
      O => \RdPtr[1]_i_1_n_0\
    );
\RdPtr[1]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54555555"
    )
        port map (
      I0 => \RdPtr[0]_i_2__0_n_0\,
      I1 => FifoCntrRd_0(2),
      I2 => FifoCntrRd_0(1),
      I3 => \^wb_req_pnd_vec_ff_reg[1]\,
      I4 => \WrPtr_reg[0]_0\,
      O => \RdPtr[1]_i_2__7_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1_n_0\,
      Q => RdPtr(0),
      R => FifoCntrRd
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1_n_0\,
      Q => RdPtr(1),
      R => FifoCntrRd
    );
\WrPtr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D515"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \^wb_req_pnd_vec_ff_reg[1]\,
      I2 => \WrPtr_reg[0]_0\,
      I3 => WrPtr(0),
      O => \WrPtr[0]_i_1_n_0\
    );
\WrPtr[0]_i_1__14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \WrPtr_reg[0]_1\(0),
      O => D(0)
    );
\WrPtr[0]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => Q(0),
      O => empty_ff_reg_1(0)
    );
\WrPtr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F6660666"
    )
        port map (
      I0 => WrPtr(0),
      I1 => WrPtr(1),
      I2 => \^wb_req_pnd_vec_ff_reg[1]\,
      I3 => \WrPtr_reg[0]_0\,
      I4 => WrPtr(1),
      O => \WrPtr[1]_i_1_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1_n_0\,
      Q => WrPtr(0),
      R => FifoCntrRd
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1_n_0\,
      Q => WrPtr(1),
      R => FifoCntrRd
    );
\almost_full_ff_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => FifoCntrWr(2),
      I1 => FifoCntrWr(1),
      I2 => FifoCntrWr(0),
      O => \almost_full_ff_i_1__6_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__6_n_0\,
      Q => \^almost_full_ff\,
      R => FifoCntrRd
    );
\empty_ff_i_1__15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F010FFFFFFFFF"
    )
        port map (
      I0 => wb_dat_fl,
      I1 => wb_info_fl,
      I2 => \empty_ff_i_2__7_n_0\,
      I3 => FifoCntrRd_0(0),
      I4 => \^empty_ff_reg_0\,
      I5 => empty_ff_reg_2(0),
      O => \empty_ff_i_1__15_n_0\
    );
\empty_ff_i_2__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => FifoCntrRd_0(2),
      I1 => FifoCntrRd_0(1),
      O => \empty_ff_i_2__7_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__15_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
\wb_req_pnd_vec_ff[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5DDD"
    )
        port map (
      I0 => \^wb_req_pnd_vec_ff_reg[1]\,
      I1 => \wb_req_pnd_vec_ff_reg[1]_1\(1),
      I2 => wcp_rid_ff_0,
      I3 => wcp_vld_ff,
      O => \wb_req_pnd_vec_ff_reg[1]_0\(0)
    );
wbrq_vld_nn1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404040400040404"
    )
        port map (
      I0 => \^almost_full_ff\,
      I1 => h2c_xdma_wbrq_vld,
      I2 => \wb_req_pnd_vec_ff_reg[1]_1\(0),
      I3 => arbhist_ff(0),
      I4 => c2h_xdma_wbrq_vld,
      I5 => \wb_req_pnd_vec_ff_reg[1]_1\(1),
      O => wbrq_gnt(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFOHead is
  port (
    wpl_ld : out STD_LOGIC;
    \wrreq_cnt_ff_reg[4]\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \WrPtr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    wpl_vld_nxt : out STD_LOGIC;
    wtlp_srcbt_noinc : out STD_LOGIC;
    wtlp_dstbt_whole_len1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    wtlp_srcbt_whole_len1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    \Head_reg[34]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Head0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \awstrptr_ff_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \awstrptr_ff_reg[0]_0\ : in STD_LOGIC;
    wpl_vld_ff : in STD_LOGIC;
    wtlp_sm_500 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wtlp_dat_fifo_af_nn1 : in STD_LOGIC;
    \Head_reg[34]_1\ : in STD_LOGIC_VECTOR ( 22 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFOHead : entity is "xdma_v4_1_8_GenericFIFOHead";
end xdma_0_xdma_v4_1_8_GenericFIFOHead;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFOHead is
  signal \FifoCntrRd[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[4]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[4]_i_2_n_0\ : STD_LOGIC;
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^fifocntrrd_reg[0]_0\ : STD_LOGIC;
  signal \Head[34]_i_1__1_n_0\ : STD_LOGIC;
  signal \^head_reg[34]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \Head_reg_n_0_[1]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \RdPtr1__1\ : STD_LOGIC;
  signal \RdPtr[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \RdPtr[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \RdPtr[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \RdPtr[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \RdPtr[3]_i_1_n_0\ : STD_LOGIC;
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^wrptr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \empty_ff_i_1__6_n_0\ : STD_LOGIC;
  signal empty_ff_reg_n_0 : STD_LOGIC;
  signal \p_0_in1_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wpl_bytelen : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^wpl_ld\ : STD_LOGIC;
  signal \^wrreq_cnt_ff_reg[4]\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff[2]_i_3_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff[2]_i_4_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff[2]_i_5_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[8]_i_3_n_0\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[8]_i_3_n_1\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[8]_i_3_n_2\ : STD_LOGIC;
  signal \wtlp_dstbt_len_ff_reg[8]_i_3_n_3\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff[2]_i_3_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff[2]_i_4_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff[2]_i_5_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[2]_i_2_n_1\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[2]_i_2_n_2\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[2]_i_2_n_3\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \wtlp_srcbt_len_ff_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_i_3_n_0 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_i_4_n_0 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_i_5_n_0 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_0 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_1 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_2 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_3 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_4 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_5 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_6 : STD_LOGIC;
  signal wtlp_srcbt_noinc_ff_reg_i_2_n_7 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__5\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_1__6\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \FifoCntrRd[3]_i_1__1\ : label is "soft_lutpair415";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_2__1\ : label is "soft_lutpair414";
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__6\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__6\ : label is "soft_lutpair417";
  attribute SOFT_HLUTNM of \WrPtr[2]_i_1__1\ : label is "soft_lutpair416";
  attribute SOFT_HLUTNM of \WrPtr[3]_i_1\ : label is "soft_lutpair416";
begin
  \FifoCntrRd_reg[0]_0\ <= \^fifocntrrd_reg[0]_0\;
  \Head_reg[34]_0\(10 downto 0) <= \^head_reg[34]_0\(10 downto 0);
  Q(3 downto 0) <= \^q\(3 downto 0);
  SR(0) <= \^sr\(0);
  \WrPtr_reg[3]_0\(3 downto 0) <= \^wrptr_reg[3]_0\(3 downto 0);
  wpl_ld <= \^wpl_ld\;
  \wrreq_cnt_ff_reg[4]\ <= \^wrreq_cnt_ff_reg[4]\;
\FifoCntrRd[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd_reg(0),
      O => \FifoCntrRd[0]_i_1__5_n_0\
    );
\FifoCntrRd[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \^wrreq_cnt_ff_reg[4]\,
      I1 => FifoCntrRd_reg(1),
      I2 => FifoCntrRd_reg(0),
      O => \FifoCntrRd[1]_i_1__5_n_0\
    );
\FifoCntrRd[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => \^wrreq_cnt_ff_reg[4]\,
      I1 => FifoCntrRd_reg(1),
      I2 => FifoCntrRd_reg(2),
      I3 => FifoCntrRd_reg(0),
      O => \FifoCntrRd[2]_i_1__6_n_0\
    );
\FifoCntrRd[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => FifoCntrRd_reg(0),
      I2 => FifoCntrRd_reg(1),
      I3 => \^wrreq_cnt_ff_reg[4]\,
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrRd[3]_i_1__1_n_0\
    );
\FifoCntrRd[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => empty_ff_reg_n_0,
      I1 => \^wpl_ld\,
      I2 => \^wrreq_cnt_ff_reg[4]\,
      O => \FifoCntrRd[4]_i_1_n_0\
    );
\FifoCntrRd[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"78F0F0F0F0F0F0E1"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(4),
      I3 => FifoCntrRd_reg(0),
      I4 => FifoCntrRd_reg(1),
      I5 => \^wrreq_cnt_ff_reg[4]\,
      O => \FifoCntrRd[4]_i_2_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[4]_i_1_n_0\,
      D => \FifoCntrRd[0]_i_1__5_n_0\,
      Q => FifoCntrRd_reg(0),
      R => \^sr\(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[4]_i_1_n_0\,
      D => \FifoCntrRd[1]_i_1__5_n_0\,
      Q => FifoCntrRd_reg(1),
      R => \^sr\(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[4]_i_1_n_0\,
      D => \FifoCntrRd[2]_i_1__6_n_0\,
      Q => FifoCntrRd_reg(2),
      R => \^sr\(0)
    );
\FifoCntrRd_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[4]_i_1_n_0\,
      D => \FifoCntrRd[3]_i_1__1_n_0\,
      Q => FifoCntrRd_reg(3),
      R => \^sr\(0)
    );
\FifoCntrRd_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[4]_i_1_n_0\,
      D => \FifoCntrRd[4]_i_2_n_0\,
      Q => FifoCntrRd_reg(4),
      R => \^sr\(0)
    );
\Head[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(0),
      I1 => \^fifocntrrd_reg[0]_0\,
      O => \p_0_in1_in__0\(0)
    );
\Head[34]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"222F"
    )
        port map (
      I0 => \^wpl_ld\,
      I1 => empty_ff_reg_n_0,
      I2 => FifoCntrRd_reg(0),
      I3 => \RdPtr[2]_i_4__1_n_0\,
      O => \Head[34]_i_1__1_n_0\
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \p_0_in1_in__0\(0),
      Q => \^head_reg[34]_0\(0),
      R => \^sr\(0)
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(1),
      Q => wpl_bytelen(0),
      R => \^sr\(0)
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(2),
      Q => wpl_bytelen(1),
      R => \^sr\(0)
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(3),
      Q => wpl_bytelen(2),
      R => \^sr\(0)
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(4),
      Q => wpl_bytelen(3),
      R => \^sr\(0)
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(5),
      Q => wpl_bytelen(4),
      R => \^sr\(0)
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(6),
      Q => wpl_bytelen(5),
      R => \^sr\(0)
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(7),
      Q => wpl_bytelen(6),
      R => \^sr\(0)
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(8),
      Q => wpl_bytelen(7),
      R => \^sr\(0)
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(9),
      Q => wpl_bytelen(8),
      R => \^sr\(0)
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(10),
      Q => wpl_bytelen(9),
      R => \^sr\(0)
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(0),
      Q => \Head_reg_n_0_[1]\,
      R => \^sr\(0)
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(11),
      Q => wpl_bytelen(10),
      R => \^sr\(0)
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(12),
      Q => wpl_bytelen(11),
      R => \^sr\(0)
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(13),
      Q => \^head_reg[34]_0\(1),
      R => \^sr\(0)
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(14),
      Q => \^head_reg[34]_0\(2),
      R => \^sr\(0)
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(15),
      Q => \^head_reg[34]_0\(3),
      R => \^sr\(0)
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(16),
      Q => \^head_reg[34]_0\(4),
      R => \^sr\(0)
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(17),
      Q => \^head_reg[34]_0\(5),
      R => \^sr\(0)
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(18),
      Q => \^head_reg[34]_0\(6),
      R => \^sr\(0)
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(19),
      Q => \^head_reg[34]_0\(7),
      R => \^sr\(0)
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(20),
      Q => \^head_reg[34]_0\(8),
      R => \^sr\(0)
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(21),
      Q => \^head_reg[34]_0\(9),
      R => \^sr\(0)
    );
\Head_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[34]_i_1__1_n_0\,
      D => \Head_reg[34]_1\(22),
      Q => \^head_reg[34]_0\(10),
      R => \^sr\(0)
    );
MemArray_reg_0_15_0_5_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001010101010101"
    )
        port map (
      I0 => \awstrptr_ff_reg[0]\(3),
      I1 => \awstrptr_ff_reg[0]\(4),
      I2 => \awstrptr_ff_reg[0]_0\,
      I3 => \awstrptr_ff_reg[0]\(2),
      I4 => \awstrptr_ff_reg[0]\(0),
      I5 => \awstrptr_ff_reg[0]\(1),
      O => \^wrreq_cnt_ff_reg[4]\
    );
\RdPtr[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFB11FB0404EE04"
    )
        port map (
      I0 => \RdPtr[2]_i_4__1_n_0\,
      I1 => \^wrreq_cnt_ff_reg[4]\,
      I2 => FifoCntrRd_reg(0),
      I3 => \^wpl_ld\,
      I4 => empty_ff_reg_n_0,
      I5 => \^q\(0),
      O => \RdPtr[0]_i_1__5_n_0\
    );
\RdPtr[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555FF7FAAAA0080"
    )
        port map (
      I0 => \^q\(0),
      I1 => \RdPtr[2]_i_4__1_n_0\,
      I2 => \^wpl_ld\,
      I3 => empty_ff_reg_n_0,
      I4 => \^fifocntrrd_reg[0]_0\,
      I5 => \^q\(1),
      O => \RdPtr[1]_i_1__6_n_0\
    );
\RdPtr[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5777FFFFA8880000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^fifocntrrd_reg[0]_0\,
      I2 => \RdPtr[2]_i_3__1_n_0\,
      I3 => \RdPtr[2]_i_4__1_n_0\,
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \RdPtr[2]_i_1__1_n_0\
    );
\RdPtr[2]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04044404"
    )
        port map (
      I0 => \RdPtr[2]_i_4__1_n_0\,
      I1 => \^wrreq_cnt_ff_reg[4]\,
      I2 => FifoCntrRd_reg(0),
      I3 => \^wpl_ld\,
      I4 => empty_ff_reg_n_0,
      O => \^fifocntrrd_reg[0]_0\
    );
\RdPtr[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000005555555D"
    )
        port map (
      I0 => wpl_vld_ff,
      I1 => wtlp_sm_500(0),
      I2 => wtlp_dat_fifo_af_nn1,
      I3 => wtlp_sm_500(2),
      I4 => wtlp_sm_500(1),
      I5 => empty_ff_reg_n_0,
      O => \RdPtr[2]_i_3__1_n_0\
    );
\RdPtr[2]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => FifoCntrRd_reg(4),
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => FifoCntrRd_reg(1),
      O => \RdPtr[2]_i_4__1_n_0\
    );
\RdPtr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \RdPtr1__1\,
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \RdPtr[3]_i_1_n_0\
    );
\RdPtr[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFE0000"
    )
        port map (
      I0 => FifoCntrRd_reg(4),
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => FifoCntrRd_reg(1),
      I4 => \RdPtr[2]_i_3__1_n_0\,
      I5 => \^fifocntrrd_reg[0]_0\,
      O => \RdPtr1__1\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__5_n_0\,
      Q => \^q\(0),
      R => \^sr\(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__6_n_0\,
      Q => \^q\(1),
      R => \^sr\(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[2]_i_1__1_n_0\,
      Q => \^q\(2),
      R => \^sr\(0)
    );
\RdPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[3]_i_1_n_0\,
      Q => \^q\(3),
      R => \^sr\(0)
    );
\WrPtr[0]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^wrptr_reg[3]_0\(0),
      I1 => \^wrreq_cnt_ff_reg[4]\,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^wrreq_cnt_ff_reg[4]\,
      I1 => \^wrptr_reg[3]_0\(0),
      I2 => \^wrptr_reg[3]_0\(1),
      O => \WrPtr__0\(1)
    );
\WrPtr[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^wrptr_reg[3]_0\(1),
      I1 => \^wrptr_reg[3]_0\(0),
      I2 => \^wrreq_cnt_ff_reg[4]\,
      I3 => \^wrptr_reg[3]_0\(2),
      O => \WrPtr__0\(2)
    );
\WrPtr[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^wrptr_reg[3]_0\(2),
      I1 => \^wrreq_cnt_ff_reg[4]\,
      I2 => \^wrptr_reg[3]_0\(0),
      I3 => \^wrptr_reg[3]_0\(1),
      I4 => \^wrptr_reg[3]_0\(3),
      O => \WrPtr__0\(3)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => \^wrptr_reg[3]_0\(0),
      R => \^sr\(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => \^wrptr_reg[3]_0\(1),
      R => \^sr\(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => \^wrptr_reg[3]_0\(2),
      R => \^sr\(0)
    );
\WrPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(3),
      Q => \^wrptr_reg[3]_0\(3),
      R => \^sr\(0)
    );
\empty_ff_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"57557777"
    )
        port map (
      I0 => empty_ff_reg_0(0),
      I1 => \RdPtr[2]_i_4__1_n_0\,
      I2 => empty_ff_reg_n_0,
      I3 => \^wpl_ld\,
      I4 => FifoCntrRd_reg(0),
      O => \empty_ff_i_1__6_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__6_n_0\,
      Q => empty_ff_reg_n_0,
      R => '0'
    );
\r_write_ptr[8]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => empty_ff_reg_0(0),
      O => \^sr\(0)
    );
wpl_vld_ff_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA2FFFFFFFF"
    )
        port map (
      I0 => wpl_vld_ff,
      I1 => wtlp_sm_500(0),
      I2 => wtlp_dat_fifo_af_nn1,
      I3 => wtlp_sm_500(2),
      I4 => wtlp_sm_500(1),
      I5 => empty_ff_reg_n_0,
      O => wpl_vld_nxt
    );
\wtlp_dstbt_len_ff[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(2),
      I1 => \^head_reg[34]_0\(3),
      O => \wtlp_dstbt_len_ff[2]_i_3_n_0\
    );
\wtlp_dstbt_len_ff[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(1),
      I1 => \^head_reg[34]_0\(2),
      O => \wtlp_dstbt_len_ff[2]_i_4_n_0\
    );
\wtlp_dstbt_len_ff[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(0),
      I1 => \^head_reg[34]_0\(1),
      O => \wtlp_dstbt_len_ff[2]_i_5_n_0\
    );
\wtlp_dstbt_len_ff[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0100FFFF"
    )
        port map (
      I0 => wtlp_sm_500(1),
      I1 => wtlp_sm_500(2),
      I2 => wtlp_dat_fifo_af_nn1,
      I3 => wtlp_sm_500(0),
      I4 => wpl_vld_ff,
      O => \^wpl_ld\
    );
\wtlp_dstbt_len_ff_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wtlp_dstbt_len_ff_reg[2]_i_2_n_0\,
      CO(2) => \wtlp_dstbt_len_ff_reg[2]_i_2_n_1\,
      CO(1) => \wtlp_dstbt_len_ff_reg[2]_i_2_n_2\,
      CO(0) => \wtlp_dstbt_len_ff_reg[2]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => wpl_bytelen(3 downto 0),
      O(3 downto 0) => wtlp_dstbt_whole_len1(3 downto 0),
      S(3) => wpl_bytelen(3),
      S(2) => \wtlp_dstbt_len_ff[2]_i_3_n_0\,
      S(1) => \wtlp_dstbt_len_ff[2]_i_4_n_0\,
      S(0) => \wtlp_dstbt_len_ff[2]_i_5_n_0\
    );
\wtlp_dstbt_len_ff_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wtlp_dstbt_len_ff_reg[2]_i_2_n_0\,
      CO(3) => \wtlp_dstbt_len_ff_reg[7]_i_2_n_0\,
      CO(2) => \wtlp_dstbt_len_ff_reg[7]_i_2_n_1\,
      CO(1) => \wtlp_dstbt_len_ff_reg[7]_i_2_n_2\,
      CO(0) => \wtlp_dstbt_len_ff_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => wpl_bytelen(5 downto 4),
      O(3 downto 0) => wtlp_dstbt_whole_len1(7 downto 4),
      S(3 downto 0) => wpl_bytelen(7 downto 4)
    );
\wtlp_dstbt_len_ff_reg[8]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \wtlp_dstbt_len_ff_reg[7]_i_2_n_0\,
      CO(3) => \wtlp_dstbt_len_ff_reg[8]_i_3_n_0\,
      CO(2) => \wtlp_dstbt_len_ff_reg[8]_i_3_n_1\,
      CO(1) => \wtlp_dstbt_len_ff_reg[8]_i_3_n_2\,
      CO(0) => \wtlp_dstbt_len_ff_reg[8]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => wtlp_dstbt_whole_len1(11 downto 8),
      S(3 downto 0) => wpl_bytelen(11 downto 8)
    );
\wtlp_srcbt_len_ff[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(2),
      I1 => \^head_reg[34]_0\(9),
      O => \wtlp_srcbt_len_ff[2]_i_3_n_0\
    );
\wtlp_srcbt_len_ff[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(1),
      I1 => \^head_reg[34]_0\(8),
      O => \wtlp_srcbt_len_ff[2]_i_4_n_0\
    );
\wtlp_srcbt_len_ff[2]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_bytelen(0),
      I1 => \^head_reg[34]_0\(7),
      O => \wtlp_srcbt_len_ff[2]_i_5_n_0\
    );
\wtlp_srcbt_len_ff_reg[2]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wtlp_srcbt_len_ff_reg[2]_i_2_n_0\,
      CO(2) => \wtlp_srcbt_len_ff_reg[2]_i_2_n_1\,
      CO(1) => \wtlp_srcbt_len_ff_reg[2]_i_2_n_2\,
      CO(0) => \wtlp_srcbt_len_ff_reg[2]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => wpl_bytelen(3 downto 0),
      O(3 downto 0) => wtlp_srcbt_whole_len1(3 downto 0),
      S(3) => wpl_bytelen(3),
      S(2) => \wtlp_srcbt_len_ff[2]_i_3_n_0\,
      S(1) => \wtlp_srcbt_len_ff[2]_i_4_n_0\,
      S(0) => \wtlp_srcbt_len_ff[2]_i_5_n_0\
    );
\wtlp_srcbt_len_ff_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wtlp_srcbt_len_ff_reg[2]_i_2_n_0\,
      CO(3) => \wtlp_srcbt_len_ff_reg[7]_i_2_n_0\,
      CO(2) => \wtlp_srcbt_len_ff_reg[7]_i_2_n_1\,
      CO(1) => \wtlp_srcbt_len_ff_reg[7]_i_2_n_2\,
      CO(0) => \wtlp_srcbt_len_ff_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => wpl_bytelen(5 downto 4),
      O(3 downto 0) => wtlp_srcbt_whole_len1(7 downto 4),
      S(3 downto 0) => wpl_bytelen(7 downto 4)
    );
\wtlp_srcbt_len_ff_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \wtlp_srcbt_len_ff_reg[7]_i_2_n_0\,
      CO(3) => \wtlp_srcbt_len_ff_reg[8]_i_2_n_0\,
      CO(2) => \wtlp_srcbt_len_ff_reg[8]_i_2_n_1\,
      CO(1) => \wtlp_srcbt_len_ff_reg[8]_i_2_n_2\,
      CO(0) => \wtlp_srcbt_len_ff_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => wtlp_srcbt_whole_len1(11 downto 8),
      S(3 downto 0) => wpl_bytelen(11 downto 8)
    );
wtlp_srcbt_noinc_ff_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0E"
    )
        port map (
      I0 => wtlp_srcbt_noinc_ff_reg_i_2_n_5,
      I1 => wtlp_srcbt_noinc_ff_reg_i_2_n_6,
      I2 => \Head_reg_n_0_[1]\,
      I3 => wtlp_srcbt_noinc_ff_reg_i_2_n_7,
      O => wtlp_srcbt_noinc
    );
wtlp_srcbt_noinc_ff_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^head_reg[34]_0\(9),
      I1 => wpl_bytelen(2),
      O => wtlp_srcbt_noinc_ff_i_3_n_0
    );
wtlp_srcbt_noinc_ff_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^head_reg[34]_0\(8),
      I1 => wpl_bytelen(1),
      O => wtlp_srcbt_noinc_ff_i_4_n_0
    );
wtlp_srcbt_noinc_ff_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^head_reg[34]_0\(7),
      I1 => wpl_bytelen(0),
      O => wtlp_srcbt_noinc_ff_i_5_n_0
    );
wtlp_srcbt_noinc_ff_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => wtlp_srcbt_noinc_ff_reg_i_2_n_0,
      CO(2) => wtlp_srcbt_noinc_ff_reg_i_2_n_1,
      CO(1) => wtlp_srcbt_noinc_ff_reg_i_2_n_2,
      CO(0) => wtlp_srcbt_noinc_ff_reg_i_2_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => \^head_reg[34]_0\(9 downto 7),
      O(3) => wtlp_srcbt_noinc_ff_reg_i_2_n_4,
      O(2) => wtlp_srcbt_noinc_ff_reg_i_2_n_5,
      O(1) => wtlp_srcbt_noinc_ff_reg_i_2_n_6,
      O(0) => wtlp_srcbt_noinc_ff_reg_i_2_n_7,
      S(3) => wpl_bytelen(3),
      S(2) => wtlp_srcbt_noinc_ff_i_3_n_0,
      S(1) => wtlp_srcbt_noinc_ff_i_4_n_0,
      S(0) => wtlp_srcbt_noinc_ff_i_5_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFOHead2 is
  port (
    m_axis_rq_tvalid_d_ff_reg : out STD_LOGIC;
    m_axis_rq_tlast_d_ff_reg : out STD_LOGIC;
    tag_sel_ff_reg : out STD_LOGIC;
    tag_sel_ff0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wtlp_hdr_pop00_out : out STD_LOGIC;
    \reqdtlpSm512_cs_reg[2]\ : out STD_LOGIC;
    \rreq_head_info_ff_reg[0][adr][63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \reqdtlpSm_cs_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rreq_head_info_ff_reg[1][lbe][2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \reqdtlpSm_cs_reg[1]\ : out STD_LOGIC;
    \rreq_head_info_ff_reg[1][fbe][3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    wpl_hdr_btlene1_ff_reg : out STD_LOGIC;
    \reqdtlpSm_cs_reg[0]_0\ : out STD_LOGIC;
    \reqdtlpSm_cs_reg[1]_0\ : out STD_LOGIC;
    wtlp_hdr_rd_ff0 : out STD_LOGIC;
    \wpl_hdr_fbe_ff_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \m_axis_rq_tuser_d_nxt[0]__0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rdIssued_0 : out STD_LOGIC;
    \wpl_hdr_lbe_ff_reg[0]\ : out STD_LOGIC;
    \wpl_hdr_lbe_ff_reg[1]\ : out STD_LOGIC;
    \wpl_hdr_lbe_ff_reg[2]\ : out STD_LOGIC;
    \wpl_hdr_lbe_ff_reg[3]\ : out STD_LOGIC;
    \wpl_hdr_btlenm1_ff_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
    \rreq_head_info_ff_reg[0][tag][0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_vld_ff_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_info_nxt[0][rcb]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \rreq_head_vld_ff_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rreq_head_ld_new_1 : out STD_LOGIC;
    \rreq_head_info_nxt[0][chn]\ : out STD_LOGIC;
    \rreq_head_info_ff_reg[1][tag][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rreq_head_info_ff_reg[1][rid][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \rreq_head_info_ff_reg[1][did][8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \rreq_head_info_ff_reg[1][adr][63]\ : out STD_LOGIC_VECTOR ( 61 downto 0 );
    \flush_txn_linkdown_ff_reg[3]\ : out STD_LOGIC;
    \wtlp_hdr_rd_cnt_nn1_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    wcp_vld_ff_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wrq_pnd_cnt_ff_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \reqdtlpSm512_cs_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    wpl_hdr_vld_nxt : out STD_LOGIC;
    wtlp_dat_vld : out STD_LOGIC_VECTOR ( 0 to 0 );
    \reqdtlpSm512_cs_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wtlp_dat_cnt_nn1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    wtlp_dat_ren : out STD_LOGIC;
    wtlp_wpl_wen_500_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wtlp_rd_dat_cnt_nn1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    wtlp_wpl_wen_503_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \m_axis_rq\\.tvalid\ : out STD_LOGIC;
    empty_ff_reg_0 : out STD_LOGIC;
    \rreq_head_vld_ff_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RcbAvail_new_ff_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    rreq_head_info_both_rcb_nxt : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \rreq_head_vld_ff_reg[0]_2\ : out STD_LOGIC;
    tag_rd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_info_ff_reg[0][tag][0]_0\ : out STD_LOGIC;
    \rreq_head_info_ff_reg[0][tag][0]_1\ : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
    \Head_reg[126]_0\ : out STD_LOGIC_VECTOR ( 76 downto 0 );
    m_axis_rq_tvalid_d_ff_reg_0 : in STD_LOGIC;
    m_axis_rq_tvalid_d_ff : in STD_LOGIC;
    m_axis_rq_tlast_d_nxt : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 76 downto 0 );
    tag_sel_ff : in STD_LOGIC;
    beatdone : in STD_LOGIC;
    reqdtlpSm512_cs : in STD_LOGIC_VECTOR ( 1 downto 0 );
    reqdtlpSm_cs : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrWr_reg[0]_0\ : in STD_LOGIC;
    wtlp_hdr_ld_500 : in STD_LOGIC;
    \pcie_dma_in\\.cfg_phy_link_down\ : in STD_LOGIC;
    \FifoCntrWr_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \reqdtlpSm512_cs_reg[2]_0\ : in STD_LOGIC;
    p_0_in123_out : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 61 downto 0 );
    \m_axis_rq_thead_d_ff_reg[0][63]\ : in STD_LOGIC_VECTOR ( 61 downto 0 );
    \rreq_head_info_ff_reg[0][lbe][2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rreq_head_info_ff_reg[0][lbe][2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_info_ff_reg[0][fbe][3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_info_ff_reg[0][fbe][3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in116_out : in STD_LOGIC;
    wrreq : in STD_LOGIC;
    wpl_hdr_btlene1_ff : in STD_LOGIC;
    rdIssued_s10 : in STD_LOGIC;
    \reqdtlpSm_cs_reg[0]_1\ : in STD_LOGIC;
    force_ready_flush_ff : in STD_LOGIC;
    \wr_user__0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rreq_rro_ff : in STD_LOGIC;
    \m_axis_rq_thead_d_ff_reg[0][37]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \m_axis_rq_thead_d_ff_reg[0][10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wr_user : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \m_axis_rq_tuser_comb_ff_reg[26]\ : in STD_LOGIC;
    \beatrem_ff_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \m_axis_rq_tuser_comb_ff_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \m_axis_rq_tuser_d_ff_reg[0][3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \m_axis_rq_tuser_d_ff_reg[0][3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \m_axis_rq_thead_d_ff_reg[0][2]\ : in STD_LOGIC;
    \m_axis_rq_thead_d_ff_reg[0][2]_0\ : in STD_LOGIC;
    \beatrem_ff_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \beatrem_ff_reg[9]_1\ : in STD_LOGIC;
    \beatrem_ff_reg[8]\ : in STD_LOGIC;
    \beatrem_ff_reg[5]\ : in STD_LOGIC;
    \beatrem_ff_reg[4]\ : in STD_LOGIC;
    \m_axis_rq_thead_d_ff[0][9]_i_2_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \canissueRd_ff_reg[0]\ : in STD_LOGIC;
    \canissueRd_ff_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rreq_active0 : in STD_LOGIC;
    \canissueRd_ff_reg[0]_1\ : in STD_LOGIC;
    \canissueRd_ff_reg[1]\ : in STD_LOGIC;
    RcbAvail_upd_ff : in STD_LOGIC;
    RcbAvail_nxt0 : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \rreq_head_info_ff_reg[0][rcb][7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rreq_head_info_ff_reg[0][rcb][0]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[1][rcb]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \rreq_head_info_ff_reg[0][rcb][1]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][rcb][2]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][rcb][3]\ : in STD_LOGIC;
    \rreq_head_rcb_ok_ff_reg[0]_i_2_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rreq_head_info_ff_reg[0][rcb][4]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][rcb][7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rreq_head_info_ff_reg[0][rcb][5]\ : in STD_LOGIC;
    RcbAvail_nxt : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rreq_head_info_ff_reg[0][rcb][7]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    tag_ep_0 : in STD_LOGIC;
    tag_ep_1 : in STD_LOGIC;
    empty_ff_0 : in STD_LOGIC;
    \rreq_head_info_ff_reg[1][chn]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][chn][0]\ : in STD_LOGIC_VECTOR ( 79 downto 0 );
    \rreq_head_info_ff_reg[0][lbe][0]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][tag][5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \tag_dout[1]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \tag_dout[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \rreq_head_info_ff_reg[0][rid][5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rreq_head_info_ff_reg[0][did][8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \rreq_head_info_ff_reg[0][adr][63]_0\ : in STD_LOGIC_VECTOR ( 61 downto 0 );
    \m_axis_rq_thead_d_ff_reg[0][0]\ : in STD_LOGIC;
    flush_txn_linkdown : in STD_LOGIC;
    \wtlp_hdr_rd_cnt_nn1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wtlp_hdr_ld_501 : in STD_LOGIC;
    wcp_vld_ff : in STD_LOGIC;
    \wrq_pnd_cnt_ff_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wpl_hdr_vld_ff : in STD_LOGIC;
    \wtlp_dat_vld_ff_reg[0]\ : in STD_LOGIC;
    wtlp_dat_vld_ff : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wtlp_dat_cnt_nn1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wtlp_wpl_wen_500 : in STD_LOGIC;
    \wtlp_rd_dat_cnt_nn1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wtlp_wpl_wen_503 : in STD_LOGIC;
    wpl_hdr_chn_ff : in STD_LOGIC;
    DI : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RdPtr[1]_i_3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rreq_head_info_ff_reg[0][len][3]\ : in STD_LOGIC;
    \rreq_head_info_ff_reg[0][len][10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
    A : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \rreq_head_rcb_ok_ff_reg[1]_i_14_0\ : in STD_LOGIC;
    \rreq_head_rcb_ok_ff_reg[1]_i_14_1\ : in STD_LOGIC;
    \rreq_head_rcb_ok_ff_reg[1]_i_14_2\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \m_axis_rq\\.tready\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFOHead2 : entity is "xdma_v4_1_8_GenericFIFOHead2";
end xdma_0_xdma_v4_1_8_GenericFIFOHead2;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFOHead2 is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FifoCntrRd[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_2_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FifoCntrWr[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__11_n_0\ : STD_LOGIC;
  signal \Head[63]_i_1__8_n_0\ : STD_LOGIC;
  signal \Head[63]_i_2_n_0\ : STD_LOGIC;
  signal \Head[63]_i_4_n_0\ : STD_LOGIC;
  signal \Head[63]_i_5_n_0\ : STD_LOGIC;
  signal MemArray : STD_LOGIC_VECTOR ( 126 downto 0 );
  signal \MemArray[126]_i_1_n_0\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC;
  attribute MAX_FANOUT : string;
  attribute MAX_FANOUT of RdPtr : signal is "128";
  attribute RTL_MAX_FANOUT : string;
  attribute RTL_MAX_FANOUT of RdPtr : signal is "found";
  signal \RdPtr[0]_i_1__11_n_0\ : STD_LOGIC;
  signal WrEn0 : STD_LOGIC;
  signal WrPtr : STD_LOGIC;
  attribute MAX_FANOUT of WrPtr : signal is "128";
  attribute RTL_MAX_FANOUT of WrPtr : signal is "found";
  signal \beatrem_ff[9]_i_4_n_0\ : STD_LOGIC;
  signal \empty_ff_i_1__10_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \full_ff_i_1__6_n_0\ : STD_LOGIC;
  signal full_ff_reg_n_0 : STD_LOGIC;
  signal ldrem : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \m_axis_rq_thead_d_ff[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][32]_i_4_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][32]_i_7_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][3]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][4]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][4]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][5]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][5]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][6]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][6]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][7]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][7]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][8]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][8]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][9]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_thead_d_ff[0][9]_i_3_n_0\ : STD_LOGIC;
  signal m_axis_rq_tlast_d_ff_i_3_n_0 : STD_LOGIC;
  signal m_axis_rq_tlast_d_ff_i_4_n_0 : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[24]_i_4_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[26]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[26]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[26]_i_4_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[26]_i_5_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[26]_i_6_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[4]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[4]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[5]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[5]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[6]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[6]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[7]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_comb_ff[7]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][1]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][1]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][2]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][2]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][3]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rq_tuser_d_ff[0][3]_i_3_n_0\ : STD_LOGIC;
  signal m_axis_rq_tvalid_d_ff_i_3_n_0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 126 downto 0 );
  signal \^rdissued_0\ : STD_LOGIC;
  signal rdIssued_s01 : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_10_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_13_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_14_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_15_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_16_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_17_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_18_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_2_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_3_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_4_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_5_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_6_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_7_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_8_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[0]_i_9_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[2]_i_2_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[2]_i_3_n_0\ : STD_LOGIC;
  signal \reqdtlpSm512_cs[2]_i_4_n_0\ : STD_LOGIC;
  signal \reqdtlpSm_cs[0]_i_2_n_0\ : STD_LOGIC;
  signal \reqdtlpSm_cs[0]_i_3_n_0\ : STD_LOGIC;
  signal \reqdtlpSm_cs[0]_i_4_n_0\ : STD_LOGIC;
  signal \reqdtlpSm_cs[0]_i_6_n_0\ : STD_LOGIC;
  signal \reqdtlpSm_cs[1]_i_2_n_0\ : STD_LOGIC;
  signal \^reqdtlpsm_cs_reg[0]_0\ : STD_LOGIC;
  signal \^reqdtlpsm_cs_reg[1]\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][10]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][10]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][10]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][3]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][3]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][3]_i_5_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][3]_i_6_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][7]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][7]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][7]_i_4_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][len][7]_i_5_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][rcb][6]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][rcb][6]_i_3_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][rcb][7]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][rcb][7]_i_6_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff[0][rcb][7]_i_7_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][10]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][10]_i_1_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][3]_i_1_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][3]_i_1_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][3]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][3]_i_1_n_3\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][7]_i_1_n_0\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][7]_i_1_n_1\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][7]_i_1_n_2\ : STD_LOGIC;
  signal \rreq_head_info_ff_reg[0][len][7]_i_1_n_3\ : STD_LOGIC;
  signal \^rreq_head_info_nxt[0][rcb]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \rreq_head_rcb_ok_ff[0]_i_10_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_11_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_12_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_5_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_6_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_7_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_8_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[0]_i_9_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_16_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_17_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_18_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_19_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_20_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_21_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_22_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff[1]_i_23_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_14_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_14_n_1\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_14_n_2\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_14_n_3\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_15_n_0\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_15_n_1\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_15_n_2\ : STD_LOGIC;
  signal \rreq_head_rcb_ok_ff_reg[1]_i_15_n_3\ : STD_LOGIC;
  signal \rreq_head_vld_ff[0]_i_3_n_0\ : STD_LOGIC;
  signal \^tag_sel_ff0\ : STD_LOGIC;
  signal \wpl_hdr_adr_ff[63]_i_3_n_0\ : STD_LOGIC;
  signal \wrq_pnd_cnt_ff[3]_i_3_n_0\ : STD_LOGIC;
  signal \wseq_ff[3]_i_4_n_0\ : STD_LOGIC;
  signal \^wtlp_dat_ren\ : STD_LOGIC;
  signal wtlp_dat_vld6_in : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wtlp_dat_vld_ff[0]_i_4_n_0\ : STD_LOGIC;
  signal \wtlp_dat_vld_ff[0]_i_5_n_0\ : STD_LOGIC;
  signal \wtlp_dat_vld_ff[0]_i_7_n_0\ : STD_LOGIC;
  signal \wtlp_dat_vld_ff[0]_i_8_n_0\ : STD_LOGIC;
  signal wtlp_hdr_av_i_2_n_0 : STD_LOGIC;
  signal \^wtlp_hdr_pop00_out\ : STD_LOGIC;
  signal \wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0\ : STD_LOGIC;
  signal \wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0\ : STD_LOGIC;
  signal \^wtlp_hdr_rd_cnt_nn1_reg[2]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^wtlp_hdr_rd_ff0\ : STD_LOGIC;
  signal \NLW_rreq_head_info_ff_reg[0][len][10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_rreq_head_info_ff_reg[0][len][10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rreq_head_rcb_ok_ff_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__10\ : label is "soft_lutpair1614";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_2\ : label is "soft_lutpair1614";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__10\ : label is "soft_lutpair1615";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__11\ : label is "soft_lutpair1615";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_1__3\ : label is "soft_lutpair1621";
  attribute RAM_STYLE : string;
  attribute RAM_STYLE of \MemArray_reg[0]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[10]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[11]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[126]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[12]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[13]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[14]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[15]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[16]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[17]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[18]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[19]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[1]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[20]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[21]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[22]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[23]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[24]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[25]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[26]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[27]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[28]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[29]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[2]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[30]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[31]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[32]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[33]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[34]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[35]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[36]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[37]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[38]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[39]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[3]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[40]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[41]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[42]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[43]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[44]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[45]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[46]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[47]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[48]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[49]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[4]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[50]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[51]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[52]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[53]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[54]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[55]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[56]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[57]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[58]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[59]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[5]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[60]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[61]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[62]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[63]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[66]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[67]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[68]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[69]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[6]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[70]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[71]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[72]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[73]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[7]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[8]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[90]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[91]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[92]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[93]\ : label is "distributed";
  attribute RAM_STYLE of \MemArray_reg[9]\ : label is "distributed";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_4\ : label is "soft_lutpair1595";
  attribute MAX_FANOUT of \RdPtr_reg[0]\ : label is "128";
  attribute RTL_MAX_FANOUT of \RdPtr_reg[0]\ : label is "found";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \RdPtr_reg[0]\ : label is "no";
  attribute SOFT_HLUTNM of \beatrem_ff[0]_i_1__0\ : label is "soft_lutpair1612";
  attribute SOFT_HLUTNM of \beatrem_ff[1]_i_1__0\ : label is "soft_lutpair1612";
  attribute SOFT_HLUTNM of \beatrem_ff[9]_i_4\ : label is "soft_lutpair1608";
  attribute SOFT_HLUTNM of \empty_ff_i_2__4\ : label is "soft_lutpair1608";
  attribute SOFT_HLUTNM of \m_axis_rq_thead_d_ff[0][63]_i_1\ : label is "soft_lutpair1606";
  attribute SOFT_HLUTNM of \m_axis_rq_thead_d_ff[0][63]_i_5\ : label is "soft_lutpair1598";
  attribute SOFT_HLUTNM of m_axis_rq_tlast_d_ff_i_3 : label is "soft_lutpair1609";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[0]_i_1\ : label is "soft_lutpair1602";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[1]_i_1\ : label is "soft_lutpair1601";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[24]_i_2\ : label is "soft_lutpair1596";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[26]_i_5\ : label is "soft_lutpair1604";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[2]_i_1\ : label is "soft_lutpair1600";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_comb_ff[3]_i_1\ : label is "soft_lutpair1599";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_d_ff[0][0]_i_1\ : label is "soft_lutpair1602";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_d_ff[0][1]_i_1\ : label is "soft_lutpair1601";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_d_ff[0][2]_i_1\ : label is "soft_lutpair1600";
  attribute SOFT_HLUTNM of \m_axis_rq_tuser_d_ff[0][3]_i_1\ : label is "soft_lutpair1599";
  attribute SOFT_HLUTNM of \reqdtlpSm512_cs[0]_i_15\ : label is "soft_lutpair1606";
  attribute SOFT_HLUTNM of \reqdtlpSm512_cs[0]_i_17\ : label is "soft_lutpair1603";
  attribute SOFT_HLUTNM of \reqdtlpSm512_cs[0]_i_8\ : label is "soft_lutpair1596";
  attribute SOFT_HLUTNM of \reqdtlpSm512_cs[2]_i_3\ : label is "soft_lutpair1604";
  attribute SOFT_HLUTNM of \reqdtlpSm_cs[0]_i_4\ : label is "soft_lutpair1603";
  attribute SOFT_HLUTNM of \reqdtlpSm_cs[0]_i_6\ : label is "soft_lutpair1609";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][10]_i_1\ : label is "soft_lutpair1657";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][11]_i_1\ : label is "soft_lutpair1657";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][12]_i_1\ : label is "soft_lutpair1656";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][13]_i_1\ : label is "soft_lutpair1656";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][14]_i_1\ : label is "soft_lutpair1655";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][15]_i_1\ : label is "soft_lutpair1655";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][16]_i_1\ : label is "soft_lutpair1654";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][17]_i_1\ : label is "soft_lutpair1654";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][18]_i_1\ : label is "soft_lutpair1653";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][19]_i_1\ : label is "soft_lutpair1653";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][20]_i_1\ : label is "soft_lutpair1652";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][21]_i_1\ : label is "soft_lutpair1652";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][22]_i_1\ : label is "soft_lutpair1651";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][23]_i_1\ : label is "soft_lutpair1651";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][24]_i_1\ : label is "soft_lutpair1650";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][25]_i_1\ : label is "soft_lutpair1650";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][26]_i_1\ : label is "soft_lutpair1649";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][27]_i_1\ : label is "soft_lutpair1649";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][28]_i_1\ : label is "soft_lutpair1648";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][29]_i_1\ : label is "soft_lutpair1648";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][2]_i_1\ : label is "soft_lutpair1661";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][30]_i_1\ : label is "soft_lutpair1647";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][31]_i_1\ : label is "soft_lutpair1647";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][32]_i_1\ : label is "soft_lutpair1646";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][33]_i_1\ : label is "soft_lutpair1646";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][34]_i_1\ : label is "soft_lutpair1645";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][35]_i_1\ : label is "soft_lutpair1645";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][36]_i_1\ : label is "soft_lutpair1644";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][37]_i_1\ : label is "soft_lutpair1644";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][38]_i_1\ : label is "soft_lutpair1643";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][39]_i_1\ : label is "soft_lutpair1643";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][3]_i_1\ : label is "soft_lutpair1661";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][40]_i_1\ : label is "soft_lutpair1642";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][41]_i_1\ : label is "soft_lutpair1642";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][42]_i_1\ : label is "soft_lutpair1641";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][43]_i_1\ : label is "soft_lutpair1641";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][44]_i_1\ : label is "soft_lutpair1640";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][45]_i_1\ : label is "soft_lutpair1640";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][46]_i_1\ : label is "soft_lutpair1639";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][47]_i_1\ : label is "soft_lutpair1639";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][48]_i_1\ : label is "soft_lutpair1638";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][49]_i_1\ : label is "soft_lutpair1638";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][4]_i_1\ : label is "soft_lutpair1660";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][50]_i_1\ : label is "soft_lutpair1637";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][51]_i_1\ : label is "soft_lutpair1637";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][52]_i_1\ : label is "soft_lutpair1636";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][53]_i_1\ : label is "soft_lutpair1636";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][54]_i_1\ : label is "soft_lutpair1635";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][55]_i_1\ : label is "soft_lutpair1635";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][56]_i_1\ : label is "soft_lutpair1634";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][57]_i_1\ : label is "soft_lutpair1634";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][58]_i_1\ : label is "soft_lutpair1633";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][59]_i_1\ : label is "soft_lutpair1633";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][5]_i_1\ : label is "soft_lutpair1660";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][60]_i_1\ : label is "soft_lutpair1632";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][61]_i_1\ : label is "soft_lutpair1632";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][62]_i_1\ : label is "soft_lutpair1631";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][63]_i_1\ : label is "soft_lutpair1631";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][6]_i_1\ : label is "soft_lutpair1659";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][7]_i_1\ : label is "soft_lutpair1659";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][8]_i_1\ : label is "soft_lutpair1658";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][adr][9]_i_1\ : label is "soft_lutpair1658";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][chn][0]_i_1\ : label is "soft_lutpair1622";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][0]_i_1\ : label is "soft_lutpair1630";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][1]_i_1\ : label is "soft_lutpair1630";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][2]_i_1\ : label is "soft_lutpair1629";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][3]_i_1\ : label is "soft_lutpair1629";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][4]_i_1\ : label is "soft_lutpair1628";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][5]_i_1\ : label is "soft_lutpair1628";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][6]_i_1\ : label is "soft_lutpair1627";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][7]_i_1\ : label is "soft_lutpair1627";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][did][8]_i_1\ : label is "soft_lutpair1626";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][fbe][0]_i_1\ : label is "soft_lutpair1613";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][fbe][3]_i_1\ : label is "soft_lutpair1620";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][lbe][0]_i_1\ : label is "soft_lutpair1622";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][lbe][1]_i_1\ : label is "soft_lutpair1619";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][lbe][2]_i_1\ : label is "soft_lutpair1620";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rcb][6]_i_2\ : label is "soft_lutpair1617";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rcb][6]_i_3\ : label is "soft_lutpair1613";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rcb][7]_i_2\ : label is "soft_lutpair1618";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rcb][7]_i_6\ : label is "soft_lutpair1616";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rcb][7]_i_7\ : label is "soft_lutpair1619";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][0]_i_1\ : label is "soft_lutpair1626";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][1]_i_1\ : label is "soft_lutpair1625";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][2]_i_1\ : label is "soft_lutpair1625";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][3]_i_1\ : label is "soft_lutpair1624";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][4]_i_1\ : label is "soft_lutpair1624";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][rid][5]_i_1\ : label is "soft_lutpair1623";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][tag][0]_i_1\ : label is "soft_lutpair1623";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[0][tag][5]_i_1\ : label is "soft_lutpair1618";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][rcb][7]_i_1\ : label is "soft_lutpair1616";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \rreq_head_rcb_ok_ff_reg[0]_i_1\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \rreq_head_rcb_ok_ff_reg[0]_i_2\ : label is 11;
  attribute SOFT_HLUTNM of \rreq_head_vld_ff[0]_i_3\ : label is "soft_lutpair1617";
  attribute SOFT_HLUTNM of \rreq_head_vld_ff[1]_i_1\ : label is "soft_lutpair1595";
  attribute SOFT_HLUTNM of \tlp_rrq_snt_ff[0]_i_1\ : label is "soft_lutpair1664";
  attribute SOFT_HLUTNM of \tlp_rrq_snt_ff[1]_i_1\ : label is "soft_lutpair1664";
  attribute SOFT_HLUTNM of \tlp_rrq_tag_ff[0][5]_i_1\ : label is "soft_lutpair1662";
  attribute SOFT_HLUTNM of \tlp_rrq_tag_ff[1][5]_i_1\ : label is "soft_lutpair1662";
  attribute SOFT_HLUTNM of wpl_hdr_vld_ff_i_1 : label is "soft_lutpair1621";
  attribute SOFT_HLUTNM of \wrq_pnd_cnt_ff[1]_i_1\ : label is "soft_lutpair1605";
  attribute SOFT_HLUTNM of \wrq_pnd_cnt_ff[3]_i_3\ : label is "soft_lutpair1605";
  attribute SOFT_HLUTNM of \wseq_ff[3]_i_2\ : label is "soft_lutpair1597";
  attribute SOFT_HLUTNM of \wseq_ff[3]_i_4\ : label is "soft_lutpair1597";
  attribute SOFT_HLUTNM of \wtlp_dat_cnt_nn1[1]_i_1__0\ : label is "soft_lutpair1610";
  attribute SOFT_HLUTNM of \wtlp_dat_cnt_nn1[2]_i_1__0\ : label is "soft_lutpair1610";
  attribute SOFT_HLUTNM of \wtlp_dat_cnt_nn1[3]_i_1__0\ : label is "soft_lutpair1663";
  attribute SOFT_HLUTNM of \wtlp_hdr_rd_cnt_nn1[0]_i_1\ : label is "soft_lutpair1607";
  attribute SOFT_HLUTNM of \wtlp_hdr_rd_cnt_nn1[1]_i_1\ : label is "soft_lutpair1607";
  attribute SOFT_HLUTNM of wtlp_hdr_rd_ff_i_1 : label is "soft_lutpair1598";
  attribute SOFT_HLUTNM of \wtlp_rd_dat_cnt_nn1[1]_i_1__0\ : label is "soft_lutpair1611";
  attribute SOFT_HLUTNM of \wtlp_rd_dat_cnt_nn1[2]_i_1__0\ : label is "soft_lutpair1611";
  attribute SOFT_HLUTNM of \wtlp_rd_dat_cnt_nn1[3]_i_1__0\ : label is "soft_lutpair1663";
begin
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  rdIssued_0 <= \^rdissued_0\;
  \reqdtlpSm_cs_reg[0]_0\ <= \^reqdtlpsm_cs_reg[0]_0\;
  \reqdtlpSm_cs_reg[1]\ <= \^reqdtlpsm_cs_reg[1]\;
  \rreq_head_info_nxt[0][rcb]\(7 downto 0) <= \^rreq_head_info_nxt[0][rcb]\(7 downto 0);
  tag_sel_ff0 <= \^tag_sel_ff0\;
  wtlp_dat_ren <= \^wtlp_dat_ren\;
  wtlp_hdr_pop00_out <= \^wtlp_hdr_pop00_out\;
  \wtlp_hdr_rd_cnt_nn1_reg[2]\(3 downto 0) <= \^wtlp_hdr_rd_cnt_nn1_reg[2]\(3 downto 0);
  wtlp_hdr_rd_ff0 <= \^wtlp_hdr_rd_ff0\;
\FifoCntrRd[0]_i_1__10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__10_n_0\
    );
\FifoCntrRd[1]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22D2"
    )
        port map (
      I0 => \m_axis_rq\\.tready\,
      I1 => \^empty_ff_reg_0\,
      I2 => m_axis_rq_tvalid_d_ff,
      I3 => full_ff_reg_n_0,
      O => \FifoCntrRd[1]_i_1__8_n_0\
    );
\FifoCntrRd[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => m_axis_rq_tvalid_d_ff,
      I1 => full_ff_reg_n_0,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(0),
      O => \FifoCntrRd[1]_i_2_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[1]_i_1__8_n_0\,
      D => \FifoCntrRd[0]_i_1__10_n_0\,
      Q => FifoCntrRd(0),
      R => \Head[63]_i_1__8_n_0\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[1]_i_1__8_n_0\,
      D => \FifoCntrRd[1]_i_2_n_0\,
      Q => FifoCntrRd(1),
      R => \Head[63]_i_1__8_n_0\
    );
\FifoCntrWr[0]_i_1__10\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__10_n_0\
    );
\FifoCntrWr[1]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => m_axis_rq_tvalid_d_ff,
      I1 => full_ff_reg_n_0,
      I2 => FifoCntrWr(1),
      I3 => FifoCntrWr(0),
      O => \FifoCntrWr[1]_i_1__11_n_0\
    );
\FifoCntrWr[3]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => \^wtlp_hdr_pop00_out\,
      I1 => \FifoCntrWr_reg[0]_0\,
      I2 => wtlp_hdr_ld_500,
      O => E(0)
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[1]_i_1__8_n_0\,
      D => \FifoCntrWr[0]_i_1__10_n_0\,
      Q => FifoCntrWr(0),
      R => \Head[63]_i_1__8_n_0\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[1]_i_1__8_n_0\,
      D => \FifoCntrWr[1]_i_1__11_n_0\,
      Q => FifoCntrWr(1),
      R => \Head[63]_i_1__8_n_0\
    );
\Head[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(0),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(0),
      O => p_1_in(0)
    );
\Head[10]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(10),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(10),
      O => p_1_in(10)
    );
\Head[11]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(11),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(11),
      O => p_1_in(11)
    );
\Head[126]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(76),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(126),
      O => p_1_in(126)
    );
\Head[12]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(12),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(12),
      O => p_1_in(12)
    );
\Head[13]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(13),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(13),
      O => p_1_in(13)
    );
\Head[14]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(14),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(14),
      O => p_1_in(14)
    );
\Head[15]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(15),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(15),
      O => p_1_in(15)
    );
\Head[16]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(16),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(16),
      O => p_1_in(16)
    );
\Head[17]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(17),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(17),
      O => p_1_in(17)
    );
\Head[18]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(18),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(18),
      O => p_1_in(18)
    );
\Head[19]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(19),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(19),
      O => p_1_in(19)
    );
\Head[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(1),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(1),
      O => p_1_in(1)
    );
\Head[20]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(20),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(20),
      O => p_1_in(20)
    );
\Head[21]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(21),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(21),
      O => p_1_in(21)
    );
\Head[22]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(22),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(22),
      O => p_1_in(22)
    );
\Head[23]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(23),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(23),
      O => p_1_in(23)
    );
\Head[24]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(24),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(24),
      O => p_1_in(24)
    );
\Head[25]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(25),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(25),
      O => p_1_in(25)
    );
\Head[26]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(26),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(26),
      O => p_1_in(26)
    );
\Head[27]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(27),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(27),
      O => p_1_in(27)
    );
\Head[28]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(28),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(28),
      O => p_1_in(28)
    );
\Head[29]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(29),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(29),
      O => p_1_in(29)
    );
\Head[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(2),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(2),
      O => p_1_in(2)
    );
\Head[30]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(30),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(30),
      O => p_1_in(30)
    );
\Head[31]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(31),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(31),
      O => p_1_in(31)
    );
\Head[32]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(32),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(32),
      O => p_1_in(32)
    );
\Head[33]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(33),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(33),
      O => p_1_in(33)
    );
\Head[34]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(34),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(34),
      O => p_1_in(34)
    );
\Head[35]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(35),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(35),
      O => p_1_in(35)
    );
\Head[36]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(36),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(36),
      O => p_1_in(36)
    );
\Head[37]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(37),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(37),
      O => p_1_in(37)
    );
\Head[38]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(38),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(38),
      O => p_1_in(38)
    );
\Head[39]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(39),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(39),
      O => p_1_in(39)
    );
\Head[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(3),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(3),
      O => p_1_in(3)
    );
\Head[40]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(40),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(40),
      O => p_1_in(40)
    );
\Head[41]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(41),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(41),
      O => p_1_in(41)
    );
\Head[42]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(42),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(42),
      O => p_1_in(42)
    );
\Head[43]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(43),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(43),
      O => p_1_in(43)
    );
\Head[44]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(44),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(44),
      O => p_1_in(44)
    );
\Head[45]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(45),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(45),
      O => p_1_in(45)
    );
\Head[46]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(46),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(46),
      O => p_1_in(46)
    );
\Head[47]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(47),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(47),
      O => p_1_in(47)
    );
\Head[48]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(48),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(48),
      O => p_1_in(48)
    );
\Head[49]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(49),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(49),
      O => p_1_in(49)
    );
\Head[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(4),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(4),
      O => p_1_in(4)
    );
\Head[50]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(50),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(50),
      O => p_1_in(50)
    );
\Head[51]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(51),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(51),
      O => p_1_in(51)
    );
\Head[52]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(52),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(52),
      O => p_1_in(52)
    );
\Head[53]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(53),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(53),
      O => p_1_in(53)
    );
\Head[54]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(54),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(54),
      O => p_1_in(54)
    );
\Head[55]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(55),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(55),
      O => p_1_in(55)
    );
\Head[56]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(56),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(56),
      O => p_1_in(56)
    );
\Head[57]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(57),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(57),
      O => p_1_in(57)
    );
\Head[58]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(58),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(58),
      O => p_1_in(58)
    );
\Head[59]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(59),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(59),
      O => p_1_in(59)
    );
\Head[5]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(5),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(5),
      O => p_1_in(5)
    );
\Head[60]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(60),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(60),
      O => p_1_in(60)
    );
\Head[61]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(61),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(61),
      O => p_1_in(61)
    );
\Head[62]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(62),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(62),
      O => p_1_in(62)
    );
\Head[63]_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \pcie_dma_in\\.cfg_phy_link_down\,
      I1 => \FifoCntrWr_reg[0]_1\(0),
      O => \Head[63]_i_1__8_n_0\
    );
\Head[63]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3075"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => \^empty_ff_reg_0\,
      I2 => \m_axis_rq\\.tready\,
      I3 => FifoCntrRd(0),
      O => \Head[63]_i_2_n_0\
    );
\Head[63]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(63),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(63),
      O => p_1_in(63)
    );
\Head[63]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004F00"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \m_axis_rq\\.tready\,
      I2 => FifoCntrRd(0),
      I3 => m_axis_rq_tvalid_d_ff,
      I4 => full_ff_reg_n_0,
      O => \Head[63]_i_4_n_0\
    );
\Head[63]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFB0FFFF"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \m_axis_rq\\.tready\,
      I2 => FifoCntrRd(0),
      I3 => full_ff_reg_n_0,
      I4 => m_axis_rq_tvalid_d_ff,
      O => \Head[63]_i_5_n_0\
    );
\Head[66]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(64),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(66),
      O => p_1_in(66)
    );
\Head[67]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(65),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(67),
      O => p_1_in(67)
    );
\Head[68]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(66),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(68),
      O => p_1_in(68)
    );
\Head[69]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(67),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(69),
      O => p_1_in(69)
    );
\Head[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(6),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(6),
      O => p_1_in(6)
    );
\Head[70]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(68),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(70),
      O => p_1_in(70)
    );
\Head[71]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(69),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(71),
      O => p_1_in(71)
    );
\Head[72]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(70),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(72),
      O => p_1_in(72)
    );
\Head[73]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(71),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(73),
      O => p_1_in(73)
    );
\Head[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(7),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(7),
      O => p_1_in(7)
    );
\Head[8]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(8),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(8),
      O => p_1_in(8)
    );
\Head[90]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(72),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(90),
      O => p_1_in(90)
    );
\Head[91]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(73),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(91),
      O => p_1_in(91)
    );
\Head[92]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(74),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(92),
      O => p_1_in(92)
    );
\Head[93]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(75),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(93),
      O => p_1_in(93)
    );
\Head[9]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFC0808"
    )
        port map (
      I0 => \Head[63]_i_4_n_0\,
      I1 => D(9),
      I2 => FifoCntrRd(1),
      I3 => \Head[63]_i_5_n_0\,
      I4 => MemArray(9),
      O => p_1_in(9)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(0),
      Q => \Head_reg[126]_0\(0),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(10),
      Q => \Head_reg[126]_0\(10),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(11),
      Q => \Head_reg[126]_0\(11),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(126),
      Q => \Head_reg[126]_0\(76),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(12),
      Q => \Head_reg[126]_0\(12),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(13),
      Q => \Head_reg[126]_0\(13),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(14),
      Q => \Head_reg[126]_0\(14),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(15),
      Q => \Head_reg[126]_0\(15),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(16),
      Q => \Head_reg[126]_0\(16),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(17),
      Q => \Head_reg[126]_0\(17),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(18),
      Q => \Head_reg[126]_0\(18),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(19),
      Q => \Head_reg[126]_0\(19),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(1),
      Q => \Head_reg[126]_0\(1),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(20),
      Q => \Head_reg[126]_0\(20),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(21),
      Q => \Head_reg[126]_0\(21),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(22),
      Q => \Head_reg[126]_0\(22),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(23),
      Q => \Head_reg[126]_0\(23),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(24),
      Q => \Head_reg[126]_0\(24),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(25),
      Q => \Head_reg[126]_0\(25),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(26),
      Q => \Head_reg[126]_0\(26),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(27),
      Q => \Head_reg[126]_0\(27),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(28),
      Q => \Head_reg[126]_0\(28),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(29),
      Q => \Head_reg[126]_0\(29),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(2),
      Q => \Head_reg[126]_0\(2),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(30),
      Q => \Head_reg[126]_0\(30),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(31),
      Q => \Head_reg[126]_0\(31),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(32),
      Q => \Head_reg[126]_0\(32),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(33),
      Q => \Head_reg[126]_0\(33),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(34),
      Q => \Head_reg[126]_0\(34),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(35),
      Q => \Head_reg[126]_0\(35),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(36),
      Q => \Head_reg[126]_0\(36),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(37),
      Q => \Head_reg[126]_0\(37),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(38),
      Q => \Head_reg[126]_0\(38),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(39),
      Q => \Head_reg[126]_0\(39),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(3),
      Q => \Head_reg[126]_0\(3),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(40),
      Q => \Head_reg[126]_0\(40),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(41),
      Q => \Head_reg[126]_0\(41),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(42),
      Q => \Head_reg[126]_0\(42),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(43),
      Q => \Head_reg[126]_0\(43),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(44),
      Q => \Head_reg[126]_0\(44),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(45),
      Q => \Head_reg[126]_0\(45),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(46),
      Q => \Head_reg[126]_0\(46),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(47),
      Q => \Head_reg[126]_0\(47),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(48),
      Q => \Head_reg[126]_0\(48),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(49),
      Q => \Head_reg[126]_0\(49),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(4),
      Q => \Head_reg[126]_0\(4),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(50),
      Q => \Head_reg[126]_0\(50),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(51),
      Q => \Head_reg[126]_0\(51),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(52),
      Q => \Head_reg[126]_0\(52),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(53),
      Q => \Head_reg[126]_0\(53),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(54),
      Q => \Head_reg[126]_0\(54),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(55),
      Q => \Head_reg[126]_0\(55),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(56),
      Q => \Head_reg[126]_0\(56),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(57),
      Q => \Head_reg[126]_0\(57),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(58),
      Q => \Head_reg[126]_0\(58),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(59),
      Q => \Head_reg[126]_0\(59),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(5),
      Q => \Head_reg[126]_0\(5),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(60),
      Q => \Head_reg[126]_0\(60),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(61),
      Q => \Head_reg[126]_0\(61),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(62),
      Q => \Head_reg[126]_0\(62),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(63),
      Q => \Head_reg[126]_0\(63),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(66),
      Q => \Head_reg[126]_0\(64),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(67),
      Q => \Head_reg[126]_0\(65),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(68),
      Q => \Head_reg[126]_0\(66),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(69),
      Q => \Head_reg[126]_0\(67),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(6),
      Q => \Head_reg[126]_0\(6),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(70),
      Q => \Head_reg[126]_0\(68),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(71),
      Q => \Head_reg[126]_0\(69),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(72),
      Q => \Head_reg[126]_0\(70),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(73),
      Q => \Head_reg[126]_0\(71),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(7),
      Q => \Head_reg[126]_0\(7),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(8),
      Q => \Head_reg[126]_0\(8),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(90),
      Q => \Head_reg[126]_0\(72),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(91),
      Q => \Head_reg[126]_0\(73),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(92),
      Q => \Head_reg[126]_0\(74),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(93),
      Q => \Head_reg[126]_0\(75),
      R => \Head[63]_i_1__8_n_0\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[63]_i_2_n_0\,
      D => p_1_in(9),
      Q => \Head_reg[126]_0\(9),
      R => \Head[63]_i_1__8_n_0\
    );
\MemArray[126]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => full_ff_reg_n_0,
      I1 => m_axis_rq_tvalid_d_ff,
      I2 => WrPtr,
      O => \MemArray[126]_i_1_n_0\
    );
\MemArray_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(0),
      Q => MemArray(0),
      R => '0'
    );
\MemArray_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(10),
      Q => MemArray(10),
      R => '0'
    );
\MemArray_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(11),
      Q => MemArray(11),
      R => '0'
    );
\MemArray_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(76),
      Q => MemArray(126),
      R => '0'
    );
\MemArray_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(12),
      Q => MemArray(12),
      R => '0'
    );
\MemArray_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(13),
      Q => MemArray(13),
      R => '0'
    );
\MemArray_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(14),
      Q => MemArray(14),
      R => '0'
    );
\MemArray_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(15),
      Q => MemArray(15),
      R => '0'
    );
\MemArray_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(16),
      Q => MemArray(16),
      R => '0'
    );
\MemArray_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(17),
      Q => MemArray(17),
      R => '0'
    );
\MemArray_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(18),
      Q => MemArray(18),
      R => '0'
    );
\MemArray_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(19),
      Q => MemArray(19),
      R => '0'
    );
\MemArray_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(1),
      Q => MemArray(1),
      R => '0'
    );
\MemArray_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(20),
      Q => MemArray(20),
      R => '0'
    );
\MemArray_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(21),
      Q => MemArray(21),
      R => '0'
    );
\MemArray_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(22),
      Q => MemArray(22),
      R => '0'
    );
\MemArray_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(23),
      Q => MemArray(23),
      R => '0'
    );
\MemArray_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(24),
      Q => MemArray(24),
      R => '0'
    );
\MemArray_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(25),
      Q => MemArray(25),
      R => '0'
    );
\MemArray_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(26),
      Q => MemArray(26),
      R => '0'
    );
\MemArray_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(27),
      Q => MemArray(27),
      R => '0'
    );
\MemArray_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(28),
      Q => MemArray(28),
      R => '0'
    );
\MemArray_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(29),
      Q => MemArray(29),
      R => '0'
    );
\MemArray_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(2),
      Q => MemArray(2),
      R => '0'
    );
\MemArray_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(30),
      Q => MemArray(30),
      R => '0'
    );
\MemArray_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(31),
      Q => MemArray(31),
      R => '0'
    );
\MemArray_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(32),
      Q => MemArray(32),
      R => '0'
    );
\MemArray_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(33),
      Q => MemArray(33),
      R => '0'
    );
\MemArray_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(34),
      Q => MemArray(34),
      R => '0'
    );
\MemArray_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(35),
      Q => MemArray(35),
      R => '0'
    );
\MemArray_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(36),
      Q => MemArray(36),
      R => '0'
    );
\MemArray_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(37),
      Q => MemArray(37),
      R => '0'
    );
\MemArray_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(38),
      Q => MemArray(38),
      R => '0'
    );
\MemArray_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(39),
      Q => MemArray(39),
      R => '0'
    );
\MemArray_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(3),
      Q => MemArray(3),
      R => '0'
    );
\MemArray_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(40),
      Q => MemArray(40),
      R => '0'
    );
\MemArray_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(41),
      Q => MemArray(41),
      R => '0'
    );
\MemArray_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(42),
      Q => MemArray(42),
      R => '0'
    );
\MemArray_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(43),
      Q => MemArray(43),
      R => '0'
    );
\MemArray_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(44),
      Q => MemArray(44),
      R => '0'
    );
\MemArray_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(45),
      Q => MemArray(45),
      R => '0'
    );
\MemArray_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(46),
      Q => MemArray(46),
      R => '0'
    );
\MemArray_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(47),
      Q => MemArray(47),
      R => '0'
    );
\MemArray_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(48),
      Q => MemArray(48),
      R => '0'
    );
\MemArray_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(49),
      Q => MemArray(49),
      R => '0'
    );
\MemArray_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(4),
      Q => MemArray(4),
      R => '0'
    );
\MemArray_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(50),
      Q => MemArray(50),
      R => '0'
    );
\MemArray_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(51),
      Q => MemArray(51),
      R => '0'
    );
\MemArray_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(52),
      Q => MemArray(52),
      R => '0'
    );
\MemArray_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(53),
      Q => MemArray(53),
      R => '0'
    );
\MemArray_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(54),
      Q => MemArray(54),
      R => '0'
    );
\MemArray_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(55),
      Q => MemArray(55),
      R => '0'
    );
\MemArray_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(56),
      Q => MemArray(56),
      R => '0'
    );
\MemArray_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(57),
      Q => MemArray(57),
      R => '0'
    );
\MemArray_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(58),
      Q => MemArray(58),
      R => '0'
    );
\MemArray_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(59),
      Q => MemArray(59),
      R => '0'
    );
\MemArray_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(5),
      Q => MemArray(5),
      R => '0'
    );
\MemArray_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(60),
      Q => MemArray(60),
      R => '0'
    );
\MemArray_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(61),
      Q => MemArray(61),
      R => '0'
    );
\MemArray_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(62),
      Q => MemArray(62),
      R => '0'
    );
\MemArray_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(63),
      Q => MemArray(63),
      R => '0'
    );
\MemArray_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(64),
      Q => MemArray(66),
      R => '0'
    );
\MemArray_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(65),
      Q => MemArray(67),
      R => '0'
    );
\MemArray_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(66),
      Q => MemArray(68),
      R => '0'
    );
\MemArray_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(67),
      Q => MemArray(69),
      R => '0'
    );
\MemArray_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(6),
      Q => MemArray(6),
      R => '0'
    );
\MemArray_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(68),
      Q => MemArray(70),
      R => '0'
    );
\MemArray_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(69),
      Q => MemArray(71),
      R => '0'
    );
\MemArray_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(70),
      Q => MemArray(72),
      R => '0'
    );
\MemArray_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(71),
      Q => MemArray(73),
      R => '0'
    );
\MemArray_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(7),
      Q => MemArray(7),
      R => '0'
    );
\MemArray_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(8),
      Q => MemArray(8),
      R => '0'
    );
\MemArray_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(72),
      Q => MemArray(90),
      R => '0'
    );
\MemArray_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(73),
      Q => MemArray(91),
      R => '0'
    );
\MemArray_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(74),
      Q => MemArray(92),
      R => '0'
    );
\MemArray_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(75),
      Q => MemArray(93),
      R => '0'
    );
\MemArray_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \MemArray[126]_i_1_n_0\,
      D => D(9),
      Q => MemArray(9),
      R => '0'
    );
RQ_FIFOi_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => WrPtr
    );
\RdPtr[0]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => RdPtr,
      I1 => \FifoCntrWr_reg[0]_1\(0),
      I2 => \pcie_dma_in\\.cfg_phy_link_down\,
      O => \RdPtr[0]_i_1__11_n_0\
    );
\RdPtr[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DF00FFFF"
    )
        port map (
      I0 => \canissueRd_ff_reg[0]_0\(0),
      I1 => \^rdissued_0\,
      I2 => \canissueRd_ff_reg[0]_0\(1),
      I3 => rreq_active0,
      I4 => \RdPtr[1]_i_3__1\(0),
      O => \rreq_head_vld_ff_reg[0]_2\
    );
\RdPtr[2]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000E0A000000000"
    )
        port map (
      I0 => wtlp_dat_vld6_in(0),
      I1 => \beatrem_ff[9]_i_4_n_0\,
      I2 => reqdtlpSm512_cs(1),
      I3 => reqdtlpSm512_cs(1),
      I4 => reqdtlpSm_cs(1),
      I5 => reqdtlpSm_cs(0),
      O => \^wtlp_dat_ren\
    );
\RdPtr[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1015101500001015"
    )
        port map (
      I0 => empty_ff_0,
      I1 => tag_ep_1,
      I2 => tag_sel_ff,
      I3 => tag_ep_0,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_vld_ff[0]_i_3_n_0\,
      O => \^tag_sel_ff0\
    );
\RdPtr[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000B0000"
    )
        port map (
      I0 => \rreq_head_vld_ff[0]_i_3_n_0\,
      I1 => \canissueRd_ff_reg[0]_0\(1),
      I2 => tag_ep_1,
      I3 => empty_ff_0,
      I4 => tag_sel_ff,
      O => tag_rd(1)
    );
\RdPtr[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000000B"
    )
        port map (
      I0 => \rreq_head_vld_ff[0]_i_3_n_0\,
      I1 => \canissueRd_ff_reg[0]_0\(1),
      I2 => tag_ep_0,
      I3 => empty_ff_0,
      I4 => tag_sel_ff,
      O => tag_rd(0)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__11_n_0\,
      Q => RdPtr,
      R => '0'
    );
\beatrem_ff[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(0),
      I1 => ldrem(0),
      I2 => \beatrem_ff_reg[9]\(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(0)
    );
\beatrem_ff[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAC3"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(1),
      I1 => \beatrem_ff_reg[9]\(1),
      I2 => \beatrem_ff_reg[9]\(0),
      I3 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(1)
    );
\beatrem_ff[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAACCC3"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(2),
      I1 => \beatrem_ff_reg[9]\(2),
      I2 => \beatrem_ff_reg[9]\(0),
      I3 => \beatrem_ff_reg[9]\(1),
      I4 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(2)
    );
\beatrem_ff[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFFC0003"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(3),
      I1 => \beatrem_ff_reg[9]\(0),
      I2 => \beatrem_ff_reg[9]\(1),
      I3 => \beatrem_ff_reg[9]\(2),
      I4 => \beatrem_ff_reg[9]\(3),
      I5 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(3)
    );
\beatrem_ff[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFFC0003"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(4),
      I1 => \beatrem_ff_reg[4]\,
      I2 => \beatrem_ff_reg[9]\(3),
      I3 => \beatrem_ff_reg[9]\(2),
      I4 => \beatrem_ff_reg[9]\(4),
      I5 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(4)
    );
\beatrem_ff[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAF0F0F0C3"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(5),
      I1 => \beatrem_ff_reg[5]\,
      I2 => \beatrem_ff_reg[9]\(5),
      I3 => \beatrem_ff_reg[9]\(0),
      I4 => \beatrem_ff_reg[9]\(1),
      I5 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(5)
    );
\beatrem_ff[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA3C"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(6),
      I1 => \beatrem_ff_reg[8]\,
      I2 => \beatrem_ff_reg[9]\(6),
      I3 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(6)
    );
\beatrem_ff[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAF03C"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(7),
      I1 => \beatrem_ff_reg[8]\,
      I2 => \beatrem_ff_reg[9]\(7),
      I3 => \beatrem_ff_reg[9]\(6),
      I4 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(7)
    );
\beatrem_ff[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAFFF3000C"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(8),
      I1 => \beatrem_ff_reg[8]\,
      I2 => \beatrem_ff_reg[9]\(6),
      I3 => \beatrem_ff_reg[9]\(7),
      I4 => \beatrem_ff_reg[9]\(8),
      I5 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(8)
    );
\beatrem_ff[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0F0F2F0F0F0"
    )
        port map (
      I0 => reqdtlpSm_cs(0),
      I1 => reqdtlpSm_cs(1),
      I2 => ldrem(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm512_cs(1),
      I5 => \beatrem_ff[9]_i_4_n_0\,
      O => \reqdtlpSm_cs_reg[0]\(0)
    );
\beatrem_ff[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAC3"
    )
        port map (
      I0 => \beatrem_ff_reg[9]_0\(9),
      I1 => \beatrem_ff_reg[9]\(9),
      I2 => \beatrem_ff_reg[9]_1\,
      I3 => ldrem(0),
      O => \wpl_hdr_btlenm1_ff_reg[9]\(9)
    );
\beatrem_ff[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F040004"
    )
        port map (
      I0 => p_0_in123_out,
      I1 => wrreq,
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(0),
      I4 => wtlp_dat_vld6_in(0),
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => ldrem(0)
    );
\beatrem_ff[9]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008A00"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => force_ready_flush_ff,
      I2 => full_ff_reg_n_0,
      I3 => m_axis_rq_tvalid_d_ff,
      I4 => reqdtlpSm_cs(1),
      O => \beatrem_ff[9]_i_4_n_0\
    );
\canissueRd_ff[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFCFFF00000AAA0"
    )
        port map (
      I0 => \canissueRd_ff_reg[0]\,
      I1 => \canissueRd_ff_reg[0]_0\(1),
      I2 => rreq_active0,
      I3 => \canissueRd_ff_reg[0]_0\(0),
      I4 => \^rdissued_0\,
      I5 => \canissueRd_ff_reg[0]_1\,
      O => \rreq_head_vld_ff_reg[0]\(0)
    );
\canissueRd_ff[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFF00C000AA0080"
    )
        port map (
      I0 => \canissueRd_ff_reg[1]\,
      I1 => rreq_active0,
      I2 => \canissueRd_ff_reg[0]_0\(0),
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \canissueRd_ff_reg[0]_1\,
      O => \rreq_head_vld_ff_reg[0]\(1)
    );
\empty_ff_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001055"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => \^empty_ff_reg_0\,
      I2 => \m_axis_rq\\.tready\,
      I3 => FifoCntrRd(0),
      I4 => WrEn0,
      I5 => \Head[63]_i_1__8_n_0\,
      O => \empty_ff_i_1__10_n_0\
    );
\empty_ff_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => m_axis_rq_tvalid_d_ff,
      I1 => full_ff_reg_n_0,
      O => WrEn0
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__10_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
\full_ff_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000064406464"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => WrEn0,
      I3 => \^empty_ff_reg_0\,
      I4 => \m_axis_rq\\.tready\,
      I5 => \Head[63]_i_1__8_n_0\,
      O => \full_ff_i_1__6_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__6_n_0\,
      Q => full_ff_reg_n_0,
      R => '0'
    );
\m_axis_rq\\.tvalid_INST_0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      O => \m_axis_rq\\.tvalid\
    );
\m_axis_rq_thead_d_ff[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A0000000C000000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(0),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(0),
      I2 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm512_cs(0),
      I5 => reqdtlpSm_cs(1),
      O => \rreq_head_info_ff_reg[0][adr][63]\(0)
    );
\m_axis_rq_thead_d_ff[0][10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(8),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(8),
      I4 => \m_axis_rq_thead_d_ff_reg[0][10]\(10),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(10)
    );
\m_axis_rq_thead_d_ff[0][11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \^wtlp_hdr_rd_ff0\,
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => \m_axis_rq_thead_d_ff_reg[0][63]\(9),
      I3 => Q(9),
      I4 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(11)
    );
\m_axis_rq_thead_d_ff[0][12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(10),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(10),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(12)
    );
\m_axis_rq_thead_d_ff[0][13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(11),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(11),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(13)
    );
\m_axis_rq_thead_d_ff[0][14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(12),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(12),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(14)
    );
\m_axis_rq_thead_d_ff[0][15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(13),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(13),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(15)
    );
\m_axis_rq_thead_d_ff[0][16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(14),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(14),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(16)
    );
\m_axis_rq_thead_d_ff[0][17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(15),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(15),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(17)
    );
\m_axis_rq_thead_d_ff[0][18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(16),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(16),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(18)
    );
\m_axis_rq_thead_d_ff[0][19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(17),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(17),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(19)
    );
\m_axis_rq_thead_d_ff[0][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A0000000C000000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(1),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(1),
      I2 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm512_cs(0),
      I5 => reqdtlpSm_cs(1),
      O => \rreq_head_info_ff_reg[0][adr][63]\(1)
    );
\m_axis_rq_thead_d_ff[0][20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(18),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(18),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(20)
    );
\m_axis_rq_thead_d_ff[0][21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(19),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(19),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(21)
    );
\m_axis_rq_thead_d_ff[0][22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(20),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(20),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(22)
    );
\m_axis_rq_thead_d_ff[0][23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(21),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(21),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(23)
    );
\m_axis_rq_thead_d_ff[0][24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(22),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(22),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(24)
    );
\m_axis_rq_thead_d_ff[0][25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(23),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(23),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(25)
    );
\m_axis_rq_thead_d_ff[0][26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(24),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(24),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(26)
    );
\m_axis_rq_thead_d_ff[0][27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(25),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(25),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(27)
    );
\m_axis_rq_thead_d_ff[0][28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(26),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(26),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(28)
    );
\m_axis_rq_thead_d_ff[0][29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(27),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(27),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(29)
    );
\m_axis_rq_thead_d_ff[0][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(0),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(0),
      I5 => \m_axis_rq_thead_d_ff[0][2]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(2)
    );
\m_axis_rq_thead_d_ff[0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(0),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(0),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][2]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][2]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(2),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(2),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][2]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(28),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(28),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(30)
    );
\m_axis_rq_thead_d_ff[0][31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(29),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(29),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(31)
    );
\m_axis_rq_thead_d_ff[0][32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(30),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(30),
      I5 => \m_axis_rq_thead_d_ff[0][32]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(32)
    );
\m_axis_rq_thead_d_ff[0][32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => reqdtlpSm512_cs(1),
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(0),
      I4 => wtlp_dat_vld6_in(0),
      I5 => beatdone,
      O => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][32]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A200AAAAA200A200"
    )
        port map (
      I0 => \reqdtlpSm_cs[0]_i_4_n_0\,
      I1 => reqdtlpSm512_cs(0),
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(1),
      I4 => p_0_in123_out,
      I5 => beatdone,
      O => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][32]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(30),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(30),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_7_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][32]_i_4_n_0\
    );
\m_axis_rq_thead_d_ff[0][32]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][37]\(0),
      I1 => wpl_hdr_chn_ff,
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][32]_i_7_n_0\
    );
\m_axis_rq_thead_d_ff[0][33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(31),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(31),
      I4 => \m_axis_rq_thead_d_ff_reg[0][37]\(1),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(33)
    );
\m_axis_rq_thead_d_ff[0][34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(32),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(32),
      I4 => \m_axis_rq_thead_d_ff_reg[0][37]\(2),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(34)
    );
\m_axis_rq_thead_d_ff[0][35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(33),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(33),
      I4 => \m_axis_rq_thead_d_ff_reg[0][37]\(3),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(35)
    );
\m_axis_rq_thead_d_ff[0][36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(34),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(34),
      I4 => \m_axis_rq_thead_d_ff_reg[0][37]\(4),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(36)
    );
\m_axis_rq_thead_d_ff[0][37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(35),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(35),
      I4 => \m_axis_rq_thead_d_ff_reg[0][37]\(5),
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(37)
    );
\m_axis_rq_thead_d_ff[0][38]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(36),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(36),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(38)
    );
\m_axis_rq_thead_d_ff[0][39]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEAEAEA"
    )
        port map (
      I0 => \^wtlp_hdr_rd_ff0\,
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => \m_axis_rq_thead_d_ff_reg[0][63]\(37),
      I3 => Q(37),
      I4 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(39)
    );
\m_axis_rq_thead_d_ff[0][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(1),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(1),
      I5 => \m_axis_rq_thead_d_ff[0][3]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(3)
    );
\m_axis_rq_thead_d_ff[0][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(1),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(1),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][3]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][3]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(3),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(3),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][3]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][40]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(38),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(38),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(40)
    );
\m_axis_rq_thead_d_ff[0][41]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(39),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(39),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(41)
    );
\m_axis_rq_thead_d_ff[0][42]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(40),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(40),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(42)
    );
\m_axis_rq_thead_d_ff[0][43]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(41),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(41),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(43)
    );
\m_axis_rq_thead_d_ff[0][44]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(42),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(42),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(44)
    );
\m_axis_rq_thead_d_ff[0][45]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(43),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(43),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(45)
    );
\m_axis_rq_thead_d_ff[0][46]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(44),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(44),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(46)
    );
\m_axis_rq_thead_d_ff[0][47]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(45),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(45),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(47)
    );
\m_axis_rq_thead_d_ff[0][48]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(46),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(46),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(48)
    );
\m_axis_rq_thead_d_ff[0][49]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(47),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(47),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(49)
    );
\m_axis_rq_thead_d_ff[0][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(2),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(2),
      I5 => \m_axis_rq_thead_d_ff[0][4]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(4)
    );
\m_axis_rq_thead_d_ff[0][4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(2),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(2),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][4]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][4]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(4),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(4),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][4]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][50]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(48),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(48),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(50)
    );
\m_axis_rq_thead_d_ff[0][51]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(49),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(49),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(51)
    );
\m_axis_rq_thead_d_ff[0][52]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(50),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(50),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(52)
    );
\m_axis_rq_thead_d_ff[0][53]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(51),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(51),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(53)
    );
\m_axis_rq_thead_d_ff[0][54]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(52),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(52),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(54)
    );
\m_axis_rq_thead_d_ff[0][55]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(53),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(53),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(55)
    );
\m_axis_rq_thead_d_ff[0][56]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(54),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(54),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(56)
    );
\m_axis_rq_thead_d_ff[0][57]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(55),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(55),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(57)
    );
\m_axis_rq_thead_d_ff[0][58]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(56),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(56),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(58)
    );
\m_axis_rq_thead_d_ff[0][59]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(57),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(57),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(59)
    );
\m_axis_rq_thead_d_ff[0][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(3),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(3),
      I5 => \m_axis_rq_thead_d_ff[0][5]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(5)
    );
\m_axis_rq_thead_d_ff[0][5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(3),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(3),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][5]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][5]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(5),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(5),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][5]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][60]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(58),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(58),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(60)
    );
\m_axis_rq_thead_d_ff[0][61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      I1 => Q(59),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff_reg[0][63]\(59),
      I4 => rreq_rro_ff,
      I5 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(61)
    );
\m_axis_rq_thead_d_ff[0][62]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(60),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(60),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(62)
    );
\m_axis_rq_thead_d_ff[0][63]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0002"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => reqdtlpSm512_cs(0),
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(1),
      I4 => wtlp_dat_vld6_in(0),
      O => \reqdtlpSm512_cs_reg[0]_0\(0)
    );
\m_axis_rq_thead_d_ff[0][63]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(61),
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => Q(61),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(63)
    );
\m_axis_rq_thead_d_ff[0][63]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF01010100000000"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => reqdtlpSm_cs(1),
      I2 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\,
      I4 => beatdone,
      I5 => p_0_in123_out,
      O => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][63]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEFFAAAA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\,
      I1 => beatdone,
      I2 => p_0_in123_out,
      I3 => \reqdtlpSm512_cs_reg[2]_0\,
      I4 => \reqdtlpSm_cs[0]_i_4_n_0\,
      O => \m_axis_rq_thead_d_ff[0][63]_i_4_n_0\
    );
\m_axis_rq_thead_d_ff[0][63]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => wtlp_dat_vld6_in(0),
      I1 => reqdtlpSm512_cs(0),
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(1),
      I4 => rdIssued_s01,
      O => \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\
    );
\m_axis_rq_thead_d_ff[0][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(4),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(4),
      I5 => \m_axis_rq_thead_d_ff[0][6]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(6)
    );
\m_axis_rq_thead_d_ff[0][6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(4),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(4),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][6]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][6]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(6),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(6),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][6]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(5),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(5),
      I5 => \m_axis_rq_thead_d_ff[0][7]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(7)
    );
\m_axis_rq_thead_d_ff[0][7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(5),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(5),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][7]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][7]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(7),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(7),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][7]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(6),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(6),
      I5 => \m_axis_rq_thead_d_ff[0][8]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(8)
    );
\m_axis_rq_thead_d_ff[0][8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(6),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(6),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][8]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][8]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(8),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(8),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][8]_i_3_n_0\
    );
\m_axis_rq_thead_d_ff[0][9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF888F000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I3 => Q(7),
      I4 => \m_axis_rq_thead_d_ff_reg[0][63]\(7),
      I5 => \m_axis_rq_thead_d_ff[0][9]_i_2_n_0\,
      O => \rreq_head_info_ff_reg[0][adr][63]\(9)
    );
\m_axis_rq_thead_d_ff[0][9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFF888"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][63]\(7),
      I1 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I2 => Q(7),
      I3 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      I4 => \m_axis_rq_thead_d_ff[0][9]_i_3_n_0\,
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_thead_d_ff[0][9]_i_2_n_0\
    );
\m_axis_rq_thead_d_ff[0][9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A000C000"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][10]\(9),
      I1 => \m_axis_rq_thead_d_ff[0][9]_i_2_0\(9),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \m_axis_rq_thead_d_ff[0][9]_i_3_n_0\
    );
m_axis_rq_tlast_d_ff_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABA8"
    )
        port map (
      I0 => m_axis_rq_tlast_d_nxt,
      I1 => m_axis_rq_tlast_d_ff_i_3_n_0,
      I2 => m_axis_rq_tlast_d_ff_i_4_n_0,
      I3 => D(76),
      O => m_axis_rq_tlast_d_ff_reg
    );
m_axis_rq_tlast_d_ff_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4400C800"
    )
        port map (
      I0 => reqdtlpSm512_cs(1),
      I1 => rdIssued_s01,
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => m_axis_rq_tlast_d_ff_i_3_n_0
    );
m_axis_rq_tlast_d_ff_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000C8"
    )
        port map (
      I0 => p_0_in123_out,
      I1 => rdIssued_s01,
      I2 => wrreq,
      I3 => reqdtlpSm512_cs(0),
      I4 => reqdtlpSm_cs(1),
      I5 => reqdtlpSm512_cs(1),
      O => m_axis_rq_tlast_d_ff_i_4_n_0
    );
\m_axis_rq_tuser_comb_ff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I1 => \wr_user__0\(0),
      I2 => \m_axis_rq_tuser_d_ff[0][0]_i_3_n_0\,
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_d_ff[0][0]_i_2_n_0\,
      O => \wpl_hdr_fbe_ff_reg[3]\(0)
    );
\m_axis_rq_tuser_comb_ff[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I1 => \wr_user__0\(1),
      I2 => \m_axis_rq_tuser_d_ff[0][1]_i_3_n_0\,
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_d_ff[0][1]_i_2_n_0\,
      O => \wpl_hdr_fbe_ff_reg[3]\(1)
    );
\m_axis_rq_tuser_comb_ff[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => wr_user(1),
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\,
      I2 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I3 => D(72),
      I4 => \m_axis_rq_tuser_comb_ff[24]_i_4_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(4)
    );
\m_axis_rq_tuser_comb_ff[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => wrreq,
      I1 => p_0_in123_out,
      I2 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I3 => reqdtlpSm_cs(1),
      I4 => reqdtlpSm512_cs(0),
      O => \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[24]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D0D0FFD000000000"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(1),
      I3 => beatdone,
      I4 => p_0_in123_out,
      I5 => \reqdtlpSm_cs[0]_i_4_n_0\,
      O => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\
    );
\m_axis_rq_tuser_comb_ff[24]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFEFEFF"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => reqdtlpSm_cs(1),
      I2 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I3 => wrreq,
      I4 => p_0_in123_out,
      I5 => wtlp_dat_vld6_in(0),
      O => \m_axis_rq_tuser_comb_ff[24]_i_4_n_0\
    );
\m_axis_rq_tuser_comb_ff[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => wr_user(2),
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\,
      I2 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I3 => D(73),
      I4 => \m_axis_rq_tuser_comb_ff[24]_i_4_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(5)
    );
\m_axis_rq_tuser_comb_ff[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBAAA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[26]_i_2_n_0\,
      I1 => p_0_in123_out,
      I2 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I3 => \m_axis_rq_tuser_comb_ff[26]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_comb_ff[26]_i_4_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(6)
    );
\m_axis_rq_tuser_comb_ff[26]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF280028002800"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff_reg[26]\,
      I1 => \beatrem_ff_reg[9]\(0),
      I2 => \beatrem_ff_reg[9]\(1),
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\,
      I4 => D(74),
      I5 => \m_axis_rq_tuser_comb_ff[26]_i_5_n_0\,
      O => \m_axis_rq_tuser_comb_ff[26]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[26]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000022A222A2"
    )
        port map (
      I0 => D(74),
      I1 => m_axis_rq_tvalid_d_ff,
      I2 => full_ff_reg_n_0,
      I3 => force_ready_flush_ff,
      I4 => wr_user(3),
      I5 => wrreq,
      O => \m_axis_rq_tuser_comb_ff[26]_i_3_n_0\
    );
\m_axis_rq_tuser_comb_ff[26]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0808"
    )
        port map (
      I0 => wr_user(3),
      I1 => \reqdtlpSm_cs[0]_i_4_n_0\,
      I2 => \reqdtlpSm512_cs_reg[2]_0\,
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_comb_ff[26]_i_6_n_0\,
      O => \m_axis_rq_tuser_comb_ff[26]_i_4_n_0\
    );
\m_axis_rq_tuser_comb_ff[26]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22A2"
    )
        port map (
      I0 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I1 => m_axis_rq_tvalid_d_ff,
      I2 => full_ff_reg_n_0,
      I3 => force_ready_flush_ff,
      O => \m_axis_rq_tuser_comb_ff[26]_i_5_n_0\
    );
\m_axis_rq_tuser_comb_ff[26]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222200002222F022"
    )
        port map (
      I0 => D(74),
      I1 => wtlp_dat_vld6_in(0),
      I2 => wr_user(3),
      I3 => wrreq,
      I4 => \m_axis_rq_thead_d_ff_reg[0][0]\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_comb_ff[26]_i_6_n_0\
    );
\m_axis_rq_tuser_comb_ff[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
        port map (
      I0 => wr_user(4),
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_2_n_0\,
      I2 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I3 => D(75),
      I4 => \m_axis_rq_tuser_comb_ff[24]_i_4_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(7)
    );
\m_axis_rq_tuser_comb_ff[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I1 => \wr_user__0\(2),
      I2 => \m_axis_rq_tuser_d_ff[0][2]_i_3_n_0\,
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_d_ff[0][2]_i_2_n_0\,
      O => \wpl_hdr_fbe_ff_reg[3]\(2)
    );
\m_axis_rq_tuser_comb_ff[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I1 => \wr_user__0\(3),
      I2 => \m_axis_rq_tuser_d_ff[0][3]_i_3_n_0\,
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => \m_axis_rq_tuser_d_ff[0][3]_i_2_n_0\,
      O => \wpl_hdr_fbe_ff_reg[3]\(3)
    );
\m_axis_rq_tuser_comb_ff[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[4]_i_2_n_0\,
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I2 => \wr_user__0\(4),
      I3 => \m_axis_rq_tuser_comb_ff[4]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wpl_hdr_lbe_ff_reg[0]\
    );
\m_axis_rq_tuser_comb_ff[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => D(68),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(0),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_comb_ff[4]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => D(68),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(0),
      I4 => \wr_user__0\(4),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_comb_ff[4]_i_3_n_0\
    );
\m_axis_rq_tuser_comb_ff[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[5]_i_2_n_0\,
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I2 => \wr_user__0\(5),
      I3 => \m_axis_rq_tuser_comb_ff[5]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wpl_hdr_lbe_ff_reg[1]\
    );
\m_axis_rq_tuser_comb_ff[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => D(69),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(1),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_comb_ff[5]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => D(69),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(1),
      I4 => \wr_user__0\(5),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_comb_ff[5]_i_3_n_0\
    );
\m_axis_rq_tuser_comb_ff[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[6]_i_2_n_0\,
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I2 => \wr_user__0\(6),
      I3 => \m_axis_rq_tuser_comb_ff[6]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wpl_hdr_lbe_ff_reg[2]\
    );
\m_axis_rq_tuser_comb_ff[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => D(70),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(2),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_comb_ff[6]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => D(70),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(2),
      I4 => \wr_user__0\(6),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_comb_ff[6]_i_3_n_0\
    );
\m_axis_rq_tuser_comb_ff[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_comb_ff[7]_i_2_n_0\,
      I1 => \m_axis_rq_tuser_comb_ff[24]_i_3_n_0\,
      I2 => \wr_user__0\(7),
      I3 => \m_axis_rq_tuser_comb_ff[7]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wpl_hdr_lbe_ff_reg[3]\
    );
\m_axis_rq_tuser_comb_ff[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => D(71),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(3),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_comb_ff[7]_i_2_n_0\
    );
\m_axis_rq_tuser_comb_ff[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => D(71),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_comb_ff_reg[7]\(3),
      I4 => \wr_user__0\(7),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_comb_ff[7]_i_3_n_0\
    );
\m_axis_rq_tuser_d_ff[0][0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff[0][0]_i_2_n_0\,
      I1 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I2 => \wr_user__0\(0),
      I3 => \m_axis_rq_tuser_d_ff[0][0]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(0)
    );
\m_axis_rq_tuser_d_ff[0][0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff_reg[0][3]\(0),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(0),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_d_ff[0][0]_i_2_n_0\
    );
\m_axis_rq_tuser_d_ff[0][0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => \m_axis_rq_tuser_d_ff_reg[0][3]\(0),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(0),
      I4 => \wr_user__0\(0),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_d_ff[0][0]_i_3_n_0\
    );
\m_axis_rq_tuser_d_ff[0][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff[0][1]_i_2_n_0\,
      I1 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I2 => \wr_user__0\(1),
      I3 => \m_axis_rq_tuser_d_ff[0][1]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(1)
    );
\m_axis_rq_tuser_d_ff[0][1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff_reg[0][3]\(1),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(1),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_d_ff[0][1]_i_2_n_0\
    );
\m_axis_rq_tuser_d_ff[0][1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => \m_axis_rq_tuser_d_ff_reg[0][3]\(1),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(1),
      I4 => \wr_user__0\(1),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_d_ff[0][1]_i_3_n_0\
    );
\m_axis_rq_tuser_d_ff[0][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff[0][2]_i_2_n_0\,
      I1 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I2 => \wr_user__0\(2),
      I3 => \m_axis_rq_tuser_d_ff[0][2]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(2)
    );
\m_axis_rq_tuser_d_ff[0][2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff_reg[0][3]\(2),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(2),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_d_ff[0][2]_i_2_n_0\
    );
\m_axis_rq_tuser_d_ff[0][2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => \m_axis_rq_tuser_d_ff_reg[0][3]\(2),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(2),
      I4 => \wr_user__0\(2),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_d_ff[0][2]_i_3_n_0\
    );
\m_axis_rq_tuser_d_ff[0][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAEAFFEA"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff[0][3]_i_2_n_0\,
      I1 => \m_axis_rq_thead_d_ff[0][32]_i_3_n_0\,
      I2 => \wr_user__0\(3),
      I3 => \m_axis_rq_tuser_d_ff[0][3]_i_3_n_0\,
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \m_axis_rq_tuser_d_nxt[0]__0\(3)
    );
\m_axis_rq_tuser_d_ff[0][3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF08080808080808"
    )
        port map (
      I0 => \m_axis_rq_tuser_d_ff_reg[0][3]\(3),
      I1 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(3),
      I4 => \m_axis_rq_thead_d_ff[0][32]_i_2_n_0\,
      I5 => p_0_in123_out,
      O => \m_axis_rq_tuser_d_ff[0][3]_i_2_n_0\
    );
\m_axis_rq_tuser_d_ff[0][3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I1 => \m_axis_rq_tuser_d_ff_reg[0][3]\(3),
      I2 => \m_axis_rq_thead_d_ff_reg[0][2]\,
      I3 => \m_axis_rq_tuser_d_ff_reg[0][3]_0\(3),
      I4 => \wr_user__0\(3),
      I5 => \m_axis_rq_thead_d_ff_reg[0][2]_0\,
      O => \m_axis_rq_tuser_d_ff[0][3]_i_3_n_0\
    );
m_axis_rq_tvalid_d_ff_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => m_axis_rq_tvalid_d_ff_reg_0,
      I1 => m_axis_rq_tvalid_d_ff_i_3_n_0,
      I2 => m_axis_rq_tvalid_d_ff,
      O => m_axis_rq_tvalid_d_ff_reg
    );
m_axis_rq_tvalid_d_ff_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008C000F00"
    )
        port map (
      I0 => beatdone,
      I1 => wtlp_dat_vld6_in(0),
      I2 => reqdtlpSm512_cs(0),
      I3 => rdIssued_s01,
      I4 => reqdtlpSm512_cs(1),
      I5 => reqdtlpSm_cs(1),
      O => m_axis_rq_tvalid_d_ff_i_3_n_0
    );
\rdIssued_ff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => rdIssued_s01,
      I2 => reqdtlpSm512_cs(1),
      I3 => reqdtlpSm_cs(1),
      I4 => wtlp_dat_vld6_in(0),
      O => \^rdissued_0\
    );
\reqdtlpSm512_cs[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAAFFFEAAAA"
    )
        port map (
      I0 => \^reqdtlpsm_cs_reg[0]_0\,
      I1 => \reqdtlpSm512_cs[0]_i_2_n_0\,
      I2 => \reqdtlpSm512_cs[0]_i_3_n_0\,
      I3 => \reqdtlpSm512_cs[0]_i_4_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_5_n_0\,
      I5 => \reqdtlpSm512_cs[0]_i_6_n_0\,
      O => wpl_hdr_btlene1_ff_reg
    );
\reqdtlpSm512_cs[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAFAAAAAAAAAAAA"
    )
        port map (
      I0 => \^wtlp_hdr_rd_ff0\,
      I1 => \m_axis_rq_thead_d_ff_reg[0][0]\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => wrreq,
      I4 => \reqdtlpSm512_cs_reg[2]_0\,
      I5 => reqdtlpSm_cs(1),
      O => \reqdtlpSm512_cs[0]_i_10_n_0\
    );
\reqdtlpSm512_cs[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080800000008"
    )
        port map (
      I0 => reqdtlpSm512_cs(1),
      I1 => \reqdtlpSm512_cs_reg[2]_0\,
      I2 => wtlp_dat_vld6_in(0),
      I3 => p_0_in123_out,
      I4 => wrreq,
      I5 => \m_axis_rq_thead_d_ff_reg[0][0]\,
      O => \reqdtlpSm512_cs[0]_i_13_n_0\
    );
\reqdtlpSm512_cs[0]_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF8F88"
    )
        port map (
      I0 => \reqdtlpSm512_cs[0]_i_17_n_0\,
      I1 => reqdtlpSm_cs(1),
      I2 => beatdone,
      I3 => \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_18_n_0\,
      O => \reqdtlpSm512_cs[0]_i_14_n_0\
    );
\reqdtlpSm512_cs[0]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => rdIssued_s01,
      I2 => reqdtlpSm512_cs(1),
      I3 => reqdtlpSm_cs(1),
      I4 => wtlp_dat_vld6_in(0),
      O => \reqdtlpSm512_cs[0]_i_15_n_0\
    );
\reqdtlpSm512_cs[0]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000A200"
    )
        port map (
      I0 => m_axis_rq_tvalid_d_ff,
      I1 => full_ff_reg_n_0,
      I2 => force_ready_flush_ff,
      I3 => reqdtlpSm512_cs(1),
      I4 => reqdtlpSm_cs(1),
      O => \reqdtlpSm512_cs[0]_i_16_n_0\
    );
\reqdtlpSm512_cs[0]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => wtlp_dat_vld6_in(0),
      I1 => reqdtlpSm512_cs(1),
      I2 => rdIssued_s01,
      O => \reqdtlpSm512_cs[0]_i_17_n_0\
    );
\reqdtlpSm512_cs[0]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555D0000"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => reqdtlpSm512_cs(1),
      I2 => reqdtlpSm_cs(1),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm512_cs(1),
      O => \reqdtlpSm512_cs[0]_i_18_n_0\
    );
\reqdtlpSm512_cs[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000FE"
    )
        port map (
      I0 => \reqdtlpSm_cs[0]_i_2_n_0\,
      I1 => \reqdtlpSm512_cs[0]_i_7_n_0\,
      I2 => \reqdtlpSm512_cs[0]_i_8_n_0\,
      I3 => \reqdtlpSm512_cs[0]_i_9_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_10_n_0\,
      I5 => wpl_hdr_btlene1_ff,
      O => \reqdtlpSm512_cs[0]_i_2_n_0\
    );
\reqdtlpSm512_cs[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000AAA8"
    )
        port map (
      I0 => rdIssued_s10,
      I1 => \reqdtlpSm_cs[0]_i_2_n_0\,
      I2 => \reqdtlpSm512_cs[0]_i_7_n_0\,
      I3 => \reqdtlpSm512_cs[0]_i_8_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_9_n_0\,
      I5 => \reqdtlpSm512_cs[0]_i_10_n_0\,
      O => \reqdtlpSm512_cs[0]_i_3_n_0\
    );
\reqdtlpSm512_cs[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEE000000000"
    )
        port map (
      I0 => \reqdtlpSm512_cs[0]_i_9_n_0\,
      I1 => \reqdtlpSm512_cs[0]_i_10_n_0\,
      I2 => \reqdtlpSm_cs[0]_i_2_n_0\,
      I3 => \reqdtlpSm512_cs[0]_i_7_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_8_n_0\,
      I5 => p_0_in116_out,
      O => \reqdtlpSm512_cs[0]_i_4_n_0\
    );
\reqdtlpSm512_cs[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFEEEFEEEFFFF"
    )
        port map (
      I0 => \reqdtlpSm512_cs[0]_i_10_n_0\,
      I1 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I2 => reqdtlpSm_cs(1),
      I3 => \reqdtlpSm512_cs[2]_i_2_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_13_n_0\,
      I5 => \reqdtlpSm512_cs[0]_i_14_n_0\,
      O => \reqdtlpSm512_cs[0]_i_5_n_0\
    );
\reqdtlpSm512_cs[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEE000000000"
    )
        port map (
      I0 => \reqdtlpSm512_cs[0]_i_9_n_0\,
      I1 => \reqdtlpSm512_cs[0]_i_10_n_0\,
      I2 => \reqdtlpSm_cs[0]_i_2_n_0\,
      I3 => \reqdtlpSm512_cs[0]_i_7_n_0\,
      I4 => \reqdtlpSm512_cs[0]_i_8_n_0\,
      I5 => wrreq,
      O => \reqdtlpSm512_cs[0]_i_6_n_0\
    );
\reqdtlpSm512_cs[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0F2F0F0F0F0F0"
    )
        port map (
      I0 => \reqdtlpSm512_cs_reg[2]_0\,
      I1 => beatdone,
      I2 => \reqdtlpSm512_cs[0]_i_15_n_0\,
      I3 => rdIssued_s01,
      I4 => wrreq,
      I5 => \reqdtlpSm512_cs[0]_i_16_n_0\,
      O => \reqdtlpSm512_cs[0]_i_7_n_0\
    );
\reqdtlpSm512_cs[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00030002"
    )
        port map (
      I0 => p_0_in123_out,
      I1 => reqdtlpSm512_cs(0),
      I2 => reqdtlpSm_cs(1),
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => wrreq,
      O => \reqdtlpSm512_cs[0]_i_8_n_0\
    );
\reqdtlpSm512_cs[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF80AA80AA80AA"
    )
        port map (
      I0 => p_0_in123_out,
      I1 => beatdone,
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_5_n_0\,
      I3 => \reqdtlpSm_cs[0]_i_6_n_0\,
      I4 => reqdtlpSm_cs(1),
      I5 => \reqdtlpSm512_cs[2]_i_2_n_0\,
      O => \reqdtlpSm512_cs[0]_i_9_n_0\
    );
\reqdtlpSm512_cs[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFEFEFCFCFCFC"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_2_n_0\,
      I1 => \reqdtlpSm_cs[0]_i_3_n_0\,
      I2 => \reqdtlpSm512_cs[2]_i_3_n_0\,
      I3 => \reqdtlpSm512_cs[2]_i_4_n_0\,
      I4 => \reqdtlpSm512_cs_reg[2]_0\,
      I5 => reqdtlpSm512_cs(1),
      O => \reqdtlpSm512_cs_reg[2]\
    );
\reqdtlpSm512_cs[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004F0000FFFFFFFF"
    )
        port map (
      I0 => force_ready_flush_ff,
      I1 => full_ff_reg_n_0,
      I2 => m_axis_rq_tvalid_d_ff,
      I3 => reqdtlpSm_cs(1),
      I4 => reqdtlpSm512_cs(1),
      I5 => rdIssued_s01,
      O => \reqdtlpSm512_cs[2]_i_2_n_0\
    );
\reqdtlpSm512_cs[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45000000"
    )
        port map (
      I0 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I1 => force_ready_flush_ff,
      I2 => full_ff_reg_n_0,
      I3 => m_axis_rq_tvalid_d_ff,
      I4 => reqdtlpSm_cs(1),
      O => \reqdtlpSm512_cs[2]_i_3_n_0\
    );
\reqdtlpSm512_cs[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000EEEF"
    )
        port map (
      I0 => reqdtlpSm_cs(1),
      I1 => reqdtlpSm512_cs(0),
      I2 => wrreq,
      I3 => p_0_in123_out,
      I4 => wtlp_dat_vld6_in(0),
      O => \reqdtlpSm512_cs[2]_i_4_n_0\
    );
\reqdtlpSm_cs[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFFFFFEFEFFFE"
    )
        port map (
      I0 => \reqdtlpSm_cs[0]_i_2_n_0\,
      I1 => \reqdtlpSm_cs[0]_i_3_n_0\,
      I2 => \reqdtlpSm_cs[0]_i_4_n_0\,
      I3 => p_0_in123_out,
      I4 => \reqdtlpSm_cs[0]_i_6_n_0\,
      I5 => wrreq,
      O => \^reqdtlpsm_cs_reg[0]_0\
    );
\reqdtlpSm_cs[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"75FF557720000000"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => \reqdtlpSm_cs_reg[0]_1\,
      I2 => p_0_in123_out,
      I3 => wtlp_dat_vld6_in(0),
      I4 => \reqdtlpSm512_cs_reg[2]_0\,
      I5 => reqdtlpSm_cs(0),
      O => \reqdtlpSm_cs[0]_i_2_n_0\
    );
\reqdtlpSm_cs[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400C0000000000"
    )
        port map (
      I0 => beatdone,
      I1 => wtlp_dat_vld6_in(0),
      I2 => reqdtlpSm512_cs(0),
      I3 => reqdtlpSm_cs(1),
      I4 => reqdtlpSm512_cs(1),
      I5 => rdIssued_s01,
      O => \reqdtlpSm_cs[0]_i_3_n_0\
    );
\reqdtlpSm_cs[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => reqdtlpSm_cs(1),
      I1 => reqdtlpSm512_cs(1),
      I2 => wtlp_dat_vld6_in(0),
      I3 => wrreq,
      I4 => rdIssued_s01,
      O => \reqdtlpSm_cs[0]_i_4_n_0\
    );
\reqdtlpSm_cs[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => reqdtlpSm_cs(1),
      I1 => reqdtlpSm512_cs(1),
      I2 => rdIssued_s01,
      I3 => reqdtlpSm512_cs(0),
      O => \reqdtlpSm_cs[0]_i_6_n_0\
    );
\reqdtlpSm_cs[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF8"
    )
        port map (
      I0 => \reqdtlpSm512_cs[2]_i_2_n_0\,
      I1 => reqdtlpSm_cs(1),
      I2 => \m_axis_rq_thead_d_ff[0][63]_i_3_n_0\,
      I3 => \reqdtlpSm_cs[1]_i_2_n_0\,
      I4 => \^wtlp_hdr_rd_ff0\,
      O => \reqdtlpSm_cs_reg[1]_0\
    );
\reqdtlpSm_cs[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0022002200AA0002"
    )
        port map (
      I0 => reqdtlpSm_cs(1),
      I1 => reqdtlpSm512_cs(1),
      I2 => wrreq,
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm512_cs(0),
      I5 => reqdtlpSm_cs(1),
      O => \reqdtlpSm_cs[1]_i_2_n_0\
    );
\rreq_head_info_ff[0][adr][10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(8),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(25),
      O => \rreq_head_info_ff_reg[1][adr][63]\(8)
    );
\rreq_head_info_ff[0][adr][11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(9),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(26),
      O => \rreq_head_info_ff_reg[1][adr][63]\(9)
    );
\rreq_head_info_ff[0][adr][12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(10),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(27),
      O => \rreq_head_info_ff_reg[1][adr][63]\(10)
    );
\rreq_head_info_ff[0][adr][13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(11),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(28),
      O => \rreq_head_info_ff_reg[1][adr][63]\(11)
    );
\rreq_head_info_ff[0][adr][14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(12),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(29),
      O => \rreq_head_info_ff_reg[1][adr][63]\(12)
    );
\rreq_head_info_ff[0][adr][15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(13),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(30),
      O => \rreq_head_info_ff_reg[1][adr][63]\(13)
    );
\rreq_head_info_ff[0][adr][16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(14),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(31),
      O => \rreq_head_info_ff_reg[1][adr][63]\(14)
    );
\rreq_head_info_ff[0][adr][17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(15),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(32),
      O => \rreq_head_info_ff_reg[1][adr][63]\(15)
    );
\rreq_head_info_ff[0][adr][18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(16),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(33),
      O => \rreq_head_info_ff_reg[1][adr][63]\(16)
    );
\rreq_head_info_ff[0][adr][19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(17),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(34),
      O => \rreq_head_info_ff_reg[1][adr][63]\(17)
    );
\rreq_head_info_ff[0][adr][20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(18),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(35),
      O => \rreq_head_info_ff_reg[1][adr][63]\(18)
    );
\rreq_head_info_ff[0][adr][21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(19),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(36),
      O => \rreq_head_info_ff_reg[1][adr][63]\(19)
    );
\rreq_head_info_ff[0][adr][22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(20),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(37),
      O => \rreq_head_info_ff_reg[1][adr][63]\(20)
    );
\rreq_head_info_ff[0][adr][23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(21),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(38),
      O => \rreq_head_info_ff_reg[1][adr][63]\(21)
    );
\rreq_head_info_ff[0][adr][24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(22),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(39),
      O => \rreq_head_info_ff_reg[1][adr][63]\(22)
    );
\rreq_head_info_ff[0][adr][25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(23),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(40),
      O => \rreq_head_info_ff_reg[1][adr][63]\(23)
    );
\rreq_head_info_ff[0][adr][26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(24),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(41),
      O => \rreq_head_info_ff_reg[1][adr][63]\(24)
    );
\rreq_head_info_ff[0][adr][27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(25),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(42),
      O => \rreq_head_info_ff_reg[1][adr][63]\(25)
    );
\rreq_head_info_ff[0][adr][28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(26),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(43),
      O => \rreq_head_info_ff_reg[1][adr][63]\(26)
    );
\rreq_head_info_ff[0][adr][29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(27),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(44),
      O => \rreq_head_info_ff_reg[1][adr][63]\(27)
    );
\rreq_head_info_ff[0][adr][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(17),
      O => \rreq_head_info_ff_reg[1][adr][63]\(0)
    );
\rreq_head_info_ff[0][adr][30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(28),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(45),
      O => \rreq_head_info_ff_reg[1][adr][63]\(28)
    );
\rreq_head_info_ff[0][adr][31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(29),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(46),
      O => \rreq_head_info_ff_reg[1][adr][63]\(29)
    );
\rreq_head_info_ff[0][adr][32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(30),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(47),
      O => \rreq_head_info_ff_reg[1][adr][63]\(30)
    );
\rreq_head_info_ff[0][adr][33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(31),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(48),
      O => \rreq_head_info_ff_reg[1][adr][63]\(31)
    );
\rreq_head_info_ff[0][adr][34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(32),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(49),
      O => \rreq_head_info_ff_reg[1][adr][63]\(32)
    );
\rreq_head_info_ff[0][adr][35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(33),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(50),
      O => \rreq_head_info_ff_reg[1][adr][63]\(33)
    );
\rreq_head_info_ff[0][adr][36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(34),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(51),
      O => \rreq_head_info_ff_reg[1][adr][63]\(34)
    );
\rreq_head_info_ff[0][adr][37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(35),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(52),
      O => \rreq_head_info_ff_reg[1][adr][63]\(35)
    );
\rreq_head_info_ff[0][adr][38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(36),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(53),
      O => \rreq_head_info_ff_reg[1][adr][63]\(36)
    );
\rreq_head_info_ff[0][adr][39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(37),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(54),
      O => \rreq_head_info_ff_reg[1][adr][63]\(37)
    );
\rreq_head_info_ff[0][adr][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(18),
      O => \rreq_head_info_ff_reg[1][adr][63]\(1)
    );
\rreq_head_info_ff[0][adr][40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(38),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(55),
      O => \rreq_head_info_ff_reg[1][adr][63]\(38)
    );
\rreq_head_info_ff[0][adr][41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(39),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(56),
      O => \rreq_head_info_ff_reg[1][adr][63]\(39)
    );
\rreq_head_info_ff[0][adr][42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(40),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(57),
      O => \rreq_head_info_ff_reg[1][adr][63]\(40)
    );
\rreq_head_info_ff[0][adr][43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(41),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(58),
      O => \rreq_head_info_ff_reg[1][adr][63]\(41)
    );
\rreq_head_info_ff[0][adr][44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(42),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(59),
      O => \rreq_head_info_ff_reg[1][adr][63]\(42)
    );
\rreq_head_info_ff[0][adr][45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(43),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(60),
      O => \rreq_head_info_ff_reg[1][adr][63]\(43)
    );
\rreq_head_info_ff[0][adr][46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(44),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(61),
      O => \rreq_head_info_ff_reg[1][adr][63]\(44)
    );
\rreq_head_info_ff[0][adr][47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(45),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(62),
      O => \rreq_head_info_ff_reg[1][adr][63]\(45)
    );
\rreq_head_info_ff[0][adr][48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(46),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(63),
      O => \rreq_head_info_ff_reg[1][adr][63]\(46)
    );
\rreq_head_info_ff[0][adr][49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(47),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(64),
      O => \rreq_head_info_ff_reg[1][adr][63]\(47)
    );
\rreq_head_info_ff[0][adr][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(19),
      O => \rreq_head_info_ff_reg[1][adr][63]\(2)
    );
\rreq_head_info_ff[0][adr][50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(48),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(65),
      O => \rreq_head_info_ff_reg[1][adr][63]\(48)
    );
\rreq_head_info_ff[0][adr][51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(49),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(66),
      O => \rreq_head_info_ff_reg[1][adr][63]\(49)
    );
\rreq_head_info_ff[0][adr][52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(50),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(67),
      O => \rreq_head_info_ff_reg[1][adr][63]\(50)
    );
\rreq_head_info_ff[0][adr][53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(51),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(68),
      O => \rreq_head_info_ff_reg[1][adr][63]\(51)
    );
\rreq_head_info_ff[0][adr][54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(52),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(69),
      O => \rreq_head_info_ff_reg[1][adr][63]\(52)
    );
\rreq_head_info_ff[0][adr][55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(53),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(70),
      O => \rreq_head_info_ff_reg[1][adr][63]\(53)
    );
\rreq_head_info_ff[0][adr][56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(54),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(71),
      O => \rreq_head_info_ff_reg[1][adr][63]\(54)
    );
\rreq_head_info_ff[0][adr][57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(55),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(72),
      O => \rreq_head_info_ff_reg[1][adr][63]\(55)
    );
\rreq_head_info_ff[0][adr][58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(56),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(73),
      O => \rreq_head_info_ff_reg[1][adr][63]\(56)
    );
\rreq_head_info_ff[0][adr][59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(57),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(74),
      O => \rreq_head_info_ff_reg[1][adr][63]\(57)
    );
\rreq_head_info_ff[0][adr][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(3),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(20),
      O => \rreq_head_info_ff_reg[1][adr][63]\(3)
    );
\rreq_head_info_ff[0][adr][60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(58),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(75),
      O => \rreq_head_info_ff_reg[1][adr][63]\(58)
    );
\rreq_head_info_ff[0][adr][61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(59),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(76),
      O => \rreq_head_info_ff_reg[1][adr][63]\(59)
    );
\rreq_head_info_ff[0][adr][62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(60),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(77),
      O => \rreq_head_info_ff_reg[1][adr][63]\(60)
    );
\rreq_head_info_ff[0][adr][63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(61),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(78),
      O => \rreq_head_info_ff_reg[1][adr][63]\(61)
    );
\rreq_head_info_ff[0][adr][6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(4),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(21),
      O => \rreq_head_info_ff_reg[1][adr][63]\(4)
    );
\rreq_head_info_ff[0][adr][7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(5),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(22),
      O => \rreq_head_info_ff_reg[1][adr][63]\(5)
    );
\rreq_head_info_ff[0][adr][8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(6),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(23),
      O => \rreq_head_info_ff_reg[1][adr][63]\(6)
    );
\rreq_head_info_ff[0][adr][9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][adr][63]_0\(7),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(24),
      O => \rreq_head_info_ff_reg[1][adr][63]\(7)
    );
\rreq_head_info_ff[0][chn][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[1][chn]\,
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(79),
      O => \rreq_head_info_nxt[0][chn]\
    );
\rreq_head_info_ff[0][did][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(0),
      O => \rreq_head_info_ff_reg[1][did][8]\(0)
    );
\rreq_head_info_ff[0][did][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(1),
      O => \rreq_head_info_ff_reg[1][did][8]\(1)
    );
\rreq_head_info_ff[0][did][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(2),
      O => \rreq_head_info_ff_reg[1][did][8]\(2)
    );
\rreq_head_info_ff[0][did][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(3),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(3),
      O => \rreq_head_info_ff_reg[1][did][8]\(3)
    );
\rreq_head_info_ff[0][did][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(4),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(4),
      O => \rreq_head_info_ff_reg[1][did][8]\(4)
    );
\rreq_head_info_ff[0][did][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(5),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(5),
      O => \rreq_head_info_ff_reg[1][did][8]\(5)
    );
\rreq_head_info_ff[0][did][6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(6),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(6),
      O => \rreq_head_info_ff_reg[1][did][8]\(6)
    );
\rreq_head_info_ff[0][did][7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(7),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(7),
      O => \rreq_head_info_ff_reg[1][did][8]\(7)
    );
\rreq_head_info_ff[0][did][8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][did][8]\(8),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(8),
      O => \rreq_head_info_ff_reg[1][did][8]\(8)
    );
\rreq_head_info_ff[0][fbe][0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"888B"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][fbe][3]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(15),
      I3 => \rreq_head_info_ff_reg[0][chn][0]\(16),
      O => \rreq_head_info_ff_reg[1][fbe][3]\(0)
    );
\rreq_head_info_ff[0][fbe][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][fbe][3]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][fbe][3]_0\(0),
      O => \rreq_head_info_ff_reg[1][fbe][3]\(1)
    );
\rreq_head_info_ff[0][lbe][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][lbe][2]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][lbe][0]\,
      O => \rreq_head_info_ff_reg[1][lbe][2]\(0)
    );
\rreq_head_info_ff[0][lbe][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][lbe][2]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][lbe][2]_0\(0),
      O => \rreq_head_info_ff_reg[1][lbe][2]\(1)
    );
\rreq_head_info_ff[0][lbe][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][lbe][2]\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][lbe][2]_0\(1),
      O => \rreq_head_info_ff_reg[1][lbe][2]\(2)
    );
\rreq_head_info_ff[0][len][10]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(10),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(10),
      O => \rreq_head_info_ff[0][len][10]_i_2_n_0\
    );
\rreq_head_info_ff[0][len][10]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(9),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(9),
      O => \rreq_head_info_ff[0][len][10]_i_3_n_0\
    );
\rreq_head_info_ff[0][len][10]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(8),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(8),
      O => \rreq_head_info_ff[0][len][10]_i_4_n_0\
    );
\rreq_head_info_ff[0][len][3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(3),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(3),
      O => \rreq_head_info_ff[0][len][3]_i_3_n_0\
    );
\rreq_head_info_ff[0][len][3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(2),
      O => \rreq_head_info_ff[0][len][3]_i_4_n_0\
    );
\rreq_head_info_ff[0][len][3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(1),
      O => \rreq_head_info_ff[0][len][3]_i_5_n_0\
    );
\rreq_head_info_ff[0][len][3]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(0),
      O => \rreq_head_info_ff[0][len][3]_i_6_n_0\
    );
\rreq_head_info_ff[0][len][7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(7),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(7),
      O => \rreq_head_info_ff[0][len][7]_i_2_n_0\
    );
\rreq_head_info_ff[0][len][7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(6),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(6),
      O => \rreq_head_info_ff[0][len][7]_i_3_n_0\
    );
\rreq_head_info_ff[0][len][7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(5),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(5),
      O => \rreq_head_info_ff[0][len][7]_i_4_n_0\
    );
\rreq_head_info_ff[0][len][7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][len][10]\(4),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => A(4),
      O => \rreq_head_info_ff[0][len][7]_i_5_n_0\
    );
\rreq_head_info_ff[0][rcb][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB8F0B800B8F0B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(0),
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][0]\,
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_info_ff_reg[1][rcb]\(0),
      O => \^rreq_head_info_nxt[0][rcb]\(0)
    );
\rreq_head_info_ff[0][rcb][1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB8F0B800B8F0B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(1),
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][1]\,
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_info_ff_reg[1][rcb]\(1),
      O => \^rreq_head_info_nxt[0][rcb]\(1)
    );
\rreq_head_info_ff[0][rcb][2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB8F0B800B8F0B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(2),
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][2]\,
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_info_ff_reg[1][rcb]\(2),
      O => \^rreq_head_info_nxt[0][rcb]\(2)
    );
\rreq_head_info_ff[0][rcb][3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB8F0B800B8F0B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(3),
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][3]\,
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_info_ff_reg[1][rcb]\(3),
      O => \^rreq_head_info_nxt[0][rcb]\(3)
    );
\rreq_head_info_ff[0][rcb][4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB8F0B800B8F0B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(4),
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][4]\,
      I3 => \^rdissued_0\,
      I4 => \canissueRd_ff_reg[0]_0\(1),
      I5 => \rreq_head_info_ff_reg[1][rcb]\(4),
      O => \^rreq_head_info_nxt[0][rcb]\(4)
    );
\rreq_head_info_ff[0][rcb][5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFE22E0000E22E"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(5),
      I1 => \rreq_head_vld_ff[0]_i_3_n_0\,
      I2 => \rreq_head_info_ff_reg[0][rcb][7]_0\(0),
      I3 => \rreq_head_info_ff_reg[0][rcb][5]\,
      I4 => \^reqdtlpsm_cs_reg[1]\,
      I5 => \rreq_head_info_ff_reg[1][rcb]\(5),
      O => \^rreq_head_info_nxt[0][rcb]\(5)
    );
\rreq_head_info_ff[0][rcb][6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEBEEAAAA"
    )
        port map (
      I0 => \rreq_head_info_ff[0][rcb][6]_i_2_n_0\,
      I1 => \rreq_head_info_ff_reg[0][rcb][7]_1\(0),
      I2 => \rreq_head_info_ff_reg[0][rcb][5]\,
      I3 => \rreq_head_info_ff_reg[0][rcb][7]_0\(0),
      I4 => \rreq_head_info_ff[0][rcb][7]_i_6_n_0\,
      I5 => \rreq_head_info_ff[0][rcb][6]_i_3_n_0\,
      O => \^rreq_head_info_nxt[0][rcb]\(6)
    );
\rreq_head_info_ff[0][rcb][6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(6),
      I1 => \^rdissued_0\,
      I2 => \canissueRd_ff_reg[0]_0\(0),
      O => \rreq_head_info_ff[0][rcb][6]_i_2_n_0\
    );
\rreq_head_info_ff[0][rcb][6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[1][rcb]\(6),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      O => \rreq_head_info_ff[0][rcb][6]_i_3_n_0\
    );
\rreq_head_info_ff[0][rcb][7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBAAAAAAA"
    )
        port map (
      I0 => \rreq_head_info_ff[0][rcb][7]_i_2_n_0\,
      I1 => \rreq_head_info_ff_reg[0][rcb][5]\,
      I2 => \rreq_head_info_ff_reg[0][rcb][7]_0\(0),
      I3 => \rreq_head_info_ff_reg[0][rcb][7]_1\(0),
      I4 => \rreq_head_info_ff[0][rcb][7]_i_6_n_0\,
      I5 => \rreq_head_info_ff[0][rcb][7]_i_7_n_0\,
      O => \^rreq_head_info_nxt[0][rcb]\(7)
    );
\rreq_head_info_ff[0][rcb][7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(7),
      I1 => \^rdissued_0\,
      I2 => \canissueRd_ff_reg[0]_0\(0),
      O => \rreq_head_info_ff[0][rcb][7]_i_2_n_0\
    );
\rreq_head_info_ff[0][rcb][7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"35"
    )
        port map (
      I0 => \canissueRd_ff_reg[0]_0\(0),
      I1 => \canissueRd_ff_reg[0]_0\(1),
      I2 => \^rdissued_0\,
      O => \rreq_head_info_ff[0][rcb][7]_i_6_n_0\
    );
\rreq_head_info_ff[0][rcb][7]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[1][rcb]\(7),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      O => \rreq_head_info_ff[0][rcb][7]_i_7_n_0\
    );
\rreq_head_info_ff[0][rid][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(9),
      O => \rreq_head_info_ff_reg[1][rid][5]\(0)
    );
\rreq_head_info_ff[0][rid][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(10),
      O => \rreq_head_info_ff_reg[1][rid][5]\(1)
    );
\rreq_head_info_ff[0][rid][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(11),
      O => \rreq_head_info_ff_reg[1][rid][5]\(2)
    );
\rreq_head_info_ff[0][rid][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(3),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(12),
      O => \rreq_head_info_ff_reg[1][rid][5]\(3)
    );
\rreq_head_info_ff[0][rid][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(4),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(13),
      O => \rreq_head_info_ff_reg[1][rid][5]\(4)
    );
\rreq_head_info_ff[0][rid][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rid][5]\(5),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \rreq_head_info_ff_reg[0][chn][0]\(14),
      O => \rreq_head_info_ff_reg[1][rid][5]\(5)
    );
\rreq_head_info_ff[0][tag][0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(0),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => tag_sel_ff,
      O => \rreq_head_info_ff_reg[1][tag][5]\(0)
    );
\rreq_head_info_ff[0][tag][1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(1),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \tag_dout[1]_1\(0),
      I3 => tag_sel_ff,
      I4 => \tag_dout[0]_0\(0),
      O => \rreq_head_info_ff_reg[1][tag][5]\(1)
    );
\rreq_head_info_ff[0][tag][2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(2),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \tag_dout[1]_1\(1),
      I3 => tag_sel_ff,
      I4 => \tag_dout[0]_0\(1),
      O => \rreq_head_info_ff_reg[1][tag][5]\(2)
    );
\rreq_head_info_ff[0][tag][3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(3),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \tag_dout[1]_1\(2),
      I3 => tag_sel_ff,
      I4 => \tag_dout[0]_0\(2),
      O => \rreq_head_info_ff_reg[1][tag][5]\(3)
    );
\rreq_head_info_ff[0][tag][4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(4),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \tag_dout[1]_1\(3),
      I3 => tag_sel_ff,
      I4 => \tag_dout[0]_0\(3),
      O => \rreq_head_info_ff_reg[1][tag][5]\(4)
    );
\rreq_head_info_ff[0][tag][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => \canissueRd_ff_reg[0]_0\(0),
      I1 => \^rdissued_0\,
      O => \rreq_head_vld_ff_reg[0]_1\(0)
    );
\rreq_head_info_ff[0][tag][5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][tag][5]\(5),
      I1 => \^reqdtlpsm_cs_reg[1]\,
      I2 => \tag_dout[1]_1\(4),
      I3 => tag_sel_ff,
      I4 => \tag_dout[0]_0\(4),
      O => \rreq_head_info_ff_reg[1][tag][5]\(5)
    );
\rreq_head_info_ff[1][rcb][7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C2"
    )
        port map (
      I0 => \canissueRd_ff_reg[0]_0\(0),
      I1 => \canissueRd_ff_reg[0]_0\(1),
      I2 => \^rdissued_0\,
      O => rreq_head_ld_new_1
    );
\rreq_head_info_ff_reg[0][len][10]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[0][len][7]_i_1_n_0\,
      CO(3 downto 2) => \NLW_rreq_head_info_ff_reg[0][len][10]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \rreq_head_info_ff_reg[0][len][10]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[0][len][10]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_rreq_head_info_ff_reg[0][len][10]_i_1_O_UNCONNECTED\(3),
      O(2 downto 0) => \out\(10 downto 8),
      S(3) => '0',
      S(2) => \rreq_head_info_ff[0][len][10]_i_2_n_0\,
      S(1) => \rreq_head_info_ff[0][len][10]_i_3_n_0\,
      S(0) => \rreq_head_info_ff[0][len][10]_i_4_n_0\
    );
\rreq_head_info_ff_reg[0][len][3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_info_ff_reg[0][len][3]_i_1_n_0\,
      CO(2) => \rreq_head_info_ff_reg[0][len][3]_i_1_n_1\,
      CO(1) => \rreq_head_info_ff_reg[0][len][3]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[0][len][3]_i_1_n_3\,
      CYINIT => \rreq_head_info_ff_reg[0][len][3]\,
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \out\(3 downto 0),
      S(3) => \rreq_head_info_ff[0][len][3]_i_3_n_0\,
      S(2) => \rreq_head_info_ff[0][len][3]_i_4_n_0\,
      S(1) => \rreq_head_info_ff[0][len][3]_i_5_n_0\,
      S(0) => \rreq_head_info_ff[0][len][3]_i_6_n_0\
    );
\rreq_head_info_ff_reg[0][len][7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_info_ff_reg[0][len][3]_i_1_n_0\,
      CO(3) => \rreq_head_info_ff_reg[0][len][7]_i_1_n_0\,
      CO(2) => \rreq_head_info_ff_reg[0][len][7]_i_1_n_1\,
      CO(1) => \rreq_head_info_ff_reg[0][len][7]_i_1_n_2\,
      CO(0) => \rreq_head_info_ff_reg[0][len][7]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \out\(7 downto 4),
      S(3) => \rreq_head_info_ff[0][len][7]_i_2_n_0\,
      S(2) => \rreq_head_info_ff[0][len][7]_i_3_n_0\,
      S(1) => \rreq_head_info_ff[0][len][7]_i_4_n_0\,
      S(0) => \rreq_head_info_ff[0][len][7]_i_5_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4141414188224411"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(4),
      I1 => \^rreq_head_info_nxt[0][rcb]\(5),
      I2 => \rreq_head_rcb_ok_ff_reg[0]_i_2_0\(0),
      I3 => RcbAvail_nxt0(5),
      I4 => RcbAvail_nxt0(4),
      I5 => RcbAvail_upd_ff,
      O => \rreq_head_rcb_ok_ff[0]_i_10_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00845521"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(3),
      I1 => RcbAvail_nxt0(2),
      I2 => RcbAvail_nxt0(3),
      I3 => RcbAvail_upd_ff,
      I4 => \^rreq_head_info_nxt[0][rcb]\(2),
      O => \rreq_head_rcb_ok_ff[0]_i_11_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00845521"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(1),
      I1 => RcbAvail_nxt0(0),
      I2 => RcbAvail_nxt0(1),
      I3 => RcbAvail_upd_ff,
      I4 => \^rreq_head_info_nxt[0][rcb]\(0),
      O => \rreq_head_rcb_ok_ff[0]_i_12_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7171713030307130"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(6),
      I1 => \^rreq_head_info_nxt[0][rcb]\(7),
      I2 => RcbAvail_nxt(0),
      I3 => RcbAvail_nxt0(6),
      I4 => RcbAvail_upd_ff,
      I5 => \rreq_head_rcb_ok_ff_reg[0]_i_2_0\(1),
      O => \rreq_head_rcb_ok_ff[0]_i_5_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F004F4F0F000404"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(4),
      I1 => RcbAvail_nxt0(4),
      I2 => \^rreq_head_info_nxt[0][rcb]\(5),
      I3 => \rreq_head_rcb_ok_ff_reg[0]_i_2_0\(0),
      I4 => RcbAvail_upd_ff,
      I5 => RcbAvail_nxt0(5),
      O => \rreq_head_rcb_ok_ff[0]_i_6_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07010500"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(3),
      I1 => \^rreq_head_info_nxt[0][rcb]\(2),
      I2 => RcbAvail_upd_ff,
      I3 => RcbAvail_nxt0(3),
      I4 => RcbAvail_nxt0(2),
      O => \rreq_head_rcb_ok_ff[0]_i_7_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07010500"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(1),
      I1 => \^rreq_head_info_nxt[0][rcb]\(0),
      I2 => RcbAvail_upd_ff,
      I3 => RcbAvail_nxt0(1),
      I4 => RcbAvail_nxt0(0),
      O => \rreq_head_rcb_ok_ff[0]_i_8_n_0\
    );
\rreq_head_rcb_ok_ff[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8282824141418241"
    )
        port map (
      I0 => \^rreq_head_info_nxt[0][rcb]\(6),
      I1 => \^rreq_head_info_nxt[0][rcb]\(7),
      I2 => RcbAvail_nxt(0),
      I3 => RcbAvail_nxt0(6),
      I4 => RcbAvail_upd_ff,
      I5 => \rreq_head_rcb_ok_ff_reg[0]_i_2_0\(1),
      O => \rreq_head_rcb_ok_ff[0]_i_9_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(7),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(7),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_rcb_ok_ff_reg[1]_i_14_2\,
      O => \rreq_head_rcb_ok_ff[1]_i_16_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(6),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(6),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_rcb_ok_ff_reg[1]_i_14_1\,
      O => \rreq_head_rcb_ok_ff[1]_i_17_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(5),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(5),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_rcb_ok_ff_reg[1]_i_14_0\,
      O => \rreq_head_rcb_ok_ff[1]_i_18_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(4),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(4),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_info_ff_reg[0][rcb][4]\,
      O => \rreq_head_rcb_ok_ff[1]_i_19_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(3),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(3),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_info_ff_reg[0][rcb][3]\,
      O => \rreq_head_rcb_ok_ff[1]_i_20_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(2),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(2),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_info_ff_reg[0][rcb][2]\,
      O => \rreq_head_rcb_ok_ff[1]_i_21_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(1),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(1),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_info_ff_reg[0][rcb][1]\,
      O => \rreq_head_rcb_ok_ff[1]_i_22_n_0\
    );
\rreq_head_rcb_ok_ff[1]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"36353333C6CACCCC"
    )
        port map (
      I0 => \rreq_head_info_ff_reg[0][rcb][7]\(0),
      I1 => \rreq_head_info_ff_reg[1][rcb]\(0),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      I4 => \canissueRd_ff_reg[0]_0\(0),
      I5 => \rreq_head_info_ff_reg[0][rcb][0]\,
      O => \rreq_head_rcb_ok_ff[1]_i_23_n_0\
    );
\rreq_head_rcb_ok_ff_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_rcb_ok_ff_reg[0]_i_2_n_0\,
      CO(3 downto 1) => \NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \RcbAvail_new_ff_reg[9]\(0),
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => DI(0),
      O(3 downto 0) => \NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => S(0)
    );
\rreq_head_rcb_ok_ff_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_rcb_ok_ff_reg[0]_i_2_n_0\,
      CO(2) => \rreq_head_rcb_ok_ff_reg[0]_i_2_n_1\,
      CO(1) => \rreq_head_rcb_ok_ff_reg[0]_i_2_n_2\,
      CO(0) => \rreq_head_rcb_ok_ff_reg[0]_i_2_n_3\,
      CYINIT => '1',
      DI(3) => \rreq_head_rcb_ok_ff[0]_i_5_n_0\,
      DI(2) => \rreq_head_rcb_ok_ff[0]_i_6_n_0\,
      DI(1) => \rreq_head_rcb_ok_ff[0]_i_7_n_0\,
      DI(0) => \rreq_head_rcb_ok_ff[0]_i_8_n_0\,
      O(3 downto 0) => \NLW_rreq_head_rcb_ok_ff_reg[0]_i_2_O_UNCONNECTED\(3 downto 0),
      S(3) => \rreq_head_rcb_ok_ff[0]_i_9_n_0\,
      S(2) => \rreq_head_rcb_ok_ff[0]_i_10_n_0\,
      S(1) => \rreq_head_rcb_ok_ff[0]_i_11_n_0\,
      S(0) => \rreq_head_rcb_ok_ff[0]_i_12_n_0\
    );
\rreq_head_rcb_ok_ff_reg[1]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_rcb_ok_ff_reg[1]_i_14_n_0\,
      CO(3 downto 1) => \NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_CO_UNCONNECTED\(3 downto 1),
      CO(0) => rreq_head_info_both_rcb_nxt(8),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_O_UNCONNECTED\(3 downto 0),
      S(3 downto 0) => B"0001"
    );
\rreq_head_rcb_ok_ff_reg[1]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \rreq_head_rcb_ok_ff_reg[1]_i_15_n_0\,
      CO(3) => \rreq_head_rcb_ok_ff_reg[1]_i_14_n_0\,
      CO(2) => \rreq_head_rcb_ok_ff_reg[1]_i_14_n_1\,
      CO(1) => \rreq_head_rcb_ok_ff_reg[1]_i_14_n_2\,
      CO(0) => \rreq_head_rcb_ok_ff_reg[1]_i_14_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => \^rreq_head_info_nxt[0][rcb]\(7 downto 4),
      O(3 downto 0) => rreq_head_info_both_rcb_nxt(7 downto 4),
      S(3) => \rreq_head_rcb_ok_ff[1]_i_16_n_0\,
      S(2) => \rreq_head_rcb_ok_ff[1]_i_17_n_0\,
      S(1) => \rreq_head_rcb_ok_ff[1]_i_18_n_0\,
      S(0) => \rreq_head_rcb_ok_ff[1]_i_19_n_0\
    );
\rreq_head_rcb_ok_ff_reg[1]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rreq_head_rcb_ok_ff_reg[1]_i_15_n_0\,
      CO(2) => \rreq_head_rcb_ok_ff_reg[1]_i_15_n_1\,
      CO(1) => \rreq_head_rcb_ok_ff_reg[1]_i_15_n_2\,
      CO(0) => \rreq_head_rcb_ok_ff_reg[1]_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => \^rreq_head_info_nxt[0][rcb]\(3 downto 0),
      O(3 downto 0) => rreq_head_info_both_rcb_nxt(3 downto 0),
      S(3) => \rreq_head_rcb_ok_ff[1]_i_20_n_0\,
      S(2) => \rreq_head_rcb_ok_ff[1]_i_21_n_0\,
      S(1) => \rreq_head_rcb_ok_ff[1]_i_22_n_0\,
      S(0) => \rreq_head_rcb_ok_ff[1]_i_23_n_0\
    );
\rreq_head_vld_ff[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAABFBFFFFFFFF"
    )
        port map (
      I0 => \^reqdtlpsm_cs_reg[1]\,
      I1 => tag_ep_0,
      I2 => tag_sel_ff,
      I3 => tag_ep_1,
      I4 => empty_ff_0,
      I5 => \rreq_head_vld_ff[0]_i_3_n_0\,
      O => \rreq_head_vld_ff_reg[0]_0\(0)
    );
\rreq_head_vld_ff[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => wtlp_dat_vld6_in(0),
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(1),
      I3 => rdIssued_s01,
      I4 => reqdtlpSm512_cs(0),
      I5 => \canissueRd_ff_reg[0]_0\(1),
      O => \^reqdtlpsm_cs_reg[1]\
    );
\rreq_head_vld_ff[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^rdissued_0\,
      I1 => \canissueRd_ff_reg[0]_0\(0),
      O => \rreq_head_vld_ff[0]_i_3_n_0\
    );
\rreq_head_vld_ff[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AF08"
    )
        port map (
      I0 => rreq_active0,
      I1 => \canissueRd_ff_reg[0]_0\(0),
      I2 => \^rdissued_0\,
      I3 => \canissueRd_ff_reg[0]_0\(1),
      O => \rreq_head_vld_ff_reg[0]_0\(1)
    );
tag_sel_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^tag_sel_ff0\,
      I1 => tag_sel_ff,
      O => tag_sel_ff_reg
    );
\tlp_rrq_snt_ff[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rdissued_0\,
      I1 => \m_axis_rq_thead_d_ff_reg[0][37]\(0),
      O => \rreq_head_info_ff_reg[0][tag][0]\(0)
    );
\tlp_rrq_snt_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][37]\(0),
      I1 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][tag][0]\(1)
    );
\tlp_rrq_tag_ff[0][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][37]\(0),
      I1 => \^rdissued_0\,
      O => \rreq_head_info_ff_reg[0][tag][0]_1\
    );
\tlp_rrq_tag_ff[1][5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^rdissued_0\,
      I1 => \m_axis_rq_thead_d_ff_reg[0][37]\(0),
      O => \rreq_head_info_ff_reg[0][tag][0]_0\
    );
\wpl_hdr_adr_ff[63]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0040FFFF"
    )
        port map (
      I0 => reqdtlpSm_cs(1),
      I1 => reqdtlpSm512_cs(0),
      I2 => wtlp_dat_vld6_in(0),
      I3 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I4 => wpl_hdr_vld_ff,
      O => \^wtlp_hdr_pop00_out\
    );
\wpl_hdr_adr_ff[63]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B0"
    )
        port map (
      I0 => force_ready_flush_ff,
      I1 => full_ff_reg_n_0,
      I2 => m_axis_rq_tvalid_d_ff,
      O => wtlp_dat_vld6_in(0)
    );
\wpl_hdr_adr_ff[63]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => reqdtlpSm512_cs(1),
      O => \wpl_hdr_adr_ff[63]_i_3_n_0\
    );
wpl_hdr_vld_ff_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^wtlp_hdr_pop00_out\,
      I1 => \FifoCntrWr_reg[0]_0\,
      O => wpl_hdr_vld_nxt
    );
\wrq_pnd_cnt_ff[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96669696"
    )
        port map (
      I0 => \wrq_pnd_cnt_ff_reg[3]\(0),
      I1 => \wrq_pnd_cnt_ff_reg[3]\(1),
      I2 => wcp_vld_ff,
      I3 => wr_user(0),
      I4 => \^wtlp_hdr_rd_ff0\,
      O => \wrq_pnd_cnt_ff_reg[2]\(0)
    );
\wrq_pnd_cnt_ff[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A96AA96A6A6A6A"
    )
        port map (
      I0 => \wrq_pnd_cnt_ff_reg[3]\(2),
      I1 => \wrq_pnd_cnt_ff_reg[3]\(0),
      I2 => \wrq_pnd_cnt_ff_reg[3]\(1),
      I3 => \^wtlp_hdr_rd_ff0\,
      I4 => wr_user(0),
      I5 => wcp_vld_ff,
      O => \wrq_pnd_cnt_ff_reg[2]\(1)
    );
\wrq_pnd_cnt_ff[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAA9AAAAAA"
    )
        port map (
      I0 => wcp_vld_ff,
      I1 => wr_user(0),
      I2 => reqdtlpSm_cs(1),
      I3 => reqdtlpSm512_cs(0),
      I4 => wtlp_dat_vld6_in(0),
      I5 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => wcp_vld_ff_reg(0)
    );
\wrq_pnd_cnt_ff[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => \wrq_pnd_cnt_ff_reg[3]\(2),
      I1 => \wrq_pnd_cnt_ff_reg[3]\(1),
      I2 => \wrq_pnd_cnt_ff_reg[3]\(3),
      I3 => \wrq_pnd_cnt_ff[3]_i_3_n_0\,
      O => \wrq_pnd_cnt_ff_reg[2]\(2)
    );
\wrq_pnd_cnt_ff[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75FF0075"
    )
        port map (
      I0 => wcp_vld_ff,
      I1 => wr_user(0),
      I2 => \^wtlp_hdr_rd_ff0\,
      I3 => \wrq_pnd_cnt_ff_reg[3]\(1),
      I4 => \wrq_pnd_cnt_ff_reg[3]\(0),
      O => \wrq_pnd_cnt_ff[3]_i_3_n_0\
    );
\wseq_ff[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40000000FFFFFFFF"
    )
        port map (
      I0 => \wseq_ff[3]_i_4_n_0\,
      I1 => wr_user(4),
      I2 => wr_user(3),
      I3 => wr_user(1),
      I4 => wr_user(2),
      I5 => \FifoCntrWr_reg[0]_1\(0),
      O => SR(0)
    );
\wseq_ff[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I1 => wtlp_dat_vld6_in(0),
      I2 => reqdtlpSm512_cs(0),
      I3 => reqdtlpSm_cs(1),
      I4 => wr_user(0),
      O => \reqdtlpSm512_cs_reg[0]\(0)
    );
\wseq_ff[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => wr_user(0),
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wseq_ff[3]_i_4_n_0\
    );
\wtlp_dat_cnt_nn1[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9969"
    )
        port map (
      I0 => \wtlp_dat_cnt_nn1_reg[3]\(0),
      I1 => \wtlp_dat_cnt_nn1_reg[3]\(1),
      I2 => wtlp_wpl_wen_500,
      I3 => \^wtlp_dat_ren\,
      O => \wtlp_dat_cnt_nn1_reg[2]\(0)
    );
\wtlp_dat_cnt_nn1[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6AAAA59"
    )
        port map (
      I0 => \wtlp_dat_cnt_nn1_reg[3]\(2),
      I1 => wtlp_wpl_wen_500,
      I2 => \^wtlp_dat_ren\,
      I3 => \wtlp_dat_cnt_nn1_reg[3]\(1),
      I4 => \wtlp_dat_cnt_nn1_reg[3]\(0),
      O => \wtlp_dat_cnt_nn1_reg[2]\(1)
    );
\wtlp_dat_cnt_nn1[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wtlp_wpl_wen_500,
      I1 => \^wtlp_dat_ren\,
      O => wtlp_wpl_wen_500_reg(0)
    );
\wtlp_dat_cnt_nn1[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F078F0E1E1F0E1"
    )
        port map (
      I0 => \wtlp_dat_cnt_nn1_reg[3]\(2),
      I1 => \wtlp_dat_cnt_nn1_reg[3]\(1),
      I2 => \wtlp_dat_cnt_nn1_reg[3]\(3),
      I3 => wtlp_wpl_wen_500,
      I4 => \^wtlp_dat_ren\,
      I5 => \wtlp_dat_cnt_nn1_reg[3]\(0),
      O => \wtlp_dat_cnt_nn1_reg[2]\(2)
    );
\wtlp_dat_vld_ff[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0F8F0080"
    )
        port map (
      I0 => reqdtlpSm512_cs(1),
      I1 => \wtlp_dat_vld_ff_reg[0]\,
      I2 => rdIssued_s01,
      I3 => beatdone,
      I4 => \wtlp_dat_vld_ff[0]_i_4_n_0\,
      I5 => \wtlp_dat_vld_ff[0]_i_5_n_0\,
      O => wtlp_dat_vld(0)
    );
\wtlp_dat_vld_ff[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22A2"
    )
        port map (
      I0 => wtlp_dat_vld_ff(0),
      I1 => m_axis_rq_tvalid_d_ff,
      I2 => full_ff_reg_n_0,
      I3 => force_ready_flush_ff,
      O => \wtlp_dat_vld_ff[0]_i_4_n_0\
    );
\wtlp_dat_vld_ff[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAEAEAEEEA"
    )
        port map (
      I0 => \wtlp_dat_vld_ff[0]_i_7_n_0\,
      I1 => \wtlp_dat_vld_ff[0]_i_8_n_0\,
      I2 => \wtlp_dat_vld_ff[0]_i_4_n_0\,
      I3 => rdIssued_s01,
      I4 => reqdtlpSm512_cs(1),
      I5 => \wtlp_dat_vld_ff_reg[0]\,
      O => \wtlp_dat_vld_ff[0]_i_5_n_0\
    );
\wtlp_dat_vld_ff[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000020C000002000"
    )
        port map (
      I0 => rdIssued_s01,
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(0),
      I3 => reqdtlpSm512_cs(1),
      I4 => wtlp_dat_vld6_in(0),
      I5 => wtlp_dat_vld_ff(0),
      O => \wtlp_dat_vld_ff[0]_i_7_n_0\
    );
\wtlp_dat_vld_ff[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF00FF00FFB0"
    )
        port map (
      I0 => p_0_in123_out,
      I1 => wrreq,
      I2 => wtlp_dat_vld_ff(0),
      I3 => reqdtlpSm512_cs(1),
      I4 => wtlp_dat_vld6_in(0),
      I5 => reqdtlpSm_cs(1),
      O => \wtlp_dat_vld_ff[0]_i_8_n_0\
    );
wtlp_hdr_av_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEFEEEFEEEEEE"
    )
        port map (
      I0 => wtlp_hdr_av_i_2_n_0,
      I1 => \^wtlp_hdr_rd_cnt_nn1_reg[2]\(3),
      I2 => flush_txn_linkdown,
      I3 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      I4 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(1),
      I5 => \wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0\,
      O => \flush_txn_linkdown_ff_reg[3]\
    );
wtlp_hdr_av_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5554145544555554"
    )
        port map (
      I0 => flush_txn_linkdown,
      I1 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(2),
      I2 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(1),
      I3 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      I4 => \^wtlp_hdr_rd_ff0\,
      I5 => wtlp_hdr_ld_501,
      O => wtlp_hdr_av_i_2_n_0
    );
\wtlp_hdr_rd_cnt_nn1[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0096"
    )
        port map (
      I0 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      I1 => \^wtlp_hdr_rd_ff0\,
      I2 => wtlp_hdr_ld_501,
      I3 => flush_txn_linkdown,
      O => \^wtlp_hdr_rd_cnt_nn1_reg[2]\(0)
    );
\wtlp_hdr_rd_cnt_nn1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DB24"
    )
        port map (
      I0 => wtlp_hdr_ld_501,
      I1 => \^wtlp_hdr_rd_ff0\,
      I2 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      I3 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(1),
      I4 => flush_txn_linkdown,
      O => \^wtlp_hdr_rd_cnt_nn1_reg[2]\(1)
    );
\wtlp_hdr_rd_cnt_nn1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFB2004"
    )
        port map (
      I0 => wtlp_hdr_ld_501,
      I1 => \^wtlp_hdr_rd_ff0\,
      I2 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      I3 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(1),
      I4 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(2),
      I5 => flush_txn_linkdown,
      O => \^wtlp_hdr_rd_cnt_nn1_reg[2]\(2)
    );
\wtlp_hdr_rd_cnt_nn1[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FE7F0180"
    )
        port map (
      I0 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(2),
      I1 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(1),
      I2 => \wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0\,
      I3 => \wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0\,
      I4 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(3),
      I5 => flush_txn_linkdown,
      O => \^wtlp_hdr_rd_cnt_nn1_reg[2]\(3)
    );
\wtlp_hdr_rd_cnt_nn1[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => wtlp_hdr_ld_501,
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      O => \wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0\
    );
\wtlp_hdr_rd_cnt_nn1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555FFFFFFFF"
    )
        port map (
      I0 => wtlp_hdr_ld_501,
      I1 => reqdtlpSm_cs(1),
      I2 => reqdtlpSm512_cs(0),
      I3 => wtlp_dat_vld6_in(0),
      I4 => \wpl_hdr_adr_ff[63]_i_3_n_0\,
      I5 => \wtlp_hdr_rd_cnt_nn1_reg[3]\(0),
      O => \wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0\
    );
wtlp_hdr_rd_ff_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => reqdtlpSm512_cs(0),
      I1 => rdIssued_s01,
      I2 => reqdtlpSm512_cs(1),
      I3 => wtlp_dat_vld6_in(0),
      I4 => reqdtlpSm_cs(1),
      O => \^wtlp_hdr_rd_ff0\
    );
wtlp_hdr_rd_ff_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000001"
    )
        port map (
      I0 => \m_axis_rq_thead_d_ff_reg[0][0]\,
      I1 => reqdtlpSm512_cs(1),
      I2 => reqdtlpSm512_cs(1),
      I3 => reqdtlpSm_cs(1),
      I4 => reqdtlpSm_cs(0),
      I5 => wtlp_dat_vld6_in(0),
      O => rdIssued_s01
    );
\wtlp_rd_dat_cnt_nn1[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9969"
    )
        port map (
      I0 => \wtlp_rd_dat_cnt_nn1_reg[3]\(1),
      I1 => \wtlp_rd_dat_cnt_nn1_reg[3]\(0),
      I2 => wtlp_wpl_wen_503,
      I3 => \^wtlp_dat_ren\,
      O => \wtlp_rd_dat_cnt_nn1_reg[2]\(0)
    );
\wtlp_rd_dat_cnt_nn1[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A6AAAA59"
    )
        port map (
      I0 => \wtlp_rd_dat_cnt_nn1_reg[3]\(2),
      I1 => wtlp_wpl_wen_503,
      I2 => \^wtlp_dat_ren\,
      I3 => \wtlp_rd_dat_cnt_nn1_reg[3]\(1),
      I4 => \wtlp_rd_dat_cnt_nn1_reg[3]\(0),
      O => \wtlp_rd_dat_cnt_nn1_reg[2]\(1)
    );
\wtlp_rd_dat_cnt_nn1[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wtlp_wpl_wen_503,
      I1 => \^wtlp_dat_ren\,
      O => wtlp_wpl_wen_503_reg(0)
    );
\wtlp_rd_dat_cnt_nn1[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F078F0E1E1F0E1"
    )
        port map (
      I0 => \wtlp_rd_dat_cnt_nn1_reg[3]\(2),
      I1 => \wtlp_rd_dat_cnt_nn1_reg[3]\(1),
      I2 => \wtlp_rd_dat_cnt_nn1_reg[3]\(3),
      I3 => wtlp_wpl_wen_503,
      I4 => \^wtlp_dat_ren\,
      I5 => \wtlp_rd_dat_cnt_nn1_reg[3]\(0),
      O => \wtlp_rd_dat_cnt_nn1_reg[2]\(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized0\ is
  port (
    \WrPtr_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[0]_0\ : out STD_LOGIC;
    wb_info_fl : out STD_LOGIC;
    empty_ff_reg_0 : out STD_LOGIC;
    empty_ff_reg_1 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    wb_win_vld : in STD_LOGIC;
    FifoCntrRd : in STD_LOGIC;
    arbstall : in STD_LOGIC;
    empty_ff : in STD_LOGIC;
    empty_ff_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized0\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized0\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized0\ is
  signal \FifoCntrRd[0]_i_1__14_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__10_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__10_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[0]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[1]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[2]\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__16_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__10_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__11_n_0\ : STD_LOGIC;
  signal \Head[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \Head[0]_i_2_n_0\ : STD_LOGIC;
  signal \Head[0]_i_3_n_0\ : STD_LOGIC;
  signal \^head_reg[0]_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_0_0_n_0 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[1]_i_2__6_n_0\ : STD_LOGIC;
  signal RdPtr_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 to 1 );
  signal WrPtr_1 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^wrptr_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \almost_full_ff_i_1__5_n_0\ : STD_LOGIC;
  signal \empty_ff_i_1__16_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \^empty_ff_reg_1\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_0_SPO_UNCONNECTED : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__10\ : label is "soft_lutpair1383";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__4\ : label is "soft_lutpair1383";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__10\ : label is "soft_lutpair1382";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__11\ : label is "soft_lutpair1382";
  attribute SOFT_HLUTNM of \Head[0]_i_2\ : label is "soft_lutpair1381";
  attribute SOFT_HLUTNM of \Head[0]_i_3\ : label is "soft_lutpair1381";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_0 : label is 4;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_0 : label is "WB_CHNL_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_0 : label is "RAM_TDP";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of MemArray_reg_0_3_0_0 : label is "RAM16X1D";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_0 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_0 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_0 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_0 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_0 : label is 0;
begin
  \Head_reg[0]_0\ <= \^head_reg[0]_0\;
  \WrPtr_reg[0]_0\(0) <= \^wrptr_reg[0]_0\(0);
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  empty_ff_reg_1 <= \^empty_ff_reg_1\;
\FifoCntrRd[0]_i_1__14\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[0]_i_1__14_n_0\
    );
\FifoCntrRd[1]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => \FifoCntrRd_reg_n_0_[1]\,
      I2 => empty_ff,
      O => \FifoCntrRd[1]_i_1__10_n_0\
    );
\FifoCntrRd[2]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1E"
    )
        port map (
      I0 => arbstall,
      I1 => \^empty_ff_reg_0\,
      I2 => empty_ff,
      O => \FifoCntrRd[2]_i_1__10_n_0\
    );
\FifoCntrRd[2]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A69A"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[2]\,
      I1 => \FifoCntrRd_reg_n_0_[1]\,
      I2 => empty_ff,
      I3 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[2]_i_2__4_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrRd[0]_i_1__14_n_0\,
      Q => \FifoCntrRd_reg_n_0_[0]\,
      R => FifoCntrRd
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrRd[1]_i_1__10_n_0\,
      Q => \FifoCntrRd_reg_n_0_[1]\,
      R => FifoCntrRd
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrRd[2]_i_2__4_n_0\,
      Q => \FifoCntrRd_reg_n_0_[2]\,
      R => FifoCntrRd
    );
\FifoCntrWr[0]_i_1__16\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__16_n_0\
    );
\FifoCntrWr[1]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => empty_ff,
      O => \FifoCntrWr[1]_i_1__10_n_0\
    );
\FifoCntrWr[2]_i_1__11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A69A"
    )
        port map (
      I0 => FifoCntrWr(2),
      I1 => FifoCntrWr(0),
      I2 => empty_ff,
      I3 => FifoCntrWr(1),
      O => \FifoCntrWr[2]_i_1__11_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrWr[0]_i_1__16_n_0\,
      Q => FifoCntrWr(0),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrWr[1]_i_1__10_n_0\,
      Q => FifoCntrWr(1),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__10_n_0\,
      D => \FifoCntrWr[2]_i_1__11_n_0\,
      Q => FifoCntrWr(2),
      R => FifoCntrRd
    );
\Head[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BA8AFFFFBA8A0000"
    )
        port map (
      I0 => MemArray_reg_0_3_0_0_n_0,
      I1 => empty_ff,
      I2 => \Head[0]_i_2_n_0\,
      I3 => Q(0),
      I4 => \Head[0]_i_3_n_0\,
      I5 => \^head_reg[0]_0\,
      O => \Head[0]_i_1__6_n_0\
    );
\Head[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010103"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => \FifoCntrRd_reg_n_0_[2]\,
      I2 => \FifoCntrRd_reg_n_0_[1]\,
      I3 => \^empty_ff_reg_0\,
      I4 => arbstall,
      O => \Head[0]_i_2_n_0\
    );
\Head[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1111111F"
    )
        port map (
      I0 => arbstall,
      I1 => \^empty_ff_reg_0\,
      I2 => \FifoCntrRd_reg_n_0_[2]\,
      I3 => \FifoCntrRd_reg_n_0_[1]\,
      I4 => \FifoCntrRd_reg_n_0_[0]\,
      O => \Head[0]_i_3_n_0\
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \Head[0]_i_1__6_n_0\,
      Q => \^head_reg[0]_0\,
      R => FifoCntrRd
    );
MemArray_reg_0_3_0_0: unisim.vcomponents.RAM32X1D
    generic map(
      INIT => X"00000000"
    )
        port map (
      A0 => \^wrptr_reg[0]_0\(0),
      A1 => WrPtr_1(1),
      A2 => '0',
      A3 => '0',
      A4 => '0',
      D => Q(0),
      DPO => MemArray_reg_0_3_0_0_n_0,
      DPRA0 => RdPtr_0(0),
      DPRA1 => RdPtr_0(1),
      DPRA2 => '0',
      DPRA3 => '0',
      DPRA4 => '0',
      SPO => NLW_MemArray_reg_0_3_0_0_SPO_UNCONNECTED,
      WCLK => user_clk,
      WE => wb_win_vld
    );
MemArray_reg_0_3_108_112_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      O => \^empty_ff_reg_1\
    );
\RdPtr[0]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5559AAAA5559AAA9"
    )
        port map (
      I0 => RdPtr_0(0),
      I1 => empty_ff,
      I2 => \FifoCntrRd_reg_n_0_[1]\,
      I3 => \FifoCntrRd_reg_n_0_[2]\,
      I4 => \^empty_ff_reg_1\,
      I5 => \FifoCntrRd_reg_n_0_[0]\,
      O => RdPtr(0)
    );
\RdPtr[1]_i_1__15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5AAA5A59AAAAAAAA"
    )
        port map (
      I0 => RdPtr_0(1),
      I1 => \FifoCntrRd_reg_n_0_[0]\,
      I2 => \^empty_ff_reg_1\,
      I3 => \RdPtr[1]_i_2__6_n_0\,
      I4 => empty_ff,
      I5 => RdPtr_0(0),
      O => RdPtr(1)
    );
\RdPtr[1]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[2]\,
      I1 => \FifoCntrRd_reg_n_0_[1]\,
      O => \RdPtr[1]_i_2__6_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RdPtr(0),
      Q => RdPtr_0(0),
      R => FifoCntrRd
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RdPtr(1),
      Q => RdPtr_0(1),
      R => FifoCntrRd
    );
\WrPtr[1]_i_1__14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => WrPtr_1(1),
      I1 => empty_ff,
      I2 => \^wrptr_reg[0]_0\(0),
      O => WrPtr(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \^wrptr_reg[0]_0\(0),
      R => FifoCntrRd
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => WrPtr(1),
      Q => WrPtr_1(1),
      R => FifoCntrRd
    );
\almost_full_ff_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => FifoCntrWr(2),
      I1 => empty_ff,
      I2 => FifoCntrWr(1),
      I3 => FifoCntrWr(0),
      O => \almost_full_ff_i_1__5_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__5_n_0\,
      Q => wb_info_fl,
      R => FifoCntrRd
    );
\empty_ff_i_1__16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3333333F3337333F"
    )
        port map (
      I0 => arbstall,
      I1 => empty_ff_reg_2(0),
      I2 => \FifoCntrRd_reg_n_0_[2]\,
      I3 => \FifoCntrRd_reg_n_0_[1]\,
      I4 => \FifoCntrRd_reg_n_0_[0]\,
      I5 => \^empty_ff_reg_0\,
      O => \empty_ff_i_1__16_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__16_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    empty_ff_reg_1 : out STD_LOGIC;
    DataOut : out STD_LOGIC_VECTOR ( 81 downto 0 );
    full_ff_reg_0 : out STD_LOGIC;
    \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35\ : in STD_LOGIC;
    \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0\ : in STD_LOGIC;
    almost_full_ff_0 : in STD_LOGIC;
    rrq_rdy_nn1 : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    empty_ff_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[2]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 80 downto 0 );
    empty_ff_reg_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1_n_0\ : STD_LOGIC;
  signal Head0 : STD_LOGIC_VECTOR ( 119 downto 8 );
  signal Head1 : STD_LOGIC;
  signal \Head[119]_i_1_n_0\ : STD_LOGIC;
  signal \Head[33]_i_1__1_n_0\ : STD_LOGIC;
  signal \Head[47]_i_1__4_n_0\ : STD_LOGIC;
  signal \Head[60]_i_1__5_n_0\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal empty_ff_i_1_n_0 : STD_LOGIC;
  signal \^empty_ff_reg_1\ : STD_LOGIC;
  signal full_ff_i_1_n_0 : STD_LOGIC;
  signal \^full_ff_reg_0\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 119 downto 8 );
  signal p_2_in : STD_LOGIC_VECTOR ( 15 downto 14 );
  signal rrq_vld_new : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1\ : label is "soft_lutpair1230";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1\ : label is "soft_lutpair1231";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1\ : label is "soft_lutpair1231";
  attribute SOFT_HLUTNM of \Head[100]_i_1\ : label is "soft_lutpair1265";
  attribute SOFT_HLUTNM of \Head[101]_i_1\ : label is "soft_lutpair1265";
  attribute SOFT_HLUTNM of \Head[102]_i_1\ : label is "soft_lutpair1266";
  attribute SOFT_HLUTNM of \Head[103]_i_1\ : label is "soft_lutpair1266";
  attribute SOFT_HLUTNM of \Head[104]_i_1\ : label is "soft_lutpair1267";
  attribute SOFT_HLUTNM of \Head[105]_i_1\ : label is "soft_lutpair1267";
  attribute SOFT_HLUTNM of \Head[106]_i_1\ : label is "soft_lutpair1268";
  attribute SOFT_HLUTNM of \Head[107]_i_1\ : label is "soft_lutpair1268";
  attribute SOFT_HLUTNM of \Head[108]_i_1\ : label is "soft_lutpair1269";
  attribute SOFT_HLUTNM of \Head[109]_i_1\ : label is "soft_lutpair1269";
  attribute SOFT_HLUTNM of \Head[10]_i_1\ : label is "soft_lutpair1235";
  attribute SOFT_HLUTNM of \Head[110]_i_1\ : label is "soft_lutpair1270";
  attribute SOFT_HLUTNM of \Head[111]_i_1\ : label is "soft_lutpair1270";
  attribute SOFT_HLUTNM of \Head[112]_i_1\ : label is "soft_lutpair1271";
  attribute SOFT_HLUTNM of \Head[113]_i_1\ : label is "soft_lutpair1271";
  attribute SOFT_HLUTNM of \Head[114]_i_1\ : label is "soft_lutpair1272";
  attribute SOFT_HLUTNM of \Head[115]_i_1\ : label is "soft_lutpair1272";
  attribute SOFT_HLUTNM of \Head[116]_i_1\ : label is "soft_lutpair1273";
  attribute SOFT_HLUTNM of \Head[117]_i_1\ : label is "soft_lutpair1273";
  attribute SOFT_HLUTNM of \Head[118]_i_1\ : label is "soft_lutpair1274";
  attribute SOFT_HLUTNM of \Head[119]_i_2\ : label is "soft_lutpair1274";
  attribute SOFT_HLUTNM of \Head[11]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \Head[12]_i_1\ : label is "soft_lutpair1236";
  attribute SOFT_HLUTNM of \Head[13]_i_1\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \Head[14]_i_1\ : label is "soft_lutpair1237";
  attribute SOFT_HLUTNM of \Head[15]_i_1\ : label is "soft_lutpair1238";
  attribute SOFT_HLUTNM of \Head[20]_i_1\ : label is "soft_lutpair1238";
  attribute SOFT_HLUTNM of \Head[21]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \Head[22]_i_1\ : label is "soft_lutpair1239";
  attribute SOFT_HLUTNM of \Head[23]_i_1\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \Head[24]_i_1\ : label is "soft_lutpair1240";
  attribute SOFT_HLUTNM of \Head[25]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \Head[26]_i_1\ : label is "soft_lutpair1241";
  attribute SOFT_HLUTNM of \Head[27]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \Head[28]_i_1\ : label is "soft_lutpair1242";
  attribute SOFT_HLUTNM of \Head[29]_i_1\ : label is "soft_lutpair1243";
  attribute SOFT_HLUTNM of \Head[30]_i_1\ : label is "soft_lutpair1243";
  attribute SOFT_HLUTNM of \Head[31]_i_1\ : label is "soft_lutpair1244";
  attribute SOFT_HLUTNM of \Head[32]_i_1\ : label is "soft_lutpair1244";
  attribute SOFT_HLUTNM of \Head[33]_i_1__1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \Head[46]_i_1\ : label is "soft_lutpair1245";
  attribute SOFT_HLUTNM of \Head[47]_i_1__4\ : label is "soft_lutpair1234";
  attribute SOFT_HLUTNM of \Head[60]_i_1__5\ : label is "soft_lutpair1235";
  attribute SOFT_HLUTNM of \Head[61]_i_1\ : label is "soft_lutpair1245";
  attribute SOFT_HLUTNM of \Head[62]_i_1\ : label is "soft_lutpair1246";
  attribute SOFT_HLUTNM of \Head[63]_i_1\ : label is "soft_lutpair1246";
  attribute SOFT_HLUTNM of \Head[64]_i_1\ : label is "soft_lutpair1247";
  attribute SOFT_HLUTNM of \Head[65]_i_1\ : label is "soft_lutpair1247";
  attribute SOFT_HLUTNM of \Head[66]_i_1\ : label is "soft_lutpair1248";
  attribute SOFT_HLUTNM of \Head[67]_i_1\ : label is "soft_lutpair1248";
  attribute SOFT_HLUTNM of \Head[68]_i_1\ : label is "soft_lutpair1249";
  attribute SOFT_HLUTNM of \Head[69]_i_1\ : label is "soft_lutpair1249";
  attribute SOFT_HLUTNM of \Head[70]_i_1\ : label is "soft_lutpair1250";
  attribute SOFT_HLUTNM of \Head[71]_i_1\ : label is "soft_lutpair1250";
  attribute SOFT_HLUTNM of \Head[72]_i_1\ : label is "soft_lutpair1251";
  attribute SOFT_HLUTNM of \Head[73]_i_1\ : label is "soft_lutpair1251";
  attribute SOFT_HLUTNM of \Head[74]_i_1\ : label is "soft_lutpair1252";
  attribute SOFT_HLUTNM of \Head[75]_i_1\ : label is "soft_lutpair1252";
  attribute SOFT_HLUTNM of \Head[76]_i_1\ : label is "soft_lutpair1253";
  attribute SOFT_HLUTNM of \Head[77]_i_1\ : label is "soft_lutpair1253";
  attribute SOFT_HLUTNM of \Head[78]_i_1\ : label is "soft_lutpair1254";
  attribute SOFT_HLUTNM of \Head[79]_i_1\ : label is "soft_lutpair1254";
  attribute SOFT_HLUTNM of \Head[80]_i_1\ : label is "soft_lutpair1255";
  attribute SOFT_HLUTNM of \Head[81]_i_1\ : label is "soft_lutpair1255";
  attribute SOFT_HLUTNM of \Head[82]_i_1\ : label is "soft_lutpair1256";
  attribute SOFT_HLUTNM of \Head[83]_i_1\ : label is "soft_lutpair1256";
  attribute SOFT_HLUTNM of \Head[84]_i_1\ : label is "soft_lutpair1257";
  attribute SOFT_HLUTNM of \Head[85]_i_1\ : label is "soft_lutpair1257";
  attribute SOFT_HLUTNM of \Head[86]_i_1\ : label is "soft_lutpair1258";
  attribute SOFT_HLUTNM of \Head[87]_i_1\ : label is "soft_lutpair1258";
  attribute SOFT_HLUTNM of \Head[88]_i_1\ : label is "soft_lutpair1259";
  attribute SOFT_HLUTNM of \Head[89]_i_1\ : label is "soft_lutpair1259";
  attribute SOFT_HLUTNM of \Head[8]_i_1\ : label is "soft_lutpair1233";
  attribute SOFT_HLUTNM of \Head[90]_i_1\ : label is "soft_lutpair1260";
  attribute SOFT_HLUTNM of \Head[91]_i_1\ : label is "soft_lutpair1260";
  attribute SOFT_HLUTNM of \Head[92]_i_1\ : label is "soft_lutpair1261";
  attribute SOFT_HLUTNM of \Head[93]_i_1\ : label is "soft_lutpair1261";
  attribute SOFT_HLUTNM of \Head[94]_i_1\ : label is "soft_lutpair1262";
  attribute SOFT_HLUTNM of \Head[95]_i_1\ : label is "soft_lutpair1262";
  attribute SOFT_HLUTNM of \Head[96]_i_1\ : label is "soft_lutpair1263";
  attribute SOFT_HLUTNM of \Head[97]_i_1\ : label is "soft_lutpair1263";
  attribute SOFT_HLUTNM of \Head[98]_i_1\ : label is "soft_lutpair1264";
  attribute SOFT_HLUTNM of \Head[99]_i_1\ : label is "soft_lutpair1264";
  attribute SOFT_HLUTNM of \Head[9]_i_1\ : label is "soft_lutpair1234";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 484;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_113 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_113 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_113 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_114_119 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_114_119 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_114_119 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_3_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_35 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_35 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_42_47 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_42_47 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1\ : label is "soft_lutpair1232";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1\ : label is "soft_lutpair1232";
begin
  empty_ff_reg_1 <= \^empty_ff_reg_1\;
  full_ff_reg_0 <= \^full_ff_reg_0\;
\FifoCntrRd[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => rrq_rdy_nn1,
      I1 => \out\,
      I2 => empty_ff_reg_2(0),
      I3 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1_n_0\
    );
\FifoCntrRd[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA7F1580"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => rrq_rdy_nn1,
      I2 => \out\,
      I3 => empty_ff_reg_2(0),
      I4 => FifoCntrRd(1),
      O => \FifoCntrRd[1]_i_1_n_0\
    );
\FifoCntrRd[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEE7FFF01118000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(1),
      I2 => rrq_rdy_nn1,
      I3 => \out\,
      I4 => empty_ff_reg_2(0),
      I5 => FifoCntrRd(2),
      O => \FifoCntrRd[2]_i_1_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1_n_0\,
      Q => FifoCntrRd(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1_n_0\,
      Q => FifoCntrRd(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_1_n_0\,
      Q => FifoCntrRd(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"956A"
    )
        port map (
      I0 => empty_ff_reg_2(0),
      I1 => \out\,
      I2 => rrq_rdy_nn1,
      I3 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1_n_0\
    );
\FifoCntrWr[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DBBB2444"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => empty_ff_reg_2(0),
      I2 => \out\,
      I3 => rrq_rdy_nn1,
      I4 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1_n_0\
    );
\FifoCntrWr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7EFEFEF08101010"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => empty_ff_reg_2(0),
      I3 => \out\,
      I4 => rrq_rdy_nn1,
      I5 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1_n_0\,
      Q => FifoCntrWr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1_n_0\,
      Q => FifoCntrWr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1_n_0\,
      Q => FifoCntrWr(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head[100]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head0(100),
      I2 => Head1,
      O => p_0_in1_in(100)
    );
\Head[101]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head0(101),
      I2 => Head1,
      O => p_0_in1_in(101)
    );
\Head[102]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head0(102),
      I2 => Head1,
      O => p_0_in1_in(102)
    );
\Head[103]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head0(103),
      I2 => Head1,
      O => p_0_in1_in(103)
    );
\Head[104]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head0(104),
      I2 => Head1,
      O => p_0_in1_in(104)
    );
\Head[105]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head0(105),
      I2 => Head1,
      O => p_0_in1_in(105)
    );
\Head[106]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head0(106),
      I2 => Head1,
      O => p_0_in1_in(106)
    );
\Head[107]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head0(107),
      I2 => Head1,
      O => p_0_in1_in(107)
    );
\Head[108]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head0(108),
      I2 => Head1,
      O => p_0_in1_in(108)
    );
\Head[109]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head0(109),
      I2 => Head1,
      O => p_0_in1_in(109)
    );
\Head[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(2),
      I1 => Head0(10),
      I2 => Head1,
      O => p_0_in1_in(10)
    );
\Head[110]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head0(110),
      I2 => Head1,
      O => p_0_in1_in(110)
    );
\Head[111]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head0(111),
      I2 => Head1,
      O => p_0_in1_in(111)
    );
\Head[112]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head0(112),
      I2 => Head1,
      O => p_0_in1_in(112)
    );
\Head[113]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head0(113),
      I2 => Head1,
      O => p_0_in1_in(113)
    );
\Head[114]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head0(114),
      I2 => Head1,
      O => p_0_in1_in(114)
    );
\Head[115]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head0(115),
      I2 => Head1,
      O => p_0_in1_in(115)
    );
\Head[116]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head0(116),
      I2 => Head1,
      O => p_0_in1_in(116)
    );
\Head[117]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head0(117),
      I2 => Head1,
      O => p_0_in1_in(117)
    );
\Head[118]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head0(118),
      I2 => Head1,
      O => p_0_in1_in(118)
    );
\Head[119]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEF"
    )
        port map (
      I0 => Head1,
      I1 => empty_ff_reg_2(0),
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(0),
      O => \Head[119]_i_1_n_0\
    );
\Head[119]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head0(119),
      I2 => Head1,
      O => p_0_in1_in(119)
    );
\Head[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head0(11),
      I2 => Head1,
      O => p_0_in1_in(11)
    );
\Head[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head0(12),
      I2 => Head1,
      O => p_0_in1_in(12)
    );
\Head[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head0(13),
      I2 => Head1,
      O => p_0_in1_in(13)
    );
\Head[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head0(14),
      I2 => Head1,
      O => p_0_in1_in(14)
    );
\Head[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head0(15),
      I2 => Head1,
      O => p_0_in1_in(15)
    );
\Head[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head0(20),
      I2 => Head1,
      O => p_0_in1_in(20)
    );
\Head[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head0(21),
      I2 => Head1,
      O => p_0_in1_in(21)
    );
\Head[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head0(22),
      I2 => Head1,
      O => p_0_in1_in(22)
    );
\Head[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head0(23),
      I2 => Head1,
      O => p_0_in1_in(23)
    );
\Head[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head0(24),
      I2 => Head1,
      O => p_0_in1_in(24)
    );
\Head[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head0(25),
      I2 => Head1,
      O => p_0_in1_in(25)
    );
\Head[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head0(26),
      I2 => Head1,
      O => p_0_in1_in(26)
    );
\Head[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head0(27),
      I2 => Head1,
      O => p_0_in1_in(27)
    );
\Head[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head0(28),
      I2 => Head1,
      O => p_0_in1_in(28)
    );
\Head[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head0(29),
      I2 => Head1,
      O => p_0_in1_in(29)
    );
\Head[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head0(30),
      I2 => Head1,
      O => p_0_in1_in(30)
    );
\Head[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head0(31),
      I2 => Head1,
      O => p_0_in1_in(31)
    );
\Head[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head0(32),
      I2 => Head1,
      O => p_0_in1_in(32)
    );
\Head[33]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(33),
      I1 => Head1,
      O => \Head[33]_i_1__1_n_0\
    );
\Head[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head0(46),
      I2 => Head1,
      O => p_0_in1_in(46)
    );
\Head[47]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(47),
      I1 => Head1,
      O => \Head[47]_i_1__4_n_0\
    );
\Head[60]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(60),
      I1 => Head1,
      O => \Head[60]_i_1__5_n_0\
    );
\Head[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head0(61),
      I2 => Head1,
      O => p_0_in1_in(61)
    );
\Head[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head0(62),
      I2 => Head1,
      O => p_0_in1_in(62)
    );
\Head[63]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head0(63),
      I2 => Head1,
      O => p_0_in1_in(63)
    );
\Head[64]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head0(64),
      I2 => Head1,
      O => p_0_in1_in(64)
    );
\Head[65]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head0(65),
      I2 => Head1,
      O => p_0_in1_in(65)
    );
\Head[66]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head0(66),
      I2 => Head1,
      O => p_0_in1_in(66)
    );
\Head[67]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head0(67),
      I2 => Head1,
      O => p_0_in1_in(67)
    );
\Head[68]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head0(68),
      I2 => Head1,
      O => p_0_in1_in(68)
    );
\Head[69]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head0(69),
      I2 => Head1,
      O => p_0_in1_in(69)
    );
\Head[70]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head0(70),
      I2 => Head1,
      O => p_0_in1_in(70)
    );
\Head[71]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head0(71),
      I2 => Head1,
      O => p_0_in1_in(71)
    );
\Head[72]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head0(72),
      I2 => Head1,
      O => p_0_in1_in(72)
    );
\Head[73]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head0(73),
      I2 => Head1,
      O => p_0_in1_in(73)
    );
\Head[74]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head0(74),
      I2 => Head1,
      O => p_0_in1_in(74)
    );
\Head[75]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head0(75),
      I2 => Head1,
      O => p_0_in1_in(75)
    );
\Head[76]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head0(76),
      I2 => Head1,
      O => p_0_in1_in(76)
    );
\Head[77]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head0(77),
      I2 => Head1,
      O => p_0_in1_in(77)
    );
\Head[78]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head0(78),
      I2 => Head1,
      O => p_0_in1_in(78)
    );
\Head[79]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head0(79),
      I2 => Head1,
      O => p_0_in1_in(79)
    );
\Head[80]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head0(80),
      I2 => Head1,
      O => p_0_in1_in(80)
    );
\Head[81]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head0(81),
      I2 => Head1,
      O => p_0_in1_in(81)
    );
\Head[82]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head0(82),
      I2 => Head1,
      O => p_0_in1_in(82)
    );
\Head[83]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head0(83),
      I2 => Head1,
      O => p_0_in1_in(83)
    );
\Head[84]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head0(84),
      I2 => Head1,
      O => p_0_in1_in(84)
    );
\Head[85]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head0(85),
      I2 => Head1,
      O => p_0_in1_in(85)
    );
\Head[86]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head0(86),
      I2 => Head1,
      O => p_0_in1_in(86)
    );
\Head[87]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head0(87),
      I2 => Head1,
      O => p_0_in1_in(87)
    );
\Head[88]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head0(88),
      I2 => Head1,
      O => p_0_in1_in(88)
    );
\Head[89]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head0(89),
      I2 => Head1,
      O => p_0_in1_in(89)
    );
\Head[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head0(8),
      I2 => Head1,
      O => p_0_in1_in(8)
    );
\Head[90]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head0(90),
      I2 => Head1,
      O => p_0_in1_in(90)
    );
\Head[91]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head0(91),
      I2 => Head1,
      O => p_0_in1_in(91)
    );
\Head[92]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head0(92),
      I2 => Head1,
      O => p_0_in1_in(92)
    );
\Head[93]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head0(93),
      I2 => Head1,
      O => p_0_in1_in(93)
    );
\Head[94]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head0(94),
      I2 => Head1,
      O => p_0_in1_in(94)
    );
\Head[95]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head0(95),
      I2 => Head1,
      O => p_0_in1_in(95)
    );
\Head[96]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head0(96),
      I2 => Head1,
      O => p_0_in1_in(96)
    );
\Head[97]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head0(97),
      I2 => Head1,
      O => p_0_in1_in(97)
    );
\Head[98]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head0(98),
      I2 => Head1,
      O => p_0_in1_in(98)
    );
\Head[99]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head0(99),
      I2 => Head1,
      O => p_0_in1_in(99)
    );
\Head[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head0(9),
      I2 => Head1,
      O => p_0_in1_in(9)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(100),
      Q => DataOut(62),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(101),
      Q => DataOut(63),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(102),
      Q => DataOut(64),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(103),
      Q => DataOut(65),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(104),
      Q => DataOut(66),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(105),
      Q => DataOut(67),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(106),
      Q => DataOut(68),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(107),
      Q => DataOut(69),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(108),
      Q => DataOut(70),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(109),
      Q => DataOut(71),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(10),
      Q => DataOut(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(110),
      Q => DataOut(72),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(111),
      Q => DataOut(73),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(112),
      Q => DataOut(74),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(113),
      Q => DataOut(75),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(114),
      Q => DataOut(76),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(115),
      Q => DataOut(77),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(116),
      Q => DataOut(78),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(117),
      Q => DataOut(79),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(118),
      Q => DataOut(80),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(119),
      Q => DataOut(81),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(11),
      Q => DataOut(3),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(12),
      Q => DataOut(4),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(13),
      Q => DataOut(5),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(14),
      Q => DataOut(6),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(15),
      Q => DataOut(7),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(20),
      Q => DataOut(8),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(21),
      Q => DataOut(9),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(22),
      Q => DataOut(10),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(23),
      Q => DataOut(11),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(24),
      Q => DataOut(12),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(25),
      Q => DataOut(13),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(26),
      Q => DataOut(14),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(27),
      Q => DataOut(15),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(28),
      Q => DataOut(16),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(29),
      Q => DataOut(17),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(30),
      Q => DataOut(18),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(31),
      Q => DataOut(19),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(32),
      Q => p_2_in(14),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => \Head[33]_i_1__1_n_0\,
      Q => p_2_in(15),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(46),
      Q => DataOut(20),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => \Head[47]_i_1__4_n_0\,
      Q => DataOut(21),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => \Head[60]_i_1__5_n_0\,
      Q => DataOut(22),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(61),
      Q => DataOut(23),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(62),
      Q => DataOut(24),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(63),
      Q => DataOut(25),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(64),
      Q => DataOut(26),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(65),
      Q => DataOut(27),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(66),
      Q => DataOut(28),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(67),
      Q => DataOut(29),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(68),
      Q => DataOut(30),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(69),
      Q => DataOut(31),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(70),
      Q => DataOut(32),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(71),
      Q => DataOut(33),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(72),
      Q => DataOut(34),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(73),
      Q => DataOut(35),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(74),
      Q => DataOut(36),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(75),
      Q => DataOut(37),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(76),
      Q => DataOut(38),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(77),
      Q => DataOut(39),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(78),
      Q => DataOut(40),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(79),
      Q => DataOut(41),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(80),
      Q => DataOut(42),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(81),
      Q => DataOut(43),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(82),
      Q => DataOut(44),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(83),
      Q => DataOut(45),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(84),
      Q => DataOut(46),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(85),
      Q => DataOut(47),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(86),
      Q => DataOut(48),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(87),
      Q => DataOut(49),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(88),
      Q => DataOut(50),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(89),
      Q => DataOut(51),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(8),
      Q => DataOut(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(90),
      Q => DataOut(52),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(91),
      Q => DataOut(53),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(92),
      Q => DataOut(54),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(93),
      Q => DataOut(55),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(94),
      Q => DataOut(56),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(95),
      Q => DataOut(57),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(96),
      Q => DataOut(58),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(97),
      Q => DataOut(59),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(98),
      Q => DataOut(60),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(99),
      Q => DataOut(61),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1_n_0\,
      D => p_0_in1_in(9),
      Q => DataOut(1),
      R => \FifoCntrRd_reg[2]_0\
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(64 downto 63),
      DIB(1 downto 0) => DataIn(66 downto 65),
      DIC(1 downto 0) => DataIn(68 downto 67),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(70 downto 69),
      DIB(1 downto 0) => DataIn(72 downto 71),
      DIC(1 downto 0) => DataIn(74 downto 73),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => Head0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(76 downto 75),
      DIB(1 downto 0) => DataIn(78 downto 77),
      DIC(1 downto 0) => DataIn(80 downto 79),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(115 downto 114),
      DOB(1 downto 0) => Head0(117 downto 116),
      DOC(1 downto 0) => Head0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(5 downto 4),
      DIB(1 downto 0) => DataIn(7 downto 6),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => DataIn(9 downto 8),
      DIC(1 downto 0) => DataIn(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(13 downto 12),
      DIB(1 downto 0) => DataIn(15 downto 14),
      DIC(1 downto 0) => DataIn(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(25 downto 24),
      DOB(1 downto 0) => Head0(27 downto 26),
      DOC(1 downto 0) => Head0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(19 downto 18),
      DIB(1) => '0',
      DIB(0) => DataIn(20),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(31 downto 30),
      DOB(1 downto 0) => Head0(33 downto 32),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_30_35_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00230000"
    )
        port map (
      I0 => \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35\,
      I1 => \^empty_ff_reg_1\,
      I2 => \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0\,
      I3 => almost_full_ff_0,
      I4 => p_2_in(15),
      O => empty_ff_reg_0(1)
    );
MemArray_reg_0_3_30_35_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00230000"
    )
        port map (
      I0 => \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35\,
      I1 => \^empty_ff_reg_1\,
      I2 => \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0\,
      I3 => almost_full_ff_0,
      I4 => p_2_in(14),
      O => empty_ff_reg_0(0)
    );
MemArray_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '0',
      DIC(0) => DataIn(21),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => Head0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1) => DataIn(22),
      DIA(0) => '0',
      DIB(1 downto 0) => DataIn(24 downto 23),
      DIC(1 downto 0) => DataIn(26 downto 25),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(28 downto 27),
      DIB(1 downto 0) => DataIn(30 downto 29),
      DIC(1 downto 0) => DataIn(32 downto 31),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => DataIn(1 downto 0),
      DIC(1 downto 0) => DataIn(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_6_11_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rrq_rdy_nn1,
      I1 => \out\,
      O => rrq_vld_new
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(34 downto 33),
      DIB(1 downto 0) => DataIn(36 downto 35),
      DIC(1 downto 0) => DataIn(38 downto 37),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(40 downto 39),
      DIB(1 downto 0) => DataIn(42 downto 41),
      DIC(1 downto 0) => DataIn(44 downto 43),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(46 downto 45),
      DIB(1 downto 0) => DataIn(48 downto 47),
      DIC(1 downto 0) => DataIn(50 downto 49),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(52 downto 51),
      DIB(1 downto 0) => DataIn(54 downto 53),
      DIC(1 downto 0) => DataIn(56 downto 55),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(58 downto 57),
      DIB(1 downto 0) => DataIn(60 downto 59),
      DIC(1 downto 0) => DataIn(62 downto 61),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_new
    );
\RdPtr[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5555666A"
    )
        port map (
      I0 => RdPtr(0),
      I1 => empty_ff_reg_2(0),
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => Head1,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55577777AAA88888"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => empty_ff_reg_2(0),
      I5 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301000000000000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => empty_ff_reg_2(0),
      I4 => \out\,
      I5 => rrq_rdy_nn1,
      O => Head1
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\WrPtr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \out\,
      I2 => rrq_rdy_nn1,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => WrPtr(0),
      I1 => rrq_rdy_nn1,
      I2 => \out\,
      I3 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
empty_ff_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF000B"
    )
        port map (
      I0 => empty_ff_reg_2(0),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => empty_ff_reg_3,
      O => empty_ff_i_1_n_0
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => empty_ff_i_1_n_0,
      Q => \^empty_ff_reg_1\,
      R => '0'
    );
full_ff_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF800011118000"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \out\,
      I3 => rrq_rdy_nn1,
      I4 => FifoCntrWr(2),
      I5 => \^full_ff_reg_0\,
      O => full_ff_i_1_n_0
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => full_ff_i_1_n_0,
      Q => \^full_ff_reg_0\,
      R => \FifoCntrRd_reg[2]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_49\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[0]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[1]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[2]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[3]\ : out STD_LOGIC;
    ctl_rst_nn1_reg : out STD_LOGIC;
    ctl_rst_nn1_reg_0 : out STD_LOGIC;
    ctl_rst_nn1_reg_1 : out STD_LOGIC;
    ctl_rst_nn1_reg_2 : out STD_LOGIC;
    ctl_rst_nn1_reg_3 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    rrq_ld_90022_out : out STD_LOGIC;
    payloadOut : out STD_LOGIC_VECTOR ( 75 downto 0 );
    empty_ff_reg_1 : out STD_LOGIC;
    \Head_reg[119]_0\ : out STD_LOGIC_VECTOR ( 75 downto 0 );
    rrq_vld_902 : out STD_LOGIC;
    \rrq_sm_cur_900_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    full_ff_reg_0 : out STD_LOGIC;
    \rrq_sm_cur_900_reg[3]\ : out STD_LOGIC;
    \dat_fifo_hd_nn1_reg[9]\ : in STD_LOGIC;
    cfg_linkdown_nn1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dat_fifo_hd_nn1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
    ctl_run_re : in STD_LOGIC;
    almost_full_ff : in STD_LOGIC;
    \dat_fifo_hd_nn1_reg[8]\ : in STD_LOGIC;
    \dat_fifo_hd_nn1_reg[8]_0\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[3]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    rrq_vld_903 : in STD_LOGIC;
    \rrq_ld_901_reg_rep__5\ : in STD_LOGIC;
    rrq_vld_903_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rrq_sm_cur_900_reg[3]_1\ : in STD_LOGIC;
    rrq_stall_902 : in STD_LOGIC;
    rrq_dsc_rem0_902 : in STD_LOGIC;
    rrq_dsc_vld_902 : in STD_LOGIC;
    rrq_fl_nn1 : in STD_LOGIC;
    \FifoCntrRd_reg[2]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 75 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_49\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_49\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_49\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__1_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__2_n_0\ : STD_LOGIC;
  signal Head0 : STD_LOGIC_VECTOR ( 119 downto 18 );
  signal Head1 : STD_LOGIC;
  signal \Head[119]_i_1__1_n_0\ : STD_LOGIC;
  signal \^head_reg[119]_0\ : STD_LOGIC_VECTOR ( 75 downto 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \dat_fifo_hd_nn1[8]_i_2_n_0\ : STD_LOGIC;
  signal \empty_ff_i_1__2_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__2_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \^empty_ff_reg_1\ : STD_LOGIC;
  signal \full_ff_i_1__1_n_0\ : STD_LOGIC;
  signal full_ff_reg_n_0 : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 119 downto 18 );
  signal \^rrq_ld_90022_out\ : STD_LOGIC;
  signal \rrq_sm_cur_900[3]_i_2_n_0\ : STD_LOGIC;
  signal \^rrq_sm_cur_900_reg[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rrq_vld_903_i_2_n_0 : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__2\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__2\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_1__1\ : label is "soft_lutpair968";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__2\ : label is "soft_lutpair1008";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__2\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__2\ : label is "soft_lutpair969";
  attribute SOFT_HLUTNM of \Head[100]_i_1__2\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \Head[101]_i_1__2\ : label is "soft_lutpair998";
  attribute SOFT_HLUTNM of \Head[102]_i_1__2\ : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \Head[103]_i_1__2\ : label is "soft_lutpair999";
  attribute SOFT_HLUTNM of \Head[104]_i_1__2\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \Head[105]_i_1__2\ : label is "soft_lutpair1000";
  attribute SOFT_HLUTNM of \Head[106]_i_1__2\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \Head[107]_i_1__2\ : label is "soft_lutpair1001";
  attribute SOFT_HLUTNM of \Head[108]_i_1__2\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \Head[109]_i_1__2\ : label is "soft_lutpair1002";
  attribute SOFT_HLUTNM of \Head[110]_i_1__2\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \Head[111]_i_1__2\ : label is "soft_lutpair1003";
  attribute SOFT_HLUTNM of \Head[112]_i_1__1\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \Head[113]_i_1__1\ : label is "soft_lutpair1004";
  attribute SOFT_HLUTNM of \Head[114]_i_1__1\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \Head[115]_i_1__1\ : label is "soft_lutpair1005";
  attribute SOFT_HLUTNM of \Head[116]_i_1__1\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \Head[117]_i_1__1\ : label is "soft_lutpair1006";
  attribute SOFT_HLUTNM of \Head[118]_i_1__1\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \Head[119]_i_2__0\ : label is "soft_lutpair1007";
  attribute SOFT_HLUTNM of \Head[18]_i_1__1\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \Head[19]_i_1__1\ : label is "soft_lutpair970";
  attribute SOFT_HLUTNM of \Head[20]_i_1__2\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \Head[21]_i_1__2\ : label is "soft_lutpair971";
  attribute SOFT_HLUTNM of \Head[22]_i_1__1\ : label is "soft_lutpair972";
  attribute SOFT_HLUTNM of \Head[23]_i_1__1\ : label is "soft_lutpair972";
  attribute SOFT_HLUTNM of \Head[24]_i_1__1\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \Head[25]_i_1__1\ : label is "soft_lutpair973";
  attribute SOFT_HLUTNM of \Head[26]_i_1__1\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of \Head[27]_i_1__1\ : label is "soft_lutpair974";
  attribute SOFT_HLUTNM of \Head[28]_i_1__1\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \Head[29]_i_1__1\ : label is "soft_lutpair975";
  attribute SOFT_HLUTNM of \Head[56]_i_1__1\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \Head[57]_i_1__1\ : label is "soft_lutpair976";
  attribute SOFT_HLUTNM of \Head[58]_i_1__1\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \Head[59]_i_1__1\ : label is "soft_lutpair977";
  attribute SOFT_HLUTNM of \Head[60]_i_1__1\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \Head[61]_i_1__2\ : label is "soft_lutpair978";
  attribute SOFT_HLUTNM of \Head[62]_i_1__2\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \Head[63]_i_1__2\ : label is "soft_lutpair979";
  attribute SOFT_HLUTNM of \Head[64]_i_1__2\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \Head[65]_i_1__2\ : label is "soft_lutpair980";
  attribute SOFT_HLUTNM of \Head[66]_i_1__2\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \Head[67]_i_1__2\ : label is "soft_lutpair981";
  attribute SOFT_HLUTNM of \Head[68]_i_1__2\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \Head[69]_i_1__2\ : label is "soft_lutpair982";
  attribute SOFT_HLUTNM of \Head[70]_i_1__2\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \Head[71]_i_1__2\ : label is "soft_lutpair983";
  attribute SOFT_HLUTNM of \Head[72]_i_1__2\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \Head[73]_i_1__2\ : label is "soft_lutpair984";
  attribute SOFT_HLUTNM of \Head[74]_i_1__2\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \Head[75]_i_1__2\ : label is "soft_lutpair985";
  attribute SOFT_HLUTNM of \Head[76]_i_1__2\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \Head[77]_i_1__2\ : label is "soft_lutpair986";
  attribute SOFT_HLUTNM of \Head[78]_i_1__2\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \Head[79]_i_1__2\ : label is "soft_lutpair987";
  attribute SOFT_HLUTNM of \Head[80]_i_1__2\ : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of \Head[81]_i_1__2\ : label is "soft_lutpair988";
  attribute SOFT_HLUTNM of \Head[82]_i_1__2\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \Head[83]_i_1__2\ : label is "soft_lutpair989";
  attribute SOFT_HLUTNM of \Head[84]_i_1__2\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \Head[85]_i_1__2\ : label is "soft_lutpair990";
  attribute SOFT_HLUTNM of \Head[86]_i_1__2\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \Head[87]_i_1__2\ : label is "soft_lutpair991";
  attribute SOFT_HLUTNM of \Head[88]_i_1__2\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \Head[89]_i_1__2\ : label is "soft_lutpair992";
  attribute SOFT_HLUTNM of \Head[90]_i_1__2\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \Head[91]_i_1__2\ : label is "soft_lutpair993";
  attribute SOFT_HLUTNM of \Head[92]_i_1__2\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \Head[93]_i_1__2\ : label is "soft_lutpair994";
  attribute SOFT_HLUTNM of \Head[94]_i_1__2\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \Head[95]_i_1__2\ : label is "soft_lutpair995";
  attribute SOFT_HLUTNM of \Head[96]_i_1__2\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \Head[97]_i_1__2\ : label is "soft_lutpair996";
  attribute SOFT_HLUTNM of \Head[98]_i_1__2\ : label is "soft_lutpair997";
  attribute SOFT_HLUTNM of \Head[99]_i_1__2\ : label is "soft_lutpair997";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 484;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_113 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_113 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_113 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_114_119 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_114_119 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_114_119 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_3_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__2\ : label is "soft_lutpair1009";
  attribute SOFT_HLUTNM of rrq_dsc_ld_901_i_2 : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of rrq_ld_901_i_1 : label is "soft_lutpair967";
  attribute SOFT_HLUTNM of \rrq_sm_cur_900[4]_i_3\ : label is "soft_lutpair1009";
begin
  \Head_reg[119]_0\(75 downto 0) <= \^head_reg[119]_0\(75 downto 0);
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  empty_ff_reg_1 <= \^empty_ff_reg_1\;
  rrq_ld_90022_out <= \^rrq_ld_90022_out\;
  \rrq_sm_cur_900_reg[4]\(0) <= \^rrq_sm_cur_900_reg[4]\(0);
\FifoCntrRd[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rrq_vld_903,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__2_n_0\
    );
\FifoCntrRd[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E718"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => rrq_vld_903,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(1),
      O => \FifoCntrRd[1]_i_1__2_n_0\
    );
\FifoCntrRd[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE7F0180"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(1),
      I2 => rrq_vld_903,
      I3 => \^empty_ff_reg_0\,
      I4 => FifoCntrRd(2),
      O => \FifoCntrRd[2]_i_1__1_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1__2_n_0\,
      Q => FifoCntrRd(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1__2_n_0\,
      Q => FifoCntrRd(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_1__1_n_0\,
      Q => FifoCntrRd(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => rrq_vld_903,
      I2 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__2_n_0\
    );
\FifoCntrWr[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DB24"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => \^empty_ff_reg_0\,
      I2 => rrq_vld_903,
      I3 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__2_n_0\
    );
\FifoCntrWr[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7EF0810"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \^empty_ff_reg_0\,
      I3 => rrq_vld_903,
      I4 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1__2_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1__2_n_0\,
      Q => FifoCntrWr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1__2_n_0\,
      Q => FifoCntrWr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1__2_n_0\,
      Q => FifoCntrWr(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head[100]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head0(100),
      I2 => Head1,
      O => p_0_in1_in(100)
    );
\Head[101]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head0(101),
      I2 => Head1,
      O => p_0_in1_in(101)
    );
\Head[102]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head0(102),
      I2 => Head1,
      O => p_0_in1_in(102)
    );
\Head[103]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head0(103),
      I2 => Head1,
      O => p_0_in1_in(103)
    );
\Head[104]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head0(104),
      I2 => Head1,
      O => p_0_in1_in(104)
    );
\Head[105]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head0(105),
      I2 => Head1,
      O => p_0_in1_in(105)
    );
\Head[106]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head0(106),
      I2 => Head1,
      O => p_0_in1_in(106)
    );
\Head[107]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head0(107),
      I2 => Head1,
      O => p_0_in1_in(107)
    );
\Head[108]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head0(108),
      I2 => Head1,
      O => p_0_in1_in(108)
    );
\Head[109]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head0(109),
      I2 => Head1,
      O => p_0_in1_in(109)
    );
\Head[110]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head0(110),
      I2 => Head1,
      O => p_0_in1_in(110)
    );
\Head[111]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head0(111),
      I2 => Head1,
      O => p_0_in1_in(111)
    );
\Head[112]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head0(112),
      I2 => Head1,
      O => p_0_in1_in(112)
    );
\Head[113]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head0(113),
      I2 => Head1,
      O => p_0_in1_in(113)
    );
\Head[114]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head0(114),
      I2 => Head1,
      O => p_0_in1_in(114)
    );
\Head[115]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head0(115),
      I2 => Head1,
      O => p_0_in1_in(115)
    );
\Head[116]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head0(116),
      I2 => Head1,
      O => p_0_in1_in(116)
    );
\Head[117]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head0(117),
      I2 => Head1,
      O => p_0_in1_in(117)
    );
\Head[118]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head0(118),
      I2 => Head1,
      O => p_0_in1_in(118)
    );
\Head[119]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEF"
    )
        port map (
      I0 => Head1,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(0),
      O => \Head[119]_i_1__1_n_0\
    );
\Head[119]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head0(119),
      I2 => Head1,
      O => p_0_in1_in(119)
    );
\Head[18]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head0(18),
      I2 => Head1,
      O => p_0_in1_in(18)
    );
\Head[19]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head0(19),
      I2 => Head1,
      O => p_0_in1_in(19)
    );
\Head[20]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(2),
      I1 => Head0(20),
      I2 => Head1,
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head0(21),
      I2 => Head1,
      O => p_0_in1_in(21)
    );
\Head[22]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head0(22),
      I2 => Head1,
      O => p_0_in1_in(22)
    );
\Head[23]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head0(23),
      I2 => Head1,
      O => p_0_in1_in(23)
    );
\Head[24]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head0(24),
      I2 => Head1,
      O => p_0_in1_in(24)
    );
\Head[25]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head0(25),
      I2 => Head1,
      O => p_0_in1_in(25)
    );
\Head[26]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head0(26),
      I2 => Head1,
      O => p_0_in1_in(26)
    );
\Head[27]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head0(27),
      I2 => Head1,
      O => p_0_in1_in(27)
    );
\Head[28]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head0(28),
      I2 => Head1,
      O => p_0_in1_in(28)
    );
\Head[29]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head0(29),
      I2 => Head1,
      O => p_0_in1_in(29)
    );
\Head[56]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head0(56),
      I2 => Head1,
      O => p_0_in1_in(56)
    );
\Head[57]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head0(57),
      I2 => Head1,
      O => p_0_in1_in(57)
    );
\Head[58]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head0(58),
      I2 => Head1,
      O => p_0_in1_in(58)
    );
\Head[59]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head0(59),
      I2 => Head1,
      O => p_0_in1_in(59)
    );
\Head[60]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head0(60),
      I2 => Head1,
      O => p_0_in1_in(60)
    );
\Head[61]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head0(61),
      I2 => Head1,
      O => p_0_in1_in(61)
    );
\Head[62]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head0(62),
      I2 => Head1,
      O => p_0_in1_in(62)
    );
\Head[63]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head0(63),
      I2 => Head1,
      O => p_0_in1_in(63)
    );
\Head[64]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head0(64),
      I2 => Head1,
      O => p_0_in1_in(64)
    );
\Head[65]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head0(65),
      I2 => Head1,
      O => p_0_in1_in(65)
    );
\Head[66]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head0(66),
      I2 => Head1,
      O => p_0_in1_in(66)
    );
\Head[67]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head0(67),
      I2 => Head1,
      O => p_0_in1_in(67)
    );
\Head[68]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head0(68),
      I2 => Head1,
      O => p_0_in1_in(68)
    );
\Head[69]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head0(69),
      I2 => Head1,
      O => p_0_in1_in(69)
    );
\Head[70]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head0(70),
      I2 => Head1,
      O => p_0_in1_in(70)
    );
\Head[71]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head0(71),
      I2 => Head1,
      O => p_0_in1_in(71)
    );
\Head[72]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head0(72),
      I2 => Head1,
      O => p_0_in1_in(72)
    );
\Head[73]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head0(73),
      I2 => Head1,
      O => p_0_in1_in(73)
    );
\Head[74]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head0(74),
      I2 => Head1,
      O => p_0_in1_in(74)
    );
\Head[75]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head0(75),
      I2 => Head1,
      O => p_0_in1_in(75)
    );
\Head[76]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head0(76),
      I2 => Head1,
      O => p_0_in1_in(76)
    );
\Head[77]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head0(77),
      I2 => Head1,
      O => p_0_in1_in(77)
    );
\Head[78]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head0(78),
      I2 => Head1,
      O => p_0_in1_in(78)
    );
\Head[79]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head0(79),
      I2 => Head1,
      O => p_0_in1_in(79)
    );
\Head[80]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head0(80),
      I2 => Head1,
      O => p_0_in1_in(80)
    );
\Head[81]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head0(81),
      I2 => Head1,
      O => p_0_in1_in(81)
    );
\Head[82]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head0(82),
      I2 => Head1,
      O => p_0_in1_in(82)
    );
\Head[83]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head0(83),
      I2 => Head1,
      O => p_0_in1_in(83)
    );
\Head[84]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head0(84),
      I2 => Head1,
      O => p_0_in1_in(84)
    );
\Head[85]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head0(85),
      I2 => Head1,
      O => p_0_in1_in(85)
    );
\Head[86]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head0(86),
      I2 => Head1,
      O => p_0_in1_in(86)
    );
\Head[87]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head0(87),
      I2 => Head1,
      O => p_0_in1_in(87)
    );
\Head[88]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head0(88),
      I2 => Head1,
      O => p_0_in1_in(88)
    );
\Head[89]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head0(89),
      I2 => Head1,
      O => p_0_in1_in(89)
    );
\Head[90]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head0(90),
      I2 => Head1,
      O => p_0_in1_in(90)
    );
\Head[91]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head0(91),
      I2 => Head1,
      O => p_0_in1_in(91)
    );
\Head[92]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head0(92),
      I2 => Head1,
      O => p_0_in1_in(92)
    );
\Head[93]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head0(93),
      I2 => Head1,
      O => p_0_in1_in(93)
    );
\Head[94]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head0(94),
      I2 => Head1,
      O => p_0_in1_in(94)
    );
\Head[95]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head0(95),
      I2 => Head1,
      O => p_0_in1_in(95)
    );
\Head[96]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head0(96),
      I2 => Head1,
      O => p_0_in1_in(96)
    );
\Head[97]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head0(97),
      I2 => Head1,
      O => p_0_in1_in(97)
    );
\Head[98]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head0(98),
      I2 => Head1,
      O => p_0_in1_in(98)
    );
\Head[99]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head0(99),
      I2 => Head1,
      O => p_0_in1_in(99)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(100),
      Q => \^head_reg[119]_0\(56),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(101),
      Q => \^head_reg[119]_0\(57),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(102),
      Q => \^head_reg[119]_0\(58),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(103),
      Q => \^head_reg[119]_0\(59),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(104),
      Q => \^head_reg[119]_0\(60),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(105),
      Q => \^head_reg[119]_0\(61),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(106),
      Q => \^head_reg[119]_0\(62),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(107),
      Q => \^head_reg[119]_0\(63),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(108),
      Q => \^head_reg[119]_0\(64),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(109),
      Q => \^head_reg[119]_0\(65),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(110),
      Q => \^head_reg[119]_0\(66),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(111),
      Q => \^head_reg[119]_0\(67),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(112),
      Q => \^head_reg[119]_0\(68),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(113),
      Q => \^head_reg[119]_0\(69),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(114),
      Q => \^head_reg[119]_0\(70),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(115),
      Q => \^head_reg[119]_0\(71),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(116),
      Q => \^head_reg[119]_0\(72),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(117),
      Q => \^head_reg[119]_0\(73),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(118),
      Q => \^head_reg[119]_0\(74),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(119),
      Q => \^head_reg[119]_0\(75),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(18),
      Q => \^head_reg[119]_0\(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(19),
      Q => \^head_reg[119]_0\(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(20),
      Q => \^head_reg[119]_0\(2),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(21),
      Q => \^head_reg[119]_0\(3),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(22),
      Q => \^head_reg[119]_0\(4),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(23),
      Q => \^head_reg[119]_0\(5),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(24),
      Q => \^head_reg[119]_0\(6),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(25),
      Q => \^head_reg[119]_0\(7),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(26),
      Q => \^head_reg[119]_0\(8),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(27),
      Q => \^head_reg[119]_0\(9),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(28),
      Q => \^head_reg[119]_0\(10),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(29),
      Q => \^head_reg[119]_0\(11),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(56),
      Q => \^head_reg[119]_0\(12),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(57),
      Q => \^head_reg[119]_0\(13),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(58),
      Q => \^head_reg[119]_0\(14),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(59),
      Q => \^head_reg[119]_0\(15),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(60),
      Q => \^head_reg[119]_0\(16),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(61),
      Q => \^head_reg[119]_0\(17),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(62),
      Q => \^head_reg[119]_0\(18),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(63),
      Q => \^head_reg[119]_0\(19),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(64),
      Q => \^head_reg[119]_0\(20),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(65),
      Q => \^head_reg[119]_0\(21),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(66),
      Q => \^head_reg[119]_0\(22),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(67),
      Q => \^head_reg[119]_0\(23),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(68),
      Q => \^head_reg[119]_0\(24),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(69),
      Q => \^head_reg[119]_0\(25),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(70),
      Q => \^head_reg[119]_0\(26),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(71),
      Q => \^head_reg[119]_0\(27),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(72),
      Q => \^head_reg[119]_0\(28),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(73),
      Q => \^head_reg[119]_0\(29),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(74),
      Q => \^head_reg[119]_0\(30),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(75),
      Q => \^head_reg[119]_0\(31),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(76),
      Q => \^head_reg[119]_0\(32),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(77),
      Q => \^head_reg[119]_0\(33),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(78),
      Q => \^head_reg[119]_0\(34),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(79),
      Q => \^head_reg[119]_0\(35),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(80),
      Q => \^head_reg[119]_0\(36),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(81),
      Q => \^head_reg[119]_0\(37),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(82),
      Q => \^head_reg[119]_0\(38),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(83),
      Q => \^head_reg[119]_0\(39),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(84),
      Q => \^head_reg[119]_0\(40),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(85),
      Q => \^head_reg[119]_0\(41),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(86),
      Q => \^head_reg[119]_0\(42),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(87),
      Q => \^head_reg[119]_0\(43),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(88),
      Q => \^head_reg[119]_0\(44),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(89),
      Q => \^head_reg[119]_0\(45),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(90),
      Q => \^head_reg[119]_0\(46),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(91),
      Q => \^head_reg[119]_0\(47),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(92),
      Q => \^head_reg[119]_0\(48),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(93),
      Q => \^head_reg[119]_0\(49),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(94),
      Q => \^head_reg[119]_0\(50),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(95),
      Q => \^head_reg[119]_0\(51),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(96),
      Q => \^head_reg[119]_0\(52),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(97),
      Q => \^head_reg[119]_0\(53),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(98),
      Q => \^head_reg[119]_0\(54),
      R => \FifoCntrRd_reg[2]_0\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__1_n_0\,
      D => p_0_in1_in(99),
      Q => \^head_reg[119]_0\(55),
      R => \FifoCntrRd_reg[2]_0\
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(59 downto 58),
      DIB(1 downto 0) => DataIn(61 downto 60),
      DIC(1 downto 0) => DataIn(63 downto 62),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_102_107_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(59),
      O => payloadOut(59)
    );
\MemArray_reg_0_3_102_107_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(58),
      O => payloadOut(58)
    );
\MemArray_reg_0_3_102_107_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(61),
      O => payloadOut(61)
    );
\MemArray_reg_0_3_102_107_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(60),
      O => payloadOut(60)
    );
\MemArray_reg_0_3_102_107_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(63),
      O => payloadOut(63)
    );
\MemArray_reg_0_3_102_107_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(62),
      O => payloadOut(62)
    );
MemArray_reg_0_3_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(65 downto 64),
      DIB(1 downto 0) => DataIn(67 downto 66),
      DIC(1 downto 0) => DataIn(69 downto 68),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => Head0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_108_113_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(65),
      O => payloadOut(65)
    );
\MemArray_reg_0_3_108_113_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(64),
      O => payloadOut(64)
    );
\MemArray_reg_0_3_108_113_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(67),
      O => payloadOut(67)
    );
\MemArray_reg_0_3_108_113_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(66),
      O => payloadOut(66)
    );
\MemArray_reg_0_3_108_113_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(69),
      O => payloadOut(69)
    );
\MemArray_reg_0_3_108_113_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(68),
      O => payloadOut(68)
    );
MemArray_reg_0_3_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(71 downto 70),
      DIB(1 downto 0) => DataIn(73 downto 72),
      DIC(1 downto 0) => DataIn(75 downto 74),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(115 downto 114),
      DOB(1 downto 0) => Head0(117 downto 116),
      DOC(1 downto 0) => Head0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_114_119_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(71),
      O => payloadOut(71)
    );
\MemArray_reg_0_3_114_119_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(70),
      O => payloadOut(70)
    );
\MemArray_reg_0_3_114_119_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(73),
      O => payloadOut(73)
    );
\MemArray_reg_0_3_114_119_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(72),
      O => payloadOut(72)
    );
\MemArray_reg_0_3_114_119_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(75),
      O => payloadOut(75)
    );
\MemArray_reg_0_3_114_119_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(74),
      O => payloadOut(74)
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_18_23_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      O => \^empty_ff_reg_0\
    );
\MemArray_reg_0_3_18_23_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(1),
      O => payloadOut(1)
    );
\MemArray_reg_0_3_18_23_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(0),
      O => payloadOut(0)
    );
\MemArray_reg_0_3_18_23_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(3),
      O => payloadOut(3)
    );
\MemArray_reg_0_3_18_23_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(2),
      O => payloadOut(2)
    );
\MemArray_reg_0_3_18_23_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(5),
      O => payloadOut(5)
    );
MemArray_reg_0_3_18_23_i_7: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(4),
      O => payloadOut(4)
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(7 downto 6),
      DIB(1 downto 0) => DataIn(9 downto 8),
      DIC(1 downto 0) => DataIn(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(25 downto 24),
      DOB(1 downto 0) => Head0(27 downto 26),
      DOC(1 downto 0) => Head0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_24_29_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(7),
      O => payloadOut(7)
    );
\MemArray_reg_0_3_24_29_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(6),
      O => payloadOut(6)
    );
\MemArray_reg_0_3_24_29_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(9),
      O => payloadOut(9)
    );
\MemArray_reg_0_3_24_29_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(8),
      O => payloadOut(8)
    );
\MemArray_reg_0_3_24_29_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(11),
      O => payloadOut(11)
    );
\MemArray_reg_0_3_24_29_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(10),
      O => payloadOut(10)
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => DataIn(13 downto 12),
      DIC(1 downto 0) => DataIn(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(57 downto 56),
      DOC(1 downto 0) => Head0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_54_59_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(13),
      O => payloadOut(13)
    );
\MemArray_reg_0_3_54_59_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(12),
      O => payloadOut(12)
    );
\MemArray_reg_0_3_54_59_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(15),
      O => payloadOut(15)
    );
\MemArray_reg_0_3_54_59_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(14),
      O => payloadOut(14)
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(17 downto 16),
      DIB(1 downto 0) => DataIn(19 downto 18),
      DIC(1 downto 0) => DataIn(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_60_65_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(17),
      O => payloadOut(17)
    );
\MemArray_reg_0_3_60_65_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(16),
      O => payloadOut(16)
    );
\MemArray_reg_0_3_60_65_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(19),
      O => payloadOut(19)
    );
\MemArray_reg_0_3_60_65_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(18),
      O => payloadOut(18)
    );
\MemArray_reg_0_3_60_65_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(21),
      O => payloadOut(21)
    );
\MemArray_reg_0_3_60_65_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(20),
      O => payloadOut(20)
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(23 downto 22),
      DIB(1 downto 0) => DataIn(25 downto 24),
      DIC(1 downto 0) => DataIn(27 downto 26),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_66_71_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(23),
      O => payloadOut(23)
    );
\MemArray_reg_0_3_66_71_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(22),
      O => payloadOut(22)
    );
\MemArray_reg_0_3_66_71_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(25),
      O => payloadOut(25)
    );
\MemArray_reg_0_3_66_71_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(24),
      O => payloadOut(24)
    );
\MemArray_reg_0_3_66_71_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(27),
      O => payloadOut(27)
    );
\MemArray_reg_0_3_66_71_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(26),
      O => payloadOut(26)
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(29 downto 28),
      DIB(1 downto 0) => DataIn(31 downto 30),
      DIC(1 downto 0) => DataIn(33 downto 32),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_72_77_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(29),
      O => payloadOut(29)
    );
\MemArray_reg_0_3_72_77_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(28),
      O => payloadOut(28)
    );
\MemArray_reg_0_3_72_77_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(31),
      O => payloadOut(31)
    );
\MemArray_reg_0_3_72_77_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(30),
      O => payloadOut(30)
    );
\MemArray_reg_0_3_72_77_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(33),
      O => payloadOut(33)
    );
\MemArray_reg_0_3_72_77_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(32),
      O => payloadOut(32)
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(35 downto 34),
      DIB(1 downto 0) => DataIn(37 downto 36),
      DIC(1 downto 0) => DataIn(39 downto 38),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_78_83_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(35),
      O => payloadOut(35)
    );
\MemArray_reg_0_3_78_83_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(34),
      O => payloadOut(34)
    );
\MemArray_reg_0_3_78_83_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(37),
      O => payloadOut(37)
    );
\MemArray_reg_0_3_78_83_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(36),
      O => payloadOut(36)
    );
\MemArray_reg_0_3_78_83_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(39),
      O => payloadOut(39)
    );
\MemArray_reg_0_3_78_83_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(38),
      O => payloadOut(38)
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(41 downto 40),
      DIB(1 downto 0) => DataIn(43 downto 42),
      DIC(1 downto 0) => DataIn(45 downto 44),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_84_89_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(41),
      O => payloadOut(41)
    );
\MemArray_reg_0_3_84_89_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(40),
      O => payloadOut(40)
    );
\MemArray_reg_0_3_84_89_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(43),
      O => payloadOut(43)
    );
\MemArray_reg_0_3_84_89_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(42),
      O => payloadOut(42)
    );
\MemArray_reg_0_3_84_89_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(45),
      O => payloadOut(45)
    );
\MemArray_reg_0_3_84_89_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(44),
      O => payloadOut(44)
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(47 downto 46),
      DIB(1 downto 0) => DataIn(49 downto 48),
      DIC(1 downto 0) => DataIn(51 downto 50),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_90_95_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(47),
      O => payloadOut(47)
    );
\MemArray_reg_0_3_90_95_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(46),
      O => payloadOut(46)
    );
\MemArray_reg_0_3_90_95_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(49),
      O => payloadOut(49)
    );
\MemArray_reg_0_3_90_95_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(48),
      O => payloadOut(48)
    );
\MemArray_reg_0_3_90_95_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(51),
      O => payloadOut(51)
    );
\MemArray_reg_0_3_90_95_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(50),
      O => payloadOut(50)
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(53 downto 52),
      DIB(1 downto 0) => DataIn(55 downto 54),
      DIC(1 downto 0) => DataIn(57 downto 56),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_96_101_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(53),
      O => payloadOut(53)
    );
\MemArray_reg_0_3_96_101_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(52),
      O => payloadOut(52)
    );
\MemArray_reg_0_3_96_101_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(55),
      O => payloadOut(55)
    );
\MemArray_reg_0_3_96_101_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(54),
      O => payloadOut(54)
    );
\MemArray_reg_0_3_96_101_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(57),
      O => payloadOut(57)
    );
\MemArray_reg_0_3_96_101_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => almost_full_ff,
      I2 => \^head_reg[119]_0\(56),
      O => payloadOut(56)
    );
\RdPtr[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5555666A"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => Head1,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55577777AAA88888"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \^empty_ff_reg_0\,
      I5 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[1]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03010000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => \^empty_ff_reg_0\,
      I4 => rrq_vld_903,
      O => Head1
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\WrPtr[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => rrq_vld_903,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => rrq_vld_903,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => \FifoCntrRd_reg[2]_0\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => \FifoCntrRd_reg[2]_0\
    );
\dat_fifo_hd_nn1[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => Q(0),
      I1 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I2 => dat_fifo_hd_nn1(0),
      I3 => ctl_run_re,
      O => \dat_fifo_hd_nxt_nn1_reg[0]\
    );
\dat_fifo_hd_nn1[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => Q(1),
      I1 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I2 => dat_fifo_hd_nn1(1),
      I3 => ctl_run_re,
      O => \dat_fifo_hd_nxt_nn1_reg[1]\
    );
\dat_fifo_hd_nn1[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => Q(2),
      I1 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I2 => dat_fifo_hd_nn1(2),
      I3 => ctl_run_re,
      O => \dat_fifo_hd_nxt_nn1_reg[2]\
    );
\dat_fifo_hd_nn1[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => Q(3),
      I1 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I2 => dat_fifo_hd_nn1(3),
      I3 => ctl_run_re,
      O => \dat_fifo_hd_nxt_nn1_reg[3]\
    );
\dat_fifo_hd_nn1[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => ctl_run_re,
      I1 => Q(4),
      I2 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I3 => dat_fifo_hd_nn1(4),
      O => ctl_rst_nn1_reg
    );
\dat_fifo_hd_nn1[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => ctl_run_re,
      I1 => Q(5),
      I2 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I3 => dat_fifo_hd_nn1(5),
      O => ctl_rst_nn1_reg_0
    );
\dat_fifo_hd_nn1[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => ctl_run_re,
      I1 => Q(6),
      I2 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I3 => dat_fifo_hd_nn1(6),
      O => ctl_rst_nn1_reg_1
    );
\dat_fifo_hd_nn1[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => ctl_run_re,
      I1 => Q(7),
      I2 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I3 => dat_fifo_hd_nn1(7),
      O => ctl_rst_nn1_reg_2
    );
\dat_fifo_hd_nn1[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAE"
    )
        port map (
      I0 => ctl_run_re,
      I1 => Q(8),
      I2 => \dat_fifo_hd_nn1[8]_i_2_n_0\,
      I3 => dat_fifo_hd_nn1(8),
      O => ctl_rst_nn1_reg_3
    );
\dat_fifo_hd_nn1[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFBFFFFFF"
    )
        port map (
      I0 => \dat_fifo_hd_nn1_reg[8]\,
      I1 => \dat_fifo_hd_nn1_reg[8]_0\,
      I2 => \rrq_sm_cur_900_reg[3]_0\(0),
      I3 => \rrq_sm_cur_900_reg[3]_0\(3),
      I4 => rrq_vld_903,
      I5 => full_ff_reg_n_0,
      O => \dat_fifo_hd_nn1[8]_i_2_n_0\
    );
\dat_fifo_hd_nn1[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11100010"
    )
        port map (
      I0 => ctl_run_re,
      I1 => \dat_fifo_hd_nn1_reg[9]\,
      I2 => dat_fifo_hd_nn1(9),
      I3 => \^rrq_ld_90022_out\,
      I4 => Q(9),
      O => D(0)
    );
\empty_ff_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_1\,
      I4 => \empty_ff_i_2__2_n_0\,
      O => \empty_ff_i_1__2_n_0\
    );
\empty_ff_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAEF"
    )
        port map (
      I0 => \dat_fifo_hd_nn1_reg[9]\,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(2),
      I5 => cfg_linkdown_nn1,
      O => \empty_ff_i_2__2_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__2_n_0\,
      Q => \^empty_ff_reg_1\,
      R => '0'
    );
\full_ff_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => rrq_vld_903,
      I3 => FifoCntrWr(2),
      I4 => full_ff_reg_n_0,
      O => \full_ff_i_1__1_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__1_n_0\,
      Q => full_ff_reg_n_0,
      R => \FifoCntrRd_reg[2]_0\
    );
rrq_dsc_ld_901_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => full_ff_reg_n_0,
      I1 => rrq_vld_903,
      I2 => \rrq_sm_cur_900_reg[3]_0\(3),
      I3 => \rrq_sm_cur_900_reg[3]_0\(2),
      O => full_ff_reg_0
    );
rrq_ld_901_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[3]_0\(2),
      I1 => \rrq_sm_cur_900_reg[3]_0\(3),
      I2 => rrq_vld_903,
      I3 => full_ff_reg_n_0,
      I4 => \rrq_ld_901_reg_rep__5\,
      O => \^rrq_ld_90022_out\
    );
\rrq_sm_cur_900[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200020000"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[3]_1\,
      I1 => \rrq_sm_cur_900[3]_i_2_n_0\,
      I2 => \rrq_sm_cur_900_reg[3]_0\(4),
      I3 => \rrq_sm_cur_900_reg[3]_0\(0),
      I4 => \rrq_sm_cur_900_reg[3]_0\(3),
      I5 => \rrq_sm_cur_900_reg[3]_0\(5),
      O => \^rrq_sm_cur_900_reg[4]\(0)
    );
\rrq_sm_cur_900[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF40"
    )
        port map (
      I0 => full_ff_reg_n_0,
      I1 => rrq_vld_903,
      I2 => \rrq_sm_cur_900_reg[3]_0\(3),
      I3 => \rrq_sm_cur_900_reg[3]_0\(1),
      I4 => \rrq_sm_cur_900_reg[3]_0\(2),
      I5 => \rrq_sm_cur_900_reg[3]_0\(6),
      O => \rrq_sm_cur_900[3]_i_2_n_0\
    );
\rrq_sm_cur_900[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[3]_0\(3),
      I1 => rrq_vld_903,
      I2 => full_ff_reg_n_0,
      O => \rrq_sm_cur_900_reg[3]\
    );
rrq_vld_903_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^rrq_sm_cur_900_reg[4]\(0),
      I1 => rrq_vld_903_i_2_n_0,
      I2 => rrq_vld_903_reg(0),
      O => rrq_vld_902
    );
rrq_vld_903_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => rrq_stall_902,
      I1 => full_ff_reg_n_0,
      I2 => rrq_dsc_rem0_902,
      I3 => rrq_dsc_vld_902,
      I4 => rrq_fl_nn1,
      O => rrq_vld_903_i_2_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_51\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[4]\ : out STD_LOGIC;
    rrq_ld_9008_out : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[5]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[6]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[7]\ : out STD_LOGIC;
    \dat_fifo_hd_nxt_nn1_reg[8]\ : out STD_LOGIC;
    \pcie_h2c_rst_3ff_reg[0]_rep__4\ : out STD_LOGIC;
    empty_ff_reg_1 : out STD_LOGIC;
    empty_ff_reg_2 : out STD_LOGIC;
    empty_ff_reg_3 : out STD_LOGIC_VECTOR ( 94 downto 0 );
    rrq_vld_902 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dat_fifo_hd_nn1_reg[9]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rrq_vld_903_reg : out STD_LOGIC;
    \Head_reg[119]_0\ : out STD_LOGIC_VECTOR ( 91 downto 0 );
    \FifoCntrRd_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \dat_fifo_hd_out_nn1_reg[0]\ : in STD_LOGIC;
    cfg_linkdown_nn1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
    ctl_run_re : in STD_LOGIC;
    dat_fifo_hd_nn1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
    \Head_reg[8]_0\ : in STD_LOGIC;
    almost_full_ff_0 : in STD_LOGIC;
    arbhist_ff : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[8]_1\ : in STD_LOGIC;
    rrq_vld_903_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rrq_sm_cur_900_reg[3]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \rrq_sm_cur_900_reg[3]_0\ : in STD_LOGIC;
    rrq_vld_903 : in STD_LOGIC;
    \rrq_ld_901_reg_rep__5\ : in STD_LOGIC;
    rrq_fl_nn1 : in STD_LOGIC;
    rrq_stall_902 : in STD_LOGIC;
    rrq_dsc_rem0_902 : in STD_LOGIC;
    rrq_dsc_vld_902 : in STD_LOGIC;
    \Head_reg[119]_1\ : in STD_LOGIC_VECTOR ( 91 downto 0 );
    \Head_reg[119]_2\ : in STD_LOGIC_VECTOR ( 81 downto 0 );
    \Head1__2_1\ : in STD_LOGIC;
    \FifoCntrRd_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrWr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 91 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_51\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_51\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized1_51\ is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__3_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__4_n_0\ : STD_LOGIC;
  signal Head0 : STD_LOGIC_VECTOR ( 119 downto 8 );
  signal Head1 : STD_LOGIC;
  signal \Head[119]_i_1__3_n_0\ : STD_LOGIC;
  signal \Head[31]_i_1__2_n_0\ : STD_LOGIC;
  signal \Head[51]_i_1__3_n_0\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \empty_ff_i_1__5_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__3_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \^empty_ff_reg_1\ : STD_LOGIC;
  signal \^empty_ff_reg_2\ : STD_LOGIC;
  signal \^empty_ff_reg_3\ : STD_LOGIC_VECTOR ( 94 downto 0 );
  signal \full_ff_i_1__3_n_0\ : STD_LOGIC;
  signal full_ff_reg_n_0 : STD_LOGIC;
  signal \h2c_xdma_rrq_req[0][adr]\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \h2c_xdma_rrq_req[0][byte_len]\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \h2c_xdma_rrq_req[0][did]\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \h2c_xdma_rrq_req[0][rid]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 119 downto 8 );
  signal \^pcie_h2c_rst_3ff_reg[0]_rep__4\ : STD_LOGIC;
  signal \^rrq_ld_9008_out\ : STD_LOGIC;
  signal \rrq_sm_cur_900[3]_i_3_n_0\ : STD_LOGIC;
  signal \rrq_vld_903_i_2__0_n_0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_48_53_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__4\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__4\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_1__3\ : label is "soft_lutpair584";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__4\ : label is "soft_lutpair633";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__4\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__4\ : label is "soft_lutpair585";
  attribute SOFT_HLUTNM of \Head[100]_i_1__5\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \Head[101]_i_1__5\ : label is "soft_lutpair623";
  attribute SOFT_HLUTNM of \Head[102]_i_1__5\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \Head[103]_i_1__5\ : label is "soft_lutpair624";
  attribute SOFT_HLUTNM of \Head[104]_i_1__5\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \Head[105]_i_1__5\ : label is "soft_lutpair625";
  attribute SOFT_HLUTNM of \Head[106]_i_1__5\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \Head[107]_i_1__5\ : label is "soft_lutpair626";
  attribute SOFT_HLUTNM of \Head[108]_i_1__5\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \Head[109]_i_1__5\ : label is "soft_lutpair627";
  attribute SOFT_HLUTNM of \Head[10]_i_1__4\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \Head[110]_i_1__5\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \Head[111]_i_1__4\ : label is "soft_lutpair628";
  attribute SOFT_HLUTNM of \Head[112]_i_1__3\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \Head[113]_i_1__3\ : label is "soft_lutpair629";
  attribute SOFT_HLUTNM of \Head[114]_i_1__3\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \Head[115]_i_1__3\ : label is "soft_lutpair630";
  attribute SOFT_HLUTNM of \Head[116]_i_1__3\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \Head[117]_i_1__3\ : label is "soft_lutpair631";
  attribute SOFT_HLUTNM of \Head[118]_i_1__3\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \Head[119]_i_2__1\ : label is "soft_lutpair632";
  attribute SOFT_HLUTNM of \Head[11]_i_1__4\ : label is "soft_lutpair588";
  attribute SOFT_HLUTNM of \Head[12]_i_1__4\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \Head[13]_i_1__4\ : label is "soft_lutpair589";
  attribute SOFT_HLUTNM of \Head[14]_i_1__4\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \Head[15]_i_1__4\ : label is "soft_lutpair590";
  attribute SOFT_HLUTNM of \Head[16]_i_1__3\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \Head[17]_i_1__3\ : label is "soft_lutpair591";
  attribute SOFT_HLUTNM of \Head[18]_i_1__4\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \Head[19]_i_1__4\ : label is "soft_lutpair592";
  attribute SOFT_HLUTNM of \Head[20]_i_1__5\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \Head[21]_i_1__5\ : label is "soft_lutpair593";
  attribute SOFT_HLUTNM of \Head[22]_i_1__3\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \Head[23]_i_1__3\ : label is "soft_lutpair594";
  attribute SOFT_HLUTNM of \Head[24]_i_1__3\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \Head[25]_i_1__3\ : label is "soft_lutpair595";
  attribute SOFT_HLUTNM of \Head[26]_i_1__3\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \Head[27]_i_1__3\ : label is "soft_lutpair596";
  attribute SOFT_HLUTNM of \Head[28]_i_1__3\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \Head[29]_i_1__3\ : label is "soft_lutpair597";
  attribute SOFT_HLUTNM of \Head[30]_i_1__2\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \Head[31]_i_1__2\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \Head[46]_i_1__2\ : label is "soft_lutpair598";
  attribute SOFT_HLUTNM of \Head[47]_i_1__3\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \Head[48]_i_1__3\ : label is "soft_lutpair599";
  attribute SOFT_HLUTNM of \Head[49]_i_1__3\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \Head[50]_i_1__3\ : label is "soft_lutpair600";
  attribute SOFT_HLUTNM of \Head[51]_i_1__3\ : label is "soft_lutpair587";
  attribute SOFT_HLUTNM of \Head[56]_i_1__4\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \Head[57]_i_1__4\ : label is "soft_lutpair601";
  attribute SOFT_HLUTNM of \Head[58]_i_1__4\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \Head[59]_i_1__4\ : label is "soft_lutpair602";
  attribute SOFT_HLUTNM of \Head[60]_i_1__4\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \Head[61]_i_1__5\ : label is "soft_lutpair603";
  attribute SOFT_HLUTNM of \Head[62]_i_1__5\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \Head[63]_i_1__5\ : label is "soft_lutpair604";
  attribute SOFT_HLUTNM of \Head[64]_i_1__5\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \Head[65]_i_1__5\ : label is "soft_lutpair605";
  attribute SOFT_HLUTNM of \Head[66]_i_1__5\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \Head[67]_i_1__5\ : label is "soft_lutpair606";
  attribute SOFT_HLUTNM of \Head[68]_i_1__5\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \Head[69]_i_1__5\ : label is "soft_lutpair607";
  attribute SOFT_HLUTNM of \Head[70]_i_1__5\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \Head[71]_i_1__5\ : label is "soft_lutpair608";
  attribute SOFT_HLUTNM of \Head[72]_i_1__5\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \Head[73]_i_1__5\ : label is "soft_lutpair609";
  attribute SOFT_HLUTNM of \Head[74]_i_1__5\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \Head[75]_i_1__5\ : label is "soft_lutpair610";
  attribute SOFT_HLUTNM of \Head[76]_i_1__5\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \Head[77]_i_1__5\ : label is "soft_lutpair611";
  attribute SOFT_HLUTNM of \Head[78]_i_1__5\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \Head[79]_i_1__5\ : label is "soft_lutpair612";
  attribute SOFT_HLUTNM of \Head[80]_i_1__5\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \Head[81]_i_1__5\ : label is "soft_lutpair613";
  attribute SOFT_HLUTNM of \Head[82]_i_1__5\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \Head[83]_i_1__5\ : label is "soft_lutpair614";
  attribute SOFT_HLUTNM of \Head[84]_i_1__5\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \Head[85]_i_1__5\ : label is "soft_lutpair615";
  attribute SOFT_HLUTNM of \Head[86]_i_1__5\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \Head[87]_i_1__5\ : label is "soft_lutpair616";
  attribute SOFT_HLUTNM of \Head[88]_i_1__5\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \Head[89]_i_1__5\ : label is "soft_lutpair617";
  attribute SOFT_HLUTNM of \Head[8]_i_1__2\ : label is "soft_lutpair586";
  attribute SOFT_HLUTNM of \Head[90]_i_1__5\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \Head[91]_i_1__5\ : label is "soft_lutpair618";
  attribute SOFT_HLUTNM of \Head[92]_i_1__5\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \Head[93]_i_1__5\ : label is "soft_lutpair619";
  attribute SOFT_HLUTNM of \Head[94]_i_1__5\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \Head[95]_i_1__5\ : label is "soft_lutpair620";
  attribute SOFT_HLUTNM of \Head[96]_i_1__5\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \Head[97]_i_1__5\ : label is "soft_lutpair621";
  attribute SOFT_HLUTNM of \Head[98]_i_1__5\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \Head[99]_i_1__5\ : label is "soft_lutpair622";
  attribute SOFT_HLUTNM of \Head[9]_i_1__4\ : label is "soft_lutpair587";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 484;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_113 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_113 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_113 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_114_119 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_114_119 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_114_119 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_3_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_35 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_35 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_42_47 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_42_47 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_48_53 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_48_53 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 484;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__5\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__5\ : label is "soft_lutpair634";
  attribute SOFT_HLUTNM of \rrq_ld_901_i_1__0\ : label is "soft_lutpair583";
  attribute SOFT_HLUTNM of \rrq_sm_cur_900[4]_i_3__0\ : label is "soft_lutpair583";
begin
  D(0) <= \^d\(0);
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  empty_ff_reg_1 <= \^empty_ff_reg_1\;
  empty_ff_reg_2 <= \^empty_ff_reg_2\;
  empty_ff_reg_3(94 downto 0) <= \^empty_ff_reg_3\(94 downto 0);
  \pcie_h2c_rst_3ff_reg[0]_rep__4\ <= \^pcie_h2c_rst_3ff_reg[0]_rep__4\;
  rrq_ld_9008_out <= \^rrq_ld_9008_out\;
\FifoCntrRd[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rrq_vld_903,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__4_n_0\
    );
\FifoCntrRd[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E718"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => rrq_vld_903,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(1),
      O => \FifoCntrRd[1]_i_1__4_n_0\
    );
\FifoCntrRd[1]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \^empty_ff_reg_3\(94),
      I2 => \FifoCntrRd_reg[1]_1\(1),
      I3 => \FifoCntrRd_reg[1]_1\(0),
      O => \FifoCntrRd_reg[1]_0\(0)
    );
\FifoCntrRd[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE7F0180"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(1),
      I2 => rrq_vld_903,
      I3 => \^empty_ff_reg_0\,
      I4 => FifoCntrRd(2),
      O => \FifoCntrRd[2]_i_1__3_n_0\
    );
\FifoCntrRd[2]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dat_fifo_hd_out_nn1_reg[0]\,
      I1 => cfg_linkdown_nn1,
      O => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd[2]_i_2__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0405"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => almost_full_ff_0,
      I3 => arbhist_ff(0),
      O => \^empty_ff_reg_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1__4_n_0\,
      Q => FifoCntrRd(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1__4_n_0\,
      Q => FifoCntrRd(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_1__3_n_0\,
      Q => FifoCntrRd(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => rrq_vld_903,
      I2 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__4_n_0\
    );
\FifoCntrWr[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DB24"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => \^empty_ff_reg_1\,
      I2 => rrq_vld_903,
      I3 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__4_n_0\
    );
\FifoCntrWr[1]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \^empty_ff_reg_3\(94),
      I2 => \FifoCntrWr_reg[1]_0\(0),
      I3 => \FifoCntrWr_reg[1]_0\(1),
      O => \FifoCntrWr_reg[0]_0\(0)
    );
\FifoCntrWr[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7EF0810"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \^empty_ff_reg_1\,
      I3 => rrq_vld_903,
      I4 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1__4_n_0\
    );
\FifoCntrWr[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0405"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => almost_full_ff_0,
      I3 => arbhist_ff(0),
      O => \^empty_ff_reg_1\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1__4_n_0\,
      Q => FifoCntrWr(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1__4_n_0\,
      Q => FifoCntrWr(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1__4_n_0\,
      Q => FifoCntrWr(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head[100]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head0(100),
      I2 => Head1,
      O => p_0_in1_in(100)
    );
\Head[100]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(72),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(44),
      I3 => \Head_reg[119]_2\(62),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(72)
    );
\Head[101]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head0(101),
      I2 => Head1,
      O => p_0_in1_in(101)
    );
\Head[101]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(73),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(45),
      I3 => \Head_reg[119]_2\(63),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(73)
    );
\Head[102]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head0(102),
      I2 => Head1,
      O => p_0_in1_in(102)
    );
\Head[102]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(74),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(46),
      I3 => \Head_reg[119]_2\(64),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(74)
    );
\Head[103]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head0(103),
      I2 => Head1,
      O => p_0_in1_in(103)
    );
\Head[103]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(75),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(47),
      I3 => \Head_reg[119]_2\(65),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(75)
    );
\Head[104]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head0(104),
      I2 => Head1,
      O => p_0_in1_in(104)
    );
\Head[104]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(76),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(48),
      I3 => \Head_reg[119]_2\(66),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(76)
    );
\Head[105]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head0(105),
      I2 => Head1,
      O => p_0_in1_in(105)
    );
\Head[105]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(77),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(49),
      I3 => \Head_reg[119]_2\(67),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(77)
    );
\Head[106]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head0(106),
      I2 => Head1,
      O => p_0_in1_in(106)
    );
\Head[106]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(78),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(50),
      I3 => \Head_reg[119]_2\(68),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(78)
    );
\Head[107]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head0(107),
      I2 => Head1,
      O => p_0_in1_in(107)
    );
\Head[107]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(79),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(51),
      I3 => \Head_reg[119]_2\(69),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(79)
    );
\Head[108]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head0(108),
      I2 => Head1,
      O => p_0_in1_in(108)
    );
\Head[108]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(80),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(52),
      I3 => \Head_reg[119]_2\(70),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(80)
    );
\Head[109]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(81),
      I1 => Head0(109),
      I2 => Head1,
      O => p_0_in1_in(109)
    );
\Head[109]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(81),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(53),
      I3 => \Head_reg[119]_2\(71),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(81)
    );
\Head[10]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(2),
      I1 => Head0(10),
      I2 => Head1,
      O => p_0_in1_in(10)
    );
\Head[10]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(2),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(2),
      I3 => \Head_reg[119]_2\(2),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(2)
    );
\Head[110]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(82),
      I1 => Head0(110),
      I2 => Head1,
      O => p_0_in1_in(110)
    );
\Head[110]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(82),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(54),
      I3 => \Head_reg[119]_2\(72),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(82)
    );
\Head[111]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(83),
      I1 => Head0(111),
      I2 => Head1,
      O => p_0_in1_in(111)
    );
\Head[111]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(83),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(55),
      I3 => \Head_reg[119]_2\(73),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(83)
    );
\Head[112]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(84),
      I1 => Head0(112),
      I2 => Head1,
      O => p_0_in1_in(112)
    );
\Head[112]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(84),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(56),
      I3 => \Head_reg[119]_2\(74),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(84)
    );
\Head[113]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(85),
      I1 => Head0(113),
      I2 => Head1,
      O => p_0_in1_in(113)
    );
\Head[113]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(85),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(57),
      I3 => \Head_reg[119]_2\(75),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(85)
    );
\Head[114]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(86),
      I1 => Head0(114),
      I2 => Head1,
      O => p_0_in1_in(114)
    );
\Head[114]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(86),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(58),
      I3 => \Head_reg[119]_2\(76),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(86)
    );
\Head[115]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(87),
      I1 => Head0(115),
      I2 => Head1,
      O => p_0_in1_in(115)
    );
\Head[115]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(87),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(59),
      I3 => \Head_reg[119]_2\(77),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(87)
    );
\Head[116]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(88),
      I1 => Head0(116),
      I2 => Head1,
      O => p_0_in1_in(116)
    );
\Head[116]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(88),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(60),
      I3 => \Head_reg[119]_2\(78),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(88)
    );
\Head[117]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(89),
      I1 => Head0(117),
      I2 => Head1,
      O => p_0_in1_in(117)
    );
\Head[117]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(89),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(61),
      I3 => \Head_reg[119]_2\(79),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(89)
    );
\Head[118]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(90),
      I1 => Head0(118),
      I2 => Head1,
      O => p_0_in1_in(118)
    );
\Head[118]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(90),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(62),
      I3 => \Head_reg[119]_2\(80),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(90)
    );
\Head[119]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEEF"
    )
        port map (
      I0 => Head1,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(0),
      O => \Head[119]_i_1__3_n_0\
    );
\Head[119]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(91),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(63),
      I3 => \Head_reg[119]_2\(81),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(91)
    );
\Head[119]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(91),
      I1 => Head0(119),
      I2 => Head1,
      O => p_0_in1_in(119)
    );
\Head[11]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head0(11),
      I2 => Head1,
      O => p_0_in1_in(11)
    );
\Head[11]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(3),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(3),
      I3 => \Head_reg[119]_2\(3),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(3)
    );
\Head[12]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head0(12),
      I2 => Head1,
      O => p_0_in1_in(12)
    );
\Head[12]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(4),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(4),
      I3 => \Head_reg[119]_2\(4),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(4)
    );
\Head[13]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head0(13),
      I2 => Head1,
      O => p_0_in1_in(13)
    );
\Head[13]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(5),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(5),
      I3 => \Head_reg[119]_2\(5),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(5)
    );
\Head[14]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head0(14),
      I2 => Head1,
      O => p_0_in1_in(14)
    );
\Head[14]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(6),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(6),
      I3 => \Head_reg[119]_2\(6),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(6)
    );
\Head[15]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head0(15),
      I2 => Head1,
      O => p_0_in1_in(15)
    );
\Head[15]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(7),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(7),
      I3 => \Head_reg[119]_2\(7),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(7)
    );
\Head[16]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head0(16),
      I2 => Head1,
      O => p_0_in1_in(16)
    );
\Head[16]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][did]\(8),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(8),
      O => \Head_reg[119]_0\(8)
    );
\Head[17]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head0(17),
      I2 => Head1,
      O => p_0_in1_in(17)
    );
\Head[18]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head0(18),
      I2 => Head1,
      O => p_0_in1_in(18)
    );
\Head[18]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][byte_len]\(0),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(9),
      O => \Head_reg[119]_0\(9)
    );
\Head[19]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head0(19),
      I2 => Head1,
      O => p_0_in1_in(19)
    );
\Head[19]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][byte_len]\(1),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(10),
      O => \Head_reg[119]_0\(10)
    );
\Head[20]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head0(20),
      I2 => Head1,
      O => p_0_in1_in(20)
    );
\Head[20]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(11),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(2),
      I3 => \Head_reg[119]_2\(8),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(11)
    );
\Head[21]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head0(21),
      I2 => Head1,
      O => p_0_in1_in(21)
    );
\Head[21]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(12),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(3),
      I3 => \Head_reg[119]_2\(9),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(12)
    );
\Head[22]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head0(22),
      I2 => Head1,
      O => p_0_in1_in(22)
    );
\Head[22]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(13),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(4),
      I3 => \Head_reg[119]_2\(10),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(13)
    );
\Head[23]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head0(23),
      I2 => Head1,
      O => p_0_in1_in(23)
    );
\Head[23]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(14),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(5),
      I3 => \Head_reg[119]_2\(11),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(14)
    );
\Head[24]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head0(24),
      I2 => Head1,
      O => p_0_in1_in(24)
    );
\Head[24]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(15),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(6),
      I3 => \Head_reg[119]_2\(12),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(15)
    );
\Head[25]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head0(25),
      I2 => Head1,
      O => p_0_in1_in(25)
    );
\Head[25]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(16),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(7),
      I3 => \Head_reg[119]_2\(13),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(16)
    );
\Head[26]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head0(26),
      I2 => Head1,
      O => p_0_in1_in(26)
    );
\Head[26]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(17),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(8),
      I3 => \Head_reg[119]_2\(14),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(17)
    );
\Head[27]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head0(27),
      I2 => Head1,
      O => p_0_in1_in(27)
    );
\Head[27]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(18),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(9),
      I3 => \Head_reg[119]_2\(15),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(18)
    );
\Head[28]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head0(28),
      I2 => Head1,
      O => p_0_in1_in(28)
    );
\Head[28]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(19),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(10),
      I3 => \Head_reg[119]_2\(16),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(19)
    );
\Head[29]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head0(29),
      I2 => Head1,
      O => p_0_in1_in(29)
    );
\Head[29]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(20),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(11),
      I3 => \Head_reg[119]_2\(17),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(20)
    );
\Head[30]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head0(30),
      I2 => Head1,
      O => p_0_in1_in(30)
    );
\Head[30]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(21),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(12),
      I3 => \Head_reg[119]_2\(18),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(21)
    );
\Head[31]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(31),
      I1 => Head1,
      O => \Head[31]_i_1__2_n_0\
    );
\Head[46]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head0(46),
      I2 => Head1,
      O => p_0_in1_in(46)
    );
\Head[46]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(22),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][rid]\(0),
      I3 => \Head_reg[119]_2\(20),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(22)
    );
\Head[47]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head0(47),
      I2 => Head1,
      O => p_0_in1_in(47)
    );
\Head[47]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(23),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][rid]\(1),
      I3 => \Head_reg[119]_2\(21),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(23)
    );
\Head[48]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head0(48),
      I2 => Head1,
      O => p_0_in1_in(48)
    );
\Head[48]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][rid]\(2),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(24),
      O => \Head_reg[119]_0\(24)
    );
\Head[49]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head0(49),
      I2 => Head1,
      O => p_0_in1_in(49)
    );
\Head[49]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][rid]\(3),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(25),
      O => \Head_reg[119]_0\(25)
    );
\Head[50]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head0(50),
      I2 => Head1,
      O => p_0_in1_in(50)
    );
\Head[50]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][rid]\(4),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(26),
      O => \Head_reg[119]_0\(26)
    );
\Head[51]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(51),
      I1 => Head1,
      O => \Head[51]_i_1__3_n_0\
    );
\Head[51]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][rid]\(5),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(27),
      O => \Head_reg[119]_0\(27)
    );
\Head[56]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head0(56),
      I2 => Head1,
      O => p_0_in1_in(56)
    );
\Head[56]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][adr]\(0),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(28),
      O => \Head_reg[119]_0\(28)
    );
\Head[57]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head0(57),
      I2 => Head1,
      O => p_0_in1_in(57)
    );
\Head[57]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][adr]\(1),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(29),
      O => \Head_reg[119]_0\(29)
    );
\Head[58]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head0(58),
      I2 => Head1,
      O => p_0_in1_in(58)
    );
\Head[58]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][adr]\(2),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(30),
      O => \Head_reg[119]_0\(30)
    );
\Head[59]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head0(59),
      I2 => Head1,
      O => p_0_in1_in(59)
    );
\Head[59]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \h2c_xdma_rrq_req[0][adr]\(3),
      I1 => \^empty_ff_reg_0\,
      I2 => \Head1__2_1\,
      I3 => \Head_reg[119]_1\(31),
      O => \Head_reg[119]_0\(31)
    );
\Head[60]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head0(60),
      I2 => Head1,
      O => p_0_in1_in(60)
    );
\Head[60]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(32),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(4),
      I3 => \Head_reg[119]_2\(22),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(32)
    );
\Head[61]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head0(61),
      I2 => Head1,
      O => p_0_in1_in(61)
    );
\Head[61]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(33),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(5),
      I3 => \Head_reg[119]_2\(23),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(33)
    );
\Head[62]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head0(62),
      I2 => Head1,
      O => p_0_in1_in(62)
    );
\Head[62]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(34),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(6),
      I3 => \Head_reg[119]_2\(24),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(34)
    );
\Head[63]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head0(63),
      I2 => Head1,
      O => p_0_in1_in(63)
    );
\Head[63]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(35),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(7),
      I3 => \Head_reg[119]_2\(25),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(35)
    );
\Head[64]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head0(64),
      I2 => Head1,
      O => p_0_in1_in(64)
    );
\Head[64]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(36),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(8),
      I3 => \Head_reg[119]_2\(26),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(36)
    );
\Head[65]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head0(65),
      I2 => Head1,
      O => p_0_in1_in(65)
    );
\Head[65]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(37),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(9),
      I3 => \Head_reg[119]_2\(27),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(37)
    );
\Head[66]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head0(66),
      I2 => Head1,
      O => p_0_in1_in(66)
    );
\Head[66]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(38),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(10),
      I3 => \Head_reg[119]_2\(28),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(38)
    );
\Head[67]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head0(67),
      I2 => Head1,
      O => p_0_in1_in(67)
    );
\Head[67]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(39),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(11),
      I3 => \Head_reg[119]_2\(29),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(39)
    );
\Head[68]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head0(68),
      I2 => Head1,
      O => p_0_in1_in(68)
    );
\Head[68]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(40),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(12),
      I3 => \Head_reg[119]_2\(30),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(40)
    );
\Head[69]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head0(69),
      I2 => Head1,
      O => p_0_in1_in(69)
    );
\Head[69]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(41),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(13),
      I3 => \Head_reg[119]_2\(31),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(41)
    );
\Head[70]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head0(70),
      I2 => Head1,
      O => p_0_in1_in(70)
    );
\Head[70]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(42),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(14),
      I3 => \Head_reg[119]_2\(32),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(42)
    );
\Head[71]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head0(71),
      I2 => Head1,
      O => p_0_in1_in(71)
    );
\Head[71]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(43),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(15),
      I3 => \Head_reg[119]_2\(33),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(43)
    );
\Head[72]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head0(72),
      I2 => Head1,
      O => p_0_in1_in(72)
    );
\Head[72]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(44),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(16),
      I3 => \Head_reg[119]_2\(34),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(44)
    );
\Head[73]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head0(73),
      I2 => Head1,
      O => p_0_in1_in(73)
    );
\Head[73]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(45),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(17),
      I3 => \Head_reg[119]_2\(35),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(45)
    );
\Head[74]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head0(74),
      I2 => Head1,
      O => p_0_in1_in(74)
    );
\Head[74]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(46),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(18),
      I3 => \Head_reg[119]_2\(36),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(46)
    );
\Head[75]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head0(75),
      I2 => Head1,
      O => p_0_in1_in(75)
    );
\Head[75]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(47),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(19),
      I3 => \Head_reg[119]_2\(37),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(47)
    );
\Head[76]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head0(76),
      I2 => Head1,
      O => p_0_in1_in(76)
    );
\Head[76]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(48),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(20),
      I3 => \Head_reg[119]_2\(38),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(48)
    );
\Head[77]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head0(77),
      I2 => Head1,
      O => p_0_in1_in(77)
    );
\Head[77]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(49),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(21),
      I3 => \Head_reg[119]_2\(39),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(49)
    );
\Head[78]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head0(78),
      I2 => Head1,
      O => p_0_in1_in(78)
    );
\Head[78]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(50),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(22),
      I3 => \Head_reg[119]_2\(40),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(50)
    );
\Head[79]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head0(79),
      I2 => Head1,
      O => p_0_in1_in(79)
    );
\Head[79]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(51),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(23),
      I3 => \Head_reg[119]_2\(41),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(51)
    );
\Head[80]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head0(80),
      I2 => Head1,
      O => p_0_in1_in(80)
    );
\Head[80]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(52),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(24),
      I3 => \Head_reg[119]_2\(42),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(52)
    );
\Head[81]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head0(81),
      I2 => Head1,
      O => p_0_in1_in(81)
    );
\Head[81]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(53),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(25),
      I3 => \Head_reg[119]_2\(43),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(53)
    );
\Head[82]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head0(82),
      I2 => Head1,
      O => p_0_in1_in(82)
    );
\Head[82]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(54),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(26),
      I3 => \Head_reg[119]_2\(44),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(54)
    );
\Head[83]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head0(83),
      I2 => Head1,
      O => p_0_in1_in(83)
    );
\Head[83]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(55),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(27),
      I3 => \Head_reg[119]_2\(45),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(55)
    );
\Head[84]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head0(84),
      I2 => Head1,
      O => p_0_in1_in(84)
    );
\Head[84]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(56),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(28),
      I3 => \Head_reg[119]_2\(46),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(56)
    );
\Head[85]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head0(85),
      I2 => Head1,
      O => p_0_in1_in(85)
    );
\Head[85]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(57),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(29),
      I3 => \Head_reg[119]_2\(47),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(57)
    );
\Head[86]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head0(86),
      I2 => Head1,
      O => p_0_in1_in(86)
    );
\Head[86]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(58),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(30),
      I3 => \Head_reg[119]_2\(48),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(58)
    );
\Head[87]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head0(87),
      I2 => Head1,
      O => p_0_in1_in(87)
    );
\Head[87]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(59),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(31),
      I3 => \Head_reg[119]_2\(49),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(59)
    );
\Head[88]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head0(88),
      I2 => Head1,
      O => p_0_in1_in(88)
    );
\Head[88]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(60),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(32),
      I3 => \Head_reg[119]_2\(50),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(60)
    );
\Head[89]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head0(89),
      I2 => Head1,
      O => p_0_in1_in(89)
    );
\Head[89]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(61),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(33),
      I3 => \Head_reg[119]_2\(51),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(61)
    );
\Head[8]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head0(8),
      I2 => Head1,
      O => p_0_in1_in(8)
    );
\Head[8]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(0),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(0),
      I3 => \Head_reg[119]_2\(0),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(0)
    );
\Head[90]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head0(90),
      I2 => Head1,
      O => p_0_in1_in(90)
    );
\Head[90]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(62),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(34),
      I3 => \Head_reg[119]_2\(52),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(62)
    );
\Head[91]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head0(91),
      I2 => Head1,
      O => p_0_in1_in(91)
    );
\Head[91]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(63),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(35),
      I3 => \Head_reg[119]_2\(53),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(63)
    );
\Head[92]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head0(92),
      I2 => Head1,
      O => p_0_in1_in(92)
    );
\Head[92]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(64),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(36),
      I3 => \Head_reg[119]_2\(54),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(64)
    );
\Head[93]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head0(93),
      I2 => Head1,
      O => p_0_in1_in(93)
    );
\Head[93]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(65),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(37),
      I3 => \Head_reg[119]_2\(55),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(65)
    );
\Head[94]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head0(94),
      I2 => Head1,
      O => p_0_in1_in(94)
    );
\Head[94]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(66),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(38),
      I3 => \Head_reg[119]_2\(56),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(66)
    );
\Head[95]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head0(95),
      I2 => Head1,
      O => p_0_in1_in(95)
    );
\Head[95]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(67),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(39),
      I3 => \Head_reg[119]_2\(57),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(67)
    );
\Head[96]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head0(96),
      I2 => Head1,
      O => p_0_in1_in(96)
    );
\Head[96]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(68),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(40),
      I3 => \Head_reg[119]_2\(58),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(68)
    );
\Head[97]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head0(97),
      I2 => Head1,
      O => p_0_in1_in(97)
    );
\Head[97]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(69),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(41),
      I3 => \Head_reg[119]_2\(59),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(69)
    );
\Head[98]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head0(98),
      I2 => Head1,
      O => p_0_in1_in(98)
    );
\Head[98]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(70),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(42),
      I3 => \Head_reg[119]_2\(60),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(70)
    );
\Head[99]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head0(99),
      I2 => Head1,
      O => p_0_in1_in(99)
    );
\Head[99]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(71),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][adr]\(43),
      I3 => \Head_reg[119]_2\(61),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(71)
    );
\Head[9]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head0(9),
      I2 => Head1,
      O => p_0_in1_in(9)
    );
\Head[9]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => \Head_reg[119]_1\(1),
      I1 => \^empty_ff_reg_0\,
      I2 => \h2c_xdma_rrq_req[0][did]\(1),
      I3 => \Head_reg[119]_2\(1),
      I4 => \Head1__2_1\,
      I5 => \^empty_ff_reg_3\(94),
      O => \Head_reg[119]_0\(1)
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(100),
      Q => \h2c_xdma_rrq_req[0][adr]\(44),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(101),
      Q => \h2c_xdma_rrq_req[0][adr]\(45),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(102),
      Q => \h2c_xdma_rrq_req[0][adr]\(46),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(103),
      Q => \h2c_xdma_rrq_req[0][adr]\(47),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(104),
      Q => \h2c_xdma_rrq_req[0][adr]\(48),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(105),
      Q => \h2c_xdma_rrq_req[0][adr]\(49),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(106),
      Q => \h2c_xdma_rrq_req[0][adr]\(50),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(107),
      Q => \h2c_xdma_rrq_req[0][adr]\(51),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(108),
      Q => \h2c_xdma_rrq_req[0][adr]\(52),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(109),
      Q => \h2c_xdma_rrq_req[0][adr]\(53),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(10),
      Q => \h2c_xdma_rrq_req[0][did]\(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(110),
      Q => \h2c_xdma_rrq_req[0][adr]\(54),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(111),
      Q => \h2c_xdma_rrq_req[0][adr]\(55),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(112),
      Q => \h2c_xdma_rrq_req[0][adr]\(56),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(113),
      Q => \h2c_xdma_rrq_req[0][adr]\(57),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(114),
      Q => \h2c_xdma_rrq_req[0][adr]\(58),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(115),
      Q => \h2c_xdma_rrq_req[0][adr]\(59),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(116),
      Q => \h2c_xdma_rrq_req[0][adr]\(60),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(117),
      Q => \h2c_xdma_rrq_req[0][adr]\(61),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(118),
      Q => \h2c_xdma_rrq_req[0][adr]\(62),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(119),
      Q => \h2c_xdma_rrq_req[0][adr]\(63),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(11),
      Q => \h2c_xdma_rrq_req[0][did]\(3),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(12),
      Q => \h2c_xdma_rrq_req[0][did]\(4),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(13),
      Q => \h2c_xdma_rrq_req[0][did]\(5),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(14),
      Q => \h2c_xdma_rrq_req[0][did]\(6),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(15),
      Q => \h2c_xdma_rrq_req[0][did]\(7),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(16),
      Q => \h2c_xdma_rrq_req[0][did]\(8),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(17),
      Q => \h2c_xdma_rrq_req[0][did]\(9),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(18),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(19),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(20),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(21),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(3),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(22),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(4),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(23),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(5),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(24),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(6),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(25),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(7),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(26),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(8),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(27),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(9),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(28),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(10),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(29),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(11),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(30),
      Q => \h2c_xdma_rrq_req[0][byte_len]\(12),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => \Head[31]_i_1__2_n_0\,
      Q => \h2c_xdma_rrq_req[0][byte_len]\(13),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(46),
      Q => \h2c_xdma_rrq_req[0][rid]\(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(47),
      Q => \h2c_xdma_rrq_req[0][rid]\(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(48),
      Q => \h2c_xdma_rrq_req[0][rid]\(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(49),
      Q => \h2c_xdma_rrq_req[0][rid]\(3),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(50),
      Q => \h2c_xdma_rrq_req[0][rid]\(4),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => \Head[51]_i_1__3_n_0\,
      Q => \h2c_xdma_rrq_req[0][rid]\(5),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(56),
      Q => \h2c_xdma_rrq_req[0][adr]\(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(57),
      Q => \h2c_xdma_rrq_req[0][adr]\(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(58),
      Q => \h2c_xdma_rrq_req[0][adr]\(2),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(59),
      Q => \h2c_xdma_rrq_req[0][adr]\(3),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(60),
      Q => \h2c_xdma_rrq_req[0][adr]\(4),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(61),
      Q => \h2c_xdma_rrq_req[0][adr]\(5),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(62),
      Q => \h2c_xdma_rrq_req[0][adr]\(6),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(63),
      Q => \h2c_xdma_rrq_req[0][adr]\(7),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(64),
      Q => \h2c_xdma_rrq_req[0][adr]\(8),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(65),
      Q => \h2c_xdma_rrq_req[0][adr]\(9),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(66),
      Q => \h2c_xdma_rrq_req[0][adr]\(10),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(67),
      Q => \h2c_xdma_rrq_req[0][adr]\(11),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(68),
      Q => \h2c_xdma_rrq_req[0][adr]\(12),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(69),
      Q => \h2c_xdma_rrq_req[0][adr]\(13),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(70),
      Q => \h2c_xdma_rrq_req[0][adr]\(14),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(71),
      Q => \h2c_xdma_rrq_req[0][adr]\(15),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(72),
      Q => \h2c_xdma_rrq_req[0][adr]\(16),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(73),
      Q => \h2c_xdma_rrq_req[0][adr]\(17),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(74),
      Q => \h2c_xdma_rrq_req[0][adr]\(18),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(75),
      Q => \h2c_xdma_rrq_req[0][adr]\(19),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(76),
      Q => \h2c_xdma_rrq_req[0][adr]\(20),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(77),
      Q => \h2c_xdma_rrq_req[0][adr]\(21),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(78),
      Q => \h2c_xdma_rrq_req[0][adr]\(22),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(79),
      Q => \h2c_xdma_rrq_req[0][adr]\(23),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(80),
      Q => \h2c_xdma_rrq_req[0][adr]\(24),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(81),
      Q => \h2c_xdma_rrq_req[0][adr]\(25),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(82),
      Q => \h2c_xdma_rrq_req[0][adr]\(26),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(83),
      Q => \h2c_xdma_rrq_req[0][adr]\(27),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(84),
      Q => \h2c_xdma_rrq_req[0][adr]\(28),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(85),
      Q => \h2c_xdma_rrq_req[0][adr]\(29),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(86),
      Q => \h2c_xdma_rrq_req[0][adr]\(30),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(87),
      Q => \h2c_xdma_rrq_req[0][adr]\(31),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(88),
      Q => \h2c_xdma_rrq_req[0][adr]\(32),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(89),
      Q => \h2c_xdma_rrq_req[0][adr]\(33),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(8),
      Q => \h2c_xdma_rrq_req[0][did]\(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(90),
      Q => \h2c_xdma_rrq_req[0][adr]\(34),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(91),
      Q => \h2c_xdma_rrq_req[0][adr]\(35),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(92),
      Q => \h2c_xdma_rrq_req[0][adr]\(36),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(93),
      Q => \h2c_xdma_rrq_req[0][adr]\(37),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(94),
      Q => \h2c_xdma_rrq_req[0][adr]\(38),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(95),
      Q => \h2c_xdma_rrq_req[0][adr]\(39),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(96),
      Q => \h2c_xdma_rrq_req[0][adr]\(40),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(97),
      Q => \h2c_xdma_rrq_req[0][adr]\(41),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(98),
      Q => \h2c_xdma_rrq_req[0][adr]\(42),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(99),
      Q => \h2c_xdma_rrq_req[0][adr]\(43),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[119]_i_1__3_n_0\,
      D => p_0_in1_in(9),
      Q => \h2c_xdma_rrq_req[0][did]\(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(75 downto 74),
      DIB(1 downto 0) => DataIn(77 downto 76),
      DIC(1 downto 0) => DataIn(79 downto 78),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_102_107_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(65),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(47),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(77)
    );
MemArray_reg_0_3_102_107_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(64),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(46),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(76)
    );
MemArray_reg_0_3_102_107_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(67),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(49),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(79)
    );
MemArray_reg_0_3_102_107_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(66),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(48),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(78)
    );
MemArray_reg_0_3_102_107_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(69),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(51),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(81)
    );
MemArray_reg_0_3_102_107_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(68),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(50),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(80)
    );
MemArray_reg_0_3_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(81 downto 80),
      DIB(1 downto 0) => DataIn(83 downto 82),
      DIC(1 downto 0) => DataIn(85 downto 84),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => Head0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_108_113_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(71),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(53),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(83)
    );
MemArray_reg_0_3_108_113_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(70),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(52),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(82)
    );
MemArray_reg_0_3_108_113_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(73),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(55),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(85)
    );
MemArray_reg_0_3_108_113_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(72),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(54),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(84)
    );
MemArray_reg_0_3_108_113_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(75),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(57),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(87)
    );
MemArray_reg_0_3_108_113_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(74),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(56),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(86)
    );
MemArray_reg_0_3_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(87 downto 86),
      DIB(1 downto 0) => DataIn(89 downto 88),
      DIC(1 downto 0) => DataIn(91 downto 90),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(115 downto 114),
      DOB(1 downto 0) => Head0(117 downto 116),
      DOC(1 downto 0) => Head0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_114_119_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(77),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(59),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(89)
    );
MemArray_reg_0_3_114_119_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(76),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(58),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(88)
    );
MemArray_reg_0_3_114_119_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(79),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(61),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(91)
    );
MemArray_reg_0_3_114_119_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(78),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(60),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(90)
    );
MemArray_reg_0_3_114_119_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(81),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(63),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(93)
    );
MemArray_reg_0_3_114_119_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(80),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(62),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(92)
    );
MemArray_reg_0_3_120_121_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0203"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => almost_full_ff_0,
      I3 => \Head_reg[8]_1\,
      O => \^empty_ff_reg_3\(94)
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(5 downto 4),
      DIB(1 downto 0) => DataIn(7 downto 6),
      DIC(1 downto 0) => DataIn(9 downto 8),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => Head0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_12_17_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(5),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(5),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(5)
    );
\MemArray_reg_0_3_12_17_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(4),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(4),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(4)
    );
\MemArray_reg_0_3_12_17_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(7),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(7),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(7)
    );
\MemArray_reg_0_3_12_17_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(6),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(6),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(6)
    );
\MemArray_reg_0_3_12_17_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][did]\(9),
      O => \^empty_ff_reg_3\(9)
    );
\MemArray_reg_0_3_12_17_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][did]\(8),
      O => \^empty_ff_reg_3\(8)
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(11 downto 10),
      DIB(1 downto 0) => DataIn(13 downto 12),
      DIC(1 downto 0) => DataIn(15 downto 14),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_18_23_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][byte_len]\(1),
      O => \^empty_ff_reg_3\(11)
    );
\MemArray_reg_0_3_18_23_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][byte_len]\(0),
      O => \^empty_ff_reg_3\(10)
    );
MemArray_reg_0_3_18_23_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(9),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(3),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(13)
    );
MemArray_reg_0_3_18_23_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(8),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(2),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(12)
    );
MemArray_reg_0_3_18_23_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(11),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(5),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(15)
    );
MemArray_reg_0_3_18_23_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(10),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(4),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(14)
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(17 downto 16),
      DIB(1 downto 0) => DataIn(19 downto 18),
      DIC(1 downto 0) => DataIn(21 downto 20),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(25 downto 24),
      DOB(1 downto 0) => Head0(27 downto 26),
      DOC(1 downto 0) => Head0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_24_29_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(13),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(7),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(17)
    );
MemArray_reg_0_3_24_29_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(12),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(6),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(16)
    );
MemArray_reg_0_3_24_29_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(15),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(9),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(19)
    );
MemArray_reg_0_3_24_29_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(14),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(8),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(18)
    );
MemArray_reg_0_3_24_29_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(17),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(11),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(21)
    );
MemArray_reg_0_3_24_29_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(16),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(10),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(20)
    );
MemArray_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1) => '0',
      DIA(0) => DataIn(22),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(31 downto 30),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_30_35_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(19),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(13),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(23)
    );
MemArray_reg_0_3_30_35_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(18),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][byte_len]\(12),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(22)
    );
MemArray_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => DataIn(24 downto 23),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => Head0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_42_47_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(21),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][rid]\(1),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(25)
    );
MemArray_reg_0_3_42_47_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(20),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][rid]\(0),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(24)
    );
MemArray_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(26 downto 25),
      DIB(1) => '0',
      DIB(0) => DataIn(27),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(49 downto 48),
      DOB(1 downto 0) => Head0(51 downto 50),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_48_53_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_48_53_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][rid]\(3),
      O => \^empty_ff_reg_3\(27)
    );
\MemArray_reg_0_3_48_53_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][rid]\(2),
      O => \^empty_ff_reg_3\(26)
    );
\MemArray_reg_0_3_48_53_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][rid]\(5),
      O => \^empty_ff_reg_3\(29)
    );
\MemArray_reg_0_3_48_53_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][rid]\(4),
      O => \^empty_ff_reg_3\(28)
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => DataIn(29 downto 28),
      DIC(1 downto 0) => DataIn(31 downto 30),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(57 downto 56),
      DOC(1 downto 0) => Head0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_54_59_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][adr]\(1),
      O => \^empty_ff_reg_3\(31)
    );
\MemArray_reg_0_3_54_59_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][adr]\(0),
      O => \^empty_ff_reg_3\(30)
    );
\MemArray_reg_0_3_54_59_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][adr]\(3),
      O => \^empty_ff_reg_3\(33)
    );
\MemArray_reg_0_3_54_59_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00450000"
    )
        port map (
      I0 => \^empty_ff_reg_2\,
      I1 => \Head_reg[8]_0\,
      I2 => arbhist_ff(0),
      I3 => almost_full_ff_0,
      I4 => \h2c_xdma_rrq_req[0][adr]\(2),
      O => \^empty_ff_reg_3\(32)
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(33 downto 32),
      DIB(1 downto 0) => DataIn(35 downto 34),
      DIC(1 downto 0) => DataIn(37 downto 36),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_60_65_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(23),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(5),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(35)
    );
MemArray_reg_0_3_60_65_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(22),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(4),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(34)
    );
MemArray_reg_0_3_60_65_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(25),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(7),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(37)
    );
MemArray_reg_0_3_60_65_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(24),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(6),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(36)
    );
MemArray_reg_0_3_60_65_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(27),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(9),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(39)
    );
MemArray_reg_0_3_60_65_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(26),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(8),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(38)
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(39 downto 38),
      DIB(1 downto 0) => DataIn(41 downto 40),
      DIC(1 downto 0) => DataIn(43 downto 42),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_66_71_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(29),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(11),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(41)
    );
MemArray_reg_0_3_66_71_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(28),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(10),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(40)
    );
MemArray_reg_0_3_66_71_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(31),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(13),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(43)
    );
MemArray_reg_0_3_66_71_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(30),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(12),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(42)
    );
MemArray_reg_0_3_66_71_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(33),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(15),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(45)
    );
MemArray_reg_0_3_66_71_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(32),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(14),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(44)
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => DataIn(1 downto 0),
      DIC(1 downto 0) => DataIn(3 downto 2),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
\MemArray_reg_0_3_6_11_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(1),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(1),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(1)
    );
\MemArray_reg_0_3_6_11_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(0),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(0),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(0)
    );
\MemArray_reg_0_3_6_11_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(3),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(3),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(3)
    );
\MemArray_reg_0_3_6_11_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(2),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][did]\(2),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(2)
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(45 downto 44),
      DIB(1 downto 0) => DataIn(47 downto 46),
      DIC(1 downto 0) => DataIn(49 downto 48),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_72_77_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(35),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(17),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(47)
    );
MemArray_reg_0_3_72_77_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(34),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(16),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(46)
    );
MemArray_reg_0_3_72_77_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(37),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(19),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(49)
    );
MemArray_reg_0_3_72_77_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(36),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(18),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(48)
    );
MemArray_reg_0_3_72_77_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(39),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(21),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(51)
    );
MemArray_reg_0_3_72_77_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(38),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(20),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(50)
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(51 downto 50),
      DIB(1 downto 0) => DataIn(53 downto 52),
      DIC(1 downto 0) => DataIn(55 downto 54),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_78_83_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(41),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(23),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(53)
    );
MemArray_reg_0_3_78_83_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(40),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(22),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(52)
    );
MemArray_reg_0_3_78_83_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(43),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(25),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(55)
    );
MemArray_reg_0_3_78_83_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(42),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(24),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(54)
    );
MemArray_reg_0_3_78_83_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(45),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(27),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(57)
    );
MemArray_reg_0_3_78_83_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(44),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(26),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(56)
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(57 downto 56),
      DIB(1 downto 0) => DataIn(59 downto 58),
      DIC(1 downto 0) => DataIn(61 downto 60),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_84_89_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(47),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(29),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(59)
    );
MemArray_reg_0_3_84_89_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(46),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(28),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(58)
    );
MemArray_reg_0_3_84_89_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(49),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(31),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(61)
    );
MemArray_reg_0_3_84_89_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(48),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(30),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(60)
    );
MemArray_reg_0_3_84_89_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(51),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(33),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(63)
    );
MemArray_reg_0_3_84_89_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(50),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(32),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(62)
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(63 downto 62),
      DIB(1 downto 0) => DataIn(65 downto 64),
      DIC(1 downto 0) => DataIn(67 downto 66),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_90_95_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(53),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(35),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(65)
    );
MemArray_reg_0_3_90_95_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(52),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(34),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(64)
    );
MemArray_reg_0_3_90_95_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(55),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(37),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(67)
    );
MemArray_reg_0_3_90_95_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(54),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(36),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(66)
    );
MemArray_reg_0_3_90_95_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(57),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(39),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(69)
    );
MemArray_reg_0_3_90_95_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(56),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(38),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(68)
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(69 downto 68),
      DIB(1 downto 0) => DataIn(71 downto 70),
      DIC(1 downto 0) => DataIn(73 downto 72),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => rrq_vld_903
    );
MemArray_reg_0_3_96_101_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(59),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(41),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(71)
    );
MemArray_reg_0_3_96_101_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(58),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(40),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(70)
    );
MemArray_reg_0_3_96_101_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(61),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(43),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(73)
    );
MemArray_reg_0_3_96_101_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(60),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(42),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(72)
    );
MemArray_reg_0_3_96_101_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(63),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(45),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(75)
    );
MemArray_reg_0_3_96_101_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => \Head_reg[119]_2\(62),
      I1 => \^empty_ff_reg_3\(94),
      I2 => \h2c_xdma_rrq_req[0][adr]\(44),
      I3 => \^empty_ff_reg_0\,
      O => \^empty_ff_reg_3\(74)
    );
\RdPtr[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5555666A"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(2),
      I3 => FifoCntrRd(1),
      I4 => Head1,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55577777AAA88888"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \^empty_ff_reg_0\,
      I5 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[1]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03010000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => \^empty_ff_reg_0\,
      I4 => rrq_vld_903,
      O => Head1
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\WrPtr[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => rrq_vld_903,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => rrq_vld_903,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\dat_fifo_hd_nn1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03000202"
    )
        port map (
      I0 => dat_fifo_hd_nn1(0),
      I1 => \dat_fifo_hd_out_nn1_reg[0]\,
      I2 => ctl_run_re,
      I3 => Q(0),
      I4 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nn1_reg[9]\(0)
    );
\dat_fifo_hd_nn1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020300"
    )
        port map (
      I0 => Q(1),
      I1 => \dat_fifo_hd_out_nn1_reg[0]\,
      I2 => ctl_run_re,
      I3 => dat_fifo_hd_nn1(1),
      I4 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nn1_reg[9]\(1)
    );
\dat_fifo_hd_nn1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03000202"
    )
        port map (
      I0 => dat_fifo_hd_nn1(2),
      I1 => \dat_fifo_hd_out_nn1_reg[0]\,
      I2 => ctl_run_re,
      I3 => Q(2),
      I4 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nn1_reg[9]\(2)
    );
\dat_fifo_hd_nn1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02020300"
    )
        port map (
      I0 => Q(3),
      I1 => \dat_fifo_hd_out_nn1_reg[0]\,
      I2 => ctl_run_re,
      I3 => dat_fifo_hd_nn1(3),
      I4 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nn1_reg[9]\(3)
    );
\dat_fifo_hd_nn1[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => Q(4),
      I1 => ctl_run_re,
      I2 => dat_fifo_hd_nn1(4),
      I3 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nxt_nn1_reg[4]\
    );
\dat_fifo_hd_nn1[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => Q(5),
      I1 => ctl_run_re,
      I2 => dat_fifo_hd_nn1(5),
      I3 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nxt_nn1_reg[5]\
    );
\dat_fifo_hd_nn1[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => Q(6),
      I1 => ctl_run_re,
      I2 => dat_fifo_hd_nn1(6),
      I3 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nxt_nn1_reg[6]\
    );
\dat_fifo_hd_nn1[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => Q(7),
      I1 => ctl_run_re,
      I2 => dat_fifo_hd_nn1(7),
      I3 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nxt_nn1_reg[7]\
    );
\dat_fifo_hd_nn1[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEFC"
    )
        port map (
      I0 => Q(8),
      I1 => ctl_run_re,
      I2 => dat_fifo_hd_nn1(8),
      I3 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nxt_nn1_reg[8]\
    );
\dat_fifo_hd_nn1[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03000202"
    )
        port map (
      I0 => dat_fifo_hd_nn1(9),
      I1 => \dat_fifo_hd_out_nn1_reg[0]\,
      I2 => ctl_run_re,
      I3 => Q(9),
      I4 => \^rrq_ld_9008_out\,
      O => \dat_fifo_hd_nn1_reg[9]\(4)
    );
\empty_ff_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_2\,
      I4 => \empty_ff_i_2__3_n_0\,
      O => \empty_ff_i_1__5_n_0\
    );
\empty_ff_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAAAAAAEF"
    )
        port map (
      I0 => \dat_fifo_hd_out_nn1_reg[0]\,
      I1 => \^empty_ff_reg_0\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(1),
      I4 => FifoCntrRd(2),
      I5 => cfg_linkdown_nn1,
      O => \empty_ff_i_2__3_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__5_n_0\,
      Q => \^empty_ff_reg_2\,
      R => '0'
    );
\full_ff_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => rrq_vld_903,
      I3 => FifoCntrWr(2),
      I4 => full_ff_reg_n_0,
      O => \full_ff_i_1__3_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__3_n_0\,
      Q => full_ff_reg_n_0,
      R => \^pcie_h2c_rst_3ff_reg[0]_rep__4\
    );
\rrq_ld_901_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[3]\(2),
      I1 => \rrq_sm_cur_900_reg[3]\(3),
      I2 => full_ff_reg_n_0,
      I3 => rrq_vld_903,
      I4 => \rrq_ld_901_reg_rep__5\,
      O => \^rrq_ld_9008_out\
    );
\rrq_sm_cur_900[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000101000"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[3]\(0),
      I1 => \rrq_sm_cur_900_reg[3]\(4),
      I2 => \rrq_sm_cur_900_reg[3]_0\,
      I3 => \rrq_sm_cur_900_reg[3]\(5),
      I4 => \rrq_sm_cur_900_reg[3]\(3),
      I5 => \rrq_sm_cur_900[3]_i_3_n_0\,
      O => \^d\(0)
    );
\rrq_sm_cur_900[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF04"
    )
        port map (
      I0 => full_ff_reg_n_0,
      I1 => rrq_vld_903,
      I2 => \rrq_sm_cur_900_reg[3]\(5),
      I3 => \rrq_sm_cur_900_reg[3]\(1),
      I4 => \rrq_sm_cur_900_reg[3]\(2),
      I5 => \rrq_sm_cur_900_reg[3]\(6),
      O => \rrq_sm_cur_900[3]_i_3_n_0\
    );
\rrq_sm_cur_900[4]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => rrq_vld_903,
      I1 => full_ff_reg_n_0,
      I2 => \rrq_sm_cur_900_reg[3]\(3),
      I3 => \rrq_sm_cur_900_reg[3]\(2),
      O => rrq_vld_903_reg
    );
\rrq_vld_903_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^d\(0),
      I1 => \rrq_vld_903_i_2__0_n_0\,
      I2 => rrq_vld_903_reg_0(0),
      O => rrq_vld_902
    );
\rrq_vld_903_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => rrq_fl_nn1,
      I1 => full_ff_reg_n_0,
      I2 => rrq_stall_902,
      I3 => rrq_dsc_rem0_902,
      I4 => rrq_dsc_vld_902,
      O => \rrq_vld_903_i_2__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2\ is
  port (
    almost_full_ff_reg_0 : out STD_LOGIC;
    ctl_non_inc_nn1_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 157 downto 0 );
    rrq_eod_903_reg : out STD_LOGIC;
    rrq_eod_903_reg_0 : out STD_LOGIC;
    rrq_eod_903_reg_1 : out STD_LOGIC;
    rrq_eod_903_reg_2 : out STD_LOGIC;
    rrq_eod_903_reg_3 : out STD_LOGIC;
    rrq_eod_903_reg_4 : out STD_LOGIC;
    \cfg_mrs_nn1_reg[11]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \FifoCntrWr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrRd_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \WrPtr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    ctl_rst : in STD_LOGIC;
    reg_sts_hlt_nn1 : in STD_LOGIC;
    \rrq_dsc_ld_901_reg_rep__3\ : in STD_LOGIC;
    evt_idl_stp_vld_nn1 : in STD_LOGIC;
    \rrq_sm_cur_900_reg[2]\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[2]_0\ : in STD_LOGIC;
    rrq_eod_903 : in STD_LOGIC;
    \rrq_sm_cur_900_reg[2]_1\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rrq_sm_cur_900_reg[1]\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[6]_0\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[1]_0\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[4]\ : in STD_LOGIC;
    rrq_dsc_ld_901_reg : in STD_LOGIC;
    cfg_mrs_nn1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dsc_mrs_dst_nn1_reg[11]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dsc_ch_evld : in STD_LOGIC_VECTOR ( 0 to 0 );
    DataIn : in STD_LOGIC_VECTOR ( 158 downto 0 );
    empty_ff_reg_0 : in STD_LOGIC;
    dsc_ch_vld : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    dsc_acc_mgc_nn1 : in STD_LOGIC;
    dsc_acc_done_nn1 : in STD_LOGIC;
    \WrPtr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrRd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2\ is
  signal \FifoCntrRd[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[3]_i_2_n_0\ : STD_LOGIC;
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \^fifocntrrd_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FifoCntrWr[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[3]_i_2_n_0\ : STD_LOGIC;
  signal FifoCntrWr_reg : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \^fifocntrwr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal Head0 : STD_LOGIC_VECTOR ( 158 downto 0 );
  signal Head1 : STD_LOGIC;
  signal \Head[158]_i_1_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_7_0_5_n_3 : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 157 downto 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \RdPtr[2]_i_1_n_0\ : STD_LOGIC;
  signal \RdPtr[2]_i_4_n_0\ : STD_LOGIC;
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^wrptr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal almost_full_ff_i_1_n_0 : STD_LOGIC;
  signal dsc_aln_nn1_i_2_n_0 : STD_LOGIC;
  signal dsc_ep_nn0 : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_2_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_3_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_4_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_5_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_2_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_3_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_4_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_5_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_2_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_3_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_4_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_5_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1_n_3\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \empty_ff_i_1__0_n_0\ : STD_LOGIC;
  signal empty_ff_i_2_n_0 : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 158 downto 0 );
  signal rrq_dsc_ld_901_i_3_n_0 : STD_LOGIC;
  signal \rrq_sm_cur_900[2]_i_3_n_0\ : STD_LOGIC;
  signal \rrq_sm_cur_900[6]_i_2_n_0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_dsc_mrs_dst_nn1_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_dsc_mrs_dst_nn1_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[3]_i_2\ : label is "soft_lutpair887";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__0\ : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_2\ : label is "soft_lutpair886";
  attribute SOFT_HLUTNM of \Head[0]_i_1\ : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \Head[100]_i_1__0\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \Head[101]_i_1__0\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \Head[102]_i_1__0\ : label is "soft_lutpair938";
  attribute SOFT_HLUTNM of \Head[103]_i_1__0\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \Head[104]_i_1__0\ : label is "soft_lutpair939";
  attribute SOFT_HLUTNM of \Head[105]_i_1__0\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \Head[106]_i_1__0\ : label is "soft_lutpair940";
  attribute SOFT_HLUTNM of \Head[107]_i_1__0\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \Head[108]_i_1__0\ : label is "soft_lutpair941";
  attribute SOFT_HLUTNM of \Head[109]_i_1__0\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \Head[10]_i_1__0\ : label is "soft_lutpair892";
  attribute SOFT_HLUTNM of \Head[110]_i_1__0\ : label is "soft_lutpair942";
  attribute SOFT_HLUTNM of \Head[111]_i_1__0\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \Head[112]_i_1__0\ : label is "soft_lutpair943";
  attribute SOFT_HLUTNM of \Head[113]_i_1__0\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \Head[114]_i_1__0\ : label is "soft_lutpair944";
  attribute SOFT_HLUTNM of \Head[115]_i_1__0\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \Head[116]_i_1__0\ : label is "soft_lutpair945";
  attribute SOFT_HLUTNM of \Head[117]_i_1__0\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \Head[118]_i_1__0\ : label is "soft_lutpair946";
  attribute SOFT_HLUTNM of \Head[119]_i_1__0\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \Head[11]_i_1__0\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \Head[120]_i_1\ : label is "soft_lutpair947";
  attribute SOFT_HLUTNM of \Head[121]_i_1\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \Head[122]_i_1\ : label is "soft_lutpair948";
  attribute SOFT_HLUTNM of \Head[123]_i_1\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \Head[124]_i_1\ : label is "soft_lutpair949";
  attribute SOFT_HLUTNM of \Head[125]_i_1\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \Head[126]_i_1\ : label is "soft_lutpair950";
  attribute SOFT_HLUTNM of \Head[127]_i_1\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \Head[128]_i_1\ : label is "soft_lutpair951";
  attribute SOFT_HLUTNM of \Head[129]_i_1\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \Head[12]_i_1__0\ : label is "soft_lutpair893";
  attribute SOFT_HLUTNM of \Head[130]_i_1\ : label is "soft_lutpair952";
  attribute SOFT_HLUTNM of \Head[131]_i_1\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \Head[132]_i_1\ : label is "soft_lutpair953";
  attribute SOFT_HLUTNM of \Head[133]_i_1\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \Head[134]_i_1\ : label is "soft_lutpair954";
  attribute SOFT_HLUTNM of \Head[135]_i_1\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \Head[136]_i_1\ : label is "soft_lutpair955";
  attribute SOFT_HLUTNM of \Head[137]_i_1\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \Head[138]_i_1\ : label is "soft_lutpair956";
  attribute SOFT_HLUTNM of \Head[139]_i_1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \Head[13]_i_1__0\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \Head[140]_i_1\ : label is "soft_lutpair957";
  attribute SOFT_HLUTNM of \Head[141]_i_1\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \Head[142]_i_1\ : label is "soft_lutpair958";
  attribute SOFT_HLUTNM of \Head[143]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \Head[144]_i_1\ : label is "soft_lutpair959";
  attribute SOFT_HLUTNM of \Head[145]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \Head[146]_i_1\ : label is "soft_lutpair960";
  attribute SOFT_HLUTNM of \Head[147]_i_1\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \Head[148]_i_1\ : label is "soft_lutpair961";
  attribute SOFT_HLUTNM of \Head[149]_i_1\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \Head[14]_i_1__0\ : label is "soft_lutpair894";
  attribute SOFT_HLUTNM of \Head[150]_i_1\ : label is "soft_lutpair962";
  attribute SOFT_HLUTNM of \Head[151]_i_1\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \Head[152]_i_1\ : label is "soft_lutpair963";
  attribute SOFT_HLUTNM of \Head[153]_i_1\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \Head[154]_i_1\ : label is "soft_lutpair964";
  attribute SOFT_HLUTNM of \Head[155]_i_1\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \Head[156]_i_1\ : label is "soft_lutpair965";
  attribute SOFT_HLUTNM of \Head[157]_i_1\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \Head[158]_i_2\ : label is "soft_lutpair966";
  attribute SOFT_HLUTNM of \Head[15]_i_1__0\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \Head[16]_i_1\ : label is "soft_lutpair895";
  attribute SOFT_HLUTNM of \Head[17]_i_1\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \Head[18]_i_1\ : label is "soft_lutpair896";
  attribute SOFT_HLUTNM of \Head[19]_i_1\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \Head[1]_i_1\ : label is "soft_lutpair888";
  attribute SOFT_HLUTNM of \Head[20]_i_1__0\ : label is "soft_lutpair897";
  attribute SOFT_HLUTNM of \Head[21]_i_1__0\ : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of \Head[22]_i_1__0\ : label is "soft_lutpair898";
  attribute SOFT_HLUTNM of \Head[23]_i_1__0\ : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of \Head[24]_i_1__0\ : label is "soft_lutpair899";
  attribute SOFT_HLUTNM of \Head[25]_i_1__0\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \Head[26]_i_1__0\ : label is "soft_lutpair900";
  attribute SOFT_HLUTNM of \Head[27]_i_1__0\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \Head[28]_i_1__0\ : label is "soft_lutpair901";
  attribute SOFT_HLUTNM of \Head[29]_i_1__0\ : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of \Head[30]_i_1__0\ : label is "soft_lutpair902";
  attribute SOFT_HLUTNM of \Head[31]_i_1__0\ : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of \Head[32]_i_1__0\ : label is "soft_lutpair903";
  attribute SOFT_HLUTNM of \Head[33]_i_1\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \Head[34]_i_1\ : label is "soft_lutpair904";
  attribute SOFT_HLUTNM of \Head[35]_i_1\ : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of \Head[36]_i_1\ : label is "soft_lutpair905";
  attribute SOFT_HLUTNM of \Head[37]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \Head[38]_i_1\ : label is "soft_lutpair906";
  attribute SOFT_HLUTNM of \Head[39]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \Head[3]_i_1\ : label is "soft_lutpair889";
  attribute SOFT_HLUTNM of \Head[40]_i_1\ : label is "soft_lutpair907";
  attribute SOFT_HLUTNM of \Head[41]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \Head[42]_i_1\ : label is "soft_lutpair908";
  attribute SOFT_HLUTNM of \Head[43]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \Head[44]_i_1\ : label is "soft_lutpair909";
  attribute SOFT_HLUTNM of \Head[45]_i_1\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \Head[46]_i_1__0\ : label is "soft_lutpair910";
  attribute SOFT_HLUTNM of \Head[47]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \Head[48]_i_1\ : label is "soft_lutpair911";
  attribute SOFT_HLUTNM of \Head[49]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \Head[4]_i_1\ : label is "soft_lutpair889";
  attribute SOFT_HLUTNM of \Head[50]_i_1\ : label is "soft_lutpair912";
  attribute SOFT_HLUTNM of \Head[51]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \Head[52]_i_1\ : label is "soft_lutpair913";
  attribute SOFT_HLUTNM of \Head[53]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \Head[54]_i_1\ : label is "soft_lutpair914";
  attribute SOFT_HLUTNM of \Head[55]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \Head[56]_i_1\ : label is "soft_lutpair915";
  attribute SOFT_HLUTNM of \Head[57]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \Head[58]_i_1\ : label is "soft_lutpair916";
  attribute SOFT_HLUTNM of \Head[59]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \Head[5]_i_1\ : label is "soft_lutpair890";
  attribute SOFT_HLUTNM of \Head[60]_i_1\ : label is "soft_lutpair917";
  attribute SOFT_HLUTNM of \Head[61]_i_1__0\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \Head[62]_i_1__0\ : label is "soft_lutpair918";
  attribute SOFT_HLUTNM of \Head[63]_i_1__0\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \Head[64]_i_1__0\ : label is "soft_lutpair919";
  attribute SOFT_HLUTNM of \Head[65]_i_1__0\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \Head[66]_i_1__0\ : label is "soft_lutpair920";
  attribute SOFT_HLUTNM of \Head[67]_i_1__0\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \Head[68]_i_1__0\ : label is "soft_lutpair921";
  attribute SOFT_HLUTNM of \Head[69]_i_1__0\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \Head[6]_i_1\ : label is "soft_lutpair890";
  attribute SOFT_HLUTNM of \Head[70]_i_1__0\ : label is "soft_lutpair922";
  attribute SOFT_HLUTNM of \Head[71]_i_1__0\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \Head[72]_i_1__0\ : label is "soft_lutpair923";
  attribute SOFT_HLUTNM of \Head[73]_i_1__0\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \Head[74]_i_1__0\ : label is "soft_lutpair924";
  attribute SOFT_HLUTNM of \Head[75]_i_1__0\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \Head[76]_i_1__0\ : label is "soft_lutpair925";
  attribute SOFT_HLUTNM of \Head[77]_i_1__0\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \Head[78]_i_1__0\ : label is "soft_lutpair926";
  attribute SOFT_HLUTNM of \Head[79]_i_1__0\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \Head[7]_i_1\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \Head[80]_i_1__0\ : label is "soft_lutpair927";
  attribute SOFT_HLUTNM of \Head[81]_i_1__0\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \Head[82]_i_1__0\ : label is "soft_lutpair928";
  attribute SOFT_HLUTNM of \Head[83]_i_1__0\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \Head[84]_i_1__0\ : label is "soft_lutpair929";
  attribute SOFT_HLUTNM of \Head[85]_i_1__0\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \Head[86]_i_1__0\ : label is "soft_lutpair930";
  attribute SOFT_HLUTNM of \Head[87]_i_1__0\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \Head[88]_i_1__0\ : label is "soft_lutpair931";
  attribute SOFT_HLUTNM of \Head[89]_i_1__0\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \Head[8]_i_1__0\ : label is "soft_lutpair891";
  attribute SOFT_HLUTNM of \Head[90]_i_1__0\ : label is "soft_lutpair932";
  attribute SOFT_HLUTNM of \Head[91]_i_1__0\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \Head[92]_i_1__0\ : label is "soft_lutpair933";
  attribute SOFT_HLUTNM of \Head[93]_i_1__0\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \Head[94]_i_1__0\ : label is "soft_lutpair934";
  attribute SOFT_HLUTNM of \Head[95]_i_1__0\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \Head[96]_i_1__0\ : label is "soft_lutpair935";
  attribute SOFT_HLUTNM of \Head[97]_i_1__0\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \Head[98]_i_1__0\ : label is "soft_lutpair936";
  attribute SOFT_HLUTNM of \Head[99]_i_1__0\ : label is "soft_lutpair937";
  attribute SOFT_HLUTNM of \Head[9]_i_1__0\ : label is "soft_lutpair892";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_7_0_5 : label is 1272;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_7_0_5 : label is 7;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_7_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_102_107 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_102_107 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_102_107 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_102_107 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_102_107 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_102_107 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_7_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_108_113 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_108_113 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_108_113 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_7_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_114_119 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_114_119 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_114_119 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_7_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_120_125 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_120_125 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_120_125 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_120_125 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_120_125 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_120_125 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_120_125 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_120_125 : label is 120;
  attribute ram_slice_end of MemArray_reg_0_7_120_125 : label is 125;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_126_131 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_126_131 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_126_131 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_126_131 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_126_131 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_126_131 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_126_131 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_126_131 : label is 126;
  attribute ram_slice_end of MemArray_reg_0_7_126_131 : label is 131;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_12_17 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_12_17 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_7_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_132_137 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_132_137 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_132_137 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_132_137 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_132_137 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_132_137 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_132_137 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_132_137 : label is 132;
  attribute ram_slice_end of MemArray_reg_0_7_132_137 : label is 137;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_138_143 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_138_143 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_138_143 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_138_143 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_138_143 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_138_143 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_138_143 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_138_143 : label is 138;
  attribute ram_slice_end of MemArray_reg_0_7_138_143 : label is 143;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_144_149 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_144_149 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_144_149 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_144_149 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_144_149 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_144_149 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_144_149 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_144_149 : label is 144;
  attribute ram_slice_end of MemArray_reg_0_7_144_149 : label is 149;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_150_155 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_150_155 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_150_155 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_150_155 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_150_155 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_150_155 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_150_155 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_150_155 : label is 150;
  attribute ram_slice_end of MemArray_reg_0_7_150_155 : label is 155;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_156_158 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_156_158 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_156_158 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_156_158 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_156_158 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_156_158 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_156_158 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_156_158 : label is 156;
  attribute ram_slice_end of MemArray_reg_0_7_156_158 : label is 158;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_18_23 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_18_23 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_7_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_24_29 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_24_29 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_7_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_30_35 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_30_35 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_7_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_36_41 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_36_41 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_7_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_42_47 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_42_47 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_7_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_48_53 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_48_53 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_7_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_54_59 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_54_59 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_7_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_60_65 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_60_65 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_7_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_66_71 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_66_71 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_7_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_6_11 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_6_11 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_7_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_72_77 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_72_77 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_7_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_78_83 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_78_83 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_7_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_84_89 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_84_89 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_7_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_90_95 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_90_95 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_7_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_96_101 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_96_101 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_7_96_101 : label is 101;
  attribute SOFT_HLUTNM of \RdPtr[2]_i_4\ : label is "soft_lutpair887";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[11]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[12]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[3]_i_1\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[7]_i_1\ : label is 35;
  attribute SOFT_HLUTNM of rrq_dsc_ld_901_i_3 : label is "soft_lutpair885";
  attribute SOFT_HLUTNM of \rrq_sm_cur_900[2]_i_3\ : label is "soft_lutpair885";
begin
  \FifoCntrRd_reg[1]_0\(1 downto 0) <= \^fifocntrrd_reg[1]_0\(1 downto 0);
  \FifoCntrWr_reg[1]_0\(1 downto 0) <= \^fifocntrwr_reg[1]_0\(1 downto 0);
  Q(157 downto 0) <= \^q\(157 downto 0);
  \WrPtr_reg[1]_0\(1 downto 0) <= \^wrptr_reg[1]_0\(1 downto 0);
\FifoCntrRd[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_0\(0),
      O => \FifoCntrRd[0]_i_1__0_n_0\
    );
\FifoCntrRd[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAA9555"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => \FifoCntrRd_reg[2]_0\(0),
      I2 => dsc_acc_mgc_nn1,
      I3 => dsc_acc_done_nn1,
      I4 => \^fifocntrrd_reg[1]_0\(1),
      I5 => \^fifocntrrd_reg[1]_0\(0),
      O => \FifoCntrRd[2]_i_1__0_n_0\
    );
\FifoCntrRd[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => dsc_ch_vld(0),
      I2 => \^fifocntrrd_reg[1]_0\(1),
      I3 => \^fifocntrrd_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrRd[3]_i_2_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[0]_i_1__0_n_0\,
      Q => \^fifocntrrd_reg[1]_0\(0),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd_reg[1]_1\(0),
      Q => \^fifocntrrd_reg[1]_0\(1),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[2]_i_1__0_n_0\,
      Q => FifoCntrRd_reg(2),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrRd_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[3]_i_2_n_0\,
      Q => FifoCntrRd_reg(3),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrWr[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[0]_i_1__0_n_0\
    );
\FifoCntrWr[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AA9"
    )
        port map (
      I0 => FifoCntrWr_reg(2),
      I1 => dsc_ch_evld(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[2]_i_1__0_n_0\
    );
\FifoCntrWr[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrWr_reg(3),
      I1 => dsc_ch_evld(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrWr_reg(2),
      O => \FifoCntrWr[3]_i_2_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[0]_i_1__0_n_0\,
      Q => \^fifocntrwr_reg[1]_0\(0),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr_reg[1]_1\(0),
      Q => \^fifocntrwr_reg[1]_0\(1),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[2]_i_1__0_n_0\,
      Q => FifoCntrWr_reg(2),
      R => \RdPtr[2]_i_1_n_0\
    );
\FifoCntrWr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[3]_i_2_n_0\,
      Q => FifoCntrWr_reg(3),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head1,
      I2 => Head0(0),
      O => p_0_in1_in(0)
    );
\Head[100]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(100),
      I1 => Head1,
      I2 => Head0(100),
      O => p_0_in1_in(100)
    );
\Head[101]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(101),
      I1 => Head1,
      I2 => Head0(101),
      O => p_0_in1_in(101)
    );
\Head[102]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(102),
      I1 => Head1,
      I2 => Head0(102),
      O => p_0_in1_in(102)
    );
\Head[103]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(103),
      I1 => Head1,
      I2 => Head0(103),
      O => p_0_in1_in(103)
    );
\Head[104]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(104),
      I1 => Head1,
      I2 => Head0(104),
      O => p_0_in1_in(104)
    );
\Head[105]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(105),
      I1 => Head1,
      I2 => Head0(105),
      O => p_0_in1_in(105)
    );
\Head[106]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(106),
      I1 => Head1,
      I2 => Head0(106),
      O => p_0_in1_in(106)
    );
\Head[107]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(107),
      I1 => Head1,
      I2 => Head0(107),
      O => p_0_in1_in(107)
    );
\Head[108]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(108),
      I1 => Head1,
      I2 => Head0(108),
      O => p_0_in1_in(108)
    );
\Head[109]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(109),
      I1 => Head1,
      I2 => Head0(109),
      O => p_0_in1_in(109)
    );
\Head[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head1,
      I2 => Head0(10),
      O => p_0_in1_in(10)
    );
\Head[110]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(110),
      I1 => Head1,
      I2 => Head0(110),
      O => p_0_in1_in(110)
    );
\Head[111]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(111),
      I1 => Head1,
      I2 => Head0(111),
      O => p_0_in1_in(111)
    );
\Head[112]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(112),
      I1 => Head1,
      I2 => Head0(112),
      O => p_0_in1_in(112)
    );
\Head[113]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(113),
      I1 => Head1,
      I2 => Head0(113),
      O => p_0_in1_in(113)
    );
\Head[114]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(114),
      I1 => Head1,
      I2 => Head0(114),
      O => p_0_in1_in(114)
    );
\Head[115]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(115),
      I1 => Head1,
      I2 => Head0(115),
      O => p_0_in1_in(115)
    );
\Head[116]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(116),
      I1 => Head1,
      I2 => Head0(116),
      O => p_0_in1_in(116)
    );
\Head[117]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(117),
      I1 => Head1,
      I2 => Head0(117),
      O => p_0_in1_in(117)
    );
\Head[118]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(118),
      I1 => Head1,
      I2 => Head0(118),
      O => p_0_in1_in(118)
    );
\Head[119]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(119),
      I1 => Head1,
      I2 => Head0(119),
      O => p_0_in1_in(119)
    );
\Head[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head1,
      I2 => Head0(11),
      O => p_0_in1_in(11)
    );
\Head[120]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(120),
      I1 => Head1,
      I2 => Head0(120),
      O => p_0_in1_in(120)
    );
\Head[121]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(121),
      I1 => Head1,
      I2 => Head0(121),
      O => p_0_in1_in(121)
    );
\Head[122]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(122),
      I1 => Head1,
      I2 => Head0(122),
      O => p_0_in1_in(122)
    );
\Head[123]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(123),
      I1 => Head1,
      I2 => Head0(123),
      O => p_0_in1_in(123)
    );
\Head[124]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(124),
      I1 => Head1,
      I2 => Head0(124),
      O => p_0_in1_in(124)
    );
\Head[125]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(125),
      I1 => Head1,
      I2 => Head0(125),
      O => p_0_in1_in(125)
    );
\Head[126]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(126),
      I1 => Head1,
      I2 => Head0(126),
      O => p_0_in1_in(126)
    );
\Head[127]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(127),
      I1 => Head1,
      I2 => Head0(127),
      O => p_0_in1_in(127)
    );
\Head[128]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(128),
      I1 => Head1,
      I2 => Head0(128),
      O => p_0_in1_in(128)
    );
\Head[129]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(129),
      I1 => Head1,
      I2 => Head0(129),
      O => p_0_in1_in(129)
    );
\Head[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head1,
      I2 => Head0(12),
      O => p_0_in1_in(12)
    );
\Head[130]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(130),
      I1 => Head1,
      I2 => Head0(130),
      O => p_0_in1_in(130)
    );
\Head[131]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(131),
      I1 => Head1,
      I2 => Head0(131),
      O => p_0_in1_in(131)
    );
\Head[132]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(132),
      I1 => Head1,
      I2 => Head0(132),
      O => p_0_in1_in(132)
    );
\Head[133]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(133),
      I1 => Head1,
      I2 => Head0(133),
      O => p_0_in1_in(133)
    );
\Head[134]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(134),
      I1 => Head1,
      I2 => Head0(134),
      O => p_0_in1_in(134)
    );
\Head[135]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(135),
      I1 => Head1,
      I2 => Head0(135),
      O => p_0_in1_in(135)
    );
\Head[136]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(136),
      I1 => Head1,
      I2 => Head0(136),
      O => p_0_in1_in(136)
    );
\Head[137]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(137),
      I1 => Head1,
      I2 => Head0(137),
      O => p_0_in1_in(137)
    );
\Head[138]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(138),
      I1 => Head1,
      I2 => Head0(138),
      O => p_0_in1_in(138)
    );
\Head[139]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(139),
      I1 => Head1,
      I2 => Head0(139),
      O => p_0_in1_in(139)
    );
\Head[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head1,
      I2 => Head0(13),
      O => p_0_in1_in(13)
    );
\Head[140]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(140),
      I1 => Head1,
      I2 => Head0(140),
      O => p_0_in1_in(140)
    );
\Head[141]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(141),
      I1 => Head1,
      I2 => Head0(141),
      O => p_0_in1_in(141)
    );
\Head[142]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(142),
      I1 => Head1,
      I2 => Head0(142),
      O => p_0_in1_in(142)
    );
\Head[143]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(143),
      I1 => Head1,
      I2 => Head0(143),
      O => p_0_in1_in(143)
    );
\Head[144]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(144),
      I1 => Head1,
      I2 => Head0(144),
      O => p_0_in1_in(144)
    );
\Head[145]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(145),
      I1 => Head1,
      I2 => Head0(145),
      O => p_0_in1_in(145)
    );
\Head[146]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(146),
      I1 => Head1,
      I2 => Head0(146),
      O => p_0_in1_in(146)
    );
\Head[147]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(147),
      I1 => Head1,
      I2 => Head0(147),
      O => p_0_in1_in(147)
    );
\Head[148]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(148),
      I1 => Head1,
      I2 => Head0(148),
      O => p_0_in1_in(148)
    );
\Head[149]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(149),
      I1 => Head1,
      I2 => Head0(149),
      O => p_0_in1_in(149)
    );
\Head[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head1,
      I2 => Head0(14),
      O => p_0_in1_in(14)
    );
\Head[150]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(150),
      I1 => Head1,
      I2 => Head0(150),
      O => p_0_in1_in(150)
    );
\Head[151]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(151),
      I1 => Head1,
      I2 => Head0(151),
      O => p_0_in1_in(151)
    );
\Head[152]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(152),
      I1 => Head1,
      I2 => Head0(152),
      O => p_0_in1_in(152)
    );
\Head[153]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(153),
      I1 => Head1,
      I2 => Head0(153),
      O => p_0_in1_in(153)
    );
\Head[154]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(154),
      I1 => Head1,
      I2 => Head0(154),
      O => p_0_in1_in(154)
    );
\Head[155]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(155),
      I1 => Head1,
      I2 => Head0(155),
      O => p_0_in1_in(155)
    );
\Head[156]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(156),
      I1 => Head1,
      I2 => Head0(156),
      O => p_0_in1_in(156)
    );
\Head[157]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(157),
      I1 => Head1,
      I2 => Head0(157),
      O => p_0_in1_in(157)
    );
\Head[158]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEEF"
    )
        port map (
      I0 => empty_ff_reg_0,
      I1 => Head1,
      I2 => \^fifocntrrd_reg[1]_0\(0),
      I3 => FifoCntrRd_reg(3),
      I4 => FifoCntrRd_reg(2),
      I5 => \^fifocntrrd_reg[1]_0\(1),
      O => \Head[158]_i_1_n_0\
    );
\Head[158]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(158),
      I1 => Head1,
      I2 => Head0(158),
      O => p_0_in1_in(158)
    );
\Head[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head1,
      I2 => Head0(15),
      O => p_0_in1_in(15)
    );
\Head[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head1,
      I2 => Head0(16),
      O => p_0_in1_in(16)
    );
\Head[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head1,
      I2 => Head0(17),
      O => p_0_in1_in(17)
    );
\Head[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head1,
      I2 => Head0(18),
      O => p_0_in1_in(18)
    );
\Head[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head1,
      I2 => Head0(19),
      O => p_0_in1_in(19)
    );
\Head[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head1,
      I2 => Head0(1),
      O => p_0_in1_in(1)
    );
\Head[20]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head1,
      I2 => Head0(20),
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head1,
      I2 => Head0(21),
      O => p_0_in1_in(21)
    );
\Head[22]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head1,
      I2 => Head0(22),
      O => p_0_in1_in(22)
    );
\Head[23]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head1,
      I2 => Head0(23),
      O => p_0_in1_in(23)
    );
\Head[24]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head1,
      I2 => Head0(24),
      O => p_0_in1_in(24)
    );
\Head[25]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head1,
      I2 => Head0(25),
      O => p_0_in1_in(25)
    );
\Head[26]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head1,
      I2 => Head0(26),
      O => p_0_in1_in(26)
    );
\Head[27]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head1,
      I2 => Head0(27),
      O => p_0_in1_in(27)
    );
\Head[28]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head1,
      I2 => Head0(28),
      O => p_0_in1_in(28)
    );
\Head[29]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head1,
      I2 => Head0(29),
      O => p_0_in1_in(29)
    );
\Head[30]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head1,
      I2 => Head0(30),
      O => p_0_in1_in(30)
    );
\Head[31]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head1,
      I2 => Head0(31),
      O => p_0_in1_in(31)
    );
\Head[32]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head1,
      I2 => Head0(32),
      O => p_0_in1_in(32)
    );
\Head[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head1,
      I2 => Head0(33),
      O => p_0_in1_in(33)
    );
\Head[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head1,
      I2 => Head0(34),
      O => p_0_in1_in(34)
    );
\Head[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head1,
      I2 => Head0(35),
      O => p_0_in1_in(35)
    );
\Head[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head1,
      I2 => Head0(36),
      O => p_0_in1_in(36)
    );
\Head[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head1,
      I2 => Head0(37),
      O => p_0_in1_in(37)
    );
\Head[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head1,
      I2 => Head0(38),
      O => p_0_in1_in(38)
    );
\Head[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head1,
      I2 => Head0(39),
      O => p_0_in1_in(39)
    );
\Head[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head1,
      I2 => Head0(3),
      O => p_0_in1_in(3)
    );
\Head[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head1,
      I2 => Head0(40),
      O => p_0_in1_in(40)
    );
\Head[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head1,
      I2 => Head0(41),
      O => p_0_in1_in(41)
    );
\Head[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head1,
      I2 => Head0(42),
      O => p_0_in1_in(42)
    );
\Head[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head1,
      I2 => Head0(43),
      O => p_0_in1_in(43)
    );
\Head[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head1,
      I2 => Head0(44),
      O => p_0_in1_in(44)
    );
\Head[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head1,
      I2 => Head0(45),
      O => p_0_in1_in(45)
    );
\Head[46]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head1,
      I2 => Head0(46),
      O => p_0_in1_in(46)
    );
\Head[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head1,
      I2 => Head0(47),
      O => p_0_in1_in(47)
    );
\Head[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head1,
      I2 => Head0(48),
      O => p_0_in1_in(48)
    );
\Head[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head1,
      I2 => Head0(49),
      O => p_0_in1_in(49)
    );
\Head[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head1,
      I2 => Head0(4),
      O => p_0_in1_in(4)
    );
\Head[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head1,
      I2 => Head0(50),
      O => p_0_in1_in(50)
    );
\Head[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head1,
      I2 => Head0(51),
      O => p_0_in1_in(51)
    );
\Head[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head1,
      I2 => Head0(52),
      O => p_0_in1_in(52)
    );
\Head[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head1,
      I2 => Head0(53),
      O => p_0_in1_in(53)
    );
\Head[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head1,
      I2 => Head0(54),
      O => p_0_in1_in(54)
    );
\Head[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head1,
      I2 => Head0(55),
      O => p_0_in1_in(55)
    );
\Head[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head1,
      I2 => Head0(56),
      O => p_0_in1_in(56)
    );
\Head[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head1,
      I2 => Head0(57),
      O => p_0_in1_in(57)
    );
\Head[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head1,
      I2 => Head0(58),
      O => p_0_in1_in(58)
    );
\Head[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head1,
      I2 => Head0(59),
      O => p_0_in1_in(59)
    );
\Head[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head1,
      I2 => Head0(5),
      O => p_0_in1_in(5)
    );
\Head[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head1,
      I2 => Head0(60),
      O => p_0_in1_in(60)
    );
\Head[61]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head1,
      I2 => Head0(61),
      O => p_0_in1_in(61)
    );
\Head[62]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head1,
      I2 => Head0(62),
      O => p_0_in1_in(62)
    );
\Head[63]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head1,
      I2 => Head0(63),
      O => p_0_in1_in(63)
    );
\Head[64]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head1,
      I2 => Head0(64),
      O => p_0_in1_in(64)
    );
\Head[65]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head1,
      I2 => Head0(65),
      O => p_0_in1_in(65)
    );
\Head[66]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head1,
      I2 => Head0(66),
      O => p_0_in1_in(66)
    );
\Head[67]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head1,
      I2 => Head0(67),
      O => p_0_in1_in(67)
    );
\Head[68]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head1,
      I2 => Head0(68),
      O => p_0_in1_in(68)
    );
\Head[69]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head1,
      I2 => Head0(69),
      O => p_0_in1_in(69)
    );
\Head[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head1,
      I2 => Head0(6),
      O => p_0_in1_in(6)
    );
\Head[70]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head1,
      I2 => Head0(70),
      O => p_0_in1_in(70)
    );
\Head[71]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head1,
      I2 => Head0(71),
      O => p_0_in1_in(71)
    );
\Head[72]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head1,
      I2 => Head0(72),
      O => p_0_in1_in(72)
    );
\Head[73]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head1,
      I2 => Head0(73),
      O => p_0_in1_in(73)
    );
\Head[74]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head1,
      I2 => Head0(74),
      O => p_0_in1_in(74)
    );
\Head[75]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head1,
      I2 => Head0(75),
      O => p_0_in1_in(75)
    );
\Head[76]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head1,
      I2 => Head0(76),
      O => p_0_in1_in(76)
    );
\Head[77]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head1,
      I2 => Head0(77),
      O => p_0_in1_in(77)
    );
\Head[78]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head1,
      I2 => Head0(78),
      O => p_0_in1_in(78)
    );
\Head[79]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head1,
      I2 => Head0(79),
      O => p_0_in1_in(79)
    );
\Head[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head1,
      I2 => Head0(7),
      O => p_0_in1_in(7)
    );
\Head[80]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head1,
      I2 => Head0(80),
      O => p_0_in1_in(80)
    );
\Head[81]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(81),
      I1 => Head1,
      I2 => Head0(81),
      O => p_0_in1_in(81)
    );
\Head[82]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(82),
      I1 => Head1,
      I2 => Head0(82),
      O => p_0_in1_in(82)
    );
\Head[83]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(83),
      I1 => Head1,
      I2 => Head0(83),
      O => p_0_in1_in(83)
    );
\Head[84]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(84),
      I1 => Head1,
      I2 => Head0(84),
      O => p_0_in1_in(84)
    );
\Head[85]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(85),
      I1 => Head1,
      I2 => Head0(85),
      O => p_0_in1_in(85)
    );
\Head[86]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(86),
      I1 => Head1,
      I2 => Head0(86),
      O => p_0_in1_in(86)
    );
\Head[87]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(87),
      I1 => Head1,
      I2 => Head0(87),
      O => p_0_in1_in(87)
    );
\Head[88]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(88),
      I1 => Head1,
      I2 => Head0(88),
      O => p_0_in1_in(88)
    );
\Head[89]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(89),
      I1 => Head1,
      I2 => Head0(89),
      O => p_0_in1_in(89)
    );
\Head[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head1,
      I2 => Head0(8),
      O => p_0_in1_in(8)
    );
\Head[90]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(90),
      I1 => Head1,
      I2 => Head0(90),
      O => p_0_in1_in(90)
    );
\Head[91]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(91),
      I1 => Head1,
      I2 => Head0(91),
      O => p_0_in1_in(91)
    );
\Head[92]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(92),
      I1 => Head1,
      I2 => Head0(92),
      O => p_0_in1_in(92)
    );
\Head[93]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(93),
      I1 => Head1,
      I2 => Head0(93),
      O => p_0_in1_in(93)
    );
\Head[94]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(94),
      I1 => Head1,
      I2 => Head0(94),
      O => p_0_in1_in(94)
    );
\Head[95]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(95),
      I1 => Head1,
      I2 => Head0(95),
      O => p_0_in1_in(95)
    );
\Head[96]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(96),
      I1 => Head1,
      I2 => Head0(96),
      O => p_0_in1_in(96)
    );
\Head[97]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(97),
      I1 => Head1,
      I2 => Head0(97),
      O => p_0_in1_in(97)
    );
\Head[98]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(98),
      I1 => Head1,
      I2 => Head0(98),
      O => p_0_in1_in(98)
    );
\Head[99]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(99),
      I1 => Head1,
      I2 => Head0(99),
      O => p_0_in1_in(99)
    );
\Head[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head1,
      I2 => Head0(9),
      O => p_0_in1_in(9)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(0),
      Q => \^q\(0),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(100),
      Q => \^q\(99),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(101),
      Q => \^q\(100),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(102),
      Q => \^q\(101),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(103),
      Q => \^q\(102),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(104),
      Q => \^q\(103),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(105),
      Q => \^q\(104),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(106),
      Q => \^q\(105),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(107),
      Q => \^q\(106),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(108),
      Q => \^q\(107),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(109),
      Q => \^q\(108),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(10),
      Q => \^q\(9),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(110),
      Q => \^q\(109),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(111),
      Q => \^q\(110),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(112),
      Q => \^q\(111),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(113),
      Q => \^q\(112),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(114),
      Q => \^q\(113),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(115),
      Q => \^q\(114),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(116),
      Q => \^q\(115),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(117),
      Q => \^q\(116),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(118),
      Q => \^q\(117),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(119),
      Q => \^q\(118),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(11),
      Q => \^q\(10),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(120),
      Q => \^q\(119),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(121),
      Q => \^q\(120),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(122),
      Q => \^q\(121),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(123),
      Q => \^q\(122),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(124),
      Q => \^q\(123),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(125),
      Q => \^q\(124),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(126),
      Q => \^q\(125),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(127),
      Q => \^q\(126),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(128),
      Q => \^q\(127),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(129),
      Q => \^q\(128),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(12),
      Q => \^q\(11),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(130),
      Q => \^q\(129),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(131),
      Q => \^q\(130),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(132),
      Q => \^q\(131),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(133),
      Q => \^q\(132),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(134),
      Q => \^q\(133),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(135),
      Q => \^q\(134),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(136),
      Q => \^q\(135),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(137),
      Q => \^q\(136),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(138),
      Q => \^q\(137),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(139),
      Q => \^q\(138),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(13),
      Q => \^q\(12),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(140),
      Q => \^q\(139),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(141),
      Q => \^q\(140),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(142),
      Q => \^q\(141),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(143),
      Q => \^q\(142),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(144),
      Q => \^q\(143),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(145),
      Q => \^q\(144),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(146),
      Q => \^q\(145),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(147),
      Q => \^q\(146),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(148),
      Q => \^q\(147),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(149),
      Q => \^q\(148),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(14),
      Q => \^q\(13),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(150),
      Q => \^q\(149),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(151),
      Q => \^q\(150),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(152),
      Q => \^q\(151),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(153),
      Q => \^q\(152),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(154),
      Q => \^q\(153),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(155),
      Q => \^q\(154),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(156),
      Q => \^q\(155),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(157),
      Q => \^q\(156),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(158),
      Q => \^q\(157),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(15),
      Q => \^q\(14),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(16),
      Q => \^q\(15),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(17),
      Q => \^q\(16),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(18),
      Q => \^q\(17),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(19),
      Q => \^q\(18),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(1),
      Q => \^q\(1),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(20),
      Q => \^q\(19),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(21),
      Q => \^q\(20),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(22),
      Q => \^q\(21),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(23),
      Q => \^q\(22),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(24),
      Q => \^q\(23),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(25),
      Q => \^q\(24),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(26),
      Q => \^q\(25),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(27),
      Q => \^q\(26),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(28),
      Q => \^q\(27),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(29),
      Q => \^q\(28),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(30),
      Q => \^q\(29),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(31),
      Q => \^q\(30),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(32),
      Q => \^q\(31),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(33),
      Q => \^q\(32),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(34),
      Q => \^q\(33),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(35),
      Q => \^q\(34),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(36),
      Q => \^q\(35),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(37),
      Q => \^q\(36),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(38),
      Q => \^q\(37),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(39),
      Q => \^q\(38),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(3),
      Q => \^q\(2),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(40),
      Q => \^q\(39),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(41),
      Q => \^q\(40),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(42),
      Q => \^q\(41),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(43),
      Q => \^q\(42),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(44),
      Q => \^q\(43),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(45),
      Q => \^q\(44),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(46),
      Q => \^q\(45),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(47),
      Q => \^q\(46),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(48),
      Q => \^q\(47),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(49),
      Q => \^q\(48),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(4),
      Q => \^q\(3),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(50),
      Q => \^q\(49),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(51),
      Q => \^q\(50),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(52),
      Q => \^q\(51),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(53),
      Q => \^q\(52),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(54),
      Q => \^q\(53),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(55),
      Q => \^q\(54),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(56),
      Q => \^q\(55),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(57),
      Q => \^q\(56),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(58),
      Q => \^q\(57),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(59),
      Q => \^q\(58),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(5),
      Q => \^q\(4),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(60),
      Q => \^q\(59),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(61),
      Q => \^q\(60),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(62),
      Q => \^q\(61),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(63),
      Q => \^q\(62),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(64),
      Q => \^q\(63),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(65),
      Q => \^q\(64),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(66),
      Q => \^q\(65),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(67),
      Q => \^q\(66),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(68),
      Q => \^q\(67),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(69),
      Q => \^q\(68),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(6),
      Q => \^q\(5),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(70),
      Q => \^q\(69),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(71),
      Q => \^q\(70),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(72),
      Q => \^q\(71),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(73),
      Q => \^q\(72),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(74),
      Q => \^q\(73),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(75),
      Q => \^q\(74),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(76),
      Q => \^q\(75),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(77),
      Q => \^q\(76),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(78),
      Q => \^q\(77),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(79),
      Q => \^q\(78),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(7),
      Q => \^q\(6),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(80),
      Q => \^q\(79),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(81),
      Q => \^q\(80),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(82),
      Q => \^q\(81),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(83),
      Q => \^q\(82),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(84),
      Q => \^q\(83),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(85),
      Q => \^q\(84),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(86),
      Q => \^q\(85),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(87),
      Q => \^q\(86),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(88),
      Q => \^q\(87),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(89),
      Q => \^q\(88),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(8),
      Q => \^q\(7),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(90),
      Q => \^q\(89),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(91),
      Q => \^q\(90),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(92),
      Q => \^q\(91),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(93),
      Q => \^q\(92),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(94),
      Q => \^q\(93),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(95),
      Q => \^q\(94),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(96),
      Q => \^q\(95),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(97),
      Q => \^q\(96),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(98),
      Q => \^q\(97),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(99),
      Q => \^q\(98),
      R => \RdPtr[2]_i_1_n_0\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1_n_0\,
      D => p_0_in1_in(9),
      Q => \^q\(8),
      R => \RdPtr[2]_i_1_n_0\
    );
MemArray_reg_0_7_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(1 downto 0),
      DOB(1) => Head0(3),
      DOB(0) => MemArray_reg_0_7_0_5_n_3,
      DOC(1 downto 0) => Head0(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(103 downto 102),
      DIB(1 downto 0) => DataIn(105 downto 104),
      DIC(1 downto 0) => DataIn(107 downto 106),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(109 downto 108),
      DIB(1 downto 0) => DataIn(111 downto 110),
      DIC(1 downto 0) => DataIn(113 downto 112),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => Head0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(115 downto 114),
      DIB(1 downto 0) => DataIn(117 downto 116),
      DIC(1 downto 0) => DataIn(119 downto 118),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(115 downto 114),
      DOB(1 downto 0) => Head0(117 downto 116),
      DOC(1 downto 0) => Head0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_120_125: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(121 downto 120),
      DIB(1 downto 0) => DataIn(123 downto 122),
      DIC(1 downto 0) => DataIn(125 downto 124),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(121 downto 120),
      DOB(1 downto 0) => Head0(123 downto 122),
      DOC(1 downto 0) => Head0(125 downto 124),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_126_131: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(127 downto 126),
      DIB(1 downto 0) => DataIn(129 downto 128),
      DIC(1 downto 0) => DataIn(131 downto 130),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(127 downto 126),
      DOB(1 downto 0) => Head0(129 downto 128),
      DOC(1 downto 0) => Head0(131 downto 130),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(13 downto 12),
      DIB(1 downto 0) => DataIn(15 downto 14),
      DIC(1 downto 0) => DataIn(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => Head0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_132_137: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(133 downto 132),
      DIB(1 downto 0) => DataIn(135 downto 134),
      DIC(1 downto 0) => DataIn(137 downto 136),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(133 downto 132),
      DOB(1 downto 0) => Head0(135 downto 134),
      DOC(1 downto 0) => Head0(137 downto 136),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_138_143: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(139 downto 138),
      DIB(1 downto 0) => DataIn(141 downto 140),
      DIC(1 downto 0) => DataIn(143 downto 142),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(139 downto 138),
      DOB(1 downto 0) => Head0(141 downto 140),
      DOC(1 downto 0) => Head0(143 downto 142),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_144_149: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(145 downto 144),
      DIB(1 downto 0) => DataIn(147 downto 146),
      DIC(1 downto 0) => DataIn(149 downto 148),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(145 downto 144),
      DOB(1 downto 0) => Head0(147 downto 146),
      DOC(1 downto 0) => Head0(149 downto 148),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_150_155: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(151 downto 150),
      DIB(1 downto 0) => DataIn(153 downto 152),
      DIC(1 downto 0) => DataIn(155 downto 154),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(151 downto 150),
      DOB(1 downto 0) => Head0(153 downto 152),
      DOC(1 downto 0) => Head0(155 downto 154),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_156_158: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(157 downto 156),
      DIB(1) => '0',
      DIB(0) => DataIn(158),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(157 downto 156),
      DOB(1) => NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED(1),
      DOB(0) => Head0(158),
      DOC(1 downto 0) => NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(19 downto 18),
      DIB(1 downto 0) => DataIn(21 downto 20),
      DIC(1 downto 0) => DataIn(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(25 downto 24),
      DIB(1 downto 0) => DataIn(27 downto 26),
      DIC(1 downto 0) => DataIn(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(25 downto 24),
      DOB(1 downto 0) => Head0(27 downto 26),
      DOC(1 downto 0) => Head0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(31 downto 30),
      DIB(1 downto 0) => DataIn(33 downto 32),
      DIC(1 downto 0) => DataIn(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(31 downto 30),
      DOB(1 downto 0) => Head0(33 downto 32),
      DOC(1 downto 0) => Head0(35 downto 34),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(37 downto 36),
      DIB(1 downto 0) => DataIn(39 downto 38),
      DIC(1 downto 0) => DataIn(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(37 downto 36),
      DOB(1 downto 0) => Head0(39 downto 38),
      DOC(1 downto 0) => Head0(41 downto 40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(43 downto 42),
      DIB(1 downto 0) => DataIn(45 downto 44),
      DIC(1 downto 0) => DataIn(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(43 downto 42),
      DOB(1 downto 0) => Head0(45 downto 44),
      DOC(1 downto 0) => Head0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(49 downto 48),
      DIB(1 downto 0) => DataIn(51 downto 50),
      DIC(1 downto 0) => DataIn(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(49 downto 48),
      DOB(1 downto 0) => Head0(51 downto 50),
      DOC(1 downto 0) => Head0(53 downto 52),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(55 downto 54),
      DIB(1 downto 0) => DataIn(57 downto 56),
      DIC(1 downto 0) => DataIn(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(55 downto 54),
      DOB(1 downto 0) => Head0(57 downto 56),
      DOC(1 downto 0) => Head0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(61 downto 60),
      DIB(1 downto 0) => DataIn(63 downto 62),
      DIC(1 downto 0) => DataIn(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(67 downto 66),
      DIB(1 downto 0) => DataIn(69 downto 68),
      DIC(1 downto 0) => DataIn(71 downto 70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(7 downto 6),
      DIB(1 downto 0) => DataIn(9 downto 8),
      DIC(1 downto 0) => DataIn(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(7 downto 6),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(73 downto 72),
      DIB(1 downto 0) => DataIn(75 downto 74),
      DIC(1 downto 0) => DataIn(77 downto 76),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(79 downto 78),
      DIB(1 downto 0) => DataIn(81 downto 80),
      DIC(1 downto 0) => DataIn(83 downto 82),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(85 downto 84),
      DIB(1 downto 0) => DataIn(87 downto 86),
      DIC(1 downto 0) => DataIn(89 downto 88),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(91 downto 90),
      DIB(1 downto 0) => DataIn(93 downto 92),
      DIC(1 downto 0) => DataIn(95 downto 94),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(97 downto 96),
      DIB(1 downto 0) => DataIn(99 downto 98),
      DIC(1 downto 0) => DataIn(101 downto 100),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
\RdPtr[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5656565656565666"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => empty_ff_reg_0,
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"557FAA80"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \RdPtr[2]_i_4_n_0\,
      I2 => empty_ff_reg_0,
      I3 => Head1,
      I4 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \rrq_dsc_ld_901_reg_rep__3\,
      I1 => ctl_rst,
      I2 => evt_idl_stp_vld_nn1,
      O => \RdPtr[2]_i_1_n_0\
    );
\RdPtr[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5777FFFFA8880000"
    )
        port map (
      I0 => RdPtr(1),
      I1 => Head1,
      I2 => empty_ff_reg_0,
      I3 => \RdPtr[2]_i_4_n_0\,
      I4 => RdPtr(0),
      I5 => RdPtr(2),
      O => \RdPtr__0\(2)
    );
\RdPtr[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000008A"
    )
        port map (
      I0 => dsc_ch_vld(0),
      I1 => empty_ff_reg_0,
      I2 => \^fifocntrrd_reg[1]_0\(0),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => Head1
    );
\RdPtr[2]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => FifoCntrRd_reg(2),
      I2 => \^fifocntrrd_reg[1]_0\(1),
      O => \RdPtr[2]_i_4_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \RdPtr[2]_i_1_n_0\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \RdPtr[2]_i_1_n_0\
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => RdPtr(2),
      R => \RdPtr[2]_i_1_n_0\
    );
\WrPtr[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^wrptr_reg[1]_0\(1),
      I1 => \^wrptr_reg[1]_0\(0),
      I2 => \FifoCntrRd_reg[2]_0\(0),
      I3 => dsc_acc_mgc_nn1,
      I4 => dsc_acc_done_nn1,
      I5 => WrPtr(2),
      O => \WrPtr__0\(2)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr_reg[1]_1\(0),
      Q => \^wrptr_reg[1]_0\(0),
      R => \RdPtr[2]_i_1_n_0\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr_reg[1]_1\(1),
      Q => \^wrptr_reg[1]_0\(1),
      R => \RdPtr[2]_i_1_n_0\
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => WrPtr(2),
      R => \RdPtr[2]_i_1_n_0\
    );
almost_full_ff_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FAFAFAF8"
    )
        port map (
      I0 => FifoCntrWr_reg(2),
      I1 => \^fifocntrwr_reg[1]_0\(1),
      I2 => FifoCntrWr_reg(3),
      I3 => dsc_ch_vld(0),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => \RdPtr[2]_i_1_n_0\,
      O => almost_full_ff_i_1_n_0
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => almost_full_ff_i_1_n_0,
      Q => almost_full_ff_reg_0,
      R => '0'
    );
dsc_aln_nn1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => dsc_aln_nn1_i_2_n_0,
      I1 => \out\,
      O => ctl_non_inc_nn1_reg
    );
dsc_aln_nn1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^q\(95),
      I1 => \^q\(30),
      I2 => \^q\(31),
      I3 => \^q\(94),
      I4 => \^q\(32),
      I5 => \^q\(96),
      O => dsc_aln_nn1_i_2_n_0
    );
\dsc_mrs_dst_nn1[11]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => cfg_mrs_nn1(4),
      I1 => \^q\(41),
      I2 => \dsc_mrs_dst_nn1_reg[11]\(4),
      O => \dsc_mrs_dst_nn1[11]_i_2_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => cfg_mrs_nn1(3),
      I1 => \^q\(40),
      I2 => \dsc_mrs_dst_nn1_reg[11]\(3),
      O => \dsc_mrs_dst_nn1[11]_i_3_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => cfg_mrs_nn1(2),
      I1 => \^q\(39),
      I2 => \dsc_mrs_dst_nn1_reg[11]\(2),
      O => \dsc_mrs_dst_nn1[11]_i_4_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => cfg_mrs_nn1(1),
      I1 => \^q\(38),
      I2 => \dsc_mrs_dst_nn1_reg[11]\(1),
      O => \dsc_mrs_dst_nn1[11]_i_5_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(33),
      O => \dsc_mrs_dst_nn1[3]_i_2_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(32),
      O => \dsc_mrs_dst_nn1[3]_i_3_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(31),
      O => \dsc_mrs_dst_nn1[3]_i_4_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(30),
      O => \dsc_mrs_dst_nn1[3]_i_5_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => cfg_mrs_nn1(0),
      I1 => \^q\(37),
      I2 => \dsc_mrs_dst_nn1_reg[11]\(0),
      O => \dsc_mrs_dst_nn1[7]_i_2_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(36),
      O => \dsc_mrs_dst_nn1[7]_i_3_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(35),
      O => \dsc_mrs_dst_nn1[7]_i_4_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(34),
      O => \dsc_mrs_dst_nn1[7]_i_5_n_0\
    );
\dsc_mrs_dst_nn1_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[7]_i_1_n_0\,
      CO(3) => \dsc_mrs_dst_nn1_reg[11]_i_1_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[11]_i_1_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[11]_i_1_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => cfg_mrs_nn1(4 downto 1),
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(11 downto 8),
      S(3) => \dsc_mrs_dst_nn1[11]_i_2_n_0\,
      S(2) => \dsc_mrs_dst_nn1[11]_i_3_n_0\,
      S(1) => \dsc_mrs_dst_nn1[11]_i_4_n_0\,
      S(0) => \dsc_mrs_dst_nn1[11]_i_5_n_0\
    );
\dsc_mrs_dst_nn1_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[11]_i_1_n_0\,
      CO(3 downto 0) => \NLW_dsc_mrs_dst_nn1_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_dsc_mrs_dst_nn1_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \cfg_mrs_nn1_reg[11]\(12),
      S(3 downto 1) => B"000",
      S(0) => S(0)
    );
\dsc_mrs_dst_nn1_reg[3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \dsc_mrs_dst_nn1_reg[3]_i_1_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[3]_i_1_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[3]_i_1_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[3]_i_1_n_3\,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(3 downto 0),
      S(3) => \dsc_mrs_dst_nn1[3]_i_2_n_0\,
      S(2) => \dsc_mrs_dst_nn1[3]_i_3_n_0\,
      S(1) => \dsc_mrs_dst_nn1[3]_i_4_n_0\,
      S(0) => \dsc_mrs_dst_nn1[3]_i_5_n_0\
    );
\dsc_mrs_dst_nn1_reg[7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[3]_i_1_n_0\,
      CO(3) => \dsc_mrs_dst_nn1_reg[7]_i_1_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[7]_i_1_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[7]_i_1_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[7]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => cfg_mrs_nn1(0),
      DI(2 downto 0) => B"000",
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(7 downto 4),
      S(3) => \dsc_mrs_dst_nn1[7]_i_2_n_0\,
      S(2) => \dsc_mrs_dst_nn1[7]_i_3_n_0\,
      S(1) => \dsc_mrs_dst_nn1[7]_i_4_n_0\,
      S(0) => \dsc_mrs_dst_nn1[7]_i_5_n_0\
    );
\empty_ff_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAAAAAABAAAB"
    )
        port map (
      I0 => empty_ff_i_2_n_0,
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => empty_ff_reg_0,
      I5 => \^fifocntrrd_reg[1]_0\(0),
      O => \empty_ff_i_1__0_n_0\
    );
empty_ff_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_0\(0),
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => dsc_ep_nn0,
      I5 => \RdPtr[2]_i_1_n_0\,
      O => empty_ff_i_2_n_0
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__0_n_0\,
      Q => dsc_ep_nn0,
      R => '0'
    );
rrq_dsc_ld_901_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg
    );
rrq_dsc_ld_901_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[6]\(1),
      I1 => dsc_ep_nn0,
      I2 => \rrq_sm_cur_900_reg[6]\(2),
      O => rrq_dsc_ld_901_i_3_n_0
    );
rrq_dsc_ld_901_rep_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg_0
    );
\rrq_dsc_ld_901_rep_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg_1
    );
\rrq_dsc_ld_901_rep_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg_2
    );
\rrq_dsc_ld_901_rep_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg_3
    );
\rrq_dsc_ld_901_rep_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => rrq_dsc_ld_901_i_3_n_0,
      I4 => \rrq_sm_cur_900_reg[4]\,
      I5 => \rrq_dsc_ld_901_reg_rep__3\,
      O => rrq_eod_903_reg_4
    );
\rrq_sm_cur_900[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABAAAAA"
    )
        port map (
      I0 => ctl_rst,
      I1 => reg_sts_hlt_nn1,
      I2 => dsc_ep_nn0,
      I3 => \rrq_sm_cur_900_reg[1]\,
      I4 => \rrq_sm_cur_900_reg[1]_0\,
      O => D(0)
    );
\rrq_sm_cur_900[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A888888888888888"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[2]\,
      I1 => \rrq_sm_cur_900[2]_i_3_n_0\,
      I2 => \rrq_sm_cur_900_reg[2]_0\,
      I3 => dsc_ep_nn0,
      I4 => rrq_eod_903,
      I5 => \rrq_sm_cur_900_reg[2]_1\,
      O => D(1)
    );
\rrq_sm_cur_900[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00110400"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[6]\(2),
      I1 => dsc_ep_nn0,
      I2 => \rrq_sm_cur_900_reg[1]\,
      I3 => \rrq_sm_cur_900_reg[6]\(1),
      I4 => \rrq_sm_cur_900_reg[6]\(0),
      O => \rrq_sm_cur_900[2]_i_3_n_0\
    );
\rrq_sm_cur_900[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0105111500040004"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[4]\,
      I1 => \rrq_sm_cur_900_reg[6]\(1),
      I2 => dsc_ep_nn0,
      I3 => \rrq_sm_cur_900_reg[6]\(2),
      I4 => rrq_eod_903,
      I5 => \rrq_sm_cur_900_reg[2]_0\,
      O => D(2)
    );
\rrq_sm_cur_900[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => ctl_rst,
      I1 => reg_sts_hlt_nn1,
      I2 => \rrq_sm_cur_900[6]_i_2_n_0\,
      O => D(3)
    );
\rrq_sm_cur_900[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFEFFFBBBB"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[6]_0\,
      I1 => \rrq_sm_cur_900_reg[6]\(3),
      I2 => dsc_ep_nn0,
      I3 => \rrq_sm_cur_900_reg[1]\,
      I4 => \rrq_sm_cur_900_reg[6]\(0),
      I5 => \rrq_sm_cur_900_reg[6]\(1),
      O => \rrq_sm_cur_900[6]_i_2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2_50\ is
  port (
    almost_full_ff_reg_0 : out STD_LOGIC;
    ctl_non_inc_nn1_reg : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \Head_reg[158]_0\ : out STD_LOGIC_VECTOR ( 157 downto 0 );
    rrq_eod_903_reg : out STD_LOGIC;
    rrq_eod_903_reg_0 : out STD_LOGIC;
    rrq_eod_903_reg_1 : out STD_LOGIC;
    rrq_eod_903_reg_2 : out STD_LOGIC;
    rrq_eod_903_reg_3 : out STD_LOGIC;
    \cfg_mrs_nn1_reg[11]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
    \FifoCntrWr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrRd_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \WrPtr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    ctl_rst : in STD_LOGIC;
    reg_sts_hlt_nn1 : in STD_LOGIC;
    \rrq_sm_cur_900_reg[6]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rrq_sm_cur_900_reg[6]_0\ : in STD_LOGIC;
    \rrq_dsc_ld_901_reg_rep__2\ : in STD_LOGIC;
    evt_idl_stp_vld_nn1 : in STD_LOGIC;
    rrq_eod_903 : in STD_LOGIC;
    rrq_ld_9008_out : in STD_LOGIC;
    rrq_dsc_ld_901_reg : in STD_LOGIC;
    rrq_dsc_ld_901_reg_0 : in STD_LOGIC;
    \rrq_sm_cur_900_reg[2]\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[1]\ : in STD_LOGIC;
    \rrq_sm_cur_900_reg[1]_0\ : in STD_LOGIC;
    \dsc_mrs_dst_nn1_reg[7]\ : in STD_LOGIC;
    \dsc_mrs_dst_nn1_reg[11]\ : in STD_LOGIC;
    \dsc_mrs_dst_nn1_reg[11]_0\ : in STD_LOGIC;
    \dsc_mrs_dst_nn1_reg[11]_1\ : in STD_LOGIC;
    \dsc_mrs_dst_nn1_reg[11]_2\ : in STD_LOGIC;
    S : in STD_LOGIC_VECTOR ( 0 to 0 );
    \dsc_mrs_dst_nn1_reg[11]_3\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    dsc_ch_evld : in STD_LOGIC_VECTOR ( 0 to 0 );
    DataIn : in STD_LOGIC_VECTOR ( 158 downto 0 );
    empty_ff_reg_0 : in STD_LOGIC;
    dsc_ch_vld : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    dsc_acc_mgc_nn1 : in STD_LOGIC;
    dsc_acc_done_nn1 : in STD_LOGIC;
    \WrPtr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FifoCntrRd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrRd_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2_50\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2_50\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized2_50\ is
  signal \FifoCntrRd[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[3]_i_2__0_n_0\ : STD_LOGIC;
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \^fifocntrrd_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \FifoCntrWr[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[3]_i_2__0_n_0\ : STD_LOGIC;
  signal FifoCntrWr_reg : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \^fifocntrwr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal Head0 : STD_LOGIC_VECTOR ( 158 downto 0 );
  signal Head1 : STD_LOGIC;
  signal \Head[158]_i_1__0_n_0\ : STD_LOGIC;
  signal \^head_reg[158]_0\ : STD_LOGIC_VECTOR ( 157 downto 0 );
  signal MemArray_reg_0_7_0_5_n_3 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \RdPtr[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \RdPtr[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^wrptr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \almost_full_ff_i_1__0_n_0\ : STD_LOGIC;
  signal \dsc_aln_nn1_i_2__0_n_0\ : STD_LOGIC;
  signal dsc_ep_nn0 : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_3__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_4__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[11]_i_5__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_3\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_3\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_1\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_2\ : STD_LOGIC;
  signal \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_3\ : STD_LOGIC;
  signal \empty_ff_i_1__3_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__0_n_0\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 158 downto 0 );
  signal \rrq_dsc_ld_901_i_2__0_n_0\ : STD_LOGIC;
  signal \rrq_sm_cur_900[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \rrq_sm_cur_900[6]_i_4_n_0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[3]_i_2__0\ : label is "soft_lutpair503";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__3\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_2__0\ : label is "soft_lutpair502";
  attribute SOFT_HLUTNM of \Head[0]_i_1__1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \Head[100]_i_1__3\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \Head[101]_i_1__3\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \Head[102]_i_1__3\ : label is "soft_lutpair554";
  attribute SOFT_HLUTNM of \Head[103]_i_1__3\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \Head[104]_i_1__3\ : label is "soft_lutpair555";
  attribute SOFT_HLUTNM of \Head[105]_i_1__3\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \Head[106]_i_1__3\ : label is "soft_lutpair556";
  attribute SOFT_HLUTNM of \Head[107]_i_1__3\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \Head[108]_i_1__3\ : label is "soft_lutpair557";
  attribute SOFT_HLUTNM of \Head[109]_i_1__3\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \Head[10]_i_1__2\ : label is "soft_lutpair508";
  attribute SOFT_HLUTNM of \Head[110]_i_1__3\ : label is "soft_lutpair558";
  attribute SOFT_HLUTNM of \Head[111]_i_1__3\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \Head[112]_i_1__2\ : label is "soft_lutpair559";
  attribute SOFT_HLUTNM of \Head[113]_i_1__2\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \Head[114]_i_1__2\ : label is "soft_lutpair560";
  attribute SOFT_HLUTNM of \Head[115]_i_1__2\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \Head[116]_i_1__2\ : label is "soft_lutpair561";
  attribute SOFT_HLUTNM of \Head[117]_i_1__2\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \Head[118]_i_1__2\ : label is "soft_lutpair562";
  attribute SOFT_HLUTNM of \Head[119]_i_1__2\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \Head[11]_i_1__2\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \Head[120]_i_1__0\ : label is "soft_lutpair563";
  attribute SOFT_HLUTNM of \Head[121]_i_1__0\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \Head[122]_i_1__0\ : label is "soft_lutpair564";
  attribute SOFT_HLUTNM of \Head[123]_i_1__0\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \Head[124]_i_1__0\ : label is "soft_lutpair565";
  attribute SOFT_HLUTNM of \Head[125]_i_1__0\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \Head[126]_i_1__0\ : label is "soft_lutpair566";
  attribute SOFT_HLUTNM of \Head[127]_i_1__0\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \Head[128]_i_1__0\ : label is "soft_lutpair567";
  attribute SOFT_HLUTNM of \Head[129]_i_1__0\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \Head[12]_i_1__2\ : label is "soft_lutpair509";
  attribute SOFT_HLUTNM of \Head[130]_i_1__0\ : label is "soft_lutpair568";
  attribute SOFT_HLUTNM of \Head[131]_i_1__0\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \Head[132]_i_1__0\ : label is "soft_lutpair569";
  attribute SOFT_HLUTNM of \Head[133]_i_1__0\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \Head[134]_i_1__0\ : label is "soft_lutpair570";
  attribute SOFT_HLUTNM of \Head[135]_i_1__0\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \Head[136]_i_1__0\ : label is "soft_lutpair571";
  attribute SOFT_HLUTNM of \Head[137]_i_1__0\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \Head[138]_i_1__0\ : label is "soft_lutpair572";
  attribute SOFT_HLUTNM of \Head[139]_i_1__0\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \Head[13]_i_1__2\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \Head[140]_i_1__0\ : label is "soft_lutpair573";
  attribute SOFT_HLUTNM of \Head[141]_i_1__0\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \Head[142]_i_1__0\ : label is "soft_lutpair574";
  attribute SOFT_HLUTNM of \Head[143]_i_1__0\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \Head[144]_i_1__0\ : label is "soft_lutpair575";
  attribute SOFT_HLUTNM of \Head[145]_i_1__0\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \Head[146]_i_1__0\ : label is "soft_lutpair576";
  attribute SOFT_HLUTNM of \Head[147]_i_1__0\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \Head[148]_i_1__0\ : label is "soft_lutpair577";
  attribute SOFT_HLUTNM of \Head[149]_i_1__0\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \Head[14]_i_1__2\ : label is "soft_lutpair510";
  attribute SOFT_HLUTNM of \Head[150]_i_1__0\ : label is "soft_lutpair578";
  attribute SOFT_HLUTNM of \Head[151]_i_1__0\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \Head[152]_i_1__0\ : label is "soft_lutpair579";
  attribute SOFT_HLUTNM of \Head[153]_i_1__0\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \Head[154]_i_1__0\ : label is "soft_lutpair580";
  attribute SOFT_HLUTNM of \Head[155]_i_1__0\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \Head[156]_i_1__0\ : label is "soft_lutpair581";
  attribute SOFT_HLUTNM of \Head[157]_i_1__0\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \Head[158]_i_2__0\ : label is "soft_lutpair582";
  attribute SOFT_HLUTNM of \Head[15]_i_1__2\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \Head[16]_i_1__1\ : label is "soft_lutpair511";
  attribute SOFT_HLUTNM of \Head[17]_i_1__1\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \Head[18]_i_1__2\ : label is "soft_lutpair512";
  attribute SOFT_HLUTNM of \Head[19]_i_1__2\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \Head[1]_i_1__1\ : label is "soft_lutpair504";
  attribute SOFT_HLUTNM of \Head[20]_i_1__3\ : label is "soft_lutpair513";
  attribute SOFT_HLUTNM of \Head[21]_i_1__3\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \Head[22]_i_1__2\ : label is "soft_lutpair514";
  attribute SOFT_HLUTNM of \Head[23]_i_1__2\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \Head[24]_i_1__2\ : label is "soft_lutpair515";
  attribute SOFT_HLUTNM of \Head[25]_i_1__2\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \Head[26]_i_1__2\ : label is "soft_lutpair516";
  attribute SOFT_HLUTNM of \Head[27]_i_1__2\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \Head[28]_i_1__2\ : label is "soft_lutpair517";
  attribute SOFT_HLUTNM of \Head[29]_i_1__2\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \Head[30]_i_1__1\ : label is "soft_lutpair518";
  attribute SOFT_HLUTNM of \Head[31]_i_1__1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \Head[32]_i_1__1\ : label is "soft_lutpair519";
  attribute SOFT_HLUTNM of \Head[33]_i_1__0\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \Head[34]_i_1__0\ : label is "soft_lutpair520";
  attribute SOFT_HLUTNM of \Head[35]_i_1__0\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \Head[36]_i_1__0\ : label is "soft_lutpair521";
  attribute SOFT_HLUTNM of \Head[37]_i_1__1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \Head[38]_i_1__1\ : label is "soft_lutpair522";
  attribute SOFT_HLUTNM of \Head[39]_i_1__1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \Head[3]_i_1__1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \Head[40]_i_1__1\ : label is "soft_lutpair523";
  attribute SOFT_HLUTNM of \Head[41]_i_1__0\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \Head[42]_i_1__0\ : label is "soft_lutpair524";
  attribute SOFT_HLUTNM of \Head[43]_i_1__0\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \Head[44]_i_1__0\ : label is "soft_lutpair525";
  attribute SOFT_HLUTNM of \Head[45]_i_1__0\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \Head[46]_i_1__1\ : label is "soft_lutpair526";
  attribute SOFT_HLUTNM of \Head[47]_i_1__1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \Head[48]_i_1__1\ : label is "soft_lutpair527";
  attribute SOFT_HLUTNM of \Head[49]_i_1__1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \Head[4]_i_1__1\ : label is "soft_lutpair505";
  attribute SOFT_HLUTNM of \Head[50]_i_1__1\ : label is "soft_lutpair528";
  attribute SOFT_HLUTNM of \Head[51]_i_1__1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \Head[52]_i_1__1\ : label is "soft_lutpair529";
  attribute SOFT_HLUTNM of \Head[53]_i_1__1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \Head[54]_i_1__1\ : label is "soft_lutpair530";
  attribute SOFT_HLUTNM of \Head[55]_i_1__1\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \Head[56]_i_1__2\ : label is "soft_lutpair531";
  attribute SOFT_HLUTNM of \Head[57]_i_1__2\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \Head[58]_i_1__2\ : label is "soft_lutpair532";
  attribute SOFT_HLUTNM of \Head[59]_i_1__2\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \Head[5]_i_1__1\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \Head[60]_i_1__2\ : label is "soft_lutpair533";
  attribute SOFT_HLUTNM of \Head[61]_i_1__3\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \Head[62]_i_1__3\ : label is "soft_lutpair534";
  attribute SOFT_HLUTNM of \Head[63]_i_1__3\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \Head[64]_i_1__3\ : label is "soft_lutpair535";
  attribute SOFT_HLUTNM of \Head[65]_i_1__3\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \Head[66]_i_1__3\ : label is "soft_lutpair536";
  attribute SOFT_HLUTNM of \Head[67]_i_1__3\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \Head[68]_i_1__3\ : label is "soft_lutpair537";
  attribute SOFT_HLUTNM of \Head[69]_i_1__3\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \Head[6]_i_1__0\ : label is "soft_lutpair506";
  attribute SOFT_HLUTNM of \Head[70]_i_1__3\ : label is "soft_lutpair538";
  attribute SOFT_HLUTNM of \Head[71]_i_1__3\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \Head[72]_i_1__3\ : label is "soft_lutpair539";
  attribute SOFT_HLUTNM of \Head[73]_i_1__3\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \Head[74]_i_1__3\ : label is "soft_lutpair540";
  attribute SOFT_HLUTNM of \Head[75]_i_1__3\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \Head[76]_i_1__3\ : label is "soft_lutpair541";
  attribute SOFT_HLUTNM of \Head[77]_i_1__3\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \Head[78]_i_1__3\ : label is "soft_lutpair542";
  attribute SOFT_HLUTNM of \Head[79]_i_1__3\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \Head[7]_i_1__0\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \Head[80]_i_1__3\ : label is "soft_lutpair543";
  attribute SOFT_HLUTNM of \Head[81]_i_1__3\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \Head[82]_i_1__3\ : label is "soft_lutpair544";
  attribute SOFT_HLUTNM of \Head[83]_i_1__3\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \Head[84]_i_1__3\ : label is "soft_lutpair545";
  attribute SOFT_HLUTNM of \Head[85]_i_1__3\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \Head[86]_i_1__3\ : label is "soft_lutpair546";
  attribute SOFT_HLUTNM of \Head[87]_i_1__3\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \Head[88]_i_1__3\ : label is "soft_lutpair547";
  attribute SOFT_HLUTNM of \Head[89]_i_1__3\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \Head[8]_i_1__1\ : label is "soft_lutpair507";
  attribute SOFT_HLUTNM of \Head[90]_i_1__3\ : label is "soft_lutpair548";
  attribute SOFT_HLUTNM of \Head[91]_i_1__3\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \Head[92]_i_1__3\ : label is "soft_lutpair549";
  attribute SOFT_HLUTNM of \Head[93]_i_1__3\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \Head[94]_i_1__3\ : label is "soft_lutpair550";
  attribute SOFT_HLUTNM of \Head[95]_i_1__3\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \Head[96]_i_1__3\ : label is "soft_lutpair551";
  attribute SOFT_HLUTNM of \Head[97]_i_1__3\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \Head[98]_i_1__3\ : label is "soft_lutpair552";
  attribute SOFT_HLUTNM of \Head[99]_i_1__3\ : label is "soft_lutpair553";
  attribute SOFT_HLUTNM of \Head[9]_i_1__2\ : label is "soft_lutpair508";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_7_0_5 : label is 1272;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_7_0_5 : label is 7;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_7_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_102_107 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_102_107 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_102_107 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_102_107 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_102_107 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_102_107 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_7_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_108_113 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_108_113 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_108_113 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_108_113 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_108_113 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_108_113 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_108_113 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_108_113 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_7_108_113 : label is 113;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_114_119 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_114_119 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_114_119 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_114_119 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_114_119 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_114_119 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_114_119 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_114_119 : label is 114;
  attribute ram_slice_end of MemArray_reg_0_7_114_119 : label is 119;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_120_125 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_120_125 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_120_125 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_120_125 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_120_125 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_120_125 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_120_125 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_120_125 : label is 120;
  attribute ram_slice_end of MemArray_reg_0_7_120_125 : label is 125;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_126_131 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_126_131 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_126_131 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_126_131 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_126_131 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_126_131 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_126_131 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_126_131 : label is 126;
  attribute ram_slice_end of MemArray_reg_0_7_126_131 : label is 131;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_12_17 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_12_17 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_7_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_132_137 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_132_137 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_132_137 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_132_137 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_132_137 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_132_137 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_132_137 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_132_137 : label is 132;
  attribute ram_slice_end of MemArray_reg_0_7_132_137 : label is 137;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_138_143 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_138_143 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_138_143 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_138_143 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_138_143 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_138_143 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_138_143 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_138_143 : label is 138;
  attribute ram_slice_end of MemArray_reg_0_7_138_143 : label is 143;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_144_149 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_144_149 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_144_149 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_144_149 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_144_149 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_144_149 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_144_149 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_144_149 : label is 144;
  attribute ram_slice_end of MemArray_reg_0_7_144_149 : label is 149;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_150_155 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_150_155 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_150_155 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_150_155 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_150_155 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_150_155 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_150_155 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_150_155 : label is 150;
  attribute ram_slice_end of MemArray_reg_0_7_150_155 : label is 155;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_156_158 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_156_158 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_156_158 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_156_158 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_156_158 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_156_158 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_156_158 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_156_158 : label is 156;
  attribute ram_slice_end of MemArray_reg_0_7_156_158 : label is 158;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_18_23 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_18_23 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_7_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_24_29 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_24_29 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_7_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_30_35 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_30_35 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_7_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_36_41 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_36_41 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_7_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_42_47 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_42_47 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_7_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_48_53 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_48_53 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_7_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_54_59 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_54_59 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_7_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_60_65 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_60_65 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_7_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_66_71 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_66_71 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_7_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_6_11 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_6_11 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_7_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_72_77 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_72_77 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_7_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_78_83 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_78_83 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_7_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_84_89 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_84_89 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_7_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_90_95 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_90_95 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_7_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_96_101 : label is 1272;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_96_101 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_7_96_101 : label is 101;
  attribute SOFT_HLUTNM of \RdPtr[2]_i_4__0\ : label is "soft_lutpair503";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[11]_i_1__0\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[12]_i_1__0\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[3]_i_1__0\ : label is 35;
  attribute ADDER_THRESHOLD of \dsc_mrs_dst_nn1_reg[7]_i_1__0\ : label is 35;
begin
  \FifoCntrRd_reg[1]_0\(1 downto 0) <= \^fifocntrrd_reg[1]_0\(1 downto 0);
  \FifoCntrWr_reg[1]_0\(1 downto 0) <= \^fifocntrwr_reg[1]_0\(1 downto 0);
  \Head_reg[158]_0\(157 downto 0) <= \^head_reg[158]_0\(157 downto 0);
  \WrPtr_reg[1]_0\(1 downto 0) <= \^wrptr_reg[1]_0\(1 downto 0);
\FifoCntrRd[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_0\(0),
      O => \FifoCntrRd[0]_i_1__3_n_0\
    );
\FifoCntrRd[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAA9555"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => \FifoCntrRd_reg[2]_0\(0),
      I2 => dsc_acc_mgc_nn1,
      I3 => dsc_acc_done_nn1,
      I4 => \^fifocntrrd_reg[1]_0\(1),
      I5 => \^fifocntrrd_reg[1]_0\(0),
      O => \FifoCntrRd[2]_i_1__2_n_0\
    );
\FifoCntrRd[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => dsc_ch_vld(0),
      I2 => \^fifocntrrd_reg[1]_0\(1),
      I3 => \^fifocntrrd_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrRd[3]_i_2__0_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[0]_i_1__3_n_0\,
      Q => \^fifocntrrd_reg[1]_0\(0),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd_reg[1]_1\(0),
      Q => \^fifocntrrd_reg[1]_0\(1),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[2]_i_1__2_n_0\,
      Q => FifoCntrRd_reg(2),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrRd_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd_reg[3]_0\(0),
      D => \FifoCntrRd[3]_i_2__0_n_0\,
      Q => FifoCntrRd_reg(3),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrWr[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[0]_i_1__3_n_0\
    );
\FifoCntrWr[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AA9"
    )
        port map (
      I0 => FifoCntrWr_reg(2),
      I1 => dsc_ch_evld(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[2]_i_1__3_n_0\
    );
\FifoCntrWr[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrWr_reg(3),
      I1 => dsc_ch_evld(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrWr_reg(2),
      O => \FifoCntrWr[3]_i_2__0_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[0]_i_1__3_n_0\,
      Q => \^fifocntrwr_reg[1]_0\(0),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr_reg[1]_1\(0),
      Q => \^fifocntrwr_reg[1]_0\(1),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[2]_i_1__3_n_0\,
      Q => FifoCntrWr_reg(2),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\FifoCntrWr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[3]_0\(0),
      D => \FifoCntrWr[3]_i_2__0_n_0\,
      Q => FifoCntrWr_reg(3),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head1,
      I2 => Head0(0),
      O => p_0_in1_in(0)
    );
\Head[100]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(100),
      I1 => Head1,
      I2 => Head0(100),
      O => p_0_in1_in(100)
    );
\Head[101]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(101),
      I1 => Head1,
      I2 => Head0(101),
      O => p_0_in1_in(101)
    );
\Head[102]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(102),
      I1 => Head1,
      I2 => Head0(102),
      O => p_0_in1_in(102)
    );
\Head[103]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(103),
      I1 => Head1,
      I2 => Head0(103),
      O => p_0_in1_in(103)
    );
\Head[104]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(104),
      I1 => Head1,
      I2 => Head0(104),
      O => p_0_in1_in(104)
    );
\Head[105]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(105),
      I1 => Head1,
      I2 => Head0(105),
      O => p_0_in1_in(105)
    );
\Head[106]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(106),
      I1 => Head1,
      I2 => Head0(106),
      O => p_0_in1_in(106)
    );
\Head[107]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(107),
      I1 => Head1,
      I2 => Head0(107),
      O => p_0_in1_in(107)
    );
\Head[108]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(108),
      I1 => Head1,
      I2 => Head0(108),
      O => p_0_in1_in(108)
    );
\Head[109]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(109),
      I1 => Head1,
      I2 => Head0(109),
      O => p_0_in1_in(109)
    );
\Head[10]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head1,
      I2 => Head0(10),
      O => p_0_in1_in(10)
    );
\Head[110]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(110),
      I1 => Head1,
      I2 => Head0(110),
      O => p_0_in1_in(110)
    );
\Head[111]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(111),
      I1 => Head1,
      I2 => Head0(111),
      O => p_0_in1_in(111)
    );
\Head[112]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(112),
      I1 => Head1,
      I2 => Head0(112),
      O => p_0_in1_in(112)
    );
\Head[113]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(113),
      I1 => Head1,
      I2 => Head0(113),
      O => p_0_in1_in(113)
    );
\Head[114]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(114),
      I1 => Head1,
      I2 => Head0(114),
      O => p_0_in1_in(114)
    );
\Head[115]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(115),
      I1 => Head1,
      I2 => Head0(115),
      O => p_0_in1_in(115)
    );
\Head[116]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(116),
      I1 => Head1,
      I2 => Head0(116),
      O => p_0_in1_in(116)
    );
\Head[117]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(117),
      I1 => Head1,
      I2 => Head0(117),
      O => p_0_in1_in(117)
    );
\Head[118]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(118),
      I1 => Head1,
      I2 => Head0(118),
      O => p_0_in1_in(118)
    );
\Head[119]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(119),
      I1 => Head1,
      I2 => Head0(119),
      O => p_0_in1_in(119)
    );
\Head[11]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head1,
      I2 => Head0(11),
      O => p_0_in1_in(11)
    );
\Head[120]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(120),
      I1 => Head1,
      I2 => Head0(120),
      O => p_0_in1_in(120)
    );
\Head[121]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(121),
      I1 => Head1,
      I2 => Head0(121),
      O => p_0_in1_in(121)
    );
\Head[122]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(122),
      I1 => Head1,
      I2 => Head0(122),
      O => p_0_in1_in(122)
    );
\Head[123]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(123),
      I1 => Head1,
      I2 => Head0(123),
      O => p_0_in1_in(123)
    );
\Head[124]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(124),
      I1 => Head1,
      I2 => Head0(124),
      O => p_0_in1_in(124)
    );
\Head[125]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(125),
      I1 => Head1,
      I2 => Head0(125),
      O => p_0_in1_in(125)
    );
\Head[126]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(126),
      I1 => Head1,
      I2 => Head0(126),
      O => p_0_in1_in(126)
    );
\Head[127]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(127),
      I1 => Head1,
      I2 => Head0(127),
      O => p_0_in1_in(127)
    );
\Head[128]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(128),
      I1 => Head1,
      I2 => Head0(128),
      O => p_0_in1_in(128)
    );
\Head[129]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(129),
      I1 => Head1,
      I2 => Head0(129),
      O => p_0_in1_in(129)
    );
\Head[12]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head1,
      I2 => Head0(12),
      O => p_0_in1_in(12)
    );
\Head[130]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(130),
      I1 => Head1,
      I2 => Head0(130),
      O => p_0_in1_in(130)
    );
\Head[131]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(131),
      I1 => Head1,
      I2 => Head0(131),
      O => p_0_in1_in(131)
    );
\Head[132]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(132),
      I1 => Head1,
      I2 => Head0(132),
      O => p_0_in1_in(132)
    );
\Head[133]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(133),
      I1 => Head1,
      I2 => Head0(133),
      O => p_0_in1_in(133)
    );
\Head[134]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(134),
      I1 => Head1,
      I2 => Head0(134),
      O => p_0_in1_in(134)
    );
\Head[135]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(135),
      I1 => Head1,
      I2 => Head0(135),
      O => p_0_in1_in(135)
    );
\Head[136]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(136),
      I1 => Head1,
      I2 => Head0(136),
      O => p_0_in1_in(136)
    );
\Head[137]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(137),
      I1 => Head1,
      I2 => Head0(137),
      O => p_0_in1_in(137)
    );
\Head[138]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(138),
      I1 => Head1,
      I2 => Head0(138),
      O => p_0_in1_in(138)
    );
\Head[139]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(139),
      I1 => Head1,
      I2 => Head0(139),
      O => p_0_in1_in(139)
    );
\Head[13]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head1,
      I2 => Head0(13),
      O => p_0_in1_in(13)
    );
\Head[140]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(140),
      I1 => Head1,
      I2 => Head0(140),
      O => p_0_in1_in(140)
    );
\Head[141]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(141),
      I1 => Head1,
      I2 => Head0(141),
      O => p_0_in1_in(141)
    );
\Head[142]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(142),
      I1 => Head1,
      I2 => Head0(142),
      O => p_0_in1_in(142)
    );
\Head[143]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(143),
      I1 => Head1,
      I2 => Head0(143),
      O => p_0_in1_in(143)
    );
\Head[144]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(144),
      I1 => Head1,
      I2 => Head0(144),
      O => p_0_in1_in(144)
    );
\Head[145]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(145),
      I1 => Head1,
      I2 => Head0(145),
      O => p_0_in1_in(145)
    );
\Head[146]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(146),
      I1 => Head1,
      I2 => Head0(146),
      O => p_0_in1_in(146)
    );
\Head[147]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(147),
      I1 => Head1,
      I2 => Head0(147),
      O => p_0_in1_in(147)
    );
\Head[148]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(148),
      I1 => Head1,
      I2 => Head0(148),
      O => p_0_in1_in(148)
    );
\Head[149]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(149),
      I1 => Head1,
      I2 => Head0(149),
      O => p_0_in1_in(149)
    );
\Head[14]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head1,
      I2 => Head0(14),
      O => p_0_in1_in(14)
    );
\Head[150]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(150),
      I1 => Head1,
      I2 => Head0(150),
      O => p_0_in1_in(150)
    );
\Head[151]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(151),
      I1 => Head1,
      I2 => Head0(151),
      O => p_0_in1_in(151)
    );
\Head[152]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(152),
      I1 => Head1,
      I2 => Head0(152),
      O => p_0_in1_in(152)
    );
\Head[153]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(153),
      I1 => Head1,
      I2 => Head0(153),
      O => p_0_in1_in(153)
    );
\Head[154]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(154),
      I1 => Head1,
      I2 => Head0(154),
      O => p_0_in1_in(154)
    );
\Head[155]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(155),
      I1 => Head1,
      I2 => Head0(155),
      O => p_0_in1_in(155)
    );
\Head[156]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(156),
      I1 => Head1,
      I2 => Head0(156),
      O => p_0_in1_in(156)
    );
\Head[157]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(157),
      I1 => Head1,
      I2 => Head0(157),
      O => p_0_in1_in(157)
    );
\Head[158]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEEEEEEEEEEEF"
    )
        port map (
      I0 => empty_ff_reg_0,
      I1 => Head1,
      I2 => \^fifocntrrd_reg[1]_0\(0),
      I3 => FifoCntrRd_reg(3),
      I4 => FifoCntrRd_reg(2),
      I5 => \^fifocntrrd_reg[1]_0\(1),
      O => \Head[158]_i_1__0_n_0\
    );
\Head[158]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(158),
      I1 => Head1,
      I2 => Head0(158),
      O => p_0_in1_in(158)
    );
\Head[15]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head1,
      I2 => Head0(15),
      O => p_0_in1_in(15)
    );
\Head[16]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head1,
      I2 => Head0(16),
      O => p_0_in1_in(16)
    );
\Head[17]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head1,
      I2 => Head0(17),
      O => p_0_in1_in(17)
    );
\Head[18]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head1,
      I2 => Head0(18),
      O => p_0_in1_in(18)
    );
\Head[19]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head1,
      I2 => Head0(19),
      O => p_0_in1_in(19)
    );
\Head[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head1,
      I2 => Head0(1),
      O => p_0_in1_in(1)
    );
\Head[20]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head1,
      I2 => Head0(20),
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head1,
      I2 => Head0(21),
      O => p_0_in1_in(21)
    );
\Head[22]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head1,
      I2 => Head0(22),
      O => p_0_in1_in(22)
    );
\Head[23]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head1,
      I2 => Head0(23),
      O => p_0_in1_in(23)
    );
\Head[24]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head1,
      I2 => Head0(24),
      O => p_0_in1_in(24)
    );
\Head[25]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head1,
      I2 => Head0(25),
      O => p_0_in1_in(25)
    );
\Head[26]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head1,
      I2 => Head0(26),
      O => p_0_in1_in(26)
    );
\Head[27]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head1,
      I2 => Head0(27),
      O => p_0_in1_in(27)
    );
\Head[28]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head1,
      I2 => Head0(28),
      O => p_0_in1_in(28)
    );
\Head[29]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head1,
      I2 => Head0(29),
      O => p_0_in1_in(29)
    );
\Head[30]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head1,
      I2 => Head0(30),
      O => p_0_in1_in(30)
    );
\Head[31]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head1,
      I2 => Head0(31),
      O => p_0_in1_in(31)
    );
\Head[32]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head1,
      I2 => Head0(32),
      O => p_0_in1_in(32)
    );
\Head[33]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head1,
      I2 => Head0(33),
      O => p_0_in1_in(33)
    );
\Head[34]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head1,
      I2 => Head0(34),
      O => p_0_in1_in(34)
    );
\Head[35]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head1,
      I2 => Head0(35),
      O => p_0_in1_in(35)
    );
\Head[36]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head1,
      I2 => Head0(36),
      O => p_0_in1_in(36)
    );
\Head[37]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head1,
      I2 => Head0(37),
      O => p_0_in1_in(37)
    );
\Head[38]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head1,
      I2 => Head0(38),
      O => p_0_in1_in(38)
    );
\Head[39]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head1,
      I2 => Head0(39),
      O => p_0_in1_in(39)
    );
\Head[3]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head1,
      I2 => Head0(3),
      O => p_0_in1_in(3)
    );
\Head[40]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head1,
      I2 => Head0(40),
      O => p_0_in1_in(40)
    );
\Head[41]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head1,
      I2 => Head0(41),
      O => p_0_in1_in(41)
    );
\Head[42]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head1,
      I2 => Head0(42),
      O => p_0_in1_in(42)
    );
\Head[43]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head1,
      I2 => Head0(43),
      O => p_0_in1_in(43)
    );
\Head[44]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head1,
      I2 => Head0(44),
      O => p_0_in1_in(44)
    );
\Head[45]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head1,
      I2 => Head0(45),
      O => p_0_in1_in(45)
    );
\Head[46]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head1,
      I2 => Head0(46),
      O => p_0_in1_in(46)
    );
\Head[47]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head1,
      I2 => Head0(47),
      O => p_0_in1_in(47)
    );
\Head[48]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head1,
      I2 => Head0(48),
      O => p_0_in1_in(48)
    );
\Head[49]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head1,
      I2 => Head0(49),
      O => p_0_in1_in(49)
    );
\Head[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head1,
      I2 => Head0(4),
      O => p_0_in1_in(4)
    );
\Head[50]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head1,
      I2 => Head0(50),
      O => p_0_in1_in(50)
    );
\Head[51]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head1,
      I2 => Head0(51),
      O => p_0_in1_in(51)
    );
\Head[52]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head1,
      I2 => Head0(52),
      O => p_0_in1_in(52)
    );
\Head[53]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head1,
      I2 => Head0(53),
      O => p_0_in1_in(53)
    );
\Head[54]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head1,
      I2 => Head0(54),
      O => p_0_in1_in(54)
    );
\Head[55]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head1,
      I2 => Head0(55),
      O => p_0_in1_in(55)
    );
\Head[56]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head1,
      I2 => Head0(56),
      O => p_0_in1_in(56)
    );
\Head[57]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head1,
      I2 => Head0(57),
      O => p_0_in1_in(57)
    );
\Head[58]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head1,
      I2 => Head0(58),
      O => p_0_in1_in(58)
    );
\Head[59]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head1,
      I2 => Head0(59),
      O => p_0_in1_in(59)
    );
\Head[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head1,
      I2 => Head0(5),
      O => p_0_in1_in(5)
    );
\Head[60]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head1,
      I2 => Head0(60),
      O => p_0_in1_in(60)
    );
\Head[61]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head1,
      I2 => Head0(61),
      O => p_0_in1_in(61)
    );
\Head[62]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head1,
      I2 => Head0(62),
      O => p_0_in1_in(62)
    );
\Head[63]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head1,
      I2 => Head0(63),
      O => p_0_in1_in(63)
    );
\Head[64]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head1,
      I2 => Head0(64),
      O => p_0_in1_in(64)
    );
\Head[65]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head1,
      I2 => Head0(65),
      O => p_0_in1_in(65)
    );
\Head[66]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head1,
      I2 => Head0(66),
      O => p_0_in1_in(66)
    );
\Head[67]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head1,
      I2 => Head0(67),
      O => p_0_in1_in(67)
    );
\Head[68]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head1,
      I2 => Head0(68),
      O => p_0_in1_in(68)
    );
\Head[69]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head1,
      I2 => Head0(69),
      O => p_0_in1_in(69)
    );
\Head[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head1,
      I2 => Head0(6),
      O => p_0_in1_in(6)
    );
\Head[70]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head1,
      I2 => Head0(70),
      O => p_0_in1_in(70)
    );
\Head[71]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head1,
      I2 => Head0(71),
      O => p_0_in1_in(71)
    );
\Head[72]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head1,
      I2 => Head0(72),
      O => p_0_in1_in(72)
    );
\Head[73]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head1,
      I2 => Head0(73),
      O => p_0_in1_in(73)
    );
\Head[74]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head1,
      I2 => Head0(74),
      O => p_0_in1_in(74)
    );
\Head[75]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head1,
      I2 => Head0(75),
      O => p_0_in1_in(75)
    );
\Head[76]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head1,
      I2 => Head0(76),
      O => p_0_in1_in(76)
    );
\Head[77]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head1,
      I2 => Head0(77),
      O => p_0_in1_in(77)
    );
\Head[78]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head1,
      I2 => Head0(78),
      O => p_0_in1_in(78)
    );
\Head[79]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head1,
      I2 => Head0(79),
      O => p_0_in1_in(79)
    );
\Head[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head1,
      I2 => Head0(7),
      O => p_0_in1_in(7)
    );
\Head[80]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head1,
      I2 => Head0(80),
      O => p_0_in1_in(80)
    );
\Head[81]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(81),
      I1 => Head1,
      I2 => Head0(81),
      O => p_0_in1_in(81)
    );
\Head[82]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(82),
      I1 => Head1,
      I2 => Head0(82),
      O => p_0_in1_in(82)
    );
\Head[83]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(83),
      I1 => Head1,
      I2 => Head0(83),
      O => p_0_in1_in(83)
    );
\Head[84]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(84),
      I1 => Head1,
      I2 => Head0(84),
      O => p_0_in1_in(84)
    );
\Head[85]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(85),
      I1 => Head1,
      I2 => Head0(85),
      O => p_0_in1_in(85)
    );
\Head[86]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(86),
      I1 => Head1,
      I2 => Head0(86),
      O => p_0_in1_in(86)
    );
\Head[87]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(87),
      I1 => Head1,
      I2 => Head0(87),
      O => p_0_in1_in(87)
    );
\Head[88]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(88),
      I1 => Head1,
      I2 => Head0(88),
      O => p_0_in1_in(88)
    );
\Head[89]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(89),
      I1 => Head1,
      I2 => Head0(89),
      O => p_0_in1_in(89)
    );
\Head[8]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head1,
      I2 => Head0(8),
      O => p_0_in1_in(8)
    );
\Head[90]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(90),
      I1 => Head1,
      I2 => Head0(90),
      O => p_0_in1_in(90)
    );
\Head[91]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(91),
      I1 => Head1,
      I2 => Head0(91),
      O => p_0_in1_in(91)
    );
\Head[92]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(92),
      I1 => Head1,
      I2 => Head0(92),
      O => p_0_in1_in(92)
    );
\Head[93]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(93),
      I1 => Head1,
      I2 => Head0(93),
      O => p_0_in1_in(93)
    );
\Head[94]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(94),
      I1 => Head1,
      I2 => Head0(94),
      O => p_0_in1_in(94)
    );
\Head[95]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(95),
      I1 => Head1,
      I2 => Head0(95),
      O => p_0_in1_in(95)
    );
\Head[96]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(96),
      I1 => Head1,
      I2 => Head0(96),
      O => p_0_in1_in(96)
    );
\Head[97]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(97),
      I1 => Head1,
      I2 => Head0(97),
      O => p_0_in1_in(97)
    );
\Head[98]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(98),
      I1 => Head1,
      I2 => Head0(98),
      O => p_0_in1_in(98)
    );
\Head[99]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(99),
      I1 => Head1,
      I2 => Head0(99),
      O => p_0_in1_in(99)
    );
\Head[9]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head1,
      I2 => Head0(9),
      O => p_0_in1_in(9)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(0),
      Q => \^head_reg[158]_0\(0),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(100),
      Q => \^head_reg[158]_0\(99),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(101),
      Q => \^head_reg[158]_0\(100),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(102),
      Q => \^head_reg[158]_0\(101),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(103),
      Q => \^head_reg[158]_0\(102),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(104),
      Q => \^head_reg[158]_0\(103),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(105),
      Q => \^head_reg[158]_0\(104),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(106),
      Q => \^head_reg[158]_0\(105),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(107),
      Q => \^head_reg[158]_0\(106),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(108),
      Q => \^head_reg[158]_0\(107),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(109),
      Q => \^head_reg[158]_0\(108),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(10),
      Q => \^head_reg[158]_0\(9),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(110),
      Q => \^head_reg[158]_0\(109),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(111),
      Q => \^head_reg[158]_0\(110),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[112]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(112),
      Q => \^head_reg[158]_0\(111),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[113]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(113),
      Q => \^head_reg[158]_0\(112),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[114]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(114),
      Q => \^head_reg[158]_0\(113),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[115]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(115),
      Q => \^head_reg[158]_0\(114),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[116]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(116),
      Q => \^head_reg[158]_0\(115),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[117]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(117),
      Q => \^head_reg[158]_0\(116),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[118]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(118),
      Q => \^head_reg[158]_0\(117),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[119]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(119),
      Q => \^head_reg[158]_0\(118),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(11),
      Q => \^head_reg[158]_0\(10),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[120]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(120),
      Q => \^head_reg[158]_0\(119),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[121]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(121),
      Q => \^head_reg[158]_0\(120),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[122]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(122),
      Q => \^head_reg[158]_0\(121),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[123]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(123),
      Q => \^head_reg[158]_0\(122),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[124]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(124),
      Q => \^head_reg[158]_0\(123),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[125]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(125),
      Q => \^head_reg[158]_0\(124),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[126]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(126),
      Q => \^head_reg[158]_0\(125),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[127]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(127),
      Q => \^head_reg[158]_0\(126),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[128]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(128),
      Q => \^head_reg[158]_0\(127),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[129]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(129),
      Q => \^head_reg[158]_0\(128),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(12),
      Q => \^head_reg[158]_0\(11),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[130]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(130),
      Q => \^head_reg[158]_0\(129),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[131]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(131),
      Q => \^head_reg[158]_0\(130),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(132),
      Q => \^head_reg[158]_0\(131),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(133),
      Q => \^head_reg[158]_0\(132),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(134),
      Q => \^head_reg[158]_0\(133),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(135),
      Q => \^head_reg[158]_0\(134),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(136),
      Q => \^head_reg[158]_0\(135),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(137),
      Q => \^head_reg[158]_0\(136),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(138),
      Q => \^head_reg[158]_0\(137),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(139),
      Q => \^head_reg[158]_0\(138),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(13),
      Q => \^head_reg[158]_0\(12),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(140),
      Q => \^head_reg[158]_0\(139),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(141),
      Q => \^head_reg[158]_0\(140),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(142),
      Q => \^head_reg[158]_0\(141),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(143),
      Q => \^head_reg[158]_0\(142),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(144),
      Q => \^head_reg[158]_0\(143),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(145),
      Q => \^head_reg[158]_0\(144),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(146),
      Q => \^head_reg[158]_0\(145),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(147),
      Q => \^head_reg[158]_0\(146),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(148),
      Q => \^head_reg[158]_0\(147),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(149),
      Q => \^head_reg[158]_0\(148),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(14),
      Q => \^head_reg[158]_0\(13),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(150),
      Q => \^head_reg[158]_0\(149),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(151),
      Q => \^head_reg[158]_0\(150),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(152),
      Q => \^head_reg[158]_0\(151),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(153),
      Q => \^head_reg[158]_0\(152),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(154),
      Q => \^head_reg[158]_0\(153),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(155),
      Q => \^head_reg[158]_0\(154),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(156),
      Q => \^head_reg[158]_0\(155),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(157),
      Q => \^head_reg[158]_0\(156),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(158),
      Q => \^head_reg[158]_0\(157),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(15),
      Q => \^head_reg[158]_0\(14),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(16),
      Q => \^head_reg[158]_0\(15),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(17),
      Q => \^head_reg[158]_0\(16),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(18),
      Q => \^head_reg[158]_0\(17),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(19),
      Q => \^head_reg[158]_0\(18),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(1),
      Q => \^head_reg[158]_0\(1),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(20),
      Q => \^head_reg[158]_0\(19),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(21),
      Q => \^head_reg[158]_0\(20),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(22),
      Q => \^head_reg[158]_0\(21),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(23),
      Q => \^head_reg[158]_0\(22),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(24),
      Q => \^head_reg[158]_0\(23),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(25),
      Q => \^head_reg[158]_0\(24),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(26),
      Q => \^head_reg[158]_0\(25),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(27),
      Q => \^head_reg[158]_0\(26),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(28),
      Q => \^head_reg[158]_0\(27),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(29),
      Q => \^head_reg[158]_0\(28),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(30),
      Q => \^head_reg[158]_0\(29),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(31),
      Q => \^head_reg[158]_0\(30),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(32),
      Q => \^head_reg[158]_0\(31),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(33),
      Q => \^head_reg[158]_0\(32),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(34),
      Q => \^head_reg[158]_0\(33),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(35),
      Q => \^head_reg[158]_0\(34),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(36),
      Q => \^head_reg[158]_0\(35),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(37),
      Q => \^head_reg[158]_0\(36),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(38),
      Q => \^head_reg[158]_0\(37),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(39),
      Q => \^head_reg[158]_0\(38),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(3),
      Q => \^head_reg[158]_0\(2),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(40),
      Q => \^head_reg[158]_0\(39),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(41),
      Q => \^head_reg[158]_0\(40),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(42),
      Q => \^head_reg[158]_0\(41),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(43),
      Q => \^head_reg[158]_0\(42),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(44),
      Q => \^head_reg[158]_0\(43),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(45),
      Q => \^head_reg[158]_0\(44),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(46),
      Q => \^head_reg[158]_0\(45),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(47),
      Q => \^head_reg[158]_0\(46),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(48),
      Q => \^head_reg[158]_0\(47),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(49),
      Q => \^head_reg[158]_0\(48),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(4),
      Q => \^head_reg[158]_0\(3),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(50),
      Q => \^head_reg[158]_0\(49),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(51),
      Q => \^head_reg[158]_0\(50),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(52),
      Q => \^head_reg[158]_0\(51),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(53),
      Q => \^head_reg[158]_0\(52),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(54),
      Q => \^head_reg[158]_0\(53),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(55),
      Q => \^head_reg[158]_0\(54),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(56),
      Q => \^head_reg[158]_0\(55),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(57),
      Q => \^head_reg[158]_0\(56),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(58),
      Q => \^head_reg[158]_0\(57),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(59),
      Q => \^head_reg[158]_0\(58),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(5),
      Q => \^head_reg[158]_0\(4),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(60),
      Q => \^head_reg[158]_0\(59),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(61),
      Q => \^head_reg[158]_0\(60),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(62),
      Q => \^head_reg[158]_0\(61),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(63),
      Q => \^head_reg[158]_0\(62),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(64),
      Q => \^head_reg[158]_0\(63),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(65),
      Q => \^head_reg[158]_0\(64),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(66),
      Q => \^head_reg[158]_0\(65),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(67),
      Q => \^head_reg[158]_0\(66),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(68),
      Q => \^head_reg[158]_0\(67),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(69),
      Q => \^head_reg[158]_0\(68),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(6),
      Q => \^head_reg[158]_0\(5),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(70),
      Q => \^head_reg[158]_0\(69),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(71),
      Q => \^head_reg[158]_0\(70),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(72),
      Q => \^head_reg[158]_0\(71),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(73),
      Q => \^head_reg[158]_0\(72),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(74),
      Q => \^head_reg[158]_0\(73),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(75),
      Q => \^head_reg[158]_0\(74),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(76),
      Q => \^head_reg[158]_0\(75),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(77),
      Q => \^head_reg[158]_0\(76),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(78),
      Q => \^head_reg[158]_0\(77),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(79),
      Q => \^head_reg[158]_0\(78),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(7),
      Q => \^head_reg[158]_0\(6),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(80),
      Q => \^head_reg[158]_0\(79),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(81),
      Q => \^head_reg[158]_0\(80),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(82),
      Q => \^head_reg[158]_0\(81),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(83),
      Q => \^head_reg[158]_0\(82),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(84),
      Q => \^head_reg[158]_0\(83),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(85),
      Q => \^head_reg[158]_0\(84),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(86),
      Q => \^head_reg[158]_0\(85),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(87),
      Q => \^head_reg[158]_0\(86),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(88),
      Q => \^head_reg[158]_0\(87),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(89),
      Q => \^head_reg[158]_0\(88),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(8),
      Q => \^head_reg[158]_0\(7),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(90),
      Q => \^head_reg[158]_0\(89),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(91),
      Q => \^head_reg[158]_0\(90),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(92),
      Q => \^head_reg[158]_0\(91),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(93),
      Q => \^head_reg[158]_0\(92),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(94),
      Q => \^head_reg[158]_0\(93),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(95),
      Q => \^head_reg[158]_0\(94),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(96),
      Q => \^head_reg[158]_0\(95),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(97),
      Q => \^head_reg[158]_0\(96),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(98),
      Q => \^head_reg[158]_0\(97),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(99),
      Q => \^head_reg[158]_0\(98),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[158]_i_1__0_n_0\,
      D => p_0_in1_in(9),
      Q => \^head_reg[158]_0\(8),
      R => \RdPtr[2]_i_1__0_n_0\
    );
MemArray_reg_0_7_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(1 downto 0),
      DOB(1) => Head0(3),
      DOB(0) => MemArray_reg_0_7_0_5_n_3,
      DOC(1 downto 0) => Head0(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(103 downto 102),
      DIB(1 downto 0) => DataIn(105 downto 104),
      DIC(1 downto 0) => DataIn(107 downto 106),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_108_113: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(109 downto 108),
      DIB(1 downto 0) => DataIn(111 downto 110),
      DIC(1 downto 0) => DataIn(113 downto 112),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => Head0(113 downto 112),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_114_119: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(115 downto 114),
      DIB(1 downto 0) => DataIn(117 downto 116),
      DIC(1 downto 0) => DataIn(119 downto 118),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(115 downto 114),
      DOB(1 downto 0) => Head0(117 downto 116),
      DOC(1 downto 0) => Head0(119 downto 118),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_120_125: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(121 downto 120),
      DIB(1 downto 0) => DataIn(123 downto 122),
      DIC(1 downto 0) => DataIn(125 downto 124),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(121 downto 120),
      DOB(1 downto 0) => Head0(123 downto 122),
      DOC(1 downto 0) => Head0(125 downto 124),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_126_131: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(127 downto 126),
      DIB(1 downto 0) => DataIn(129 downto 128),
      DIC(1 downto 0) => DataIn(131 downto 130),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(127 downto 126),
      DOB(1 downto 0) => Head0(129 downto 128),
      DOC(1 downto 0) => Head0(131 downto 130),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(13 downto 12),
      DIB(1 downto 0) => DataIn(15 downto 14),
      DIC(1 downto 0) => DataIn(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => Head0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_132_137: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(133 downto 132),
      DIB(1 downto 0) => DataIn(135 downto 134),
      DIC(1 downto 0) => DataIn(137 downto 136),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(133 downto 132),
      DOB(1 downto 0) => Head0(135 downto 134),
      DOC(1 downto 0) => Head0(137 downto 136),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_138_143: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(139 downto 138),
      DIB(1 downto 0) => DataIn(141 downto 140),
      DIC(1 downto 0) => DataIn(143 downto 142),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(139 downto 138),
      DOB(1 downto 0) => Head0(141 downto 140),
      DOC(1 downto 0) => Head0(143 downto 142),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_144_149: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(145 downto 144),
      DIB(1 downto 0) => DataIn(147 downto 146),
      DIC(1 downto 0) => DataIn(149 downto 148),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(145 downto 144),
      DOB(1 downto 0) => Head0(147 downto 146),
      DOC(1 downto 0) => Head0(149 downto 148),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_150_155: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(151 downto 150),
      DIB(1 downto 0) => DataIn(153 downto 152),
      DIC(1 downto 0) => DataIn(155 downto 154),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(151 downto 150),
      DOB(1 downto 0) => Head0(153 downto 152),
      DOC(1 downto 0) => Head0(155 downto 154),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_156_158: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(157 downto 156),
      DIB(1) => '0',
      DIB(0) => DataIn(158),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(157 downto 156),
      DOB(1) => NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED(1),
      DOB(0) => Head0(158),
      DOC(1 downto 0) => NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(19 downto 18),
      DIB(1 downto 0) => DataIn(21 downto 20),
      DIC(1 downto 0) => DataIn(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => Head0(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(25 downto 24),
      DIB(1 downto 0) => DataIn(27 downto 26),
      DIC(1 downto 0) => DataIn(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(25 downto 24),
      DOB(1 downto 0) => Head0(27 downto 26),
      DOC(1 downto 0) => Head0(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(31 downto 30),
      DIB(1 downto 0) => DataIn(33 downto 32),
      DIC(1 downto 0) => DataIn(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(31 downto 30),
      DOB(1 downto 0) => Head0(33 downto 32),
      DOC(1 downto 0) => Head0(35 downto 34),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(37 downto 36),
      DIB(1 downto 0) => DataIn(39 downto 38),
      DIC(1 downto 0) => DataIn(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(37 downto 36),
      DOB(1 downto 0) => Head0(39 downto 38),
      DOC(1 downto 0) => Head0(41 downto 40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(43 downto 42),
      DIB(1 downto 0) => DataIn(45 downto 44),
      DIC(1 downto 0) => DataIn(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(43 downto 42),
      DOB(1 downto 0) => Head0(45 downto 44),
      DOC(1 downto 0) => Head0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(49 downto 48),
      DIB(1 downto 0) => DataIn(51 downto 50),
      DIC(1 downto 0) => DataIn(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(49 downto 48),
      DOB(1 downto 0) => Head0(51 downto 50),
      DOC(1 downto 0) => Head0(53 downto 52),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(55 downto 54),
      DIB(1 downto 0) => DataIn(57 downto 56),
      DIC(1 downto 0) => DataIn(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(55 downto 54),
      DOB(1 downto 0) => Head0(57 downto 56),
      DOC(1 downto 0) => Head0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(61 downto 60),
      DIB(1 downto 0) => DataIn(63 downto 62),
      DIC(1 downto 0) => DataIn(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(67 downto 66),
      DIB(1 downto 0) => DataIn(69 downto 68),
      DIC(1 downto 0) => DataIn(71 downto 70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(7 downto 6),
      DIB(1 downto 0) => DataIn(9 downto 8),
      DIC(1 downto 0) => DataIn(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(7 downto 6),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(73 downto 72),
      DIB(1 downto 0) => DataIn(75 downto 74),
      DIC(1 downto 0) => DataIn(77 downto 76),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(79 downto 78),
      DIB(1 downto 0) => DataIn(81 downto 80),
      DIC(1 downto 0) => DataIn(83 downto 82),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(85 downto 84),
      DIB(1 downto 0) => DataIn(87 downto 86),
      DIC(1 downto 0) => DataIn(89 downto 88),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(91 downto 90),
      DIB(1 downto 0) => DataIn(93 downto 92),
      DIC(1 downto 0) => DataIn(95 downto 94),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
MemArray_reg_0_7_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2) => WrPtr(2),
      ADDRD(1 downto 0) => \^wrptr_reg[1]_0\(1 downto 0),
      DIA(1 downto 0) => DataIn(97 downto 96),
      DIB(1 downto 0) => DataIn(99 downto 98),
      DIC(1 downto 0) => DataIn(101 downto 100),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => dsc_ch_vld(0)
    );
\RdPtr[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5656565656565666"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => empty_ff_reg_0,
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"557FAA80"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \RdPtr[2]_i_4__0_n_0\,
      I2 => empty_ff_reg_0,
      I3 => Head1,
      I4 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \rrq_dsc_ld_901_reg_rep__2\,
      I1 => evt_idl_stp_vld_nn1,
      I2 => ctl_rst,
      O => \RdPtr[2]_i_1__0_n_0\
    );
\RdPtr[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5777FFFFA8880000"
    )
        port map (
      I0 => RdPtr(1),
      I1 => Head1,
      I2 => empty_ff_reg_0,
      I3 => \RdPtr[2]_i_4__0_n_0\,
      I4 => RdPtr(0),
      I5 => RdPtr(2),
      O => \RdPtr__0\(2)
    );
\RdPtr[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000008A"
    )
        port map (
      I0 => dsc_ch_vld(0),
      I1 => empty_ff_reg_0,
      I2 => \^fifocntrrd_reg[1]_0\(0),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => Head1
    );
\RdPtr[2]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => FifoCntrRd_reg(2),
      I2 => \^fifocntrrd_reg[1]_0\(1),
      O => \RdPtr[2]_i_4__0_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => RdPtr(2),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\WrPtr[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^wrptr_reg[1]_0\(1),
      I1 => \^wrptr_reg[1]_0\(0),
      I2 => \FifoCntrRd_reg[2]_0\(0),
      I3 => dsc_acc_mgc_nn1,
      I4 => dsc_acc_done_nn1,
      I5 => WrPtr(2),
      O => \WrPtr__0\(2)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr_reg[1]_1\(0),
      Q => \^wrptr_reg[1]_0\(0),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr_reg[1]_1\(1),
      Q => \^wrptr_reg[1]_0\(1),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => WrPtr(2),
      R => \RdPtr[2]_i_1__0_n_0\
    );
\almost_full_ff_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FAFAFAF8"
    )
        port map (
      I0 => FifoCntrWr_reg(2),
      I1 => \^fifocntrwr_reg[1]_0\(1),
      I2 => FifoCntrWr_reg(3),
      I3 => dsc_ch_vld(0),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => \RdPtr[2]_i_1__0_n_0\,
      O => \almost_full_ff_i_1__0_n_0\
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \almost_full_ff_i_1__0_n_0\,
      Q => almost_full_ff_reg_0,
      R => '0'
    );
\dsc_aln_nn1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \dsc_aln_nn1_i_2__0_n_0\,
      I1 => \out\,
      O => ctl_non_inc_nn1_reg
    );
\dsc_aln_nn1_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^head_reg[158]_0\(95),
      I1 => \^head_reg[158]_0\(30),
      I2 => \^head_reg[158]_0\(31),
      I3 => \^head_reg[158]_0\(96),
      I4 => \^head_reg[158]_0\(32),
      I5 => \^head_reg[158]_0\(94),
      O => \dsc_aln_nn1_i_2__0_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \dsc_mrs_dst_nn1_reg[11]\,
      I1 => \^head_reg[158]_0\(41),
      I2 => \dsc_mrs_dst_nn1_reg[11]_3\(4),
      O => \dsc_mrs_dst_nn1[11]_i_2__0_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \dsc_mrs_dst_nn1_reg[11]_0\,
      I1 => \^head_reg[158]_0\(40),
      I2 => \dsc_mrs_dst_nn1_reg[11]_3\(3),
      O => \dsc_mrs_dst_nn1[11]_i_3__0_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \dsc_mrs_dst_nn1_reg[11]_1\,
      I1 => \^head_reg[158]_0\(39),
      I2 => \dsc_mrs_dst_nn1_reg[11]_3\(2),
      O => \dsc_mrs_dst_nn1[11]_i_4__0_n_0\
    );
\dsc_mrs_dst_nn1[11]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \dsc_mrs_dst_nn1_reg[11]_2\,
      I1 => \^head_reg[158]_0\(38),
      I2 => \dsc_mrs_dst_nn1_reg[11]_3\(1),
      O => \dsc_mrs_dst_nn1[11]_i_5__0_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_2__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(33),
      O => \dsc_mrs_dst_nn1[3]_i_2__0_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(32),
      O => \dsc_mrs_dst_nn1[3]_i_3__0_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(31),
      O => \dsc_mrs_dst_nn1[3]_i_4__0_n_0\
    );
\dsc_mrs_dst_nn1[3]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(30),
      O => \dsc_mrs_dst_nn1[3]_i_5__0_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \dsc_mrs_dst_nn1_reg[7]\,
      I1 => \^head_reg[158]_0\(37),
      I2 => \dsc_mrs_dst_nn1_reg[11]_3\(0),
      O => \dsc_mrs_dst_nn1[7]_i_2__0_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(36),
      O => \dsc_mrs_dst_nn1[7]_i_3__0_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(35),
      O => \dsc_mrs_dst_nn1[7]_i_4__0_n_0\
    );
\dsc_mrs_dst_nn1[7]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^head_reg[158]_0\(34),
      O => \dsc_mrs_dst_nn1[7]_i_5__0_n_0\
    );
\dsc_mrs_dst_nn1_reg[11]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_0\,
      CO(3) => \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3) => \dsc_mrs_dst_nn1_reg[11]\,
      DI(2) => \dsc_mrs_dst_nn1_reg[11]_0\,
      DI(1) => \dsc_mrs_dst_nn1_reg[11]_1\,
      DI(0) => \dsc_mrs_dst_nn1_reg[11]_2\,
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(11 downto 8),
      S(3) => \dsc_mrs_dst_nn1[11]_i_2__0_n_0\,
      S(2) => \dsc_mrs_dst_nn1[11]_i_3__0_n_0\,
      S(1) => \dsc_mrs_dst_nn1[11]_i_4__0_n_0\,
      S(0) => \dsc_mrs_dst_nn1[11]_i_5__0_n_0\
    );
\dsc_mrs_dst_nn1_reg[12]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[11]_i_1__0_n_0\,
      CO(3 downto 0) => \NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_O_UNCONNECTED\(3 downto 1),
      O(0) => \cfg_mrs_nn1_reg[11]\(12),
      S(3 downto 1) => B"000",
      S(0) => S(0)
    );
\dsc_mrs_dst_nn1_reg[3]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_3\,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(3 downto 0),
      S(3) => \dsc_mrs_dst_nn1[3]_i_2__0_n_0\,
      S(2) => \dsc_mrs_dst_nn1[3]_i_3__0_n_0\,
      S(1) => \dsc_mrs_dst_nn1[3]_i_4__0_n_0\,
      S(0) => \dsc_mrs_dst_nn1[3]_i_5__0_n_0\
    );
\dsc_mrs_dst_nn1_reg[7]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \dsc_mrs_dst_nn1_reg[3]_i_1__0_n_0\,
      CO(3) => \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_0\,
      CO(2) => \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_1\,
      CO(1) => \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_2\,
      CO(0) => \dsc_mrs_dst_nn1_reg[7]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3) => \dsc_mrs_dst_nn1_reg[7]\,
      DI(2 downto 0) => B"000",
      O(3 downto 0) => \cfg_mrs_nn1_reg[11]\(7 downto 4),
      S(3) => \dsc_mrs_dst_nn1[7]_i_2__0_n_0\,
      S(2) => \dsc_mrs_dst_nn1[7]_i_3__0_n_0\,
      S(1) => \dsc_mrs_dst_nn1[7]_i_4__0_n_0\,
      S(0) => \dsc_mrs_dst_nn1[7]_i_5__0_n_0\
    );
\empty_ff_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABAAAAAAABAAAB"
    )
        port map (
      I0 => \empty_ff_i_2__0_n_0\,
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => empty_ff_reg_0,
      I5 => \^fifocntrrd_reg[1]_0\(0),
      O => \empty_ff_i_1__3_n_0\
    );
\empty_ff_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010000"
    )
        port map (
      I0 => \^fifocntrrd_reg[1]_0\(0),
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(2),
      I3 => \^fifocntrrd_reg[1]_0\(1),
      I4 => dsc_ep_nn0,
      I5 => \RdPtr[2]_i_1__0_n_0\,
      O => \empty_ff_i_2__0_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__3_n_0\,
      Q => dsc_ep_nn0,
      R => '0'
    );
\rrq_dsc_ld_901_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => \rrq_dsc_ld_901_i_2__0_n_0\,
      I4 => rrq_dsc_ld_901_reg_0,
      I5 => \rrq_dsc_ld_901_reg_rep__2\,
      O => rrq_eod_903_reg
    );
\rrq_dsc_ld_901_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => Q(1),
      I1 => Q(2),
      I2 => dsc_ep_nn0,
      O => \rrq_dsc_ld_901_i_2__0_n_0\
    );
\rrq_dsc_ld_901_rep__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => \rrq_dsc_ld_901_i_2__0_n_0\,
      I4 => rrq_dsc_ld_901_reg_0,
      I5 => \rrq_dsc_ld_901_reg_rep__2\,
      O => rrq_eod_903_reg_1
    );
\rrq_dsc_ld_901_rep__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => \rrq_dsc_ld_901_i_2__0_n_0\,
      I4 => rrq_dsc_ld_901_reg_0,
      I5 => \rrq_dsc_ld_901_reg_rep__2\,
      O => rrq_eod_903_reg_2
    );
\rrq_dsc_ld_901_rep__2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => \rrq_dsc_ld_901_i_2__0_n_0\,
      I4 => rrq_dsc_ld_901_reg_0,
      I5 => \rrq_dsc_ld_901_reg_rep__2\,
      O => rrq_eod_903_reg_3
    );
\rrq_dsc_ld_901_rep_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000FF08"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg,
      I1 => rrq_eod_903,
      I2 => dsc_ep_nn0,
      I3 => \rrq_dsc_ld_901_i_2__0_n_0\,
      I4 => rrq_dsc_ld_901_reg_0,
      I5 => \rrq_dsc_ld_901_reg_rep__2\,
      O => rrq_eod_903_reg_0
    );
\rrq_sm_cur_900[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAABA"
    )
        port map (
      I0 => ctl_rst,
      I1 => reg_sts_hlt_nn1,
      I2 => dsc_ep_nn0,
      I3 => \rrq_sm_cur_900_reg[1]\,
      I4 => \rrq_sm_cur_900_reg[1]_0\,
      O => D(0)
    );
\rrq_sm_cur_900[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => rrq_eod_903,
      I1 => dsc_ep_nn0,
      I2 => rrq_ld_9008_out,
      I3 => \rrq_sm_cur_900[2]_i_2__0_n_0\,
      O => D(1)
    );
\rrq_sm_cur_900[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200808"
    )
        port map (
      I0 => \rrq_sm_cur_900_reg[2]\,
      I1 => Q(0),
      I2 => Q(1),
      I3 => \rrq_sm_cur_900_reg[1]\,
      I4 => dsc_ep_nn0,
      I5 => Q(2),
      O => \rrq_sm_cur_900[2]_i_2__0_n_0\
    );
\rrq_sm_cur_900[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055555500040004"
    )
        port map (
      I0 => rrq_dsc_ld_901_reg_0,
      I1 => Q(1),
      I2 => Q(2),
      I3 => dsc_ep_nn0,
      I4 => rrq_eod_903,
      I5 => rrq_dsc_ld_901_reg,
      O => D(2)
    );
\rrq_sm_cur_900[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444454444445555"
    )
        port map (
      I0 => ctl_rst,
      I1 => reg_sts_hlt_nn1,
      I2 => \rrq_sm_cur_900_reg[6]\,
      I3 => Q(3),
      I4 => \rrq_sm_cur_900_reg[6]_0\,
      I5 => \rrq_sm_cur_900[6]_i_4_n_0\,
      O => D(3)
    );
\rrq_sm_cur_900[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF9FFF"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => \rrq_sm_cur_900_reg[1]\,
      I3 => dsc_ep_nn0,
      I4 => Q(3),
      O => \rrq_sm_cur_900[6]_i_4_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    empty_ff_reg_1 : out STD_LOGIC;
    \pcie_c2h_rst_3ff_reg[0]_rep__4\ : out STD_LOGIC;
    empty_ff_reg_2 : out STD_LOGIC_VECTOR ( 88 downto 0 );
    empty_ff_reg_3 : out STD_LOGIC;
    empty_ff_reg_4 : out STD_LOGIC_VECTOR ( 91 downto 0 );
    wrq_vld_302 : out STD_LOGIC;
    cfg_linkdown_nn1 : in STD_LOGIC;
    empty_ff_reg_5 : in STD_LOGIC;
    Head0 : in STD_LOGIC_VECTOR ( 88 downto 0 );
    \Head1__2\ : in STD_LOGIC;
    arbstall : in STD_LOGIC;
    \Head_reg[111]_0\ : in STD_LOGIC;
    \wbk_xdma_wrq_req[rid]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Head_reg[110]_0\ : in STD_LOGIC;
    p_8_in : in STD_LOGIC_VECTOR ( 61 downto 0 );
    \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\ : in STD_LOGIC_VECTOR ( 61 downto 0 );
    \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\ : in STD_LOGIC_VECTOR ( 61 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wrq_vld_303_reg : in STD_LOGIC;
    wrq_vld_303_reg_0 : in STD_LOGIC;
    wrq_vld_303 : in STD_LOGIC;
    wrq_stall_302 : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrq_vld_303_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrq_vld_303_reg_2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 86 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__1_n_0\ : STD_LOGIC;
  signal Head0_0 : STD_LOGIC_VECTOR ( 111 downto 0 );
  signal Head1 : STD_LOGIC;
  signal \Head[111]_i_1__1_n_0\ : STD_LOGIC;
  signal \Head[111]_i_2_n_0\ : STD_LOGIC;
  signal \Head[36]_i_1__1_n_0\ : STD_LOGIC;
  signal \Head[41]_i_1__2_n_0\ : STD_LOGIC;
  signal \Head[46]_i_1__3_n_0\ : STD_LOGIC;
  signal \Head[8]_i_1__3_n_0\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[1]_i_3_n_0\ : STD_LOGIC;
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \c2h_xdma_wrq_req[0][aln]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \c2h_xdma_wrq_req[0][byte_len]\ : STD_LOGIC_VECTOR ( 27 downto 0 );
  signal \c2h_xdma_wrq_req[0][eod]\ : STD_LOGIC;
  signal \c2h_xdma_wrq_req[0][eop]\ : STD_LOGIC;
  signal \c2h_xdma_wrq_req[0][eor]\ : STD_LOGIC;
  signal \c2h_xdma_wrq_req[0][rid]\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \empty_ff_i_1__1_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__1_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \^empty_ff_reg_1\ : STD_LOGIC;
  signal \full_ff_i_1__0_n_0\ : STD_LOGIC;
  signal full_ff_reg_n_0 : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 110 downto 0 );
  signal p_10_in : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal p_11_in : STD_LOGIC;
  signal \^pcie_c2h_rst_3ff_reg[0]_rep__4\ : STD_LOGIC;
  signal wrq_vld_303_i_4_n_0 : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_111_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_111_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__1\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__1\ : label is "soft_lutpair1010";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__1\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__1\ : label is "soft_lutpair1011";
  attribute SOFT_HLUTNM of \Head[0]_i_1__0\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \Head[100]_i_1__1\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \Head[101]_i_1__1\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \Head[102]_i_1__1\ : label is "soft_lutpair1053";
  attribute SOFT_HLUTNM of \Head[103]_i_1__1\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \Head[104]_i_1__1\ : label is "soft_lutpair1054";
  attribute SOFT_HLUTNM of \Head[105]_i_1__1\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \Head[106]_i_1__1\ : label is "soft_lutpair1055";
  attribute SOFT_HLUTNM of \Head[107]_i_1__1\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \Head[108]_i_1__1\ : label is "soft_lutpair1056";
  attribute SOFT_HLUTNM of \Head[109]_i_1__1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \Head[10]_i_1__1\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \Head[110]_i_1__1\ : label is "soft_lutpair1057";
  attribute SOFT_HLUTNM of \Head[111]_i_2\ : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \Head[11]_i_1__1\ : label is "soft_lutpair1018";
  attribute SOFT_HLUTNM of \Head[12]_i_1__1\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \Head[13]_i_1__1\ : label is "soft_lutpair1019";
  attribute SOFT_HLUTNM of \Head[14]_i_1__1\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \Head[15]_i_1__1\ : label is "soft_lutpair1020";
  attribute SOFT_HLUTNM of \Head[16]_i_1__0\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \Head[17]_i_1__0\ : label is "soft_lutpair1021";
  attribute SOFT_HLUTNM of \Head[18]_i_1__0\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \Head[19]_i_1__0\ : label is "soft_lutpair1022";
  attribute SOFT_HLUTNM of \Head[1]_i_1__0\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \Head[20]_i_1__1\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \Head[21]_i_1__1\ : label is "soft_lutpair1023";
  attribute SOFT_HLUTNM of \Head[2]_i_1\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \Head[36]_i_1__1\ : label is "soft_lutpair1013";
  attribute SOFT_HLUTNM of \Head[37]_i_1__0\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \Head[38]_i_1__0\ : label is "soft_lutpair1024";
  attribute SOFT_HLUTNM of \Head[39]_i_1__0\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \Head[3]_i_1__0\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \Head[40]_i_1__0\ : label is "soft_lutpair1025";
  attribute SOFT_HLUTNM of \Head[41]_i_1__2\ : label is "soft_lutpair1014";
  attribute SOFT_HLUTNM of \Head[46]_i_1__3\ : label is "soft_lutpair1015";
  attribute SOFT_HLUTNM of \Head[47]_i_1__0\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \Head[48]_i_1__0\ : label is "soft_lutpair1026";
  attribute SOFT_HLUTNM of \Head[49]_i_1__0\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \Head[4]_i_1__0\ : label is "soft_lutpair1016";
  attribute SOFT_HLUTNM of \Head[50]_i_1__0\ : label is "soft_lutpair1027";
  attribute SOFT_HLUTNM of \Head[51]_i_1__0\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \Head[52]_i_1__0\ : label is "soft_lutpair1028";
  attribute SOFT_HLUTNM of \Head[53]_i_1__0\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \Head[54]_i_1__0\ : label is "soft_lutpair1029";
  attribute SOFT_HLUTNM of \Head[55]_i_1__0\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \Head[56]_i_1__0\ : label is "soft_lutpair1030";
  attribute SOFT_HLUTNM of \Head[57]_i_1__0\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \Head[58]_i_1__0\ : label is "soft_lutpair1031";
  attribute SOFT_HLUTNM of \Head[59]_i_1__0\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \Head[5]_i_1__0\ : label is "soft_lutpair1017";
  attribute SOFT_HLUTNM of \Head[60]_i_1__0\ : label is "soft_lutpair1032";
  attribute SOFT_HLUTNM of \Head[61]_i_1__1\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \Head[62]_i_1__1\ : label is "soft_lutpair1033";
  attribute SOFT_HLUTNM of \Head[63]_i_1__1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \Head[64]_i_1__1\ : label is "soft_lutpair1034";
  attribute SOFT_HLUTNM of \Head[65]_i_1__1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \Head[66]_i_1__1\ : label is "soft_lutpair1035";
  attribute SOFT_HLUTNM of \Head[67]_i_1__1\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \Head[68]_i_1__1\ : label is "soft_lutpair1036";
  attribute SOFT_HLUTNM of \Head[69]_i_1__1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \Head[70]_i_1__1\ : label is "soft_lutpair1037";
  attribute SOFT_HLUTNM of \Head[71]_i_1__1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \Head[72]_i_1__1\ : label is "soft_lutpair1038";
  attribute SOFT_HLUTNM of \Head[73]_i_1__1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \Head[74]_i_1__1\ : label is "soft_lutpair1039";
  attribute SOFT_HLUTNM of \Head[75]_i_1__1\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \Head[76]_i_1__1\ : label is "soft_lutpair1040";
  attribute SOFT_HLUTNM of \Head[77]_i_1__1\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \Head[78]_i_1__1\ : label is "soft_lutpair1041";
  attribute SOFT_HLUTNM of \Head[79]_i_1__1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \Head[80]_i_1__1\ : label is "soft_lutpair1042";
  attribute SOFT_HLUTNM of \Head[81]_i_1__1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \Head[82]_i_1__1\ : label is "soft_lutpair1043";
  attribute SOFT_HLUTNM of \Head[83]_i_1__1\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \Head[84]_i_1__1\ : label is "soft_lutpair1044";
  attribute SOFT_HLUTNM of \Head[85]_i_1__1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \Head[86]_i_1__1\ : label is "soft_lutpair1045";
  attribute SOFT_HLUTNM of \Head[87]_i_1__1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \Head[88]_i_1__1\ : label is "soft_lutpair1046";
  attribute SOFT_HLUTNM of \Head[89]_i_1__1\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \Head[8]_i_1__3\ : label is "soft_lutpair1012";
  attribute SOFT_HLUTNM of \Head[90]_i_1__1\ : label is "soft_lutpair1047";
  attribute SOFT_HLUTNM of \Head[91]_i_1__1\ : label is "soft_lutpair1048";
  attribute SOFT_HLUTNM of \Head[92]_i_1__1\ : label is "soft_lutpair1048";
  attribute SOFT_HLUTNM of \Head[93]_i_1__1\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \Head[94]_i_1__1\ : label is "soft_lutpair1049";
  attribute SOFT_HLUTNM of \Head[95]_i_1__1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \Head[96]_i_1__1\ : label is "soft_lutpair1050";
  attribute SOFT_HLUTNM of \Head[97]_i_1__1\ : label is "soft_lutpair1051";
  attribute SOFT_HLUTNM of \Head[98]_i_1__1\ : label is "soft_lutpair1051";
  attribute SOFT_HLUTNM of \Head[99]_i_1__1\ : label is "soft_lutpair1052";
  attribute SOFT_HLUTNM of \Head[9]_i_1__1\ : label is "soft_lutpair1017";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 448;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_111 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_111 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_111 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_111 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_111 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_111 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_111 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_111 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_111 : label is 111;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_36_41 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_36_41 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_42_47 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_42_47 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_48_53 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_48_53 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__1\ : label is "soft_lutpair1058";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__1\ : label is "soft_lutpair1058";
begin
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  empty_ff_reg_1 <= \^empty_ff_reg_1\;
  \pcie_c2h_rst_3ff_reg[0]_rep__4\ <= \^pcie_c2h_rst_3ff_reg[0]_rep__4\;
\FifoCntrRd[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"59A6"
    )
        port map (
      I0 => wrq_vld_303,
      I1 => \^empty_ff_reg_1\,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__1_n_0\
    );
\FifoCntrRd[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77E78818"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => wrq_vld_303,
      I2 => \^empty_ff_reg_1\,
      I3 => \^empty_ff_reg_0\,
      I4 => FifoCntrRd(1),
      O => \FifoCntrRd[1]_i_1__1_n_0\
    );
\FifoCntrRd[2]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => empty_ff_reg_5,
      I1 => cfg_linkdown_nn1,
      O => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7FFE7F80800180"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(1),
      I2 => wrq_vld_303,
      I3 => \^empty_ff_reg_1\,
      I4 => \^empty_ff_reg_0\,
      I5 => FifoCntrRd(2),
      O => \FifoCntrRd[2]_i_2_n_0\
    );
\FifoCntrRd[2]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \Head_reg[111]_0\,
      I2 => arbstall,
      O => \^empty_ff_reg_1\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1__1_n_0\,
      Q => FifoCntrRd(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1__1_n_0\,
      Q => FifoCntrRd(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_2_n_0\,
      Q => FifoCntrRd(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4BB4"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \^empty_ff_reg_1\,
      I2 => wrq_vld_303,
      I3 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__1_n_0\
    );
\FifoCntrWr[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75EF8A10"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => \^empty_ff_reg_0\,
      I2 => \^empty_ff_reg_1\,
      I3 => wrq_vld_303,
      I4 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__1_n_0\
    );
\FifoCntrWr[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F77FEFF80880100"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \^empty_ff_reg_0\,
      I3 => \^empty_ff_reg_1\,
      I4 => wrq_vld_303,
      I5 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1__1_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1__1_n_0\,
      Q => FifoCntrWr(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1__1_n_0\,
      Q => FifoCntrWr(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1__1_n_0\,
      Q => FifoCntrWr(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head0_0(0),
      I2 => Head1,
      O => p_0_in1_in(0)
    );
\Head[0]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CC50CC00CCFFCC"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => Head0(0),
      I2 => \c2h_xdma_wrq_req[0][eor]\,
      I3 => \Head1__2\,
      I4 => arbstall,
      I5 => \Head_reg[111]_0\,
      O => empty_ff_reg_2(0)
    );
\Head[100]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head0_0(100),
      I2 => Head1,
      O => p_0_in1_in(100)
    );
\Head[100]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(77),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(53),
      I3 => p_8_in(51),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(77)
    );
\Head[101]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head0_0(101),
      I2 => Head1,
      O => p_0_in1_in(101)
    );
\Head[101]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(78),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(54),
      I3 => p_8_in(52),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(78)
    );
\Head[102]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head0_0(102),
      I2 => Head1,
      O => p_0_in1_in(102)
    );
\Head[102]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(79),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(55),
      I3 => p_8_in(53),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(79)
    );
\Head[103]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head0_0(103),
      I2 => Head1,
      O => p_0_in1_in(103)
    );
\Head[103]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(80),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(56),
      I3 => p_8_in(54),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(80)
    );
\Head[104]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head0_0(104),
      I2 => Head1,
      O => p_0_in1_in(104)
    );
\Head[104]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(81),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(57),
      I3 => p_8_in(55),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(81)
    );
\Head[105]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(81),
      I1 => Head0_0(105),
      I2 => Head1,
      O => p_0_in1_in(105)
    );
\Head[105]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(82),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(58),
      I3 => p_8_in(56),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(82)
    );
\Head[106]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(82),
      I1 => Head0_0(106),
      I2 => Head1,
      O => p_0_in1_in(106)
    );
\Head[106]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(83),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(59),
      I3 => p_8_in(57),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(83)
    );
\Head[107]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(83),
      I1 => Head0_0(107),
      I2 => Head1,
      O => p_0_in1_in(107)
    );
\Head[107]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(84),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(60),
      I3 => p_8_in(58),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(84)
    );
\Head[108]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(84),
      I1 => Head0_0(108),
      I2 => Head1,
      O => p_0_in1_in(108)
    );
\Head[108]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(85),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(61),
      I3 => p_8_in(59),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(85)
    );
\Head[109]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(85),
      I1 => Head0_0(109),
      I2 => Head1,
      O => p_0_in1_in(109)
    );
\Head[109]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(86),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(62),
      I3 => p_8_in(60),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(86)
    );
\Head[10]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head0_0(10),
      I2 => Head1,
      O => p_0_in1_in(10)
    );
\Head[10]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(1),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(7),
      O => empty_ff_reg_2(7)
    );
\Head[110]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(86),
      I1 => Head0_0(110),
      I2 => Head1,
      O => p_0_in1_in(110)
    );
\Head[110]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(87),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(63),
      I3 => p_8_in(61),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(87)
    );
\Head[111]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEAEAEAEAEAEAEFF"
    )
        port map (
      I0 => Head1,
      I1 => \^empty_ff_reg_1\,
      I2 => \^empty_ff_reg_0\,
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => FifoCntrRd(0),
      O => \Head[111]_i_1__1_n_0\
    );
\Head[111]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => p_11_in,
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(88),
      O => empty_ff_reg_2(88)
    );
\Head[111]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0_0(111),
      I1 => Head1,
      O => \Head[111]_i_2_n_0\
    );
\Head[11]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head0_0(11),
      I2 => Head1,
      O => p_0_in1_in(11)
    );
\Head[11]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CC50CC00CCFFCC"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => Head0(8),
      I2 => \c2h_xdma_wrq_req[0][byte_len]\(2),
      I3 => \Head1__2\,
      I4 => arbstall,
      I5 => \Head_reg[111]_0\,
      O => empty_ff_reg_2(8)
    );
\Head[12]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head0_0(12),
      I2 => Head1,
      O => p_0_in1_in(12)
    );
\Head[12]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(3),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(9),
      O => empty_ff_reg_2(9)
    );
\Head[13]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head0_0(13),
      I2 => Head1,
      O => p_0_in1_in(13)
    );
\Head[13]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(4),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(10),
      O => empty_ff_reg_2(10)
    );
\Head[14]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head0_0(14),
      I2 => Head1,
      O => p_0_in1_in(14)
    );
\Head[14]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(5),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(11),
      O => empty_ff_reg_2(11)
    );
\Head[15]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head0_0(15),
      I2 => Head1,
      O => p_0_in1_in(15)
    );
\Head[15]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(6),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(12),
      O => empty_ff_reg_2(12)
    );
\Head[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head0_0(16),
      I2 => Head1,
      O => p_0_in1_in(16)
    );
\Head[16]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(7),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(13),
      O => empty_ff_reg_2(13)
    );
\Head[17]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head0_0(17),
      I2 => Head1,
      O => p_0_in1_in(17)
    );
\Head[17]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(8),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(14),
      O => empty_ff_reg_2(14)
    );
\Head[18]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head0_0(18),
      I2 => Head1,
      O => p_0_in1_in(18)
    );
\Head[18]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(9),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(15),
      O => empty_ff_reg_2(15)
    );
\Head[19]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head0_0(19),
      I2 => Head1,
      O => p_0_in1_in(19)
    );
\Head[19]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(10),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(16),
      O => empty_ff_reg_2(16)
    );
\Head[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head0_0(1),
      I2 => Head1,
      O => p_0_in1_in(1)
    );
\Head[20]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head0_0(20),
      I2 => Head1,
      O => p_0_in1_in(20)
    );
\Head[20]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(11),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(17),
      O => empty_ff_reg_2(17)
    );
\Head[21]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head0_0(21),
      I2 => Head1,
      O => p_0_in1_in(21)
    );
\Head[21]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(12),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(18),
      O => empty_ff_reg_2(18)
    );
\Head[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(2),
      I1 => Head0_0(2),
      I2 => Head1,
      O => p_0_in1_in(2)
    );
\Head[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CC50CC00CCFFCC"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => Head0(1),
      I2 => \c2h_xdma_wrq_req[0][eop]\,
      I3 => \Head1__2\,
      I4 => arbstall,
      I5 => \Head_reg[111]_0\,
      O => empty_ff_reg_2(1)
    );
\Head[36]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0_0(36),
      I1 => Head1,
      O => \Head[36]_i_1__1_n_0\
    );
\Head[37]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head0_0(37),
      I2 => Head1,
      O => p_0_in1_in(37)
    );
\Head[37]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(19),
      I1 => \^empty_ff_reg_1\,
      I2 => \c2h_xdma_wrq_req[0][rid]\(0),
      I3 => \wbk_xdma_wrq_req[rid]\(0),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(19)
    );
\Head[38]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head0_0(38),
      I2 => Head1,
      O => p_0_in1_in(38)
    );
\Head[38]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][rid]\(1),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(20),
      O => empty_ff_reg_2(20)
    );
\Head[39]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head0_0(39),
      I2 => Head1,
      O => p_0_in1_in(39)
    );
\Head[39]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][rid]\(2),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(21),
      O => empty_ff_reg_2(21)
    );
\Head[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head0_0(3),
      I2 => Head1,
      O => p_0_in1_in(3)
    );
\Head[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][aln]\(0),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(2),
      O => empty_ff_reg_2(2)
    );
\Head[40]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head0_0(40),
      I2 => Head1,
      O => p_0_in1_in(40)
    );
\Head[40]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][rid]\(3),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(22),
      O => empty_ff_reg_2(22)
    );
\Head[41]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0_0(41),
      I1 => Head1,
      O => \Head[41]_i_1__2_n_0\
    );
\Head[41]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][rid]\(4),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(23),
      O => empty_ff_reg_2(23)
    );
\Head[46]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0_0(46),
      I1 => Head1,
      O => \Head[46]_i_1__3_n_0\
    );
\Head[47]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head0_0(47),
      I2 => Head1,
      O => p_0_in1_in(47)
    );
\Head[47]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => p_10_in(0),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(24),
      O => empty_ff_reg_2(24)
    );
\Head[48]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head0_0(48),
      I2 => Head1,
      O => p_0_in1_in(48)
    );
\Head[48]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => p_10_in(1),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(25),
      O => empty_ff_reg_2(25)
    );
\Head[49]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head0_0(49),
      I2 => Head1,
      O => p_0_in1_in(49)
    );
\Head[49]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(26),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(2),
      I3 => p_8_in(0),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(26)
    );
\Head[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head0_0(4),
      I2 => Head1,
      O => p_0_in1_in(4)
    );
\Head[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][aln]\(1),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(3),
      O => empty_ff_reg_2(3)
    );
\Head[50]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head0_0(50),
      I2 => Head1,
      O => p_0_in1_in(50)
    );
\Head[50]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(27),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(3),
      I3 => p_8_in(1),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(27)
    );
\Head[51]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head0_0(51),
      I2 => Head1,
      O => p_0_in1_in(51)
    );
\Head[51]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(28),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(4),
      I3 => p_8_in(2),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(28)
    );
\Head[52]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head0_0(52),
      I2 => Head1,
      O => p_0_in1_in(52)
    );
\Head[52]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(29),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(5),
      I3 => p_8_in(3),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(29)
    );
\Head[53]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head0_0(53),
      I2 => Head1,
      O => p_0_in1_in(53)
    );
\Head[53]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(30),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(6),
      I3 => p_8_in(4),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(30)
    );
\Head[54]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head0_0(54),
      I2 => Head1,
      O => p_0_in1_in(54)
    );
\Head[54]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(31),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(7),
      I3 => p_8_in(5),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(31)
    );
\Head[55]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head0_0(55),
      I2 => Head1,
      O => p_0_in1_in(55)
    );
\Head[55]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(32),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(8),
      I3 => p_8_in(6),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(32)
    );
\Head[56]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head0_0(56),
      I2 => Head1,
      O => p_0_in1_in(56)
    );
\Head[56]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(33),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(9),
      I3 => p_8_in(7),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(33)
    );
\Head[57]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head0_0(57),
      I2 => Head1,
      O => p_0_in1_in(57)
    );
\Head[57]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(34),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(10),
      I3 => p_8_in(8),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(34)
    );
\Head[58]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head0_0(58),
      I2 => Head1,
      O => p_0_in1_in(58)
    );
\Head[58]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(35),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(11),
      I3 => p_8_in(9),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(35)
    );
\Head[59]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head0_0(59),
      I2 => Head1,
      O => p_0_in1_in(59)
    );
\Head[59]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(36),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(12),
      I3 => p_8_in(10),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(36)
    );
\Head[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head0_0(5),
      I2 => Head1,
      O => p_0_in1_in(5)
    );
\Head[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][aln]\(2),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(4),
      O => empty_ff_reg_2(4)
    );
\Head[60]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head0_0(60),
      I2 => Head1,
      O => p_0_in1_in(60)
    );
\Head[60]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(37),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(13),
      I3 => p_8_in(11),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(37)
    );
\Head[61]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head0_0(61),
      I2 => Head1,
      O => p_0_in1_in(61)
    );
\Head[61]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(38),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(14),
      I3 => p_8_in(12),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(38)
    );
\Head[62]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head0_0(62),
      I2 => Head1,
      O => p_0_in1_in(62)
    );
\Head[62]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(39),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(15),
      I3 => p_8_in(13),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(39)
    );
\Head[63]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head0_0(63),
      I2 => Head1,
      O => p_0_in1_in(63)
    );
\Head[63]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(40),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(16),
      I3 => p_8_in(14),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(40)
    );
\Head[64]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head0_0(64),
      I2 => Head1,
      O => p_0_in1_in(64)
    );
\Head[64]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(41),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(17),
      I3 => p_8_in(15),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(41)
    );
\Head[65]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head0_0(65),
      I2 => Head1,
      O => p_0_in1_in(65)
    );
\Head[65]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(42),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(18),
      I3 => p_8_in(16),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(42)
    );
\Head[66]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head0_0(66),
      I2 => Head1,
      O => p_0_in1_in(66)
    );
\Head[66]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(43),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(19),
      I3 => p_8_in(17),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(43)
    );
\Head[67]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head0_0(67),
      I2 => Head1,
      O => p_0_in1_in(67)
    );
\Head[67]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(44),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(20),
      I3 => p_8_in(18),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(44)
    );
\Head[68]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head0_0(68),
      I2 => Head1,
      O => p_0_in1_in(68)
    );
\Head[68]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(45),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(21),
      I3 => p_8_in(19),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(45)
    );
\Head[69]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head0_0(69),
      I2 => Head1,
      O => p_0_in1_in(69)
    );
\Head[69]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(46),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(22),
      I3 => p_8_in(20),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(46)
    );
\Head[70]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head0_0(70),
      I2 => Head1,
      O => p_0_in1_in(70)
    );
\Head[70]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(47),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(23),
      I3 => p_8_in(21),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(47)
    );
\Head[71]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head0_0(71),
      I2 => Head1,
      O => p_0_in1_in(71)
    );
\Head[71]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(48),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(24),
      I3 => p_8_in(22),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(48)
    );
\Head[72]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head0_0(72),
      I2 => Head1,
      O => p_0_in1_in(72)
    );
\Head[72]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(49),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(25),
      I3 => p_8_in(23),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(49)
    );
\Head[73]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head0_0(73),
      I2 => Head1,
      O => p_0_in1_in(73)
    );
\Head[73]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(50),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(26),
      I3 => p_8_in(24),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(50)
    );
\Head[74]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head0_0(74),
      I2 => Head1,
      O => p_0_in1_in(74)
    );
\Head[74]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(51),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(27),
      I3 => p_8_in(25),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(51)
    );
\Head[75]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head0_0(75),
      I2 => Head1,
      O => p_0_in1_in(75)
    );
\Head[75]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(52),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(28),
      I3 => p_8_in(26),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(52)
    );
\Head[76]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head0_0(76),
      I2 => Head1,
      O => p_0_in1_in(76)
    );
\Head[76]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(53),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(29),
      I3 => p_8_in(27),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(53)
    );
\Head[77]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head0_0(77),
      I2 => Head1,
      O => p_0_in1_in(77)
    );
\Head[77]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(54),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(30),
      I3 => p_8_in(28),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(54)
    );
\Head[78]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head0_0(78),
      I2 => Head1,
      O => p_0_in1_in(78)
    );
\Head[78]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(55),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(31),
      I3 => p_8_in(29),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(55)
    );
\Head[79]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head0_0(79),
      I2 => Head1,
      O => p_0_in1_in(79)
    );
\Head[79]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(56),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(32),
      I3 => p_8_in(30),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(56)
    );
\Head[80]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head0_0(80),
      I2 => Head1,
      O => p_0_in1_in(80)
    );
\Head[80]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(57),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(33),
      I3 => p_8_in(31),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(57)
    );
\Head[81]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head0_0(81),
      I2 => Head1,
      O => p_0_in1_in(81)
    );
\Head[81]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(58),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(34),
      I3 => p_8_in(32),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(58)
    );
\Head[82]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head0_0(82),
      I2 => Head1,
      O => p_0_in1_in(82)
    );
\Head[82]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(59),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(35),
      I3 => p_8_in(33),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(59)
    );
\Head[83]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head0_0(83),
      I2 => Head1,
      O => p_0_in1_in(83)
    );
\Head[83]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(60),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(36),
      I3 => p_8_in(34),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(60)
    );
\Head[84]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head0_0(84),
      I2 => Head1,
      O => p_0_in1_in(84)
    );
\Head[84]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(61),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(37),
      I3 => p_8_in(35),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(61)
    );
\Head[85]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head0_0(85),
      I2 => Head1,
      O => p_0_in1_in(85)
    );
\Head[85]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(62),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(38),
      I3 => p_8_in(36),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(62)
    );
\Head[86]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head0_0(86),
      I2 => Head1,
      O => p_0_in1_in(86)
    );
\Head[86]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(63),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(39),
      I3 => p_8_in(37),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(63)
    );
\Head[87]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head0_0(87),
      I2 => Head1,
      O => p_0_in1_in(87)
    );
\Head[87]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(64),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(40),
      I3 => p_8_in(38),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(64)
    );
\Head[88]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head0_0(88),
      I2 => Head1,
      O => p_0_in1_in(88)
    );
\Head[88]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(65),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(41),
      I3 => p_8_in(39),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(65)
    );
\Head[89]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head0_0(89),
      I2 => Head1,
      O => p_0_in1_in(89)
    );
\Head[89]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(66),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(42),
      I3 => p_8_in(40),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(66)
    );
\Head[8]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0_0(8),
      I1 => Head1,
      O => \Head[8]_i_1__3_n_0\
    );
\Head[8]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][aln]\(5),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(5),
      O => empty_ff_reg_2(5)
    );
\Head[90]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head0_0(90),
      I2 => Head1,
      O => p_0_in1_in(90)
    );
\Head[90]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(67),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(43),
      I3 => p_8_in(41),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(67)
    );
\Head[91]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head0_0(91),
      I2 => Head1,
      O => p_0_in1_in(91)
    );
\Head[91]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(68),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(44),
      I3 => p_8_in(42),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(68)
    );
\Head[92]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head0_0(92),
      I2 => Head1,
      O => p_0_in1_in(92)
    );
\Head[92]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(69),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(45),
      I3 => p_8_in(43),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(69)
    );
\Head[93]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head0_0(93),
      I2 => Head1,
      O => p_0_in1_in(93)
    );
\Head[93]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(70),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(46),
      I3 => p_8_in(44),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(70)
    );
\Head[94]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head0_0(94),
      I2 => Head1,
      O => p_0_in1_in(94)
    );
\Head[94]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(71),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(47),
      I3 => p_8_in(45),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(71)
    );
\Head[95]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head0_0(95),
      I2 => Head1,
      O => p_0_in1_in(95)
    );
\Head[95]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(72),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(48),
      I3 => p_8_in(46),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(72)
    );
\Head[96]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head0_0(96),
      I2 => Head1,
      O => p_0_in1_in(96)
    );
\Head[96]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(73),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(49),
      I3 => p_8_in(47),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(73)
    );
\Head[97]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head0_0(97),
      I2 => Head1,
      O => p_0_in1_in(97)
    );
\Head[97]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(74),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(50),
      I3 => p_8_in(48),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(74)
    );
\Head[98]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head0_0(98),
      I2 => Head1,
      O => p_0_in1_in(98)
    );
\Head[98]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(75),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(51),
      I3 => p_8_in(49),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(75)
    );
\Head[99]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head0_0(99),
      I2 => Head1,
      O => p_0_in1_in(99)
    );
\Head[99]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFC0AAAAC0C0AAAA"
    )
        port map (
      I0 => Head0(76),
      I1 => \^empty_ff_reg_1\,
      I2 => p_10_in(52),
      I3 => p_8_in(50),
      I4 => \Head1__2\,
      I5 => \Head_reg[110]_0\,
      O => empty_ff_reg_2(76)
    );
\Head[9]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head0_0(9),
      I2 => Head1,
      O => p_0_in1_in(9)
    );
\Head[9]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(0),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      I4 => \Head1__2\,
      I5 => Head0(6),
      O => empty_ff_reg_2(6)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(0),
      Q => \c2h_xdma_wrq_req[0][eor]\,
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(100),
      Q => p_10_in(53),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(101),
      Q => p_10_in(54),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(102),
      Q => p_10_in(55),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(103),
      Q => p_10_in(56),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(104),
      Q => p_10_in(57),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(105),
      Q => p_10_in(58),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(106),
      Q => p_10_in(59),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(107),
      Q => p_10_in(60),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(108),
      Q => p_10_in(61),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(109),
      Q => p_10_in(62),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(10),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(110),
      Q => p_10_in(63),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => \Head[111]_i_2_n_0\,
      Q => p_11_in,
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(11),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(12),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(3),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(13),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(4),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(14),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(5),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(15),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(6),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(16),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(7),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(17),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(8),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(18),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(9),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(19),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(10),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(1),
      Q => \c2h_xdma_wrq_req[0][eod]\,
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(20),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(11),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(21),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(12),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(2),
      Q => \c2h_xdma_wrq_req[0][eop]\,
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => \Head[36]_i_1__1_n_0\,
      Q => \c2h_xdma_wrq_req[0][byte_len]\(27),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(37),
      Q => \c2h_xdma_wrq_req[0][rid]\(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(38),
      Q => \c2h_xdma_wrq_req[0][rid]\(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(39),
      Q => \c2h_xdma_wrq_req[0][rid]\(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(3),
      Q => \c2h_xdma_wrq_req[0][aln]\(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(40),
      Q => \c2h_xdma_wrq_req[0][rid]\(3),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => \Head[41]_i_1__2_n_0\,
      Q => \c2h_xdma_wrq_req[0][rid]\(4),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => \Head[46]_i_1__3_n_0\,
      Q => \c2h_xdma_wrq_req[0][rid]\(9),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(47),
      Q => p_10_in(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(48),
      Q => p_10_in(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(49),
      Q => p_10_in(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(4),
      Q => \c2h_xdma_wrq_req[0][aln]\(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(50),
      Q => p_10_in(3),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(51),
      Q => p_10_in(4),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(52),
      Q => p_10_in(5),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(53),
      Q => p_10_in(6),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(54),
      Q => p_10_in(7),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(55),
      Q => p_10_in(8),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(56),
      Q => p_10_in(9),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(57),
      Q => p_10_in(10),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(58),
      Q => p_10_in(11),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(59),
      Q => p_10_in(12),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(5),
      Q => \c2h_xdma_wrq_req[0][aln]\(2),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(60),
      Q => p_10_in(13),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(61),
      Q => p_10_in(14),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(62),
      Q => p_10_in(15),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(63),
      Q => p_10_in(16),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(64),
      Q => p_10_in(17),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(65),
      Q => p_10_in(18),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(66),
      Q => p_10_in(19),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(67),
      Q => p_10_in(20),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(68),
      Q => p_10_in(21),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(69),
      Q => p_10_in(22),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(70),
      Q => p_10_in(23),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(71),
      Q => p_10_in(24),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(72),
      Q => p_10_in(25),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(73),
      Q => p_10_in(26),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(74),
      Q => p_10_in(27),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(75),
      Q => p_10_in(28),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(76),
      Q => p_10_in(29),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(77),
      Q => p_10_in(30),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(78),
      Q => p_10_in(31),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(79),
      Q => p_10_in(32),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(80),
      Q => p_10_in(33),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(81),
      Q => p_10_in(34),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(82),
      Q => p_10_in(35),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(83),
      Q => p_10_in(36),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(84),
      Q => p_10_in(37),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(85),
      Q => p_10_in(38),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(86),
      Q => p_10_in(39),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(87),
      Q => p_10_in(40),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(88),
      Q => p_10_in(41),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(89),
      Q => p_10_in(42),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => \Head[8]_i_1__3_n_0\,
      Q => \c2h_xdma_wrq_req[0][aln]\(5),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(90),
      Q => p_10_in(43),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(91),
      Q => p_10_in(44),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(92),
      Q => p_10_in(45),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(93),
      Q => p_10_in(46),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(94),
      Q => p_10_in(47),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(95),
      Q => p_10_in(48),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(96),
      Q => p_10_in(49),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(97),
      Q => p_10_in(50),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(98),
      Q => p_10_in(51),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(99),
      Q => p_10_in(52),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__1_n_0\,
      D => p_0_in1_in(9),
      Q => \c2h_xdma_wrq_req[0][byte_len]\(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(1 downto 0),
      DOB(1 downto 0) => Head0_0(3 downto 2),
      DOC(1 downto 0) => Head0_0(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_0_5_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"13"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      O => empty_ff_reg_3
    );
\MemArray_reg_0_3_0_5_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][eod]\,
      O => empty_ff_reg_4(1)
    );
\MemArray_reg_0_3_0_5_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"040F"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][eor]\,
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      O => empty_ff_reg_4(0)
    );
\MemArray_reg_0_3_0_5_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][aln]\(0),
      O => empty_ff_reg_4(3)
    );
\MemArray_reg_0_3_0_5_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"040F"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][eop]\,
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      O => empty_ff_reg_4(2)
    );
\MemArray_reg_0_3_0_5_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][aln]\(2),
      O => empty_ff_reg_4(5)
    );
\MemArray_reg_0_3_0_5_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][aln]\(1),
      O => empty_ff_reg_4(4)
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(79 downto 78),
      DIB(1 downto 0) => DataIn(81 downto 80),
      DIC(1 downto 0) => DataIn(83 downto 82),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(103 downto 102),
      DOB(1 downto 0) => Head0_0(105 downto 104),
      DOC(1 downto 0) => Head0_0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_102_107_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(54),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(54),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(56),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(83)
    );
\MemArray_reg_0_3_102_107_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(53),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(53),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(55),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(82)
    );
\MemArray_reg_0_3_102_107_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(56),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(56),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(58),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(85)
    );
\MemArray_reg_0_3_102_107_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(55),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(55),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(57),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(84)
    );
\MemArray_reg_0_3_102_107_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(58),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(58),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(60),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(87)
    );
\MemArray_reg_0_3_102_107_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(57),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(57),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(59),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(86)
    );
MemArray_reg_0_3_108_111: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(85 downto 84),
      DIB(1) => '0',
      DIB(0) => DataIn(86),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(109 downto 108),
      DOB(1 downto 0) => Head0_0(111 downto 110),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_108_111_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_111_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
MemArray_reg_0_3_108_112_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(60),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(60),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(62),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(89)
    );
MemArray_reg_0_3_108_112_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(59),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(59),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(61),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(88)
    );
MemArray_reg_0_3_108_112_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => p_11_in,
      O => empty_ff_reg_4(91)
    );
MemArray_reg_0_3_108_112_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(61),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(61),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(63),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(90)
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(10 downto 9),
      DIB(1 downto 0) => DataIn(12 downto 11),
      DIC(1 downto 0) => DataIn(14 downto 13),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(13 downto 12),
      DOB(1 downto 0) => Head0_0(15 downto 14),
      DOC(1 downto 0) => Head0_0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_12_17_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(4),
      O => empty_ff_reg_4(11)
    );
\MemArray_reg_0_3_12_17_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(3),
      O => empty_ff_reg_4(10)
    );
\MemArray_reg_0_3_12_17_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(6),
      O => empty_ff_reg_4(13)
    );
\MemArray_reg_0_3_12_17_i_4__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(5),
      O => empty_ff_reg_4(12)
    );
\MemArray_reg_0_3_12_17_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(8),
      O => empty_ff_reg_4(15)
    );
\MemArray_reg_0_3_12_17_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(7),
      O => empty_ff_reg_4(14)
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(16 downto 15),
      DIB(1 downto 0) => DataIn(18 downto 17),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(19 downto 18),
      DOB(1 downto 0) => Head0_0(21 downto 20),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_18_23_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(10),
      O => empty_ff_reg_4(17)
    );
\MemArray_reg_0_3_18_23_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(9),
      O => empty_ff_reg_4(16)
    );
\MemArray_reg_0_3_18_23_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(12),
      O => empty_ff_reg_4(19)
    );
\MemArray_reg_0_3_18_23_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(11),
      O => empty_ff_reg_4(18)
    );
MemArray_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1) => DataIn(19),
      DIA(0) => '0',
      DIB(1 downto 0) => DataIn(21 downto 20),
      DIC(1) => '0',
      DIC(0) => DataIn(22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(37 downto 36),
      DOB(1 downto 0) => Head0_0(39 downto 38),
      DOC(1 downto 0) => Head0_0(41 downto 40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
MemArray_reg_0_3_36_41_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000050CC"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \wbk_xdma_wrq_req[rid]\(0),
      I2 => \c2h_xdma_wrq_req[0][rid]\(0),
      I3 => \Head_reg[111]_0\,
      I4 => arbstall,
      O => empty_ff_reg_4(21)
    );
MemArray_reg_0_3_36_41_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(27),
      O => empty_ff_reg_4(20)
    );
MemArray_reg_0_3_36_41_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][rid]\(2),
      O => empty_ff_reg_4(23)
    );
MemArray_reg_0_3_36_41_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][rid]\(1),
      O => empty_ff_reg_4(22)
    );
MemArray_reg_0_3_36_41_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][rid]\(4),
      O => empty_ff_reg_4(25)
    );
MemArray_reg_0_3_36_41_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][rid]\(3),
      O => empty_ff_reg_4(24)
    );
MemArray_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => DataIn(23),
      DIC(0) => '0',
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => Head0_0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_42_47_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => p_10_in(0),
      O => empty_ff_reg_4(27)
    );
\MemArray_reg_0_3_42_47_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][rid]\(9),
      O => empty_ff_reg_4(26)
    );
MemArray_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(25 downto 24),
      DIB(1 downto 0) => DataIn(27 downto 26),
      DIC(1 downto 0) => DataIn(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(49 downto 48),
      DOB(1 downto 0) => Head0_0(51 downto 50),
      DOC(1 downto 0) => Head0_0(53 downto 52),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
MemArray_reg_0_3_48_53_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(0),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(0),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(2),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(29)
    );
MemArray_reg_0_3_48_53_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => p_10_in(1),
      O => empty_ff_reg_4(28)
    );
MemArray_reg_0_3_48_53_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(2),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(2),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(4),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(31)
    );
MemArray_reg_0_3_48_53_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(1),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(1),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(3),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(30)
    );
MemArray_reg_0_3_48_53_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(4),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(4),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(6),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(33)
    );
MemArray_reg_0_3_48_53_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(3),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(3),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(5),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(32)
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(31 downto 30),
      DIB(1 downto 0) => DataIn(33 downto 32),
      DIC(1 downto 0) => DataIn(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(55 downto 54),
      DOB(1 downto 0) => Head0_0(57 downto 56),
      DOC(1 downto 0) => Head0_0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
MemArray_reg_0_3_54_59_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(6),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(6),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(8),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(35)
    );
MemArray_reg_0_3_54_59_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(5),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(5),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(7),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(34)
    );
MemArray_reg_0_3_54_59_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(8),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(8),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(10),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(37)
    );
MemArray_reg_0_3_54_59_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(7),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(7),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(9),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(36)
    );
MemArray_reg_0_3_54_59_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(10),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(10),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(12),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(39)
    );
MemArray_reg_0_3_54_59_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(9),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(9),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(11),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(38)
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(37 downto 36),
      DIB(1 downto 0) => DataIn(39 downto 38),
      DIC(1 downto 0) => DataIn(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(61 downto 60),
      DOB(1 downto 0) => Head0_0(63 downto 62),
      DOC(1 downto 0) => Head0_0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_60_65_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(12),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(12),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(14),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(41)
    );
\MemArray_reg_0_3_60_65_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(11),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(11),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(13),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(40)
    );
\MemArray_reg_0_3_60_65_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(14),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(14),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(16),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(43)
    );
\MemArray_reg_0_3_60_65_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(13),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(13),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(15),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(42)
    );
\MemArray_reg_0_3_60_65_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(16),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(16),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(18),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(45)
    );
\MemArray_reg_0_3_60_65_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(15),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(15),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(17),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(44)
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(43 downto 42),
      DIB(1 downto 0) => DataIn(45 downto 44),
      DIC(1 downto 0) => DataIn(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(67 downto 66),
      DOB(1 downto 0) => Head0_0(69 downto 68),
      DOC(1 downto 0) => Head0_0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_66_71_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(18),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(18),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(20),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(47)
    );
\MemArray_reg_0_3_66_71_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(17),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(17),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(19),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(46)
    );
\MemArray_reg_0_3_66_71_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(20),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(20),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(22),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(49)
    );
\MemArray_reg_0_3_66_71_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(19),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(19),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(21),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(48)
    );
\MemArray_reg_0_3_66_71_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(22),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(22),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(24),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(51)
    );
\MemArray_reg_0_3_66_71_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(21),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(21),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(23),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(50)
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => DataIn(6),
      DIB(0) => '0',
      DIC(1 downto 0) => DataIn(8 downto 7),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0_0(9 downto 8),
      DOC(1 downto 0) => Head0_0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_6_11_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(0),
      O => empty_ff_reg_4(7)
    );
\MemArray_reg_0_3_6_11_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][aln]\(5),
      O => empty_ff_reg_4(6)
    );
\MemArray_reg_0_3_6_11_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"040F"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \c2h_xdma_wrq_req[0][byte_len]\(2),
      I2 => arbstall,
      I3 => \Head_reg[111]_0\,
      O => empty_ff_reg_4(9)
    );
\MemArray_reg_0_3_6_11_i_4__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => arbstall,
      I2 => \Head_reg[111]_0\,
      I3 => \c2h_xdma_wrq_req[0][byte_len]\(1),
      O => empty_ff_reg_4(8)
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(49 downto 48),
      DIB(1 downto 0) => DataIn(51 downto 50),
      DIC(1 downto 0) => DataIn(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(73 downto 72),
      DOB(1 downto 0) => Head0_0(75 downto 74),
      DOC(1 downto 0) => Head0_0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_72_77_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(24),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(24),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(26),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(53)
    );
\MemArray_reg_0_3_72_77_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(23),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(23),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(25),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(52)
    );
\MemArray_reg_0_3_72_77_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(26),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(26),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(28),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(55)
    );
\MemArray_reg_0_3_72_77_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(25),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(25),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(27),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(54)
    );
\MemArray_reg_0_3_72_77_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(28),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(28),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(30),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(57)
    );
\MemArray_reg_0_3_72_77_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(27),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(27),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(29),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(56)
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(55 downto 54),
      DIB(1 downto 0) => DataIn(57 downto 56),
      DIC(1 downto 0) => DataIn(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(79 downto 78),
      DOB(1 downto 0) => Head0_0(81 downto 80),
      DOC(1 downto 0) => Head0_0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_78_83_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(30),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(30),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(32),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(59)
    );
\MemArray_reg_0_3_78_83_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(29),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(29),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(31),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(58)
    );
\MemArray_reg_0_3_78_83_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(32),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(32),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(34),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(61)
    );
\MemArray_reg_0_3_78_83_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(31),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(31),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(33),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(60)
    );
\MemArray_reg_0_3_78_83_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(34),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(34),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(36),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(63)
    );
\MemArray_reg_0_3_78_83_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(33),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(33),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(35),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(62)
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(61 downto 60),
      DIB(1 downto 0) => DataIn(63 downto 62),
      DIC(1 downto 0) => DataIn(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(85 downto 84),
      DOB(1 downto 0) => Head0_0(87 downto 86),
      DOC(1 downto 0) => Head0_0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_84_89_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(36),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(36),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(38),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(65)
    );
\MemArray_reg_0_3_84_89_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(35),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(35),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(37),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(64)
    );
\MemArray_reg_0_3_84_89_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(38),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(38),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(40),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(67)
    );
\MemArray_reg_0_3_84_89_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(37),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(37),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(39),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(66)
    );
\MemArray_reg_0_3_84_89_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(40),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(40),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(42),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(69)
    );
\MemArray_reg_0_3_84_89_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(39),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(39),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(41),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(68)
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(67 downto 66),
      DIB(1 downto 0) => DataIn(69 downto 68),
      DIC(1 downto 0) => DataIn(71 downto 70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(91 downto 90),
      DOB(1 downto 0) => Head0_0(93 downto 92),
      DOC(1 downto 0) => Head0_0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_90_95_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(42),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(42),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(44),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(71)
    );
\MemArray_reg_0_3_90_95_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(41),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(41),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(43),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(70)
    );
\MemArray_reg_0_3_90_95_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(44),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(44),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(46),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(73)
    );
\MemArray_reg_0_3_90_95_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(43),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(43),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(45),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(72)
    );
\MemArray_reg_0_3_90_95_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(46),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(46),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(48),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(75)
    );
\MemArray_reg_0_3_90_95_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(45),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(45),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(47),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(74)
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(73 downto 72),
      DIB(1 downto 0) => DataIn(75 downto 74),
      DIC(1 downto 0) => DataIn(77 downto 76),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0_0(97 downto 96),
      DOB(1 downto 0) => Head0_0(99 downto 98),
      DOC(1 downto 0) => Head0_0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_96_101_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(48),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(48),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(50),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(77)
    );
\MemArray_reg_0_3_96_101_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(47),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(47),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(49),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(76)
    );
\MemArray_reg_0_3_96_101_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(50),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(50),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(52),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(79)
    );
\MemArray_reg_0_3_96_101_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(49),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(49),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(51),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(78)
    );
\MemArray_reg_0_3_96_101_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(52),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(52),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(54),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(81)
    );
\MemArray_reg_0_3_96_101_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAC00AC00AC00"
    )
        port map (
      I0 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112\(51),
      I1 => \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112_0\(51),
      I2 => \wbk_xdma_wrq_req[rid]\(0),
      I3 => \Head_reg[110]_0\,
      I4 => p_10_in(53),
      I5 => \^empty_ff_reg_1\,
      O => empty_ff_reg_4(80)
    );
\RdPtr[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555559A9A9AAA"
    )
        port map (
      I0 => RdPtr(0),
      I1 => \^empty_ff_reg_0\,
      I2 => \^empty_ff_reg_1\,
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => Head1,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55577777AAA88888"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \RdPtr[1]_i_3_n_0\,
      I5 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0103010100000000"
    )
        port map (
      I0 => FifoCntrRd(0),
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => \^empty_ff_reg_0\,
      I4 => \^empty_ff_reg_1\,
      I5 => wrq_vld_303,
      O => Head1
    );
\RdPtr[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^empty_ff_reg_1\,
      I1 => \^empty_ff_reg_0\,
      O => \RdPtr[1]_i_3_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\WrPtr[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wrq_vld_303,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wrq_vld_303,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
\empty_ff_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_0\,
      I4 => \empty_ff_i_2__1_n_0\,
      I5 => empty_ff_reg_5,
      O => \empty_ff_i_1__1_n_0\
    );
\empty_ff_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABABABAAABAAAB"
    )
        port map (
      I0 => cfg_linkdown_nn1,
      I1 => FifoCntrRd(2),
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(0),
      I4 => \^empty_ff_reg_0\,
      I5 => \^empty_ff_reg_1\,
      O => \empty_ff_i_2__1_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__1_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
\full_ff_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => wrq_vld_303,
      I3 => FifoCntrWr(2),
      I4 => full_ff_reg_n_0,
      O => \full_ff_i_1__0_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__0_n_0\,
      Q => full_ff_reg_n_0,
      R => \^pcie_c2h_rst_3ff_reg[0]_rep__4\
    );
wrq_vld_303_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => D(2),
      I1 => D(1),
      I2 => wrq_vld_303_reg,
      I3 => wrq_vld_303_reg_0,
      I4 => D(0),
      I5 => wrq_vld_303_i_4_n_0,
      O => wrq_vld_302
    );
wrq_vld_303_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFEFEFF"
    )
        port map (
      I0 => wrq_vld_303,
      I1 => wrq_stall_302,
      I2 => full_ff_reg_n_0,
      I3 => CO(0),
      I4 => wrq_vld_303_reg_1(0),
      I5 => wrq_vld_303_reg_2,
      O => wrq_vld_303_i_4_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3_52\ is
  port (
    I69 : out STD_LOGIC_VECTOR ( 91 downto 0 );
    empty_ff_reg_rep_0 : out STD_LOGIC;
    \Head_reg[110]_0\ : out STD_LOGIC_VECTOR ( 86 downto 0 );
    \empty_ff_reg_rep__0_0\ : out STD_LOGIC;
    p_15_in : out STD_LOGIC;
    empty_ff_reg_0 : out STD_LOGIC;
    wrq_vld_302 : out STD_LOGIC;
    \Head_reg[0]_0\ : in STD_LOGIC;
    wrq_vld_303 : in STD_LOGIC;
    cfg_linkdown_nn1 : in STD_LOGIC;
    wrq_vld_303_reg : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    wrq_vld_303_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ctl_rst : in STD_LOGIC;
    wcp_vlderr_401 : in STD_LOGIC;
    wrq_rcp_dat_err_302 : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wrq_vld_303_i_3__0_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wrq_stall_302 : in STD_LOGIC;
    full_ff_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 87 downto 0 );
    empty_ff_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3_52\ : entity is "xdma_v4_1_8_GenericFIFOHead";
end \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3_52\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFOHead__parameterized3_52\ is
  signal FifoCntrRd : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrRd[0]_i_1__15_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__15_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__8_n_0\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__17_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__17_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__16_n_0\ : STD_LOGIC;
  signal Head0 : STD_LOGIC_VECTOR ( 111 downto 0 );
  signal Head1 : STD_LOGIC;
  signal \Head[111]_i_1__8_n_0\ : STD_LOGIC;
  signal \Head[111]_i_2__0_n_0\ : STD_LOGIC;
  signal \Head[36]_i_1__2_n_0\ : STD_LOGIC;
  signal \Head[46]_i_1__4_n_0\ : STD_LOGIC;
  signal \Head[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \^head_reg[110]_0\ : STD_LOGIC_VECTOR ( 86 downto 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[1]_i_3__3_n_0\ : STD_LOGIC;
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \empty_ff_i_1__4_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__9_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \^empty_ff_reg_rep_0\ : STD_LOGIC;
  signal \^empty_ff_reg_rep__0_0\ : STD_LOGIC;
  signal \empty_ff_rep__0_i_1_n_0\ : STD_LOGIC;
  signal empty_ff_rep_i_1_n_0 : STD_LOGIC;
  signal \full_ff_i_1__2_n_0\ : STD_LOGIC;
  signal full_ff_reg_n_0 : STD_LOGIC;
  signal \h2c_xdma_wrq_req[0][byte_len]\ : STD_LOGIC_VECTOR ( 27 to 27 );
  signal \h2c_xdma_wrq_req[0][eod]\ : STD_LOGIC;
  signal \h2c_xdma_wrq_req[0][eop]\ : STD_LOGIC;
  signal \h2c_xdma_wrq_req[0][err]\ : STD_LOGIC;
  signal \h2c_xdma_wrq_req[0][rid]\ : STD_LOGIC_VECTOR ( 9 to 9 );
  signal p_0_in1_in : STD_LOGIC_VECTOR ( 110 downto 0 );
  signal \wrq_vld_303_i_3__0_n_0\ : STD_LOGIC;
  signal wrq_vld_303_i_6_n_0 : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_111_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_108_111_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__15\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1__15\ : label is "soft_lutpair635";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__17\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__17\ : label is "soft_lutpair636";
  attribute SOFT_HLUTNM of \Head[0]_i_1__2\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \Head[100]_i_1__4\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \Head[101]_i_1__4\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \Head[102]_i_1__4\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \Head[103]_i_1__4\ : label is "soft_lutpair681";
  attribute SOFT_HLUTNM of \Head[104]_i_1__4\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \Head[105]_i_1__4\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \Head[106]_i_1__4\ : label is "soft_lutpair659";
  attribute SOFT_HLUTNM of \Head[107]_i_1__4\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \Head[108]_i_1__4\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \Head[109]_i_1__4\ : label is "soft_lutpair682";
  attribute SOFT_HLUTNM of \Head[10]_i_1__3\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \Head[110]_i_1__4\ : label is "soft_lutpair644";
  attribute SOFT_HLUTNM of \Head[111]_i_2__0\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \Head[11]_i_1__3\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \Head[12]_i_1__3\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \Head[13]_i_1__3\ : label is "soft_lutpair669";
  attribute SOFT_HLUTNM of \Head[14]_i_1__3\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \Head[15]_i_1__3\ : label is "soft_lutpair661";
  attribute SOFT_HLUTNM of \Head[16]_i_1__2\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \Head[17]_i_1__2\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \Head[18]_i_1__3\ : label is "soft_lutpair646";
  attribute SOFT_HLUTNM of \Head[19]_i_1__3\ : label is "soft_lutpair670";
  attribute SOFT_HLUTNM of \Head[1]_i_1__2\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \Head[20]_i_1__4\ : label is "soft_lutpair638";
  attribute SOFT_HLUTNM of \Head[21]_i_1__4\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \Head[2]_i_1__0\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \Head[36]_i_1__2\ : label is "soft_lutpair645";
  attribute SOFT_HLUTNM of \Head[37]_i_1__2\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \Head[38]_i_1__2\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \Head[39]_i_1__2\ : label is "soft_lutpair662";
  attribute SOFT_HLUTNM of \Head[3]_i_1__2\ : label is "soft_lutpair660";
  attribute SOFT_HLUTNM of \Head[40]_i_1__2\ : label is "soft_lutpair654";
  attribute SOFT_HLUTNM of \Head[41]_i_1__1\ : label is "soft_lutpair671";
  attribute SOFT_HLUTNM of \Head[46]_i_1__4\ : label is "soft_lutpair652";
  attribute SOFT_HLUTNM of \Head[47]_i_1__2\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \Head[48]_i_1__2\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \Head[49]_i_1__2\ : label is "soft_lutpair672";
  attribute SOFT_HLUTNM of \Head[4]_i_1__2\ : label is "soft_lutpair653";
  attribute SOFT_HLUTNM of \Head[50]_i_1__2\ : label is "soft_lutpair639";
  attribute SOFT_HLUTNM of \Head[51]_i_1__2\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \Head[52]_i_1__2\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \Head[53]_i_1__2\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \Head[54]_i_1__2\ : label is "soft_lutpair647";
  attribute SOFT_HLUTNM of \Head[55]_i_1__2\ : label is "soft_lutpair673";
  attribute SOFT_HLUTNM of \Head[56]_i_1__3\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \Head[57]_i_1__3\ : label is "soft_lutpair663";
  attribute SOFT_HLUTNM of \Head[58]_i_1__3\ : label is "soft_lutpair655";
  attribute SOFT_HLUTNM of \Head[59]_i_1__3\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \Head[5]_i_1__2\ : label is "soft_lutpair668";
  attribute SOFT_HLUTNM of \Head[60]_i_1__3\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \Head[61]_i_1__4\ : label is "soft_lutpair674";
  attribute SOFT_HLUTNM of \Head[62]_i_1__4\ : label is "soft_lutpair640";
  attribute SOFT_HLUTNM of \Head[63]_i_1__4\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \Head[64]_i_1__4\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \Head[65]_i_1__4\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \Head[66]_i_1__4\ : label is "soft_lutpair648";
  attribute SOFT_HLUTNM of \Head[67]_i_1__4\ : label is "soft_lutpair675";
  attribute SOFT_HLUTNM of \Head[68]_i_1__4\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \Head[69]_i_1__4\ : label is "soft_lutpair664";
  attribute SOFT_HLUTNM of \Head[70]_i_1__4\ : label is "soft_lutpair656";
  attribute SOFT_HLUTNM of \Head[71]_i_1__4\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \Head[72]_i_1__4\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \Head[73]_i_1__4\ : label is "soft_lutpair676";
  attribute SOFT_HLUTNM of \Head[74]_i_1__4\ : label is "soft_lutpair641";
  attribute SOFT_HLUTNM of \Head[75]_i_1__4\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \Head[76]_i_1__4\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \Head[77]_i_1__4\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \Head[78]_i_1__4\ : label is "soft_lutpair649";
  attribute SOFT_HLUTNM of \Head[79]_i_1__4\ : label is "soft_lutpair677";
  attribute SOFT_HLUTNM of \Head[80]_i_1__4\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \Head[81]_i_1__4\ : label is "soft_lutpair665";
  attribute SOFT_HLUTNM of \Head[82]_i_1__4\ : label is "soft_lutpair657";
  attribute SOFT_HLUTNM of \Head[83]_i_1__4\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \Head[84]_i_1__4\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \Head[85]_i_1__4\ : label is "soft_lutpair678";
  attribute SOFT_HLUTNM of \Head[86]_i_1__4\ : label is "soft_lutpair642";
  attribute SOFT_HLUTNM of \Head[87]_i_1__4\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \Head[88]_i_1__4\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \Head[89]_i_1__4\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \Head[8]_i_1__4\ : label is "soft_lutpair637";
  attribute SOFT_HLUTNM of \Head[90]_i_1__4\ : label is "soft_lutpair650";
  attribute SOFT_HLUTNM of \Head[91]_i_1__4\ : label is "soft_lutpair679";
  attribute SOFT_HLUTNM of \Head[92]_i_1__4\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \Head[93]_i_1__4\ : label is "soft_lutpair666";
  attribute SOFT_HLUTNM of \Head[94]_i_1__4\ : label is "soft_lutpair658";
  attribute SOFT_HLUTNM of \Head[95]_i_1__4\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \Head[96]_i_1__4\ : label is "soft_lutpair651";
  attribute SOFT_HLUTNM of \Head[97]_i_1__4\ : label is "soft_lutpair680";
  attribute SOFT_HLUTNM of \Head[98]_i_1__4\ : label is "soft_lutpair643";
  attribute SOFT_HLUTNM of \Head[99]_i_1__4\ : label is "soft_lutpair667";
  attribute SOFT_HLUTNM of \Head[9]_i_1__3\ : label is "soft_lutpair661";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 448;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_102_107 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_102_107 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_102_107 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_102_107 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_102_107 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_102_107 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_102_107 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_3_102_107 : label is 107;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_108_111 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_108_111 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_108_111 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_108_111 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_108_111 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_108_111 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_108_111 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_108_111 : label is 108;
  attribute ram_slice_end of MemArray_reg_0_3_108_111 : label is 111;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_36_41 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_36_41 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_3_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_42_47 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_42_47 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_3_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_48_53 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_48_53 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_3_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_54_59 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_54_59 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_3_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_60_65 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_60_65 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_3_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_66_71 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_66_71 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_3_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_72_77 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_72_77 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_3_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_78_83 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_78_83 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_3_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_84_89 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_84_89 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_3_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_90_95 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_90_95 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_3_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_96_101 : label is 448;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_96_101 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_3_96_101 : label is 101;
  attribute SOFT_HLUTNM of \WrPtr[0]_i_1__4\ : label is "soft_lutpair683";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__4\ : label is "soft_lutpair683";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of empty_ff_reg : label is "empty_ff_reg";
  attribute ORIG_CELL_NAME of empty_ff_reg_rep : label is "empty_ff_reg";
  attribute ORIG_CELL_NAME of \empty_ff_reg_rep__0\ : label is "empty_ff_reg";
begin
  \Head_reg[110]_0\(86 downto 0) <= \^head_reg[110]_0\(86 downto 0);
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  empty_ff_reg_rep_0 <= \^empty_ff_reg_rep_0\;
  \empty_ff_reg_rep__0_0\ <= \^empty_ff_reg_rep__0_0\;
\FifoCntrRd[0]_i_1__15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => wrq_vld_303,
      I3 => FifoCntrRd(0),
      O => \FifoCntrRd[0]_i_1__15_n_0\
    );
\FifoCntrRd[1]_i_1__15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1FFEE001"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => FifoCntrRd(0),
      I3 => wrq_vld_303,
      I4 => FifoCntrRd(1),
      O => \FifoCntrRd[1]_i_1__15_n_0\
    );
\FifoCntrRd[2]_i_2__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFFFFFEE0000001"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(1),
      I4 => wrq_vld_303,
      I5 => FifoCntrRd(2),
      O => \FifoCntrRd[2]_i_2__8_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1__15_n_0\,
      Q => FifoCntrRd(0),
      R => full_ff_reg_0
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1__15_n_0\,
      Q => FifoCntrRd(1),
      R => full_ff_reg_0
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_2__8_n_0\,
      Q => FifoCntrRd(2),
      R => full_ff_reg_0
    );
\FifoCntrWr[0]_i_1__17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \Head_reg[0]_0\,
      I2 => wrq_vld_303,
      I3 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__17_n_0\
    );
\FifoCntrWr[1]_i_1__17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1FFEE001"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \Head_reg[0]_0\,
      I2 => FifoCntrWr(0),
      I3 => wrq_vld_303,
      I4 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__17_n_0\
    );
\FifoCntrWr[2]_i_1__16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1FFFFFFEE0000001"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => \Head_reg[0]_0\,
      I2 => FifoCntrWr(0),
      I3 => FifoCntrWr(1),
      I4 => wrq_vld_303,
      I5 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1__16_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1__17_n_0\,
      Q => FifoCntrWr(0),
      R => full_ff_reg_0
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1__17_n_0\,
      Q => FifoCntrWr(1),
      R => full_ff_reg_0
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1__16_n_0\,
      Q => FifoCntrWr(2),
      R => full_ff_reg_0
    );
\Head[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(0),
      I1 => Head0(0),
      I2 => Head1,
      O => p_0_in1_in(0)
    );
\Head[100]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(77),
      I1 => Head0(100),
      I2 => Head1,
      O => p_0_in1_in(100)
    );
\Head[101]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(78),
      I1 => Head0(101),
      I2 => Head1,
      O => p_0_in1_in(101)
    );
\Head[102]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(79),
      I1 => Head0(102),
      I2 => Head1,
      O => p_0_in1_in(102)
    );
\Head[103]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(80),
      I1 => Head0(103),
      I2 => Head1,
      O => p_0_in1_in(103)
    );
\Head[104]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(81),
      I1 => Head0(104),
      I2 => Head1,
      O => p_0_in1_in(104)
    );
\Head[105]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(82),
      I1 => Head0(105),
      I2 => Head1,
      O => p_0_in1_in(105)
    );
\Head[106]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(83),
      I1 => Head0(106),
      I2 => Head1,
      O => p_0_in1_in(106)
    );
\Head[107]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(84),
      I1 => Head0(107),
      I2 => Head1,
      O => p_0_in1_in(107)
    );
\Head[108]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(85),
      I1 => Head0(108),
      I2 => Head1,
      O => p_0_in1_in(108)
    );
\Head[109]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(86),
      I1 => Head0(109),
      I2 => Head1,
      O => p_0_in1_in(109)
    );
\Head[10]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(7),
      I1 => Head0(10),
      I2 => Head1,
      O => p_0_in1_in(10)
    );
\Head[110]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(87),
      I1 => Head0(110),
      I2 => Head1,
      O => p_0_in1_in(110)
    );
\Head[111]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F1F1F1F1F1F1F1FF"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => Head1,
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => FifoCntrRd(0),
      O => \Head[111]_i_1__8_n_0\
    );
\Head[111]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(111),
      I1 => Head1,
      O => \Head[111]_i_2__0_n_0\
    );
\Head[11]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(8),
      I1 => Head0(11),
      I2 => Head1,
      O => p_0_in1_in(11)
    );
\Head[12]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(9),
      I1 => Head0(12),
      I2 => Head1,
      O => p_0_in1_in(12)
    );
\Head[13]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(10),
      I1 => Head0(13),
      I2 => Head1,
      O => p_0_in1_in(13)
    );
\Head[14]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(11),
      I1 => Head0(14),
      I2 => Head1,
      O => p_0_in1_in(14)
    );
\Head[15]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(12),
      I1 => Head0(15),
      I2 => Head1,
      O => p_0_in1_in(15)
    );
\Head[16]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(13),
      I1 => Head0(16),
      I2 => Head1,
      O => p_0_in1_in(16)
    );
\Head[17]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(14),
      I1 => Head0(17),
      I2 => Head1,
      O => p_0_in1_in(17)
    );
\Head[18]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(15),
      I1 => Head0(18),
      I2 => Head1,
      O => p_0_in1_in(18)
    );
\Head[19]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(16),
      I1 => Head0(19),
      I2 => Head1,
      O => p_0_in1_in(19)
    );
\Head[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(1),
      I1 => Head0(1),
      I2 => Head1,
      O => p_0_in1_in(1)
    );
\Head[20]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(17),
      I1 => Head0(20),
      I2 => Head1,
      O => p_0_in1_in(20)
    );
\Head[21]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(18),
      I1 => Head0(21),
      I2 => Head1,
      O => p_0_in1_in(21)
    );
\Head[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(2),
      I1 => Head0(2),
      I2 => Head1,
      O => p_0_in1_in(2)
    );
\Head[36]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(36),
      I1 => Head1,
      O => \Head[36]_i_1__2_n_0\
    );
\Head[37]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(19),
      I1 => Head0(37),
      I2 => Head1,
      O => p_0_in1_in(37)
    );
\Head[38]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(20),
      I1 => Head0(38),
      I2 => Head1,
      O => p_0_in1_in(38)
    );
\Head[39]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(21),
      I1 => Head0(39),
      I2 => Head1,
      O => p_0_in1_in(39)
    );
\Head[3]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(3),
      I1 => Head0(3),
      I2 => Head1,
      O => p_0_in1_in(3)
    );
\Head[40]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(22),
      I1 => Head0(40),
      I2 => Head1,
      O => p_0_in1_in(40)
    );
\Head[41]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(23),
      I1 => Head0(41),
      I2 => Head1,
      O => p_0_in1_in(41)
    );
\Head[46]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(46),
      I1 => Head1,
      O => \Head[46]_i_1__4_n_0\
    );
\Head[47]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(24),
      I1 => Head0(47),
      I2 => Head1,
      O => p_0_in1_in(47)
    );
\Head[48]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(25),
      I1 => Head0(48),
      I2 => Head1,
      O => p_0_in1_in(48)
    );
\Head[49]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(26),
      I1 => Head0(49),
      I2 => Head1,
      O => p_0_in1_in(49)
    );
\Head[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(4),
      I1 => Head0(4),
      I2 => Head1,
      O => p_0_in1_in(4)
    );
\Head[50]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(27),
      I1 => Head0(50),
      I2 => Head1,
      O => p_0_in1_in(50)
    );
\Head[51]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(28),
      I1 => Head0(51),
      I2 => Head1,
      O => p_0_in1_in(51)
    );
\Head[52]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(29),
      I1 => Head0(52),
      I2 => Head1,
      O => p_0_in1_in(52)
    );
\Head[53]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(30),
      I1 => Head0(53),
      I2 => Head1,
      O => p_0_in1_in(53)
    );
\Head[54]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(31),
      I1 => Head0(54),
      I2 => Head1,
      O => p_0_in1_in(54)
    );
\Head[55]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(32),
      I1 => Head0(55),
      I2 => Head1,
      O => p_0_in1_in(55)
    );
\Head[56]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(33),
      I1 => Head0(56),
      I2 => Head1,
      O => p_0_in1_in(56)
    );
\Head[57]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(34),
      I1 => Head0(57),
      I2 => Head1,
      O => p_0_in1_in(57)
    );
\Head[58]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(35),
      I1 => Head0(58),
      I2 => Head1,
      O => p_0_in1_in(58)
    );
\Head[59]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(36),
      I1 => Head0(59),
      I2 => Head1,
      O => p_0_in1_in(59)
    );
\Head[5]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(5),
      I1 => Head0(5),
      I2 => Head1,
      O => p_0_in1_in(5)
    );
\Head[60]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(37),
      I1 => Head0(60),
      I2 => Head1,
      O => p_0_in1_in(60)
    );
\Head[61]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(38),
      I1 => Head0(61),
      I2 => Head1,
      O => p_0_in1_in(61)
    );
\Head[62]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(39),
      I1 => Head0(62),
      I2 => Head1,
      O => p_0_in1_in(62)
    );
\Head[63]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(40),
      I1 => Head0(63),
      I2 => Head1,
      O => p_0_in1_in(63)
    );
\Head[64]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(41),
      I1 => Head0(64),
      I2 => Head1,
      O => p_0_in1_in(64)
    );
\Head[65]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(42),
      I1 => Head0(65),
      I2 => Head1,
      O => p_0_in1_in(65)
    );
\Head[66]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(43),
      I1 => Head0(66),
      I2 => Head1,
      O => p_0_in1_in(66)
    );
\Head[67]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(44),
      I1 => Head0(67),
      I2 => Head1,
      O => p_0_in1_in(67)
    );
\Head[68]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(45),
      I1 => Head0(68),
      I2 => Head1,
      O => p_0_in1_in(68)
    );
\Head[69]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(46),
      I1 => Head0(69),
      I2 => Head1,
      O => p_0_in1_in(69)
    );
\Head[70]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(47),
      I1 => Head0(70),
      I2 => Head1,
      O => p_0_in1_in(70)
    );
\Head[71]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(48),
      I1 => Head0(71),
      I2 => Head1,
      O => p_0_in1_in(71)
    );
\Head[72]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(49),
      I1 => Head0(72),
      I2 => Head1,
      O => p_0_in1_in(72)
    );
\Head[73]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(50),
      I1 => Head0(73),
      I2 => Head1,
      O => p_0_in1_in(73)
    );
\Head[74]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(51),
      I1 => Head0(74),
      I2 => Head1,
      O => p_0_in1_in(74)
    );
\Head[75]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(52),
      I1 => Head0(75),
      I2 => Head1,
      O => p_0_in1_in(75)
    );
\Head[76]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(53),
      I1 => Head0(76),
      I2 => Head1,
      O => p_0_in1_in(76)
    );
\Head[77]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(54),
      I1 => Head0(77),
      I2 => Head1,
      O => p_0_in1_in(77)
    );
\Head[78]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(55),
      I1 => Head0(78),
      I2 => Head1,
      O => p_0_in1_in(78)
    );
\Head[79]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(56),
      I1 => Head0(79),
      I2 => Head1,
      O => p_0_in1_in(79)
    );
\Head[80]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(57),
      I1 => Head0(80),
      I2 => Head1,
      O => p_0_in1_in(80)
    );
\Head[81]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(58),
      I1 => Head0(81),
      I2 => Head1,
      O => p_0_in1_in(81)
    );
\Head[82]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(59),
      I1 => Head0(82),
      I2 => Head1,
      O => p_0_in1_in(82)
    );
\Head[83]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(60),
      I1 => Head0(83),
      I2 => Head1,
      O => p_0_in1_in(83)
    );
\Head[84]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(61),
      I1 => Head0(84),
      I2 => Head1,
      O => p_0_in1_in(84)
    );
\Head[85]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(62),
      I1 => Head0(85),
      I2 => Head1,
      O => p_0_in1_in(85)
    );
\Head[86]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(63),
      I1 => Head0(86),
      I2 => Head1,
      O => p_0_in1_in(86)
    );
\Head[87]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(64),
      I1 => Head0(87),
      I2 => Head1,
      O => p_0_in1_in(87)
    );
\Head[88]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(65),
      I1 => Head0(88),
      I2 => Head1,
      O => p_0_in1_in(88)
    );
\Head[89]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(66),
      I1 => Head0(89),
      I2 => Head1,
      O => p_0_in1_in(89)
    );
\Head[8]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Head0(8),
      I1 => Head1,
      O => \Head[8]_i_1__4_n_0\
    );
\Head[90]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(67),
      I1 => Head0(90),
      I2 => Head1,
      O => p_0_in1_in(90)
    );
\Head[91]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(68),
      I1 => Head0(91),
      I2 => Head1,
      O => p_0_in1_in(91)
    );
\Head[92]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(69),
      I1 => Head0(92),
      I2 => Head1,
      O => p_0_in1_in(92)
    );
\Head[93]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(70),
      I1 => Head0(93),
      I2 => Head1,
      O => p_0_in1_in(93)
    );
\Head[94]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(71),
      I1 => Head0(94),
      I2 => Head1,
      O => p_0_in1_in(94)
    );
\Head[95]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(72),
      I1 => Head0(95),
      I2 => Head1,
      O => p_0_in1_in(95)
    );
\Head[96]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(73),
      I1 => Head0(96),
      I2 => Head1,
      O => p_0_in1_in(96)
    );
\Head[97]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(74),
      I1 => Head0(97),
      I2 => Head1,
      O => p_0_in1_in(97)
    );
\Head[98]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(75),
      I1 => Head0(98),
      I2 => Head1,
      O => p_0_in1_in(98)
    );
\Head[99]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(76),
      I1 => Head0(99),
      I2 => Head1,
      O => p_0_in1_in(99)
    );
\Head[9]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AC"
    )
        port map (
      I0 => DataIn(6),
      I1 => Head0(9),
      I2 => Head1,
      O => p_0_in1_in(9)
    );
\Head_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(0),
      Q => \^head_reg[110]_0\(0),
      R => full_ff_reg_0
    );
\Head_reg[100]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(100),
      Q => \^head_reg[110]_0\(76),
      R => full_ff_reg_0
    );
\Head_reg[101]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(101),
      Q => \^head_reg[110]_0\(77),
      R => full_ff_reg_0
    );
\Head_reg[102]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(102),
      Q => \^head_reg[110]_0\(78),
      R => full_ff_reg_0
    );
\Head_reg[103]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(103),
      Q => \^head_reg[110]_0\(79),
      R => full_ff_reg_0
    );
\Head_reg[104]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(104),
      Q => \^head_reg[110]_0\(80),
      R => full_ff_reg_0
    );
\Head_reg[105]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(105),
      Q => \^head_reg[110]_0\(81),
      R => full_ff_reg_0
    );
\Head_reg[106]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(106),
      Q => \^head_reg[110]_0\(82),
      R => full_ff_reg_0
    );
\Head_reg[107]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(107),
      Q => \^head_reg[110]_0\(83),
      R => full_ff_reg_0
    );
\Head_reg[108]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(108),
      Q => \^head_reg[110]_0\(84),
      R => full_ff_reg_0
    );
\Head_reg[109]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(109),
      Q => \^head_reg[110]_0\(85),
      R => full_ff_reg_0
    );
\Head_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(10),
      Q => \^head_reg[110]_0\(6),
      R => full_ff_reg_0
    );
\Head_reg[110]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(110),
      Q => \^head_reg[110]_0\(86),
      R => full_ff_reg_0
    );
\Head_reg[111]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => \Head[111]_i_2__0_n_0\,
      Q => \h2c_xdma_wrq_req[0][err]\,
      R => full_ff_reg_0
    );
\Head_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(11),
      Q => \^head_reg[110]_0\(7),
      R => full_ff_reg_0
    );
\Head_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(12),
      Q => \^head_reg[110]_0\(8),
      R => full_ff_reg_0
    );
\Head_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(13),
      Q => \^head_reg[110]_0\(9),
      R => full_ff_reg_0
    );
\Head_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(14),
      Q => \^head_reg[110]_0\(10),
      R => full_ff_reg_0
    );
\Head_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(15),
      Q => \^head_reg[110]_0\(11),
      R => full_ff_reg_0
    );
\Head_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(16),
      Q => \^head_reg[110]_0\(12),
      R => full_ff_reg_0
    );
\Head_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(17),
      Q => \^head_reg[110]_0\(13),
      R => full_ff_reg_0
    );
\Head_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(18),
      Q => \^head_reg[110]_0\(14),
      R => full_ff_reg_0
    );
\Head_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(19),
      Q => \^head_reg[110]_0\(15),
      R => full_ff_reg_0
    );
\Head_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(1),
      Q => \h2c_xdma_wrq_req[0][eod]\,
      R => full_ff_reg_0
    );
\Head_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(20),
      Q => \^head_reg[110]_0\(16),
      R => full_ff_reg_0
    );
\Head_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(21),
      Q => \^head_reg[110]_0\(17),
      R => full_ff_reg_0
    );
\Head_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(2),
      Q => \h2c_xdma_wrq_req[0][eop]\,
      R => full_ff_reg_0
    );
\Head_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => \Head[36]_i_1__2_n_0\,
      Q => \h2c_xdma_wrq_req[0][byte_len]\(27),
      R => full_ff_reg_0
    );
\Head_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(37),
      Q => \^head_reg[110]_0\(18),
      R => full_ff_reg_0
    );
\Head_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(38),
      Q => \^head_reg[110]_0\(19),
      R => full_ff_reg_0
    );
\Head_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(39),
      Q => \^head_reg[110]_0\(20),
      R => full_ff_reg_0
    );
\Head_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(3),
      Q => \^head_reg[110]_0\(1),
      R => full_ff_reg_0
    );
\Head_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(40),
      Q => \^head_reg[110]_0\(21),
      R => full_ff_reg_0
    );
\Head_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(41),
      Q => \^head_reg[110]_0\(22),
      R => full_ff_reg_0
    );
\Head_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => \Head[46]_i_1__4_n_0\,
      Q => \h2c_xdma_wrq_req[0][rid]\(9),
      R => full_ff_reg_0
    );
\Head_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(47),
      Q => \^head_reg[110]_0\(23),
      R => full_ff_reg_0
    );
\Head_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(48),
      Q => \^head_reg[110]_0\(24),
      R => full_ff_reg_0
    );
\Head_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(49),
      Q => \^head_reg[110]_0\(25),
      R => full_ff_reg_0
    );
\Head_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(4),
      Q => \^head_reg[110]_0\(2),
      R => full_ff_reg_0
    );
\Head_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(50),
      Q => \^head_reg[110]_0\(26),
      R => full_ff_reg_0
    );
\Head_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(51),
      Q => \^head_reg[110]_0\(27),
      R => full_ff_reg_0
    );
\Head_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(52),
      Q => \^head_reg[110]_0\(28),
      R => full_ff_reg_0
    );
\Head_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(53),
      Q => \^head_reg[110]_0\(29),
      R => full_ff_reg_0
    );
\Head_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(54),
      Q => \^head_reg[110]_0\(30),
      R => full_ff_reg_0
    );
\Head_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(55),
      Q => \^head_reg[110]_0\(31),
      R => full_ff_reg_0
    );
\Head_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(56),
      Q => \^head_reg[110]_0\(32),
      R => full_ff_reg_0
    );
\Head_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(57),
      Q => \^head_reg[110]_0\(33),
      R => full_ff_reg_0
    );
\Head_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(58),
      Q => \^head_reg[110]_0\(34),
      R => full_ff_reg_0
    );
\Head_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(59),
      Q => \^head_reg[110]_0\(35),
      R => full_ff_reg_0
    );
\Head_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(5),
      Q => \^head_reg[110]_0\(3),
      R => full_ff_reg_0
    );
\Head_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(60),
      Q => \^head_reg[110]_0\(36),
      R => full_ff_reg_0
    );
\Head_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(61),
      Q => \^head_reg[110]_0\(37),
      R => full_ff_reg_0
    );
\Head_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(62),
      Q => \^head_reg[110]_0\(38),
      R => full_ff_reg_0
    );
\Head_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(63),
      Q => \^head_reg[110]_0\(39),
      R => full_ff_reg_0
    );
\Head_reg[64]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(64),
      Q => \^head_reg[110]_0\(40),
      R => full_ff_reg_0
    );
\Head_reg[65]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(65),
      Q => \^head_reg[110]_0\(41),
      R => full_ff_reg_0
    );
\Head_reg[66]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(66),
      Q => \^head_reg[110]_0\(42),
      R => full_ff_reg_0
    );
\Head_reg[67]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(67),
      Q => \^head_reg[110]_0\(43),
      R => full_ff_reg_0
    );
\Head_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(68),
      Q => \^head_reg[110]_0\(44),
      R => full_ff_reg_0
    );
\Head_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(69),
      Q => \^head_reg[110]_0\(45),
      R => full_ff_reg_0
    );
\Head_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(70),
      Q => \^head_reg[110]_0\(46),
      R => full_ff_reg_0
    );
\Head_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(71),
      Q => \^head_reg[110]_0\(47),
      R => full_ff_reg_0
    );
\Head_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(72),
      Q => \^head_reg[110]_0\(48),
      R => full_ff_reg_0
    );
\Head_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(73),
      Q => \^head_reg[110]_0\(49),
      R => full_ff_reg_0
    );
\Head_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(74),
      Q => \^head_reg[110]_0\(50),
      R => full_ff_reg_0
    );
\Head_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(75),
      Q => \^head_reg[110]_0\(51),
      R => full_ff_reg_0
    );
\Head_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(76),
      Q => \^head_reg[110]_0\(52),
      R => full_ff_reg_0
    );
\Head_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(77),
      Q => \^head_reg[110]_0\(53),
      R => full_ff_reg_0
    );
\Head_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(78),
      Q => \^head_reg[110]_0\(54),
      R => full_ff_reg_0
    );
\Head_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(79),
      Q => \^head_reg[110]_0\(55),
      R => full_ff_reg_0
    );
\Head_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(80),
      Q => \^head_reg[110]_0\(56),
      R => full_ff_reg_0
    );
\Head_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(81),
      Q => \^head_reg[110]_0\(57),
      R => full_ff_reg_0
    );
\Head_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(82),
      Q => \^head_reg[110]_0\(58),
      R => full_ff_reg_0
    );
\Head_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(83),
      Q => \^head_reg[110]_0\(59),
      R => full_ff_reg_0
    );
\Head_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(84),
      Q => \^head_reg[110]_0\(60),
      R => full_ff_reg_0
    );
\Head_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(85),
      Q => \^head_reg[110]_0\(61),
      R => full_ff_reg_0
    );
\Head_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(86),
      Q => \^head_reg[110]_0\(62),
      R => full_ff_reg_0
    );
\Head_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(87),
      Q => \^head_reg[110]_0\(63),
      R => full_ff_reg_0
    );
\Head_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(88),
      Q => \^head_reg[110]_0\(64),
      R => full_ff_reg_0
    );
\Head_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(89),
      Q => \^head_reg[110]_0\(65),
      R => full_ff_reg_0
    );
\Head_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => \Head[8]_i_1__4_n_0\,
      Q => \^head_reg[110]_0\(4),
      R => full_ff_reg_0
    );
\Head_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(90),
      Q => \^head_reg[110]_0\(66),
      R => full_ff_reg_0
    );
\Head_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(91),
      Q => \^head_reg[110]_0\(67),
      R => full_ff_reg_0
    );
\Head_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(92),
      Q => \^head_reg[110]_0\(68),
      R => full_ff_reg_0
    );
\Head_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(93),
      Q => \^head_reg[110]_0\(69),
      R => full_ff_reg_0
    );
\Head_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(94),
      Q => \^head_reg[110]_0\(70),
      R => full_ff_reg_0
    );
\Head_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(95),
      Q => \^head_reg[110]_0\(71),
      R => full_ff_reg_0
    );
\Head_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(96),
      Q => \^head_reg[110]_0\(72),
      R => full_ff_reg_0
    );
\Head_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(97),
      Q => \^head_reg[110]_0\(73),
      R => full_ff_reg_0
    );
\Head_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(98),
      Q => \^head_reg[110]_0\(74),
      R => full_ff_reg_0
    );
\Head_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(99),
      Q => \^head_reg[110]_0\(75),
      R => full_ff_reg_0
    );
\Head_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \Head[111]_i_1__8_n_0\,
      D => p_0_in1_in(9),
      Q => \^head_reg[110]_0\(5),
      R => full_ff_reg_0
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(1 downto 0),
      DOB(1 downto 0) => Head0(3 downto 2),
      DOC(1 downto 0) => Head0(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_0_5_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      O => p_15_in
    );
\MemArray_reg_0_3_0_5_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \h2c_xdma_wrq_req[0][eod]\,
      O => I69(1)
    );
\MemArray_reg_0_3_0_5_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(0),
      O => I69(0)
    );
\MemArray_reg_0_3_0_5_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(1),
      O => I69(3)
    );
\MemArray_reg_0_3_0_5_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \h2c_xdma_wrq_req[0][eop]\,
      O => I69(2)
    );
\MemArray_reg_0_3_0_5_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(3),
      O => I69(5)
    );
\MemArray_reg_0_3_0_5_i_7__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(2),
      O => I69(4)
    );
MemArray_reg_0_3_102_107: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(80 downto 79),
      DIB(1 downto 0) => DataIn(82 downto 81),
      DIC(1 downto 0) => DataIn(84 downto 83),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(103 downto 102),
      DOB(1 downto 0) => Head0(105 downto 104),
      DOC(1 downto 0) => Head0(107 downto 106),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_102_107_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(79),
      O => I69(83)
    );
\MemArray_reg_0_3_102_107_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(78),
      O => I69(82)
    );
\MemArray_reg_0_3_102_107_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(81),
      O => I69(85)
    );
\MemArray_reg_0_3_102_107_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(80),
      O => I69(84)
    );
\MemArray_reg_0_3_102_107_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(83),
      O => I69(87)
    );
\MemArray_reg_0_3_102_107_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(82),
      O => I69(86)
    );
MemArray_reg_0_3_108_111: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(86 downto 85),
      DIB(1) => '0',
      DIB(0) => DataIn(87),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(109 downto 108),
      DOB(1 downto 0) => Head0(111 downto 110),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_108_111_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_108_111_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_108_112_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(85),
      O => I69(89)
    );
\MemArray_reg_0_3_108_112_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(84),
      O => I69(88)
    );
\MemArray_reg_0_3_108_112_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \h2c_xdma_wrq_req[0][err]\,
      O => I69(91)
    );
\MemArray_reg_0_3_108_112_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(86),
      O => I69(90)
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(10 downto 9),
      DIB(1 downto 0) => DataIn(12 downto 11),
      DIC(1 downto 0) => DataIn(14 downto 13),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(13 downto 12),
      DOB(1 downto 0) => Head0(15 downto 14),
      DOC(1 downto 0) => Head0(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_12_17_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(9),
      O => I69(11)
    );
\MemArray_reg_0_3_12_17_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(8),
      O => I69(10)
    );
\MemArray_reg_0_3_12_17_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(11),
      O => I69(13)
    );
\MemArray_reg_0_3_12_17_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(10),
      O => I69(12)
    );
\MemArray_reg_0_3_12_17_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(13),
      O => I69(15)
    );
\MemArray_reg_0_3_12_17_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(12),
      O => I69(14)
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(16 downto 15),
      DIB(1 downto 0) => DataIn(18 downto 17),
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(19 downto 18),
      DOB(1 downto 0) => Head0(21 downto 20),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_18_23_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(15),
      O => I69(17)
    );
\MemArray_reg_0_3_18_23_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(14),
      O => I69(16)
    );
\MemArray_reg_0_3_18_23_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(17),
      O => I69(19)
    );
\MemArray_reg_0_3_18_23_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(16),
      O => I69(18)
    );
MemArray_reg_0_3_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1) => DataIn(19),
      DIA(0) => '0',
      DIB(1 downto 0) => DataIn(21 downto 20),
      DIC(1 downto 0) => DataIn(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(37 downto 36),
      DOB(1 downto 0) => Head0(39 downto 38),
      DOC(1 downto 0) => Head0(41 downto 40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_36_41_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(18),
      O => I69(21)
    );
\MemArray_reg_0_3_36_41_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \h2c_xdma_wrq_req[0][byte_len]\(27),
      O => I69(20)
    );
\MemArray_reg_0_3_36_41_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(20),
      O => I69(23)
    );
\MemArray_reg_0_3_36_41_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(19),
      O => I69(22)
    );
\MemArray_reg_0_3_36_41_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(22),
      O => I69(25)
    );
\MemArray_reg_0_3_36_41_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(21),
      O => I69(24)
    );
MemArray_reg_0_3_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => DataIn(24),
      DIC(0) => '0',
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => Head0(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_42_47_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(23),
      O => I69(27)
    );
\MemArray_reg_0_3_42_47_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \h2c_xdma_wrq_req[0][rid]\(9),
      O => I69(26)
    );
MemArray_reg_0_3_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(26 downto 25),
      DIB(1 downto 0) => DataIn(28 downto 27),
      DIC(1 downto 0) => DataIn(30 downto 29),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(49 downto 48),
      DOB(1 downto 0) => Head0(51 downto 50),
      DOC(1 downto 0) => Head0(53 downto 52),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_48_53_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(25),
      O => I69(29)
    );
\MemArray_reg_0_3_48_53_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(24),
      O => I69(28)
    );
\MemArray_reg_0_3_48_53_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(27),
      O => I69(31)
    );
\MemArray_reg_0_3_48_53_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(26),
      O => I69(30)
    );
\MemArray_reg_0_3_48_53_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(29),
      O => I69(33)
    );
\MemArray_reg_0_3_48_53_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(28),
      O => I69(32)
    );
MemArray_reg_0_3_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(32 downto 31),
      DIB(1 downto 0) => DataIn(34 downto 33),
      DIC(1 downto 0) => DataIn(36 downto 35),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(55 downto 54),
      DOB(1 downto 0) => Head0(57 downto 56),
      DOC(1 downto 0) => Head0(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_54_59_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(31),
      O => I69(35)
    );
\MemArray_reg_0_3_54_59_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(30),
      O => I69(34)
    );
\MemArray_reg_0_3_54_59_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(33),
      O => I69(37)
    );
\MemArray_reg_0_3_54_59_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(32),
      O => I69(36)
    );
\MemArray_reg_0_3_54_59_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(35),
      O => I69(39)
    );
\MemArray_reg_0_3_54_59_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(34),
      O => I69(38)
    );
MemArray_reg_0_3_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(38 downto 37),
      DIB(1 downto 0) => DataIn(40 downto 39),
      DIC(1 downto 0) => DataIn(42 downto 41),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(61 downto 60),
      DOB(1 downto 0) => Head0(63 downto 62),
      DOC(1 downto 0) => Head0(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_60_65_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(37),
      O => I69(41)
    );
\MemArray_reg_0_3_60_65_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(36),
      O => I69(40)
    );
\MemArray_reg_0_3_60_65_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(39),
      O => I69(43)
    );
\MemArray_reg_0_3_60_65_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(38),
      O => I69(42)
    );
\MemArray_reg_0_3_60_65_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(41),
      O => I69(45)
    );
\MemArray_reg_0_3_60_65_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(40),
      O => I69(44)
    );
MemArray_reg_0_3_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(44 downto 43),
      DIB(1 downto 0) => DataIn(46 downto 45),
      DIC(1 downto 0) => DataIn(48 downto 47),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(67 downto 66),
      DOB(1 downto 0) => Head0(69 downto 68),
      DOC(1 downto 0) => Head0(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_66_71_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(43),
      O => I69(47)
    );
\MemArray_reg_0_3_66_71_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(42),
      O => I69(46)
    );
\MemArray_reg_0_3_66_71_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(45),
      O => I69(49)
    );
\MemArray_reg_0_3_66_71_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(44),
      O => I69(48)
    );
\MemArray_reg_0_3_66_71_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(47),
      O => I69(51)
    );
\MemArray_reg_0_3_66_71_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(46),
      O => I69(50)
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1) => DataIn(6),
      DIB(0) => '0',
      DIC(1 downto 0) => DataIn(8 downto 7),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => Head0(9 downto 8),
      DOC(1 downto 0) => Head0(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_6_11_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(5),
      O => I69(7)
    );
\MemArray_reg_0_3_6_11_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(4),
      O => I69(6)
    );
\MemArray_reg_0_3_6_11_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(7),
      O => I69(9)
    );
\MemArray_reg_0_3_6_11_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(6),
      O => I69(8)
    );
MemArray_reg_0_3_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(50 downto 49),
      DIB(1 downto 0) => DataIn(52 downto 51),
      DIC(1 downto 0) => DataIn(54 downto 53),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(73 downto 72),
      DOB(1 downto 0) => Head0(75 downto 74),
      DOC(1 downto 0) => Head0(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_72_77_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(49),
      O => I69(53)
    );
\MemArray_reg_0_3_72_77_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(48),
      O => I69(52)
    );
\MemArray_reg_0_3_72_77_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(51),
      O => I69(55)
    );
\MemArray_reg_0_3_72_77_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(50),
      O => I69(54)
    );
\MemArray_reg_0_3_72_77_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(53),
      O => I69(57)
    );
\MemArray_reg_0_3_72_77_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(52),
      O => I69(56)
    );
MemArray_reg_0_3_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(56 downto 55),
      DIB(1 downto 0) => DataIn(58 downto 57),
      DIC(1 downto 0) => DataIn(60 downto 59),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(79 downto 78),
      DOB(1 downto 0) => Head0(81 downto 80),
      DOC(1 downto 0) => Head0(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_78_83_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(55),
      O => I69(59)
    );
\MemArray_reg_0_3_78_83_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(54),
      O => I69(58)
    );
\MemArray_reg_0_3_78_83_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(57),
      O => I69(61)
    );
\MemArray_reg_0_3_78_83_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(56),
      O => I69(60)
    );
\MemArray_reg_0_3_78_83_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(59),
      O => I69(63)
    );
\MemArray_reg_0_3_78_83_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(58),
      O => I69(62)
    );
MemArray_reg_0_3_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(62 downto 61),
      DIB(1 downto 0) => DataIn(64 downto 63),
      DIC(1 downto 0) => DataIn(66 downto 65),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(85 downto 84),
      DOB(1 downto 0) => Head0(87 downto 86),
      DOC(1 downto 0) => Head0(89 downto 88),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_84_89_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(61),
      O => I69(65)
    );
\MemArray_reg_0_3_84_89_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(60),
      O => I69(64)
    );
\MemArray_reg_0_3_84_89_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(63),
      O => I69(67)
    );
\MemArray_reg_0_3_84_89_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(62),
      O => I69(66)
    );
\MemArray_reg_0_3_84_89_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(65),
      O => I69(69)
    );
\MemArray_reg_0_3_84_89_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(64),
      O => I69(68)
    );
MemArray_reg_0_3_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(68 downto 67),
      DIB(1 downto 0) => DataIn(70 downto 69),
      DIC(1 downto 0) => DataIn(72 downto 71),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(91 downto 90),
      DOB(1 downto 0) => Head0(93 downto 92),
      DOC(1 downto 0) => Head0(95 downto 94),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_90_95_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(67),
      O => I69(71)
    );
\MemArray_reg_0_3_90_95_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(66),
      O => I69(70)
    );
\MemArray_reg_0_3_90_95_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(69),
      O => I69(73)
    );
\MemArray_reg_0_3_90_95_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(68),
      O => I69(72)
    );
\MemArray_reg_0_3_90_95_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(71),
      O => I69(75)
    );
\MemArray_reg_0_3_90_95_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(70),
      O => I69(74)
    );
MemArray_reg_0_3_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(74 downto 73),
      DIB(1 downto 0) => DataIn(76 downto 75),
      DIC(1 downto 0) => DataIn(78 downto 77),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => Head0(97 downto 96),
      DOB(1 downto 0) => Head0(99 downto 98),
      DOC(1 downto 0) => Head0(101 downto 100),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wrq_vld_303
    );
\MemArray_reg_0_3_96_101_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(73),
      O => I69(77)
    );
\MemArray_reg_0_3_96_101_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(72),
      O => I69(76)
    );
\MemArray_reg_0_3_96_101_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(75),
      O => I69(79)
    );
\MemArray_reg_0_3_96_101_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(74),
      O => I69(78)
    );
\MemArray_reg_0_3_96_101_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep__0_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(77),
      O => I69(81)
    );
\MemArray_reg_0_3_96_101_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => \^head_reg[110]_0\(76),
      O => I69(80)
    );
\RdPtr[0]_i_1__17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0F0F0FE1E1E1F0"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => RdPtr(0),
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => Head1,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55577777AAA88888"
    )
        port map (
      I0 => RdPtr(0),
      I1 => Head1,
      I2 => FifoCntrRd(1),
      I3 => FifoCntrRd(2),
      I4 => \RdPtr[1]_i_3__3_n_0\,
      I5 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[1]_i_2__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001F00000000"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => FifoCntrRd(0),
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => wrq_vld_303,
      O => Head1
    );
\RdPtr[1]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      O => \RdPtr[1]_i_3__3_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => RdPtr(0),
      R => full_ff_reg_0
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => full_ff_reg_0
    );
\WrPtr[0]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wrq_vld_303,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wrq_vld_303,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => full_ff_reg_0
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => full_ff_reg_0
    );
\empty_ff_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_0\,
      I4 => \empty_ff_i_2__9_n_0\,
      I5 => empty_ff_reg_1,
      O => \empty_ff_i_1__4_n_0\
    );
\empty_ff_i_2__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F1F0F0F0FF"
    )
        port map (
      I0 => \^empty_ff_reg_rep_0\,
      I1 => \Head_reg[0]_0\,
      I2 => cfg_linkdown_nn1,
      I3 => FifoCntrRd(2),
      I4 => FifoCntrRd(1),
      I5 => FifoCntrRd(0),
      O => \empty_ff_i_2__9_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__4_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
empty_ff_reg_rep: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => empty_ff_rep_i_1_n_0,
      Q => \^empty_ff_reg_rep_0\,
      R => '0'
    );
\empty_ff_reg_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_rep__0_i_1_n_0\,
      Q => \^empty_ff_reg_rep__0_0\,
      R => '0'
    );
\empty_ff_rep__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_0\,
      I4 => \empty_ff_i_2__9_n_0\,
      I5 => empty_ff_reg_1,
      O => \empty_ff_rep__0_i_1_n_0\
    );
empty_ff_rep_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => FifoCntrRd(1),
      I1 => FifoCntrRd(0),
      I2 => FifoCntrRd(2),
      I3 => \^empty_ff_reg_0\,
      I4 => \empty_ff_i_2__9_n_0\,
      I5 => empty_ff_reg_1,
      O => empty_ff_rep_i_1_n_0
    );
\full_ff_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => wrq_vld_303,
      I3 => FifoCntrWr(2),
      I4 => full_ff_reg_n_0,
      O => \full_ff_i_1__2_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__2_n_0\,
      Q => full_ff_reg_n_0,
      R => full_ff_reg_0
    );
\wrq_vld_303_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020000"
    )
        port map (
      I0 => wrq_vld_303_reg,
      I1 => D(0),
      I2 => D(3),
      I3 => \wrq_vld_303_i_3__0_n_0\,
      I4 => D(2),
      I5 => D(1),
      O => wrq_vld_302
    );
\wrq_vld_303_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000000D"
    )
        port map (
      I0 => wrq_vld_303_reg_0,
      I1 => Q(0),
      I2 => ctl_rst,
      I3 => wcp_vlderr_401,
      I4 => wrq_rcp_dat_err_302,
      I5 => wrq_vld_303_i_6_n_0,
      O => \wrq_vld_303_i_3__0_n_0\
    );
wrq_vld_303_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF1"
    )
        port map (
      I0 => CO(0),
      I1 => \wrq_vld_303_i_3__0_0\(0),
      I2 => wrq_vld_303,
      I3 => wrq_stall_302,
      I4 => Q(1),
      I5 => full_ff_reg_n_0,
      O => wrq_vld_303_i_6_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_GenericFIFO_55 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    data_pop : out STD_LOGIC;
    \WrPtr_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_wready : in STD_LOGIC;
    m_axi_wvalid_ff : in STD_LOGIC;
    \RdPtr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \WrPtr_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_GenericFIFO_55 : entity is "xdma_v4_1_8_GenericFIFO";
end xdma_0_xdma_v4_1_8_GenericFIFO_55;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_GenericFIFO_55 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^wrptr_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^data_pop\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__7\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_1__2\ : label is "soft_lutpair418";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1\ : label is "soft_lutpair419";
  attribute SOFT_HLUTNM of \WrPtr[2]_i_1\ : label is "soft_lutpair419";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \WrPtr_reg[2]_0\(2 downto 0) <= \^wrptr_reg[2]_0\(2 downto 0);
  data_pop <= \^data_pop\;
\RdPtr[0]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^data_pop\,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^data_pop\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^data_pop\,
      I3 => \^q\(2),
      O => \RdPtr__0\(2)
    );
\RdPtr[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888880"
    )
        port map (
      I0 => m_axi_wready,
      I1 => m_axi_wvalid_ff,
      I2 => \RdPtr_reg[0]_0\(2),
      I3 => \RdPtr_reg[0]_0\(3),
      I4 => \RdPtr_reg[0]_0\(1),
      I5 => \RdPtr_reg[0]_0\(0),
      O => \^data_pop\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => \^q\(2),
      R => SR(0)
    );
\WrPtr[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^wrptr_reg[2]_0\(0),
      I1 => \WrPtr_reg[1]_0\,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \^wrptr_reg[2]_0\(0),
      I1 => \WrPtr_reg[1]_0\,
      I2 => \^wrptr_reg[2]_0\(1),
      O => \WrPtr__0\(1)
    );
\WrPtr[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \WrPtr_reg[1]_0\,
      I1 => \^wrptr_reg[2]_0\(0),
      I2 => \^wrptr_reg[2]_0\(1),
      I3 => \^wrptr_reg[2]_0\(2),
      O => \WrPtr__0\(2)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => \^wrptr_reg[2]_0\(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => \^wrptr_reg[2]_0\(1),
      R => SR(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => \^wrptr_reg[2]_0\(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized0\ is
  port (
    wb_dat_fl : out STD_LOGIC;
    dat_fifo_vld_102_reg : out STD_LOGIC;
    dat_fifo_vld_102_reg_0 : out STD_LOGIC;
    dat_fifo_vld_102_reg_1 : out STD_LOGIC;
    dat_fifo_vld_102_reg_2 : out STD_LOGIC;
    dat_fifo_vld_102_reg_3 : out STD_LOGIC;
    dat_fifo_vld_102_reg_4 : out STD_LOGIC;
    dat_fifo_vld_102_reg_5 : out STD_LOGIC;
    dat_fifo_vld_102_reg_6 : out STD_LOGIC;
    dat_fifo_vld_102_reg_7 : out STD_LOGIC;
    dat_fifo_vld_102_reg_8 : out STD_LOGIC;
    dat_fifo_vld_102_reg_9 : out STD_LOGIC;
    dat_fifo_vld_102_reg_10 : out STD_LOGIC;
    dat_fifo_vld_102_reg_11 : out STD_LOGIC;
    dat_fifo_vld_102_reg_12 : out STD_LOGIC;
    dat_fifo_vld_102_reg_13 : out STD_LOGIC;
    dat_fifo_vld_102_reg_14 : out STD_LOGIC;
    dat_fifo_vld_102_reg_15 : out STD_LOGIC;
    dat_fifo_vld_102_reg_16 : out STD_LOGIC;
    dat_fifo_vld_102_reg_17 : out STD_LOGIC;
    dat_fifo_vld_102_reg_18 : out STD_LOGIC;
    dat_fifo_vld_102_reg_19 : out STD_LOGIC;
    dat_fifo_vld_102_reg_20 : out STD_LOGIC;
    dat_fifo_vld_102_reg_21 : out STD_LOGIC;
    dat_fifo_vld_102_reg_22 : out STD_LOGIC;
    dat_fifo_vld_102_reg_23 : out STD_LOGIC;
    dat_fifo_vld_102_reg_24 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    FifoCntrRd : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    dat_fifo_vld_102 : in STD_LOGIC;
    \mi_c2h0_dat\\.rdat\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
    wbk_xdma_wpl_vld : in STD_LOGIC;
    wpl_ren_ff : in STD_LOGIC;
    empty_ff : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    wb_win_vld : in STD_LOGIC;
    \DataOut_reg[31]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized0\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized0\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized0\ is
  signal DataOut : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1__15_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__16_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \WrPtr[1]_i_1__15_n_0\ : STD_LOGIC;
  signal \wbk_xdma_wpl_dat[dat]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1\ : label is "soft_lutpair1386";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1\ : label is "soft_lutpair1384";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1\ : label is "soft_lutpair1384";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 144;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "WB_DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "WB_DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "WB_DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_35 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_35 : label is "WB_DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_35 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "WB_DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__15\ : label is "soft_lutpair1385";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__16\ : label is "soft_lutpair1385";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__15\ : label is "soft_lutpair1386";
begin
  Q(0) <= \^q\(0);
\DataOut_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(0),
      Q => \wbk_xdma_wpl_dat[dat]\(0),
      R => '0'
    );
\DataOut_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(10),
      Q => \wbk_xdma_wpl_dat[dat]\(10),
      R => '0'
    );
\DataOut_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(11),
      Q => \wbk_xdma_wpl_dat[dat]\(11),
      R => '0'
    );
\DataOut_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(12),
      Q => \wbk_xdma_wpl_dat[dat]\(12),
      R => '0'
    );
\DataOut_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(13),
      Q => \wbk_xdma_wpl_dat[dat]\(13),
      R => '0'
    );
\DataOut_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(14),
      Q => \wbk_xdma_wpl_dat[dat]\(14),
      R => '0'
    );
\DataOut_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(15),
      Q => \wbk_xdma_wpl_dat[dat]\(15),
      R => '0'
    );
\DataOut_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(16),
      Q => \wbk_xdma_wpl_dat[dat]\(16),
      R => '0'
    );
\DataOut_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(17),
      Q => \wbk_xdma_wpl_dat[dat]\(17),
      R => '0'
    );
\DataOut_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(18),
      Q => \wbk_xdma_wpl_dat[dat]\(18),
      R => '0'
    );
\DataOut_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(19),
      Q => \wbk_xdma_wpl_dat[dat]\(19),
      R => '0'
    );
\DataOut_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(1),
      Q => \wbk_xdma_wpl_dat[dat]\(1),
      R => '0'
    );
\DataOut_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(20),
      Q => \wbk_xdma_wpl_dat[dat]\(20),
      R => '0'
    );
\DataOut_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(21),
      Q => \wbk_xdma_wpl_dat[dat]\(21),
      R => '0'
    );
\DataOut_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(22),
      Q => \wbk_xdma_wpl_dat[dat]\(22),
      R => '0'
    );
\DataOut_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(23),
      Q => \wbk_xdma_wpl_dat[dat]\(23),
      R => '0'
    );
\DataOut_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(2),
      Q => \wbk_xdma_wpl_dat[dat]\(2),
      R => '0'
    );
\DataOut_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(30),
      Q => \wbk_xdma_wpl_dat[dat]\(30),
      R => '0'
    );
\DataOut_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(31),
      Q => \wbk_xdma_wpl_dat[dat]\(31),
      R => '0'
    );
\DataOut_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(3),
      Q => \wbk_xdma_wpl_dat[dat]\(3),
      R => '0'
    );
\DataOut_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(4),
      Q => \wbk_xdma_wpl_dat[dat]\(4),
      R => '0'
    );
\DataOut_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(5),
      Q => \wbk_xdma_wpl_dat[dat]\(5),
      R => '0'
    );
\DataOut_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(6),
      Q => \wbk_xdma_wpl_dat[dat]\(6),
      R => '0'
    );
\DataOut_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(7),
      Q => \wbk_xdma_wpl_dat[dat]\(7),
      R => '0'
    );
\DataOut_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(8),
      Q => \wbk_xdma_wpl_dat[dat]\(8),
      R => '0'
    );
\DataOut_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => DataOut(9),
      Q => \wbk_xdma_wpl_dat[dat]\(9),
      R => '0'
    );
\FifoCntrWr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => wpl_ren_ff,
      I1 => empty_ff,
      I2 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1_n_0\
    );
\FifoCntrWr[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BD42"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => wpl_ren_ff,
      I2 => empty_ff,
      I3 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1_n_0\
    );
\FifoCntrWr[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFF71008"
    )
        port map (
      I0 => FifoCntrWr(1),
      I1 => FifoCntrWr(0),
      I2 => wpl_ren_ff,
      I3 => empty_ff,
      I4 => FifoCntrWr(2),
      O => \FifoCntrWr[2]_i_1_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[0]_i_1_n_0\,
      Q => FifoCntrWr(0),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[1]_i_1_n_0\,
      Q => FifoCntrWr(1),
      R => FifoCntrRd
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrWr[2]_i_1_n_0\,
      Q => FifoCntrWr(2),
      R => FifoCntrRd
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1) => WrPtr(1),
      ADDRD(0) => \^q\(0),
      DIA(1 downto 0) => \DataOut_reg[31]_0\(1 downto 0),
      DIB(1 downto 0) => \DataOut_reg[31]_0\(3 downto 2),
      DIC(1 downto 0) => \DataOut_reg[31]_0\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(1 downto 0),
      DOB(1 downto 0) => DataOut(3 downto 2),
      DOC(1 downto 0) => DataOut(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wb_win_vld
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1) => WrPtr(1),
      ADDRD(0) => \^q\(0),
      DIA(1 downto 0) => \DataOut_reg[31]_0\(13 downto 12),
      DIB(1 downto 0) => \DataOut_reg[31]_0\(15 downto 14),
      DIC(1 downto 0) => \DataOut_reg[31]_0\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(13 downto 12),
      DOB(1 downto 0) => DataOut(15 downto 14),
      DOC(1 downto 0) => DataOut(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wb_win_vld
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1) => WrPtr(1),
      ADDRD(0) => \^q\(0),
      DIA(1 downto 0) => \DataOut_reg[31]_0\(19 downto 18),
      DIB(1 downto 0) => \DataOut_reg[31]_0\(21 downto 20),
      DIC(1 downto 0) => \DataOut_reg[31]_0\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(19 downto 18),
      DOB(1 downto 0) => DataOut(21 downto 20),
      DOC(1 downto 0) => DataOut(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wb_win_vld
    );
MemArray_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1) => WrPtr(1),
      ADDRD(0) => \^q\(0),
      DIA(1 downto 0) => \DataOut_reg[31]_0\(25 downto 24),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(31 downto 30),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wb_win_vld
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1) => WrPtr(1),
      ADDRD(0) => \^q\(0),
      DIA(1 downto 0) => \DataOut_reg[31]_0\(7 downto 6),
      DIB(1 downto 0) => \DataOut_reg[31]_0\(9 downto 8),
      DIC(1 downto 0) => \DataOut_reg[31]_0\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(7 downto 6),
      DOB(1 downto 0) => DataOut(9 downto 8),
      DOC(1 downto 0) => DataOut(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wb_win_vld
    );
\RdPtr[0]_i_1__15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => wpl_ren_ff,
      I1 => RdPtr(0),
      O => \RdPtr[0]_i_1__15_n_0\
    );
\RdPtr[1]_i_1__16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => RdPtr(1),
      I1 => RdPtr(0),
      I2 => wpl_ren_ff,
      O => \RdPtr[1]_i_1__16_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__15_n_0\,
      Q => RdPtr(0),
      R => FifoCntrRd
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__16_n_0\,
      Q => RdPtr(1),
      R => FifoCntrRd
    );
\WrPtr[1]_i_1__15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => WrPtr(1),
      I1 => empty_ff,
      I2 => \^q\(0),
      O => \WrPtr[1]_i_1__15_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => FifoCntrRd
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__15_n_0\,
      Q => WrPtr(1),
      R => FifoCntrRd
    );
almost_full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => FifoCntrWr(2),
      Q => wb_dat_fl,
      R => FifoCntrRd
    );
\wpl_dat_ff[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(0),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(0),
      O => dat_fifo_vld_102_reg
    );
\wpl_dat_ff[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(10),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(10),
      O => dat_fifo_vld_102_reg_9
    );
\wpl_dat_ff[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(11),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(11),
      O => dat_fifo_vld_102_reg_10
    );
\wpl_dat_ff[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(12),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(12),
      O => dat_fifo_vld_102_reg_11
    );
\wpl_dat_ff[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(13),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(13),
      O => dat_fifo_vld_102_reg_12
    );
\wpl_dat_ff[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(14),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(14),
      O => dat_fifo_vld_102_reg_13
    );
\wpl_dat_ff[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(15),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(15),
      O => dat_fifo_vld_102_reg_14
    );
\wpl_dat_ff[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(16),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(16),
      O => dat_fifo_vld_102_reg_15
    );
\wpl_dat_ff[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(17),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(17),
      O => dat_fifo_vld_102_reg_16
    );
\wpl_dat_ff[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(18),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(18),
      O => dat_fifo_vld_102_reg_17
    );
\wpl_dat_ff[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(19),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(19),
      O => dat_fifo_vld_102_reg_18
    );
\wpl_dat_ff[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(1),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(1),
      O => dat_fifo_vld_102_reg_0
    );
\wpl_dat_ff[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(20),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(20),
      O => dat_fifo_vld_102_reg_19
    );
\wpl_dat_ff[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(21),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(21),
      O => dat_fifo_vld_102_reg_20
    );
\wpl_dat_ff[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(22),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(22),
      O => dat_fifo_vld_102_reg_21
    );
\wpl_dat_ff[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(23),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(23),
      O => dat_fifo_vld_102_reg_22
    );
\wpl_dat_ff[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(2),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(2),
      O => dat_fifo_vld_102_reg_1
    );
\wpl_dat_ff[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(24),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(30),
      O => dat_fifo_vld_102_reg_23
    );
\wpl_dat_ff[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(25),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(31),
      O => dat_fifo_vld_102_reg_24
    );
\wpl_dat_ff[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(3),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(3),
      O => dat_fifo_vld_102_reg_2
    );
\wpl_dat_ff[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(4),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(4),
      O => dat_fifo_vld_102_reg_3
    );
\wpl_dat_ff[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(5),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(5),
      O => dat_fifo_vld_102_reg_4
    );
\wpl_dat_ff[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(6),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(6),
      O => dat_fifo_vld_102_reg_5
    );
\wpl_dat_ff[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(7),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(7),
      O => dat_fifo_vld_102_reg_6
    );
\wpl_dat_ff[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(8),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(8),
      O => dat_fifo_vld_102_reg_7
    );
\wpl_dat_ff[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => dat_fifo_vld_102,
      I1 => \mi_c2h0_dat\\.rdat\(9),
      I2 => wbk_xdma_wpl_vld,
      I3 => \wbk_xdma_wpl_dat[dat]\(9),
      O => dat_fifo_vld_102_reg_8
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1\ is
  port (
    tag_ep_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \FifoCntrWr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \WrPtr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rreq_active0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    tag_sel_ff : in STD_LOGIC;
    tag_sel_ff0 : in STD_LOGIC;
    tag_rd : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_tag_ld_nn1 : in STD_LOGIC;
    rclp_tlp_tagdone : in STD_LOGIC;
    \FifoCntrWr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \WrPtr_reg[4]_1\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    tag_ep_1 : in STD_LOGIC;
    empty_ff : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1\ is
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \FifoCntrWr[0]_i_1__11_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__8_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[4]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[5]_i_2_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[5]_i_3_n_0\ : STD_LOGIC;
  signal \^fifocntrwr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^wrptr_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \empty_ff_i_1__11_n_0\ : STD_LOGIC;
  signal \empty_ff_i_3__0_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal \^tag_ep_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__11\ : label is "soft_lutpair1424";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_1__1\ : label is "soft_lutpair1424";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__13\ : label is "soft_lutpair1423";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_1__4\ : label is "soft_lutpair1423";
begin
  \FifoCntrWr_reg[1]_0\(1 downto 0) <= \^fifocntrwr_reg[1]_0\(1 downto 0);
  Q(4 downto 0) <= \^q\(4 downto 0);
  \WrPtr_reg[4]_0\(4 downto 0) <= \^wrptr_reg[4]_0\(4 downto 0);
  tag_ep_0 <= \^tag_ep_0\;
\FifoCntrWr[0]_i_1__11\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[0]_i_1__11_n_0\
    );
\FifoCntrWr[2]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6656AAAAAAAA99A9"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => init_tag_ld_nn1,
      I2 => rclp_tlp_tagdone,
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => \^fifocntrwr_reg[1]_0\(1),
      I5 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[2]_i_1__8_n_0\
    );
\FifoCntrWr[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrWr[3]_i_1__1_n_0\
    );
\FifoCntrWr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(4),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => \FifoCntrWr[4]_i_1_n_0\
    );
\FifoCntrWr[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(5),
      I1 => FifoCntrRd_reg(2),
      I2 => \FifoCntrWr[5]_i_3_n_0\,
      I3 => FifoCntrRd_reg(3),
      I4 => FifoCntrRd_reg(4),
      O => \FifoCntrWr[5]_i_2_n_0\
    );
\FifoCntrWr[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D5D5D5D554D55454"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => \^fifocntrwr_reg[1]_0\(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => rclp_tlp_tagdone,
      I5 => init_tag_ld_nn1,
      O => \FifoCntrWr[5]_i_3_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[0]_i_1__11_n_0\,
      Q => \^fifocntrwr_reg[1]_0\(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr_reg[1]_1\(0),
      Q => \^fifocntrwr_reg[1]_0\(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[2]_i_1__8_n_0\,
      Q => FifoCntrRd_reg(2),
      R => SR(0)
    );
\FifoCntrWr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[3]_i_1__1_n_0\,
      Q => FifoCntrRd_reg(3),
      R => SR(0)
    );
\FifoCntrWr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[4]_i_1_n_0\,
      Q => FifoCntrRd_reg(4),
      R => SR(0)
    );
\FifoCntrWr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[5]_i_2_n_0\,
      Q => FifoCntrRd_reg(5),
      R => SR(0)
    );
\RdPtr[0]_i_1__12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => \^q\(0),
      I1 => tag_sel_ff,
      I2 => tag_sel_ff0,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => tag_sel_ff0,
      I1 => tag_sel_ff,
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFF2000"
    )
        port map (
      I0 => \^q\(0),
      I1 => tag_sel_ff,
      I2 => tag_sel_ff0,
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => \RdPtr__0\(2)
    );
\RdPtr[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => tag_sel_ff0,
      I2 => tag_sel_ff,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \RdPtr__0\(3)
    );
\RdPtr[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => tag_rd(0),
      I4 => \^q\(1),
      I5 => \^q\(4),
      O => \RdPtr__0\(4)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => \^q\(2),
      R => SR(0)
    );
\RdPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(3),
      Q => \^q\(3),
      R => SR(0)
    );
\RdPtr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(4),
      Q => \^q\(4),
      R => SR(0)
    );
\WrPtr[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7757FFFF88A80000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(0),
      I1 => init_tag_ld_nn1,
      I2 => rclp_tlp_tagdone,
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => \^wrptr_reg[4]_0\(1),
      I5 => \^wrptr_reg[4]_0\(2),
      O => \WrPtr__0\(2)
    );
\WrPtr[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(1),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^wrptr_reg[4]_0\(0),
      I3 => \^wrptr_reg[4]_0\(2),
      I4 => \^wrptr_reg[4]_0\(3),
      O => \WrPtr__0\(3)
    );
\WrPtr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(3),
      I1 => \^wrptr_reg[4]_0\(2),
      I2 => \^wrptr_reg[4]_0\(0),
      I3 => \WrPtr_reg[4]_1\,
      I4 => \^wrptr_reg[4]_0\(1),
      I5 => \^wrptr_reg[4]_0\(4),
      O => \WrPtr__0\(4)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \^wrptr_reg[4]_0\(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => \^wrptr_reg[4]_0\(1),
      R => SR(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => \^wrptr_reg[4]_0\(2),
      R => SR(0)
    );
\WrPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(3),
      Q => \^wrptr_reg[4]_0\(3),
      R => SR(0)
    );
\WrPtr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(4),
      Q => \^wrptr_reg[4]_0\(4),
      R => SR(0)
    );
\empty_ff_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFAEAEAEAE"
    )
        port map (
      I0 => SR(0),
      I1 => \^tag_ep_0\,
      I2 => \p_0_in__0\,
      I3 => tag_rd(0),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => \empty_ff_i_3__0_n_0\,
      O => \empty_ff_i_1__11_n_0\
    );
\empty_ff_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(1),
      I1 => FifoCntrRd_reg(2),
      I2 => FifoCntrRd_reg(3),
      I3 => FifoCntrRd_reg(4),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => FifoCntrRd_reg(5),
      O => \p_0_in__0\
    );
\empty_ff_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(1),
      I1 => FifoCntrRd_reg(2),
      I2 => FifoCntrRd_reg(3),
      I3 => FifoCntrRd_reg(5),
      I4 => FifoCntrRd_reg(4),
      O => \empty_ff_i_3__0_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__11_n_0\,
      Q => \^tag_ep_0\,
      R => '0'
    );
\rreq_head_vld_ff[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"001D"
    )
        port map (
      I0 => \^tag_ep_0\,
      I1 => tag_sel_ff,
      I2 => tag_ep_1,
      I3 => empty_ff,
      O => rreq_active0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1_48\ is
  port (
    tag_ep_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \FifoCntrWr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \WrPtr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    tag_sel_ff_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
    user_clk : in STD_LOGIC;
    tag_sel_ff : in STD_LOGIC;
    tag_sel_ff0 : in STD_LOGIC;
    tag_rd : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    init_tag_ld_nn1 : in STD_LOGIC;
    rclp_tlp_tagdone : in STD_LOGIC;
    \FifoCntrWr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \WrPtr_reg[4]_1\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \tag_dout[1]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \tag_dout[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FifoCntrWr_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1_48\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1_48\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized1_48\ is
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \FifoCntrWr[0]_i_1__12_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__9_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \^fifocntrwr_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^wrptr_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \empty_ff_i_1__12_n_0\ : STD_LOGIC;
  signal \empty_ff_i_3__1_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal \^tag_ep_1\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__12\ : label is "soft_lutpair1426";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_1__2\ : label is "soft_lutpair1426";
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__13\ : label is "soft_lutpair1427";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__14\ : label is "soft_lutpair1425";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_1__5\ : label is "soft_lutpair1425";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][tag][1]_i_1\ : label is "soft_lutpair1428";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][tag][2]_i_1\ : label is "soft_lutpair1429";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][tag][3]_i_1\ : label is "soft_lutpair1427";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][tag][4]_i_1\ : label is "soft_lutpair1429";
  attribute SOFT_HLUTNM of \rreq_head_info_ff[1][tag][5]_i_1\ : label is "soft_lutpair1428";
begin
  \FifoCntrWr_reg[1]_0\(1 downto 0) <= \^fifocntrwr_reg[1]_0\(1 downto 0);
  Q(4 downto 0) <= \^q\(4 downto 0);
  \WrPtr_reg[4]_0\(4 downto 0) <= \^wrptr_reg[4]_0\(4 downto 0);
  tag_ep_1 <= \^tag_ep_1\;
\FifoCntrWr[0]_i_1__12\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[0]_i_1__12_n_0\
    );
\FifoCntrWr[2]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5666AAAAAAAAA999"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => init_tag_ld_nn1,
      I2 => rclp_tlp_tagdone,
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => \^fifocntrwr_reg[1]_0\(1),
      I5 => \^fifocntrwr_reg[1]_0\(0),
      O => \FifoCntrWr[2]_i_1__9_n_0\
    );
\FifoCntrWr[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(3),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrWr[3]_i_1__2_n_0\
    );
\FifoCntrWr[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(4),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \^fifocntrwr_reg[1]_0\(0),
      I4 => FifoCntrRd_reg(2),
      I5 => FifoCntrRd_reg(3),
      O => \FifoCntrWr[4]_i_1__0_n_0\
    );
\FifoCntrWr[5]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAA9"
    )
        port map (
      I0 => FifoCntrRd_reg(5),
      I1 => FifoCntrRd_reg(2),
      I2 => \FifoCntrWr[5]_i_3__0_n_0\,
      I3 => FifoCntrRd_reg(3),
      I4 => FifoCntrRd_reg(4),
      O => \FifoCntrWr[5]_i_2__0_n_0\
    );
\FifoCntrWr[5]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D5D5D5D5D5545454"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => \^fifocntrwr_reg[1]_0\(0),
      I2 => \^fifocntrwr_reg[1]_0\(1),
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => rclp_tlp_tagdone,
      I5 => init_tag_ld_nn1,
      O => \FifoCntrWr[5]_i_3__0_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[0]_i_1__12_n_0\,
      Q => \^fifocntrwr_reg[1]_0\(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr_reg[1]_1\(0),
      Q => \^fifocntrwr_reg[1]_0\(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[2]_i_1__9_n_0\,
      Q => FifoCntrRd_reg(2),
      R => SR(0)
    );
\FifoCntrWr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[3]_i_1__2_n_0\,
      Q => FifoCntrRd_reg(3),
      R => SR(0)
    );
\FifoCntrWr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[4]_i_1__0_n_0\,
      Q => FifoCntrRd_reg(4),
      R => SR(0)
    );
\FifoCntrWr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => \FifoCntrWr[5]_i_2__0_n_0\,
      Q => FifoCntrRd_reg(5),
      R => SR(0)
    );
\RdPtr[0]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \^q\(0),
      I1 => tag_sel_ff,
      I2 => tag_sel_ff0,
      O => \RdPtr__0\(0)
    );
\RdPtr[1]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => tag_sel_ff0,
      I1 => tag_sel_ff,
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^q\(0),
      I1 => tag_sel_ff,
      I2 => tag_sel_ff0,
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => \RdPtr__0\(2)
    );
\RdPtr[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => tag_sel_ff0,
      I2 => tag_sel_ff,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \^q\(3),
      O => \RdPtr__0\(3)
    );
\RdPtr[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => tag_rd(0),
      I4 => \^q\(1),
      I5 => \^q\(4),
      O => \RdPtr__0\(4)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(0),
      Q => \^q\(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => \^q\(2),
      R => SR(0)
    );
\RdPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(3),
      Q => \^q\(3),
      R => SR(0)
    );
\RdPtr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(4),
      Q => \^q\(4),
      R => SR(0)
    );
\WrPtr[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5777FFFFA8880000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(0),
      I1 => init_tag_ld_nn1,
      I2 => rclp_tlp_tagdone,
      I3 => \FifoCntrWr_reg[2]_0\(0),
      I4 => \^wrptr_reg[4]_0\(1),
      I5 => \^wrptr_reg[4]_0\(2),
      O => \WrPtr__0\(2)
    );
\WrPtr[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(1),
      I1 => \WrPtr_reg[4]_1\,
      I2 => \^wrptr_reg[4]_0\(0),
      I3 => \^wrptr_reg[4]_0\(2),
      I4 => \^wrptr_reg[4]_0\(3),
      O => \WrPtr__0\(3)
    );
\WrPtr[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \^wrptr_reg[4]_0\(3),
      I1 => \^wrptr_reg[4]_0\(2),
      I2 => \^wrptr_reg[4]_0\(0),
      I3 => \WrPtr_reg[4]_1\,
      I4 => \^wrptr_reg[4]_0\(1),
      I5 => \^wrptr_reg[4]_0\(4),
      O => \WrPtr__0\(4)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \^wrptr_reg[4]_0\(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => \^wrptr_reg[4]_0\(1),
      R => SR(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => \^wrptr_reg[4]_0\(2),
      R => SR(0)
    );
\WrPtr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(3),
      Q => \^wrptr_reg[4]_0\(3),
      R => SR(0)
    );
\WrPtr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(4),
      Q => \^wrptr_reg[4]_0\(4),
      R => SR(0)
    );
\empty_ff_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAEFFFFAEAEAEAE"
    )
        port map (
      I0 => SR(0),
      I1 => \^tag_ep_1\,
      I2 => \p_0_in__0\,
      I3 => tag_rd(0),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => \empty_ff_i_3__1_n_0\,
      O => \empty_ff_i_1__12_n_0\
    );
\empty_ff_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(1),
      I1 => FifoCntrRd_reg(2),
      I2 => FifoCntrRd_reg(3),
      I3 => FifoCntrRd_reg(4),
      I4 => \^fifocntrwr_reg[1]_0\(0),
      I5 => FifoCntrRd_reg(5),
      O => \p_0_in__0\
    );
\empty_ff_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^fifocntrwr_reg[1]_0\(1),
      I1 => FifoCntrRd_reg(2),
      I2 => FifoCntrRd_reg(3),
      I3 => FifoCntrRd_reg(5),
      I4 => FifoCntrRd_reg(4),
      O => \empty_ff_i_3__1_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__12_n_0\,
      Q => \^tag_ep_1\,
      R => '0'
    );
\rreq_head_info_ff[1][tag][1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tag_dout[1]_1\(0),
      I1 => tag_sel_ff,
      I2 => \tag_dout[0]_0\(0),
      O => tag_sel_ff_reg(0)
    );
\rreq_head_info_ff[1][tag][2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tag_dout[1]_1\(1),
      I1 => tag_sel_ff,
      I2 => \tag_dout[0]_0\(1),
      O => tag_sel_ff_reg(1)
    );
\rreq_head_info_ff[1][tag][3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tag_dout[1]_1\(2),
      I1 => tag_sel_ff,
      I2 => \tag_dout[0]_0\(2),
      O => tag_sel_ff_reg(2)
    );
\rreq_head_info_ff[1][tag][4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tag_dout[1]_1\(3),
      I1 => tag_sel_ff,
      I2 => \tag_dout[0]_0\(3),
      O => tag_sel_ff_reg(3)
    );
\rreq_head_info_ff[1][tag][5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tag_dout[1]_1\(4),
      I1 => tag_sel_ff,
      I2 => \tag_dout[0]_0\(4),
      O => tag_sel_ff_reg(4)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized2\ is
  port (
    empty_ff_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \reqdtlpSm_cs_reg[1]\ : out STD_LOGIC;
    wtlp_hdr_ld_500_reg : out STD_LOGIC_VECTOR ( 9 downto 0 );
    DataOut : out STD_LOGIC_VECTOR ( 87 downto 0 );
    wtlp_hdr_ld_500_reg_0 : out STD_LOGIC;
    wtlp_hdr_pop00_out : in STD_LOGIC;
    wtlp_hdr_ld_500 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    reqdtlpSm_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
    reqdtlpSm512_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    wpl_hdr_err_ff_reg : in STD_LOGIC_VECTOR ( 98 downto 0 );
    \FifoCntrWr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized2\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized2\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized2\ is
  signal FifoCntrRd_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \FifoCntrWr[0]_i_1__9_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__13_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__7_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[3]_i_2__1_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_7_72_77_n_1 : STD_LOGIC;
  signal MemArray_reg_0_7_78_83_n_4 : STD_LOGIC;
  signal MemArray_reg_0_7_96_101_n_2 : STD_LOGIC;
  signal MemArray_reg_0_7_96_101_n_5 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \RdPtr[0]_i_1__16_n_0\ : STD_LOGIC;
  signal \RdPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal WrPtr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \WrPtr__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \empty_ff_i_1__9_n_0\ : STD_LOGIC;
  signal \empty_ff_i_2__8_n_0\ : STD_LOGIC;
  signal empty_ff_i_3_n_0 : STD_LOGIC;
  signal empty_ff_i_4_n_0 : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal \wpl_hdr_btlenm1_ff[6]_i_2_n_0\ : STD_LOGIC;
  signal \wpl_hdr_btlenm1_ff[9]_i_2_n_0\ : STD_LOGIC;
  signal wtlp_hdr_out : STD_LOGIC_VECTOR ( 71 downto 62 );
  signal NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_102_102_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_7_102_102_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_102_102_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_102_102_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_7_96_101_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__9\ : label is "soft_lutpair1709";
  attribute SOFT_HLUTNM of \FifoCntrWr[1]_i_1__13\ : label is "soft_lutpair1709";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__7\ : label is "soft_lutpair1704";
  attribute SOFT_HLUTNM of \FifoCntrWr[3]_i_2__1\ : label is "soft_lutpair1704";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_7_0_5 : label is 824;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_0_5 : label is "MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_7_0_5 : label is 7;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_7_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_7_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_102_102 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_102_102 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_102_102 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_102_102 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_102_102 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_102_102 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_102_102 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_102_102 : label is 102;
  attribute ram_slice_end of MemArray_reg_0_7_102_102 : label is 102;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_12_17 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_12_17 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_12_17 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_7_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_18_23 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_18_23 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_18_23 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_7_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_24_29 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_24_29 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_24_29 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_7_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_30_35 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_30_35 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_30_35 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_7_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_36_41 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_36_41 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_36_41 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_36_41 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_36_41 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_36_41 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_36_41 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_7_36_41 : label is 41;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_42_47 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_42_47 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_42_47 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_42_47 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_42_47 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_42_47 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_42_47 : label is 42;
  attribute ram_slice_end of MemArray_reg_0_7_42_47 : label is 47;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_48_53 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_48_53 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_48_53 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_48_53 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_48_53 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_48_53 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_48_53 : label is 48;
  attribute ram_slice_end of MemArray_reg_0_7_48_53 : label is 53;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_54_59 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_54_59 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_54_59 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_54_59 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_54_59 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_54_59 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_54_59 : label is 54;
  attribute ram_slice_end of MemArray_reg_0_7_54_59 : label is 59;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_60_65 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_60_65 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_60_65 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_60_65 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_60_65 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_60_65 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_60_65 : label is 60;
  attribute ram_slice_end of MemArray_reg_0_7_60_65 : label is 65;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_66_71 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_66_71 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_66_71 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_66_71 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_66_71 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_66_71 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_66_71 : label is 66;
  attribute ram_slice_end of MemArray_reg_0_7_66_71 : label is 71;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_6_11 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_6_11 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_6_11 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_7_6_11 : label is 11;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_72_77 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_72_77 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_72_77 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_72_77 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_72_77 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_72_77 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_72_77 : label is 72;
  attribute ram_slice_end of MemArray_reg_0_7_72_77 : label is 77;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_78_83 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_78_83 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_78_83 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_78_83 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_78_83 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_78_83 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_78_83 : label is 78;
  attribute ram_slice_end of MemArray_reg_0_7_78_83 : label is 83;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_84_89 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_84_89 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_84_89 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_84_89 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_84_89 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_84_89 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_84_89 : label is 84;
  attribute ram_slice_end of MemArray_reg_0_7_84_89 : label is 89;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_90_95 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_90_95 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_90_95 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_90_95 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_90_95 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_90_95 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_90_95 : label is 90;
  attribute ram_slice_end of MemArray_reg_0_7_90_95 : label is 95;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_7_96_101 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_7_96_101 : label is 824;
  attribute RTL_RAM_NAME of MemArray_reg_0_7_96_101 : label is "MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_7_96_101 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_7_96_101 : label is 7;
  attribute ram_offset of MemArray_reg_0_7_96_101 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_7_96_101 : label is 96;
  attribute ram_slice_end of MemArray_reg_0_7_96_101 : label is 101;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__16\ : label is "soft_lutpair1707";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__12\ : label is "soft_lutpair1700";
  attribute SOFT_HLUTNM of \RdPtr[2]_i_1__3\ : label is "soft_lutpair1700";
  attribute SOFT_HLUTNM of \WrPtr[1]_i_1__11\ : label is "soft_lutpair1706";
  attribute SOFT_HLUTNM of \WrPtr[2]_i_1__2\ : label is "soft_lutpair1706";
  attribute SOFT_HLUTNM of \empty_ff_i_2__8\ : label is "soft_lutpair1703";
  attribute SOFT_HLUTNM of empty_ff_i_3 : label is "soft_lutpair1707";
  attribute SOFT_HLUTNM of empty_ff_i_4 : label is "soft_lutpair1703";
  attribute SOFT_HLUTNM of wpl_hdr_btlene1_ff_i_1 : label is "soft_lutpair1701";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[0]_i_1\ : label is "soft_lutpair1710";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[1]_i_1\ : label is "soft_lutpair1710";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[2]_i_1\ : label is "soft_lutpair1708";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[3]_i_1\ : label is "soft_lutpair1702";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[4]_i_1\ : label is "soft_lutpair1702";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[6]_i_1\ : label is "soft_lutpair1708";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[7]_i_1\ : label is "soft_lutpair1705";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[8]_i_1\ : label is "soft_lutpair1705";
  attribute SOFT_HLUTNM of \wpl_hdr_btlenm1_ff[9]_i_1\ : label is "soft_lutpair1701";
  attribute SOFT_HLUTNM of \wtlp_hdr_wr_cnt_nn1[1]_i_1\ : label is "soft_lutpair1699";
  attribute SOFT_HLUTNM of \wtlp_hdr_wr_cnt_nn1[3]_i_2\ : label is "soft_lutpair1699";
begin
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
\FifoCntrWr[0]_i_1__9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrRd_reg(0),
      O => \FifoCntrWr[0]_i_1__9_n_0\
    );
\FifoCntrWr[1]_i_1__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => FifoCntrRd_reg(0),
      I1 => wtlp_hdr_ld_500,
      I2 => FifoCntrRd_reg(1),
      O => \FifoCntrWr[1]_i_1__13_n_0\
    );
\FifoCntrWr[2]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => FifoCntrRd_reg(0),
      I1 => wtlp_hdr_ld_500,
      I2 => FifoCntrRd_reg(2),
      I3 => FifoCntrRd_reg(1),
      O => \FifoCntrWr[2]_i_1__7_n_0\
    );
\FifoCntrWr[3]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F80FE01"
    )
        port map (
      I0 => wtlp_hdr_ld_500,
      I1 => FifoCntrRd_reg(0),
      I2 => FifoCntrRd_reg(1),
      I3 => FifoCntrRd_reg(3),
      I4 => FifoCntrRd_reg(2),
      O => \FifoCntrWr[3]_i_2__1_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[0]_0\(0),
      D => \FifoCntrWr[0]_i_1__9_n_0\,
      Q => FifoCntrRd_reg(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[0]_0\(0),
      D => \FifoCntrWr[1]_i_1__13_n_0\,
      Q => FifoCntrRd_reg(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[0]_0\(0),
      D => \FifoCntrWr[2]_i_1__7_n_0\,
      Q => FifoCntrRd_reg(2),
      R => SR(0)
    );
\FifoCntrWr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrWr_reg[0]_0\(0),
      D => \FifoCntrWr[3]_i_2__1_n_0\,
      Q => FifoCntrRd_reg(3),
      R => SR(0)
    );
MemArray_reg_0_7_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(1 downto 0),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(3 downto 2),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(1 downto 0),
      DOB(1 downto 0) => DataOut(3 downto 2),
      DOC(1 downto 0) => DataOut(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_102_102: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1) => '0',
      DIA(0) => wpl_hdr_err_ff_reg(98),
      DIB(1 downto 0) => B"00",
      DIC(1 downto 0) => B"00",
      DID(1 downto 0) => B"00",
      DOA(1) => NLW_MemArray_reg_0_7_102_102_DOA_UNCONNECTED(1),
      DOA(0) => DataOut(87),
      DOB(1 downto 0) => NLW_MemArray_reg_0_7_102_102_DOB_UNCONNECTED(1 downto 0),
      DOC(1 downto 0) => NLW_MemArray_reg_0_7_102_102_DOC_UNCONNECTED(1 downto 0),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_102_102_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(13 downto 12),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(15 downto 14),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(13 downto 12),
      DOB(1 downto 0) => DataOut(15 downto 14),
      DOC(1 downto 0) => DataOut(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(19 downto 18),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(21 downto 20),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(19 downto 18),
      DOB(1 downto 0) => DataOut(21 downto 20),
      DOC(1 downto 0) => DataOut(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(25 downto 24),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(27 downto 26),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(25 downto 24),
      DOB(1 downto 0) => DataOut(27 downto 26),
      DOC(1 downto 0) => DataOut(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(31 downto 30),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(33 downto 32),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(31 downto 30),
      DOB(1 downto 0) => DataOut(33 downto 32),
      DOC(1 downto 0) => DataOut(35 downto 34),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_36_41: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(37 downto 36),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(39 downto 38),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(41 downto 40),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(37 downto 36),
      DOB(1 downto 0) => DataOut(39 downto 38),
      DOC(1 downto 0) => DataOut(41 downto 40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_42_47: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(43 downto 42),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(45 downto 44),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(47 downto 46),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(43 downto 42),
      DOB(1 downto 0) => DataOut(45 downto 44),
      DOC(1 downto 0) => DataOut(47 downto 46),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_48_53: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(49 downto 48),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(51 downto 50),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(53 downto 52),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(49 downto 48),
      DOB(1 downto 0) => DataOut(51 downto 50),
      DOC(1 downto 0) => DataOut(53 downto 52),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_54_59: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(55 downto 54),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(57 downto 56),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(59 downto 58),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(55 downto 54),
      DOB(1 downto 0) => DataOut(57 downto 56),
      DOC(1 downto 0) => DataOut(59 downto 58),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_60_65: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(61 downto 60),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(63 downto 62),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(65 downto 64),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(61 downto 60),
      DOB(1 downto 0) => wtlp_hdr_out(63 downto 62),
      DOC(1 downto 0) => wtlp_hdr_out(65 downto 64),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_66_71: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(67 downto 66),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(69 downto 68),
      DIC(1) => '0',
      DIC(0) => wpl_hdr_err_ff_reg(70),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => wtlp_hdr_out(67 downto 66),
      DOB(1 downto 0) => wtlp_hdr_out(69 downto 68),
      DOC(1 downto 0) => wtlp_hdr_out(71 downto 70),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(7 downto 6),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(9 downto 8),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(7 downto 6),
      DOB(1 downto 0) => DataOut(9 downto 8),
      DOC(1 downto 0) => DataOut(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_72_77: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(72 downto 71),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(74 downto 73),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(76 downto 75),
      DID(1 downto 0) => B"00",
      DOA(1) => DataOut(62),
      DOA(0) => MemArray_reg_0_7_72_77_n_1,
      DOB(1 downto 0) => DataOut(64 downto 63),
      DOC(1 downto 0) => DataOut(66 downto 65),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_78_83: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(78 downto 77),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(80 downto 79),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(82 downto 81),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(68 downto 67),
      DOB(1 downto 0) => DataOut(70 downto 69),
      DOC(1) => MemArray_reg_0_7_78_83_n_4,
      DOC(0) => DataOut(71),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_84_89: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(84 downto 83),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(86 downto 85),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(88 downto 87),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(73 downto 72),
      DOB(1 downto 0) => DataOut(75 downto 74),
      DOC(1 downto 0) => DataOut(77 downto 76),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_90_95: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(90 downto 89),
      DIB(1 downto 0) => wpl_hdr_err_ff_reg(92 downto 91),
      DIC(1 downto 0) => wpl_hdr_err_ff_reg(94 downto 93),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(79 downto 78),
      DOB(1 downto 0) => DataOut(81 downto 80),
      DOC(1 downto 0) => DataOut(83 downto 82),
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
MemArray_reg_0_7_96_101: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 3) => B"00",
      ADDRA(2 downto 0) => RdPtr(2 downto 0),
      ADDRB(4 downto 3) => B"00",
      ADDRB(2 downto 0) => RdPtr(2 downto 0),
      ADDRC(4 downto 3) => B"00",
      ADDRC(2 downto 0) => RdPtr(2 downto 0),
      ADDRD(4 downto 3) => B"00",
      ADDRD(2 downto 0) => WrPtr(2 downto 0),
      DIA(1 downto 0) => wpl_hdr_err_ff_reg(96 downto 95),
      DIB(1 downto 0) => B"00",
      DIC(1) => wpl_hdr_err_ff_reg(97),
      DIC(0) => '0',
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(85 downto 84),
      DOB(1) => MemArray_reg_0_7_96_101_n_2,
      DOB(0) => NLW_MemArray_reg_0_7_96_101_DOB_UNCONNECTED(0),
      DOC(1) => DataOut(86),
      DOC(0) => MemArray_reg_0_7_96_101_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => wtlp_hdr_ld_500
    );
\RdPtr[0]_i_1__16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A6"
    )
        port map (
      I0 => RdPtr(0),
      I1 => wtlp_hdr_pop00_out,
      I2 => \^empty_ff_reg_0\,
      O => \RdPtr[0]_i_1__16_n_0\
    );
\RdPtr[1]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF40"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => wtlp_hdr_pop00_out,
      I2 => RdPtr(0),
      I3 => RdPtr(1),
      O => \RdPtr__0\(1)
    );
\RdPtr[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => RdPtr(0),
      I1 => wtlp_hdr_pop00_out,
      I2 => \^empty_ff_reg_0\,
      I3 => RdPtr(1),
      I4 => RdPtr(2),
      O => \RdPtr__0\(2)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__16_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(1),
      Q => RdPtr(1),
      R => SR(0)
    );
\RdPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr__0\(2),
      Q => RdPtr(2),
      R => SR(0)
    );
\WrPtr[0]_i_1__11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wtlp_hdr_ld_500,
      O => \WrPtr__0\(0)
    );
\WrPtr[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => WrPtr(0),
      I1 => wtlp_hdr_ld_500,
      I2 => WrPtr(1),
      O => \WrPtr__0\(1)
    );
\WrPtr[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => wtlp_hdr_ld_500,
      I1 => WrPtr(0),
      I2 => WrPtr(1),
      I3 => WrPtr(2),
      O => \WrPtr__0\(2)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(0),
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(1),
      Q => WrPtr(1),
      R => SR(0)
    );
\WrPtr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr__0\(2),
      Q => WrPtr(2),
      R => SR(0)
    );
\empty_ff_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBBBBBFBBFF"
    )
        port map (
      I0 => \empty_ff_i_2__8_n_0\,
      I1 => empty_ff_reg_1(0),
      I2 => empty_ff_i_3_n_0,
      I3 => empty_ff_i_4_n_0,
      I4 => FifoCntrRd_reg(0),
      I5 => FifoCntrRd_reg(1),
      O => \empty_ff_i_1__9_n_0\
    );
\empty_ff_i_2__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => FifoCntrRd_reg(3),
      I2 => FifoCntrRd_reg(0),
      I3 => FifoCntrRd_reg(1),
      I4 => FifoCntrRd_reg(2),
      O => \empty_ff_i_2__8_n_0\
    );
empty_ff_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^empty_ff_reg_0\,
      I1 => wtlp_hdr_pop00_out,
      O => empty_ff_i_3_n_0
    );
empty_ff_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => FifoCntrRd_reg(2),
      I1 => FifoCntrRd_reg(3),
      O => empty_ff_i_4_n_0
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__9_n_0\,
      Q => \^empty_ff_reg_0\,
      R => '0'
    );
wpl_hdr_btlene1_ff_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => wtlp_hdr_out(71),
      I1 => wtlp_hdr_out(62),
      I2 => wtlp_hdr_out(70),
      I3 => \wpl_hdr_btlenm1_ff[9]_i_2_n_0\,
      I4 => wtlp_hdr_out(69),
      O => wtlp_hdr_ld_500_reg_0
    );
\wpl_hdr_btlenm1_ff[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      O => wtlp_hdr_ld_500_reg(0)
    );
\wpl_hdr_btlenm1_ff[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wtlp_hdr_out(63),
      I1 => wtlp_hdr_out(62),
      O => wtlp_hdr_ld_500_reg(1)
    );
\wpl_hdr_btlenm1_ff[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(63),
      I2 => wtlp_hdr_out(64),
      O => wtlp_hdr_ld_500_reg(2)
    );
\wpl_hdr_btlenm1_ff[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(64),
      I2 => wtlp_hdr_out(63),
      I3 => wtlp_hdr_out(65),
      O => wtlp_hdr_ld_500_reg(3)
    );
\wpl_hdr_btlenm1_ff[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(65),
      I2 => wtlp_hdr_out(63),
      I3 => wtlp_hdr_out(64),
      I4 => wtlp_hdr_out(66),
      O => wtlp_hdr_ld_500_reg(4)
    );
\wpl_hdr_btlenm1_ff[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(66),
      I2 => wtlp_hdr_out(64),
      I3 => wtlp_hdr_out(63),
      I4 => wtlp_hdr_out(65),
      I5 => wtlp_hdr_out(67),
      O => wtlp_hdr_ld_500_reg(5)
    );
\wpl_hdr_btlenm1_ff[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => \wpl_hdr_btlenm1_ff[6]_i_2_n_0\,
      I2 => wtlp_hdr_out(68),
      O => wtlp_hdr_ld_500_reg(6)
    );
\wpl_hdr_btlenm1_ff[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => wtlp_hdr_out(66),
      I1 => wtlp_hdr_out(64),
      I2 => wtlp_hdr_out(63),
      I3 => wtlp_hdr_out(65),
      I4 => wtlp_hdr_out(67),
      O => \wpl_hdr_btlenm1_ff[6]_i_2_n_0\
    );
\wpl_hdr_btlenm1_ff[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => \wpl_hdr_btlenm1_ff[9]_i_2_n_0\,
      I2 => wtlp_hdr_out(69),
      O => wtlp_hdr_ld_500_reg(7)
    );
\wpl_hdr_btlenm1_ff[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(69),
      I2 => \wpl_hdr_btlenm1_ff[9]_i_2_n_0\,
      I3 => wtlp_hdr_out(70),
      O => wtlp_hdr_ld_500_reg(8)
    );
\wpl_hdr_btlenm1_ff[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => wtlp_hdr_out(62),
      I1 => wtlp_hdr_out(69),
      I2 => \wpl_hdr_btlenm1_ff[9]_i_2_n_0\,
      I3 => wtlp_hdr_out(70),
      I4 => wtlp_hdr_out(71),
      O => wtlp_hdr_ld_500_reg(9)
    );
\wpl_hdr_btlenm1_ff[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wtlp_hdr_out(67),
      I1 => wtlp_hdr_out(65),
      I2 => wtlp_hdr_out(63),
      I3 => wtlp_hdr_out(64),
      I4 => wtlp_hdr_out(66),
      I5 => wtlp_hdr_out(68),
      O => \wpl_hdr_btlenm1_ff[9]_i_2_n_0\
    );
wtlp_hdr_rd_ff_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reqdtlpSm_cs(0),
      I1 => reqdtlpSm512_cs(0),
      O => \reqdtlpSm_cs_reg[1]\
    );
\wtlp_hdr_wr_cnt_nn1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"758A8A75"
    )
        port map (
      I0 => wtlp_hdr_ld_500,
      I1 => \^empty_ff_reg_0\,
      I2 => wtlp_hdr_pop00_out,
      I3 => Q(1),
      I4 => Q(0),
      O => D(0)
    );
\wtlp_hdr_wr_cnt_nn1[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6A66AAAAAAAA9599"
    )
        port map (
      I0 => Q(2),
      I1 => wtlp_hdr_ld_500,
      I2 => \^empty_ff_reg_0\,
      I3 => wtlp_hdr_pop00_out,
      I4 => Q(1),
      I5 => Q(0),
      O => D(1)
    );
\wtlp_hdr_wr_cnt_nn1[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9A"
    )
        port map (
      I0 => wtlp_hdr_ld_500,
      I1 => \^empty_ff_reg_0\,
      I2 => wtlp_hdr_pop00_out,
      O => E(0)
    );
\wtlp_hdr_wr_cnt_nn1[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"78F0F0F0F0E1E1E1"
    )
        port map (
      I0 => Q(2),
      I1 => Q(1),
      I2 => Q(3),
      I3 => wtlp_hdr_ld_500,
      I4 => empty_ff_i_3_n_0,
      I5 => Q(0),
      O => D(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3\ is
  port (
    req_fifo_wr_nn0 : out STD_LOGIC;
    DataIn : out STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_0 : out STD_LOGIC;
    tar_cq_wvld : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : out STD_LOGIC;
    DataOut : out STD_LOGIC_VECTOR ( 15 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axil_arvalid : in STD_LOGIC;
    s_axil_awvalid : in STD_LOGIC;
    req_fifo_wr_nn1 : in STD_LOGIC;
    s_axil_awaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    arb_pri_nn1_0 : in STD_LOGIC;
    s_axil_araddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    dat_fifo_ep : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    tar_req_ld_nn1 : in STD_LOGIC;
    tar_row_nn1 : in STD_LOGIC;
    arb_pri_nn1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \arb_win_nn1_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3\ is
  signal \^datain\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FifoCntrRd[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__7_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[0]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[1]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[2]\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__7_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__5_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_2_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_3_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_4_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_5_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_6_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_0_5_i_7_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_1_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_2_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_3_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_4_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_5_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_i_6_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_5 : STD_LOGIC;
  signal \MemArray_reg_0_3_6_11_i_1__0_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_i_2_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_i_3_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_i_4_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_i_5_n_0 : STD_LOGIC;
  signal MemArray_reg_0_3_6_11_i_6_n_0 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal RdPtr_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal WrPtr_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal empty_ff : STD_LOGIC;
  signal \empty_ff_i_1__17_n_0\ : STD_LOGIC;
  signal \full_ff_i_1__4_n_0\ : STD_LOGIC;
  signal req_fifo_dout : STD_LOGIC_VECTOR ( 40 to 40 );
  signal req_fifo_fl : STD_LOGIC;
  signal \^req_fifo_wr_nn0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_3_36_40_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__8\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__0\ : label is "soft_lutpair392";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__7\ : label is "soft_lutpair393";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__5\ : label is "soft_lutpair393";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 164;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "usr_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "usr_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_36_40 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_36_40 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_36_40 : label is "usr_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_36_40 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_36_40 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_36_40 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_36_40 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_36_40 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_3_36_40 : label is 40;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "usr_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__9\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__10\ : label is "soft_lutpair394";
  attribute SOFT_HLUTNM of \arb_win_nn1[0]_i_1\ : label is "soft_lutpair391";
  attribute SOFT_HLUTNM of \arb_win_nn1[1]_i_3\ : label is "soft_lutpair391";
begin
  DataIn(0) <= \^datain\(0);
  req_fifo_wr_nn0 <= \^req_fifo_wr_nn0\;
\FifoCntrRd[0]_i_1__8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[0]_i_1__8_n_0\
    );
\FifoCntrRd[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9AA56565655"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => req_fifo_wr_nn1,
      I2 => req_fifo_fl,
      I3 => s_axil_awvalid,
      I4 => s_axil_arvalid,
      I5 => \FifoCntrRd_reg_n_0_[1]\,
      O => \FifoCntrRd[1]_i_1__6_n_0\
    );
\FifoCntrRd[2]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA56"
    )
        port map (
      I0 => empty_ff_reg_3(0),
      I1 => s_axil_arvalid,
      I2 => s_axil_awvalid,
      I3 => req_fifo_fl,
      I4 => req_fifo_wr_nn1,
      O => \FifoCntrRd[2]_i_1__7_n_0\
    );
\FifoCntrRd[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[1]\,
      I1 => \FifoCntrRd_reg_n_0_[0]\,
      I2 => \FifoCntrRd_reg_n_0_[2]\,
      I3 => \^req_fifo_wr_nn0\,
      O => \FifoCntrRd[2]_i_2__0_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrRd[0]_i_1__8_n_0\,
      Q => \FifoCntrRd_reg_n_0_[0]\,
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrRd[1]_i_1__6_n_0\,
      Q => \FifoCntrRd_reg_n_0_[1]\,
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrRd[2]_i_2__0_n_0\,
      Q => \FifoCntrRd_reg_n_0_[2]\,
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__7_n_0\
    );
\FifoCntrWr[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9AA56565655"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => req_fifo_wr_nn1,
      I2 => req_fifo_fl,
      I3 => s_axil_awvalid,
      I4 => s_axil_arvalid,
      I5 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__5_n_0\
    );
\FifoCntrWr[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => FifoCntrWr(1),
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(2),
      I3 => \^req_fifo_wr_nn0\,
      O => \FifoCntrWr[2]_i_1__5_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrWr[0]_i_1__7_n_0\,
      Q => FifoCntrWr(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrWr[1]_i_1__5_n_0\,
      Q => FifoCntrWr(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__7_n_0\,
      D => \FifoCntrWr[2]_i_1__5_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr_1(1 downto 0),
      DIA(1) => MemArray_reg_0_3_0_5_i_2_n_0,
      DIA(0) => MemArray_reg_0_3_0_5_i_3_n_0,
      DIB(1) => MemArray_reg_0_3_0_5_i_4_n_0,
      DIB(0) => MemArray_reg_0_3_0_5_i_5_n_0,
      DIC(1) => MemArray_reg_0_3_0_5_i_6_n_0,
      DIC(0) => MemArray_reg_0_3_0_5_i_7_n_0,
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(1 downto 0),
      DOB(1 downto 0) => DataOut(3 downto 2),
      DOC(1 downto 0) => DataOut(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_0_5_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1110"
    )
        port map (
      I0 => req_fifo_wr_nn1,
      I1 => req_fifo_fl,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      O => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_0_5_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(1),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(1),
      O => MemArray_reg_0_3_0_5_i_2_n_0
    );
MemArray_reg_0_3_0_5_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(0),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(0),
      O => MemArray_reg_0_3_0_5_i_3_n_0
    );
MemArray_reg_0_3_0_5_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(3),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(3),
      O => MemArray_reg_0_3_0_5_i_4_n_0
    );
MemArray_reg_0_3_0_5_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(2),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(2),
      O => MemArray_reg_0_3_0_5_i_5_n_0
    );
MemArray_reg_0_3_0_5_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(5),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(5),
      O => MemArray_reg_0_3_0_5_i_6_n_0
    );
MemArray_reg_0_3_0_5_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(4),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(4),
      O => MemArray_reg_0_3_0_5_i_7_n_0
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr_1(1 downto 0),
      DIA(1) => MemArray_reg_0_3_12_17_i_1_n_0,
      DIA(0) => MemArray_reg_0_3_12_17_i_2_n_0,
      DIB(1) => MemArray_reg_0_3_12_17_i_3_n_0,
      DIB(0) => MemArray_reg_0_3_12_17_i_4_n_0,
      DIC(1) => MemArray_reg_0_3_12_17_i_5_n_0,
      DIC(0) => MemArray_reg_0_3_12_17_i_6_n_0,
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(13 downto 12),
      DOB(1 downto 0) => DataOut(15 downto 14),
      DOC(1) => MemArray_reg_0_3_12_17_n_4,
      DOC(0) => MemArray_reg_0_3_12_17_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_12_17_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(13),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(13),
      O => MemArray_reg_0_3_12_17_i_1_n_0
    );
MemArray_reg_0_3_12_17_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(12),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(12),
      O => MemArray_reg_0_3_12_17_i_2_n_0
    );
MemArray_reg_0_3_12_17_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(15),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(15),
      O => MemArray_reg_0_3_12_17_i_3_n_0
    );
MemArray_reg_0_3_12_17_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(14),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(14),
      O => MemArray_reg_0_3_12_17_i_4_n_0
    );
MemArray_reg_0_3_12_17_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(17),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(17),
      O => MemArray_reg_0_3_12_17_i_5_n_0
    );
MemArray_reg_0_3_12_17_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(16),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(16),
      O => MemArray_reg_0_3_12_17_i_6_n_0
    );
MemArray_reg_0_3_36_40: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr_1(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '0',
      DIC(0) => \^datain\(0),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOB_UNCONNECTED(1 downto 0),
      DOC(1) => NLW_MemArray_reg_0_3_36_40_DOC_UNCONNECTED(1),
      DOC(0) => req_fifo_dout(40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_36_40_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => arb_pri_nn1_0,
      I1 => s_axil_awvalid,
      I2 => s_axil_arvalid,
      O => \^datain\(0)
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr_0(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr_1(1 downto 0),
      DIA(1) => \MemArray_reg_0_3_6_11_i_1__0_n_0\,
      DIA(0) => MemArray_reg_0_3_6_11_i_2_n_0,
      DIB(1) => MemArray_reg_0_3_6_11_i_3_n_0,
      DIB(0) => MemArray_reg_0_3_6_11_i_4_n_0,
      DIC(1) => MemArray_reg_0_3_6_11_i_5_n_0,
      DIC(0) => MemArray_reg_0_3_6_11_i_6_n_0,
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => DataOut(7 downto 6),
      DOB(1 downto 0) => DataOut(9 downto 8),
      DOC(1 downto 0) => DataOut(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
\MemArray_reg_0_3_6_11_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(7),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(7),
      O => \MemArray_reg_0_3_6_11_i_1__0_n_0\
    );
MemArray_reg_0_3_6_11_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(6),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(6),
      O => MemArray_reg_0_3_6_11_i_2_n_0
    );
MemArray_reg_0_3_6_11_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(9),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(9),
      O => MemArray_reg_0_3_6_11_i_3_n_0
    );
MemArray_reg_0_3_6_11_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(8),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(8),
      O => MemArray_reg_0_3_6_11_i_4_n_0
    );
MemArray_reg_0_3_6_11_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(11),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(11),
      O => MemArray_reg_0_3_6_11_i_5_n_0
    );
MemArray_reg_0_3_6_11_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFAA80AA"
    )
        port map (
      I0 => s_axil_awaddr(10),
      I1 => arb_pri_nn1_0,
      I2 => s_axil_awvalid,
      I3 => s_axil_arvalid,
      I4 => s_axil_araddr(10),
      O => MemArray_reg_0_3_6_11_i_6_n_0
    );
\RdPtr[0]_i_1__9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RdPtr_0(0),
      I1 => empty_ff_reg_3(0),
      O => RdPtr(0)
    );
\RdPtr[1]_i_1__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RdPtr_0(0),
      I1 => empty_ff_reg_3(0),
      I2 => RdPtr_0(1),
      O => RdPtr(1)
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RdPtr(0),
      Q => RdPtr_0(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RdPtr(1),
      Q => RdPtr_0(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA56"
    )
        port map (
      I0 => WrPtr_1(0),
      I1 => s_axil_arvalid,
      I2 => s_axil_awvalid,
      I3 => req_fifo_fl,
      I4 => req_fifo_wr_nn1,
      O => WrPtr(0)
    );
\WrPtr[1]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFDFDFF02020200"
    )
        port map (
      I0 => WrPtr_1(0),
      I1 => req_fifo_wr_nn1,
      I2 => req_fifo_fl,
      I3 => s_axil_awvalid,
      I4 => s_axil_arvalid,
      I5 => WrPtr_1(1),
      O => WrPtr(1)
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => WrPtr(0),
      Q => WrPtr_1(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => WrPtr(1),
      Q => WrPtr_1(1),
      R => SR(0)
    );
\arb_win_nn1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888BBB"
    )
        port map (
      I0 => arb_pri_nn1(0),
      I1 => \arb_win_nn1_reg[0]\,
      I2 => req_fifo_dout(40),
      I3 => dat_fifo_ep,
      I4 => empty_ff,
      O => D(0)
    );
\arb_win_nn1[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0444"
    )
        port map (
      I0 => empty_ff,
      I1 => arb_pri_nn1(0),
      I2 => req_fifo_dout(40),
      I3 => dat_fifo_ep,
      O => empty_ff_reg_1
    );
\empty_ff_i_1__17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555555DF"
    )
        port map (
      I0 => empty_ff_reg_2(0),
      I1 => empty_ff_reg_3(0),
      I2 => \FifoCntrRd_reg_n_0_[0]\,
      I3 => \FifoCntrRd_reg_n_0_[1]\,
      I4 => \FifoCntrRd_reg_n_0_[2]\,
      O => \empty_ff_i_1__17_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__17_n_0\,
      Q => empty_ff,
      R => '0'
    );
\full_ff_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \^req_fifo_wr_nn0\,
      I3 => FifoCntrWr(2),
      I4 => req_fifo_fl,
      O => \full_ff_i_1__4_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__4_n_0\,
      Q => req_fifo_fl,
      R => SR(0)
    );
\req_wvld_nn1_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => empty_ff,
      I1 => req_fifo_dout(40),
      I2 => dat_fifo_ep,
      O => tar_cq_wvld(0)
    );
tar_row_nn1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => req_fifo_dout(40),
      I1 => empty_ff,
      I2 => dat_fifo_ep,
      I3 => Q(0),
      I4 => tar_req_ld_nn1,
      I5 => tar_row_nn1,
      O => empty_ff_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3_58\ is
  port (
    req_fifo_wr_nn0 : out STD_LOGIC;
    tar_row_nn0 : out STD_LOGIC;
    tar_cq_wvld : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_0 : out STD_LOGIC;
    \RdPtr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axilp_arvalid : in STD_LOGIC;
    s_axilp_awvalid : in STD_LOGIC;
    \FifoCntrWr_reg[0]_0\ : in STD_LOGIC;
    tar_row_nn1_reg : in STD_LOGIC;
    tar_req_ld_nn1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    dat_fifo_ep : in STD_LOGIC;
    arb_pri_nn1_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \arb_win_nn1_reg[1]\ : in STD_LOGIC;
    DataIn : in STD_LOGIC_VECTOR ( 18 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3_58\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3_58\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized3_58\ is
  signal \FifoCntrRd[0]_i_1__9_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1__8_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[0]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[1]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[2]\ : STD_LOGIC;
  signal FifoCntrWr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FifoCntrWr[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \FifoCntrWr[2]_i_1__6_n_0\ : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_4 : STD_LOGIC;
  signal MemArray_reg_0_3_12_17_n_5 : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__11_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1__9_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__9_n_0\ : STD_LOGIC;
  signal \empty_ff_i_1__18_n_0\ : STD_LOGIC;
  signal \^empty_ff_reg_0\ : STD_LOGIC;
  signal empty_ff_reg_n_0 : STD_LOGIC;
  signal \full_ff_i_1__5_n_0\ : STD_LOGIC;
  signal req_fifo_dout : STD_LOGIC_VECTOR ( 40 to 40 );
  signal req_fifo_fl : STD_LOGIC;
  signal \^req_fifo_wr_nn0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_36_40_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_MemArray_reg_0_3_36_40_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1__9\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \FifoCntrRd[2]_i_2__1\ : label is "soft_lutpair384";
  attribute SOFT_HLUTNM of \FifoCntrWr[0]_i_1__8\ : label is "soft_lutpair385";
  attribute SOFT_HLUTNM of \FifoCntrWr[2]_i_1__6\ : label is "soft_lutpair385";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 164;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "cq_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "cq_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_36_40 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_36_40 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_36_40 : label is "cq_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_36_40 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_36_40 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_36_40 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_36_40 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_36_40 : label is 36;
  attribute ram_slice_end of MemArray_reg_0_3_36_40 : label is 40;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 164;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "cq_axilt_slv/REQ_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__10\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__11\ : label is "soft_lutpair386";
  attribute SOFT_HLUTNM of \arb_win_nn1[1]_i_1\ : label is "soft_lutpair383";
  attribute SOFT_HLUTNM of req_wvld_nn1_i_1 : label is "soft_lutpair383";
begin
  empty_ff_reg_0 <= \^empty_ff_reg_0\;
  req_fifo_wr_nn0 <= \^req_fifo_wr_nn0\;
\FifoCntrRd[0]_i_1__9\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[0]_i_1__9_n_0\
    );
\FifoCntrRd[1]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9AA56565655"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => \FifoCntrWr_reg[0]_0\,
      I2 => req_fifo_fl,
      I3 => s_axilp_awvalid,
      I4 => s_axilp_arvalid,
      I5 => \FifoCntrRd_reg_n_0_[1]\,
      O => \FifoCntrRd[1]_i_1__7_n_0\
    );
\FifoCntrRd[2]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA56"
    )
        port map (
      I0 => empty_ff_reg_2(0),
      I1 => s_axilp_arvalid,
      I2 => s_axilp_awvalid,
      I3 => req_fifo_fl,
      I4 => \FifoCntrWr_reg[0]_0\,
      O => \FifoCntrRd[2]_i_1__8_n_0\
    );
\FifoCntrRd[2]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[1]\,
      I1 => \FifoCntrRd_reg_n_0_[0]\,
      I2 => \FifoCntrRd_reg_n_0_[2]\,
      I3 => \^req_fifo_wr_nn0\,
      O => \FifoCntrRd[2]_i_2__1_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrRd[0]_i_1__9_n_0\,
      Q => \FifoCntrRd_reg_n_0_[0]\,
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrRd[1]_i_1__7_n_0\,
      Q => \FifoCntrRd_reg_n_0_[1]\,
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrRd[2]_i_2__1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[2]\,
      R => SR(0)
    );
\FifoCntrWr[0]_i_1__8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => FifoCntrWr(0),
      O => \FifoCntrWr[0]_i_1__8_n_0\
    );
\FifoCntrWr[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A9A9AA56565655"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => \FifoCntrWr_reg[0]_0\,
      I2 => req_fifo_fl,
      I3 => s_axilp_awvalid,
      I4 => s_axilp_arvalid,
      I5 => FifoCntrWr(1),
      O => \FifoCntrWr[1]_i_1__6_n_0\
    );
\FifoCntrWr[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"78E1"
    )
        port map (
      I0 => FifoCntrWr(1),
      I1 => FifoCntrWr(0),
      I2 => FifoCntrWr(2),
      I3 => \^req_fifo_wr_nn0\,
      O => \FifoCntrWr[2]_i_1__6_n_0\
    );
\FifoCntrWr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrWr[0]_i_1__8_n_0\,
      Q => FifoCntrWr(0),
      R => SR(0)
    );
\FifoCntrWr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrWr[1]_i_1__6_n_0\,
      Q => FifoCntrWr(1),
      R => SR(0)
    );
\FifoCntrWr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \FifoCntrRd[2]_i_1__8_n_0\,
      D => \FifoCntrWr[2]_i_1__6_n_0\,
      Q => FifoCntrWr(2),
      R => SR(0)
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(1 downto 0),
      DIB(1 downto 0) => DataIn(3 downto 2),
      DIC(1 downto 0) => DataIn(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(1 downto 0),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(3 downto 2),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
\MemArray_reg_0_3_0_5_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1110"
    )
        port map (
      I0 => \FifoCntrWr_reg[0]_0\,
      I1 => req_fifo_fl,
      I2 => s_axilp_awvalid,
      I3 => s_axilp_arvalid,
      O => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(13 downto 12),
      DIB(1 downto 0) => DataIn(15 downto 14),
      DIC(1 downto 0) => DataIn(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(13 downto 12),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(15 downto 14),
      DOC(1) => MemArray_reg_0_3_12_17_n_4,
      DOC(0) => MemArray_reg_0_3_12_17_n_5,
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_36_40: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => B"00",
      DIB(1 downto 0) => B"00",
      DIC(1) => '0',
      DIC(0) => DataIn(18),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOA_UNCONNECTED(1 downto 0),
      DOB(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOB_UNCONNECTED(1 downto 0),
      DOC(1) => NLW_MemArray_reg_0_3_36_40_DOC_UNCONNECTED(1),
      DOC(0) => req_fifo_dout(40),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_36_40_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => DataIn(7 downto 6),
      DIB(1 downto 0) => DataIn(9 downto 8),
      DIC(1 downto 0) => DataIn(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(7 downto 6),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(9 downto 8),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^req_fifo_wr_nn0\
    );
\RdPtr[0]_i_1__10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => RdPtr(0),
      I1 => empty_ff_reg_2(0),
      O => \RdPtr[0]_i_1__10_n_0\
    );
\RdPtr[1]_i_1__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RdPtr(0),
      I1 => empty_ff_reg_2(0),
      I2 => RdPtr(1),
      O => \RdPtr[1]_i_1__11_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__10_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__11_n_0\,
      Q => RdPtr(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAA56"
    )
        port map (
      I0 => WrPtr(0),
      I1 => s_axilp_arvalid,
      I2 => s_axilp_awvalid,
      I3 => req_fifo_fl,
      I4 => \FifoCntrWr_reg[0]_0\,
      O => \WrPtr[0]_i_1__9_n_0\
    );
\WrPtr[1]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFDFDFF02020200"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \FifoCntrWr_reg[0]_0\,
      I2 => req_fifo_fl,
      I3 => s_axilp_awvalid,
      I4 => s_axilp_arvalid,
      I5 => WrPtr(1),
      O => \WrPtr[1]_i_1__9_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__9_n_0\,
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__9_n_0\,
      Q => WrPtr(1),
      R => SR(0)
    );
\arb_win_nn1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888BBB"
    )
        port map (
      I0 => arb_pri_nn1_0(0),
      I1 => \^empty_ff_reg_0\,
      I2 => req_fifo_dout(40),
      I3 => dat_fifo_ep,
      I4 => empty_ff_reg_n_0,
      O => D(0)
    );
\arb_win_nn1[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0070"
    )
        port map (
      I0 => dat_fifo_ep,
      I1 => req_fifo_dout(40),
      I2 => arb_pri_nn1_0(0),
      I3 => empty_ff_reg_n_0,
      I4 => \arb_win_nn1_reg[1]\,
      O => \^empty_ff_reg_0\
    );
\empty_ff_i_1__18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555555DF"
    )
        port map (
      I0 => empty_ff_reg_1(0),
      I1 => empty_ff_reg_2(0),
      I2 => \FifoCntrRd_reg_n_0_[0]\,
      I3 => \FifoCntrRd_reg_n_0_[1]\,
      I4 => \FifoCntrRd_reg_n_0_[2]\,
      O => \empty_ff_i_1__18_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__18_n_0\,
      Q => empty_ff_reg_n_0,
      R => '0'
    );
\full_ff_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF801180"
    )
        port map (
      I0 => FifoCntrWr(0),
      I1 => FifoCntrWr(1),
      I2 => \^req_fifo_wr_nn0\,
      I3 => FifoCntrWr(2),
      I4 => req_fifo_fl,
      O => \full_ff_i_1__5_n_0\
    );
full_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \full_ff_i_1__5_n_0\,
      Q => req_fifo_fl,
      R => SR(0)
    );
req_wvld_nn1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => empty_ff_reg_n_0,
      I1 => req_fifo_dout(40),
      I2 => dat_fifo_ep,
      O => tar_cq_wvld(0)
    );
tar_row_nn1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAEAAAAA"
    )
        port map (
      I0 => tar_row_nn1_reg,
      I1 => tar_req_ld_nn1,
      I2 => Q(0),
      I3 => empty_ff_reg_n_0,
      I4 => req_fifo_dout(40),
      I5 => dat_fifo_ep,
      O => tar_row_nn0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4\ is
  port (
    dat_fifo_ep : out STD_LOGIC;
    dat_fifo_wr_nn0 : out STD_LOGIC;
    \RdPtr_reg[1]_0\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wvld_nn1 : in STD_LOGIC;
    s_axi_wvld_nn1 : in STD_LOGIC;
    dat_exp_nn1 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \tar_dat_nn1_reg[31]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4\ is
  signal \FifoCntrRd[0]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[0]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[1]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[2]\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1__7_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__8_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \^dat_fifo_wr_nn0\ : STD_LOGIC;
  signal \empty_ff_i_1__19_n_0\ : STD_LOGIC;
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1\ : label is "soft_lutpair389";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1\ : label is "soft_lutpair389";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 144;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_35 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_35 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_35 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "usr_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__7\ : label is "soft_lutpair390";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__8\ : label is "soft_lutpair390";
begin
  dat_fifo_wr_nn0 <= \^dat_fifo_wr_nn0\;
\FifoCntrRd[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => req_wvld_nn1,
      I1 => empty_ff_reg_1(0),
      I2 => \^dat_fifo_wr_nn0\,
      I3 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[0]_i_1_n_0\
    );
\FifoCntrRd[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D5BF2A40"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => req_wvld_nn1,
      I2 => empty_ff_reg_1(0),
      I3 => \^dat_fifo_wr_nn0\,
      I4 => \FifoCntrRd_reg_n_0_[1]\,
      O => \FifoCntrRd[1]_i_1_n_0\
    );
\FifoCntrRd[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777EFFF08881000"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[1]\,
      I1 => \FifoCntrRd_reg_n_0_[0]\,
      I2 => req_wvld_nn1,
      I3 => empty_ff_reg_1(0),
      I4 => \^dat_fifo_wr_nn0\,
      I5 => \FifoCntrRd_reg_n_0_[2]\,
      O => \FifoCntrRd[2]_i_1_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[0]\,
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[1]\,
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[2]\,
      R => SR(0)
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(1 downto 0),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(3 downto 2),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(1 downto 0),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(3 downto 2),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(13 downto 12),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(15 downto 14),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(13 downto 12),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(15 downto 14),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(19 downto 18),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(21 downto 20),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(19 downto 18),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(21 downto 20),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(25 downto 24),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(27 downto 26),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(25 downto 24),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(27 downto 26),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(31 downto 30),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(33 downto 32),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(31 downto 30),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(33 downto 32),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(35 downto 34),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => \tar_dat_nn1_reg[31]\(7 downto 6),
      DIB(1 downto 0) => \tar_dat_nn1_reg[31]\(9 downto 8),
      DIC(1 downto 0) => \tar_dat_nn1_reg[31]\(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \RdPtr_reg[1]_0\(7 downto 6),
      DOB(1 downto 0) => \RdPtr_reg[1]_0\(9 downto 8),
      DOC(1 downto 0) => \RdPtr_reg[1]_0\(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
\RdPtr[0]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => RdPtr(0),
      I1 => req_wvld_nn1,
      I2 => empty_ff_reg_1(0),
      O => \RdPtr[0]_i_1__7_n_0\
    );
\RdPtr[1]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => RdPtr(0),
      I1 => empty_ff_reg_1(0),
      I2 => req_wvld_nn1,
      I3 => RdPtr(1),
      O => \RdPtr[1]_i_1__8_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__7_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__8_n_0\,
      Q => RdPtr(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5556AAAA"
    )
        port map (
      I0 => WrPtr(0),
      I1 => dat_exp_nn1(1),
      I2 => dat_exp_nn1(0),
      I3 => dat_exp_nn1(2),
      I4 => s_axi_wvld_nn1,
      O => \WrPtr[0]_i_1__8_n_0\
    );
\WrPtr[1]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777F88888880"
    )
        port map (
      I0 => WrPtr(0),
      I1 => s_axi_wvld_nn1,
      I2 => dat_exp_nn1(2),
      I3 => dat_exp_nn1(0),
      I4 => dat_exp_nn1(1),
      I5 => WrPtr(1),
      O => \WrPtr[1]_i_1__8_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__8_n_0\,
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__8_n_0\,
      Q => WrPtr(1),
      R => SR(0)
    );
dat_fifo_wr_nn1_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => s_axi_wvld_nn1,
      I1 => dat_exp_nn1(2),
      I2 => dat_exp_nn1(0),
      I3 => dat_exp_nn1(1),
      O => \^dat_fifo_wr_nn0\
    );
\empty_ff_i_1__19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555555D5FF"
    )
        port map (
      I0 => empty_ff_reg_0(0),
      I1 => empty_ff_reg_1(0),
      I2 => req_wvld_nn1,
      I3 => \FifoCntrRd_reg_n_0_[0]\,
      I4 => \FifoCntrRd_reg_n_0_[1]\,
      I5 => \FifoCntrRd_reg_n_0_[2]\,
      O => \empty_ff_i_1__19_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__19_n_0\,
      Q => dat_fifo_ep,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4_57\ is
  port (
    dat_fifo_ep : out STD_LOGIC;
    dat_fifo_wr_nn0 : out STD_LOGIC;
    \arb_win_nn2_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \arb_win_nn2_reg[1]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    user_clk : in STD_LOGIC;
    empty_ff_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    empty_ff_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_wvld_nn1 : in STD_LOGIC;
    s_axi_wvld_nn1 : in STD_LOGIC;
    \WrPtr_reg[1]_0\ : in STD_LOGIC;
    \WrPtr_reg[1]_1\ : in STD_LOGIC;
    \WrPtr_reg[1]_2\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    DataOut : in STD_LOGIC_VECTOR ( 35 downto 0 );
    I180 : in STD_LOGIC_VECTOR ( 35 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4_57\ : entity is "xdma_v4_1_8_GenericFIFO";
end \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4_57\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_GenericFIFO__parameterized4_57\ is
  signal \DataOut0_out__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \FifoCntrRd[0]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[1]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd[2]_i_1_n_0\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[0]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[1]\ : STD_LOGIC;
  signal \FifoCntrRd_reg_n_0_[2]\ : STD_LOGIC;
  signal RdPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \RdPtr[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \RdPtr[1]_i_1__9_n_0\ : STD_LOGIC;
  signal WrPtr : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \WrPtr[0]_i_1__10_n_0\ : STD_LOGIC;
  signal \WrPtr[1]_i_1__10_n_0\ : STD_LOGIC;
  signal \^dat_fifo_wr_nn0\ : STD_LOGIC;
  signal \empty_ff_i_1__20_n_0\ : STD_LOGIC;
  signal \tar_cq_be[1]_10\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FifoCntrRd[0]_i_1\ : label is "soft_lutpair363";
  attribute SOFT_HLUTNM of \FifoCntrRd[1]_i_1\ : label is "soft_lutpair363";
  attribute METHODOLOGY_DRC_VIOS : string;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_0_5 : label is "";
  attribute RTL_RAM_BITS : integer;
  attribute RTL_RAM_BITS of MemArray_reg_0_3_0_5 : label is 144;
  attribute RTL_RAM_NAME : string;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_0_5 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE : string;
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_0_5 : label is "RAM_SDP";
  attribute ram_addr_begin : integer;
  attribute ram_addr_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_addr_end : integer;
  attribute ram_addr_end of MemArray_reg_0_3_0_5 : label is 3;
  attribute ram_offset : integer;
  attribute ram_offset of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_begin : integer;
  attribute ram_slice_begin of MemArray_reg_0_3_0_5 : label is 0;
  attribute ram_slice_end : integer;
  attribute ram_slice_end of MemArray_reg_0_3_0_5 : label is 5;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_12_17 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_12_17 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_12_17 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_12_17 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_12_17 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_12_17 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_12_17 : label is 12;
  attribute ram_slice_end of MemArray_reg_0_3_12_17 : label is 17;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_18_23 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_18_23 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_18_23 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_18_23 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_18_23 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_18_23 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_18_23 : label is 18;
  attribute ram_slice_end of MemArray_reg_0_3_18_23 : label is 23;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_24_29 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_24_29 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_24_29 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_24_29 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_24_29 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_24_29 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_24_29 : label is 24;
  attribute ram_slice_end of MemArray_reg_0_3_24_29 : label is 29;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_30_35 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_30_35 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_30_35 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_30_35 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_30_35 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_30_35 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_30_35 : label is 30;
  attribute ram_slice_end of MemArray_reg_0_3_30_35 : label is 35;
  attribute METHODOLOGY_DRC_VIOS of MemArray_reg_0_3_6_11 : label is "";
  attribute RTL_RAM_BITS of MemArray_reg_0_3_6_11 : label is 144;
  attribute RTL_RAM_NAME of MemArray_reg_0_3_6_11 : label is "cq_axilt_slv/DAT_FIFO/MemArray";
  attribute RTL_RAM_TYPE of MemArray_reg_0_3_6_11 : label is "RAM_SDP";
  attribute ram_addr_begin of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_addr_end of MemArray_reg_0_3_6_11 : label is 3;
  attribute ram_offset of MemArray_reg_0_3_6_11 : label is 0;
  attribute ram_slice_begin of MemArray_reg_0_3_6_11 : label is 6;
  attribute ram_slice_end of MemArray_reg_0_3_6_11 : label is 11;
  attribute SOFT_HLUTNM of \RdPtr[0]_i_1__8\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \RdPtr[1]_i_1__9\ : label is "soft_lutpair364";
  attribute SOFT_HLUTNM of \tar_be_nn1[0]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \tar_be_nn1[1]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \tar_be_nn1[2]_i_1\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \tar_be_nn1[3]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \tar_dat_nn1[0]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \tar_dat_nn1[10]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \tar_dat_nn1[11]_i_1\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \tar_dat_nn1[12]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \tar_dat_nn1[13]_i_1\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \tar_dat_nn1[14]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \tar_dat_nn1[15]_i_1\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \tar_dat_nn1[16]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \tar_dat_nn1[17]_i_1\ : label is "soft_lutpair380";
  attribute SOFT_HLUTNM of \tar_dat_nn1[18]_i_1\ : label is "soft_lutpair369";
  attribute SOFT_HLUTNM of \tar_dat_nn1[19]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \tar_dat_nn1[1]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \tar_dat_nn1[20]_i_1\ : label is "soft_lutpair366";
  attribute SOFT_HLUTNM of \tar_dat_nn1[21]_i_1\ : label is "soft_lutpair375";
  attribute SOFT_HLUTNM of \tar_dat_nn1[22]_i_1\ : label is "soft_lutpair372";
  attribute SOFT_HLUTNM of \tar_dat_nn1[23]_i_1\ : label is "soft_lutpair379";
  attribute SOFT_HLUTNM of \tar_dat_nn1[24]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \tar_dat_nn1[25]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \tar_dat_nn1[26]_i_1\ : label is "soft_lutpair365";
  attribute SOFT_HLUTNM of \tar_dat_nn1[27]_i_1\ : label is "soft_lutpair374";
  attribute SOFT_HLUTNM of \tar_dat_nn1[28]_i_1\ : label is "soft_lutpair371";
  attribute SOFT_HLUTNM of \tar_dat_nn1[29]_i_1\ : label is "soft_lutpair378";
  attribute SOFT_HLUTNM of \tar_dat_nn1[2]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \tar_dat_nn1[30]_i_1\ : label is "soft_lutpair368";
  attribute SOFT_HLUTNM of \tar_dat_nn1[31]_i_1\ : label is "soft_lutpair377";
  attribute SOFT_HLUTNM of \tar_dat_nn1[3]_i_1\ : label is "soft_lutpair376";
  attribute SOFT_HLUTNM of \tar_dat_nn1[4]_i_1\ : label is "soft_lutpair373";
  attribute SOFT_HLUTNM of \tar_dat_nn1[5]_i_1\ : label is "soft_lutpair382";
  attribute SOFT_HLUTNM of \tar_dat_nn1[6]_i_1\ : label is "soft_lutpair370";
  attribute SOFT_HLUTNM of \tar_dat_nn1[7]_i_1\ : label is "soft_lutpair381";
  attribute SOFT_HLUTNM of \tar_dat_nn1[8]_i_1\ : label is "soft_lutpair367";
  attribute SOFT_HLUTNM of \tar_dat_nn1[9]_i_1\ : label is "soft_lutpair376";
begin
  dat_fifo_wr_nn0 <= \^dat_fifo_wr_nn0\;
\FifoCntrRd[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => req_wvld_nn1,
      I1 => empty_ff_reg_1(0),
      I2 => \^dat_fifo_wr_nn0\,
      I3 => \FifoCntrRd_reg_n_0_[0]\,
      O => \FifoCntrRd[0]_i_1_n_0\
    );
\FifoCntrRd[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D5BF2A40"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[0]\,
      I1 => req_wvld_nn1,
      I2 => empty_ff_reg_1(0),
      I3 => \^dat_fifo_wr_nn0\,
      I4 => \FifoCntrRd_reg_n_0_[1]\,
      O => \FifoCntrRd[1]_i_1_n_0\
    );
\FifoCntrRd[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F777EFFF08881000"
    )
        port map (
      I0 => \FifoCntrRd_reg_n_0_[1]\,
      I1 => \FifoCntrRd_reg_n_0_[0]\,
      I2 => req_wvld_nn1,
      I3 => empty_ff_reg_1(0),
      I4 => \^dat_fifo_wr_nn0\,
      I5 => \FifoCntrRd_reg_n_0_[2]\,
      O => \FifoCntrRd[2]_i_1_n_0\
    );
\FifoCntrRd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[0]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[0]\,
      R => SR(0)
    );
\FifoCntrRd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[1]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[1]\,
      R => SR(0)
    );
\FifoCntrRd_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \FifoCntrRd[2]_i_1_n_0\,
      Q => \FifoCntrRd_reg_n_0_[2]\,
      R => SR(0)
    );
MemArray_reg_0_3_0_5: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(1 downto 0),
      DIB(1 downto 0) => I180(3 downto 2),
      DIC(1 downto 0) => I180(5 downto 4),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(1 downto 0),
      DOB(1 downto 0) => \DataOut0_out__0\(3 downto 2),
      DOC(1 downto 0) => \DataOut0_out__0\(5 downto 4),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
\MemArray_reg_0_3_0_5_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => s_axi_wvld_nn1,
      I1 => \WrPtr_reg[1]_0\,
      I2 => \WrPtr_reg[1]_1\,
      I3 => \WrPtr_reg[1]_2\,
      O => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_12_17: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(13 downto 12),
      DIB(1 downto 0) => I180(15 downto 14),
      DIC(1 downto 0) => I180(17 downto 16),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(13 downto 12),
      DOB(1 downto 0) => \DataOut0_out__0\(15 downto 14),
      DOC(1 downto 0) => \DataOut0_out__0\(17 downto 16),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_18_23: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(19 downto 18),
      DIB(1 downto 0) => I180(21 downto 20),
      DIC(1 downto 0) => I180(23 downto 22),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(19 downto 18),
      DOB(1 downto 0) => \DataOut0_out__0\(21 downto 20),
      DOC(1 downto 0) => \DataOut0_out__0\(23 downto 22),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_24_29: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(25 downto 24),
      DIB(1 downto 0) => I180(27 downto 26),
      DIC(1 downto 0) => I180(29 downto 28),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(25 downto 24),
      DOB(1 downto 0) => \DataOut0_out__0\(27 downto 26),
      DOC(1 downto 0) => \DataOut0_out__0\(29 downto 28),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_30_35: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(31 downto 30),
      DIB(1 downto 0) => I180(33 downto 32),
      DIC(1 downto 0) => I180(35 downto 34),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(31 downto 30),
      DOB(1 downto 0) => \tar_cq_be[1]_10\(1 downto 0),
      DOC(1 downto 0) => \tar_cq_be[1]_10\(3 downto 2),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
MemArray_reg_0_3_6_11: unisim.vcomponents.RAM32M
     port map (
      ADDRA(4 downto 2) => B"000",
      ADDRA(1 downto 0) => RdPtr(1 downto 0),
      ADDRB(4 downto 2) => B"000",
      ADDRB(1 downto 0) => RdPtr(1 downto 0),
      ADDRC(4 downto 2) => B"000",
      ADDRC(1 downto 0) => RdPtr(1 downto 0),
      ADDRD(4 downto 2) => B"000",
      ADDRD(1 downto 0) => WrPtr(1 downto 0),
      DIA(1 downto 0) => I180(7 downto 6),
      DIB(1 downto 0) => I180(9 downto 8),
      DIC(1 downto 0) => I180(11 downto 10),
      DID(1 downto 0) => B"00",
      DOA(1 downto 0) => \DataOut0_out__0\(7 downto 6),
      DOB(1 downto 0) => \DataOut0_out__0\(9 downto 8),
      DOC(1 downto 0) => \DataOut0_out__0\(11 downto 10),
      DOD(1 downto 0) => NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED(1 downto 0),
      WCLK => user_clk,
      WE => \^dat_fifo_wr_nn0\
    );
\RdPtr[0]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => RdPtr(0),
      I1 => req_wvld_nn1,
      I2 => empty_ff_reg_1(0),
      O => \RdPtr[0]_i_1__8_n_0\
    );
\RdPtr[1]_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => RdPtr(0),
      I1 => empty_ff_reg_1(0),
      I2 => req_wvld_nn1,
      I3 => RdPtr(1),
      O => \RdPtr[1]_i_1__9_n_0\
    );
\RdPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[0]_i_1__8_n_0\,
      Q => RdPtr(0),
      R => SR(0)
    );
\RdPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RdPtr[1]_i_1__9_n_0\,
      Q => RdPtr(1),
      R => SR(0)
    );
\WrPtr[0]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5556AAAA"
    )
        port map (
      I0 => WrPtr(0),
      I1 => \WrPtr_reg[1]_2\,
      I2 => \WrPtr_reg[1]_1\,
      I3 => \WrPtr_reg[1]_0\,
      I4 => s_axi_wvld_nn1,
      O => \WrPtr[0]_i_1__10_n_0\
    );
\WrPtr[1]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7777777F88888880"
    )
        port map (
      I0 => WrPtr(0),
      I1 => s_axi_wvld_nn1,
      I2 => \WrPtr_reg[1]_0\,
      I3 => \WrPtr_reg[1]_1\,
      I4 => \WrPtr_reg[1]_2\,
      I5 => WrPtr(1),
      O => \WrPtr[1]_i_1__10_n_0\
    );
\WrPtr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[0]_i_1__10_n_0\,
      Q => WrPtr(0),
      R => SR(0)
    );
\WrPtr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \WrPtr[1]_i_1__10_n_0\,
      Q => WrPtr(1),
      R => SR(0)
    );
\empty_ff_i_1__20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555555555D5FF"
    )
        port map (
      I0 => empty_ff_reg_0(0),
      I1 => empty_ff_reg_1(0),
      I2 => req_wvld_nn1,
      I3 => \FifoCntrRd_reg_n_0_[0]\,
      I4 => \FifoCntrRd_reg_n_0_[1]\,
      I5 => \FifoCntrRd_reg_n_0_[2]\,
      O => \empty_ff_i_1__20_n_0\
    );
empty_ff_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \empty_ff_i_1__20_n_0\,
      Q => dat_fifo_ep,
      R => '0'
    );
\tar_be_nn1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tar_cq_be[1]_10\(0),
      I1 => Q(0),
      I2 => DataOut(32),
      O => \arb_win_nn2_reg[1]\(0)
    );
\tar_be_nn1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tar_cq_be[1]_10\(1),
      I1 => Q(0),
      I2 => DataOut(33),
      O => \arb_win_nn2_reg[1]\(1)
    );
\tar_be_nn1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tar_cq_be[1]_10\(2),
      I1 => Q(0),
      I2 => DataOut(34),
      O => \arb_win_nn2_reg[1]\(2)
    );
\tar_be_nn1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \tar_cq_be[1]_10\(3),
      I1 => Q(0),
      I2 => DataOut(35),
      O => \arb_win_nn2_reg[1]\(3)
    );
\tar_dat_nn1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(0),
      I1 => Q(0),
      I2 => DataOut(0),
      O => \arb_win_nn2_reg[1]_0\(0)
    );
\tar_dat_nn1[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(10),
      I1 => Q(0),
      I2 => DataOut(10),
      O => \arb_win_nn2_reg[1]_0\(10)
    );
\tar_dat_nn1[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(11),
      I1 => Q(0),
      I2 => DataOut(11),
      O => \arb_win_nn2_reg[1]_0\(11)
    );
\tar_dat_nn1[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(12),
      I1 => Q(0),
      I2 => DataOut(12),
      O => \arb_win_nn2_reg[1]_0\(12)
    );
\tar_dat_nn1[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(13),
      I1 => Q(0),
      I2 => DataOut(13),
      O => \arb_win_nn2_reg[1]_0\(13)
    );
\tar_dat_nn1[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(14),
      I1 => Q(0),
      I2 => DataOut(14),
      O => \arb_win_nn2_reg[1]_0\(14)
    );
\tar_dat_nn1[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(15),
      I1 => Q(0),
      I2 => DataOut(15),
      O => \arb_win_nn2_reg[1]_0\(15)
    );
\tar_dat_nn1[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(16),
      I1 => Q(0),
      I2 => DataOut(16),
      O => \arb_win_nn2_reg[1]_0\(16)
    );
\tar_dat_nn1[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(17),
      I1 => Q(0),
      I2 => DataOut(17),
      O => \arb_win_nn2_reg[1]_0\(17)
    );
\tar_dat_nn1[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(18),
      I1 => Q(0),
      I2 => DataOut(18),
      O => \arb_win_nn2_reg[1]_0\(18)
    );
\tar_dat_nn1[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(19),
      I1 => Q(0),
      I2 => DataOut(19),
      O => \arb_win_nn2_reg[1]_0\(19)
    );
\tar_dat_nn1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(1),
      I1 => Q(0),
      I2 => DataOut(1),
      O => \arb_win_nn2_reg[1]_0\(1)
    );
\tar_dat_nn1[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(20),
      I1 => Q(0),
      I2 => DataOut(20),
      O => \arb_win_nn2_reg[1]_0\(20)
    );
\tar_dat_nn1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(21),
      I1 => Q(0),
      I2 => DataOut(21),
      O => \arb_win_nn2_reg[1]_0\(21)
    );
\tar_dat_nn1[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(22),
      I1 => Q(0),
      I2 => DataOut(22),
      O => \arb_win_nn2_reg[1]_0\(22)
    );
\tar_dat_nn1[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(23),
      I1 => Q(0),
      I2 => DataOut(23),
      O => \arb_win_nn2_reg[1]_0\(23)
    );
\tar_dat_nn1[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(24),
      I1 => Q(0),
      I2 => DataOut(24),
      O => \arb_win_nn2_reg[1]_0\(24)
    );
\tar_dat_nn1[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(25),
      I1 => Q(0),
      I2 => DataOut(25),
      O => \arb_win_nn2_reg[1]_0\(25)
    );
\tar_dat_nn1[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(26),
      I1 => Q(0),
      I2 => DataOut(26),
      O => \arb_win_nn2_reg[1]_0\(26)
    );
\tar_dat_nn1[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(27),
      I1 => Q(0),
      I2 => DataOut(27),
      O => \arb_win_nn2_reg[1]_0\(27)
    );
\tar_dat_nn1[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(28),
      I1 => Q(0),
      I2 => DataOut(28),
      O => \arb_win_nn2_reg[1]_0\(28)
    );
\tar_dat_nn1[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(29),
      I1 => Q(0),
      I2 => DataOut(29),
      O => \arb_win_nn2_reg[1]_0\(29)
    );
\tar_dat_nn1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(2),
      I1 => Q(0),
      I2 => DataOut(2),
      O => \arb_win_nn2_reg[1]_0\(2)
    );
\tar_dat_nn1[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(30),
      I1 => Q(0),
      I2 => DataOut(30),
      O => \arb_win_nn2_reg[1]_0\(30)
    );
\tar_dat_nn1[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(31),
      I1 => Q(0),
      I2 => DataOut(31),
      O => \arb_win_nn2_reg[1]_0\(31)
    );
\tar_dat_nn1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(3),
      I1 => Q(0),
      I2 => DataOut(3),
      O => \arb_win_nn2_reg[1]_0\(3)
    );
\tar_dat_nn1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(4),
      I1 => Q(0),
      I2 => DataOut(4),
      O => \arb_win_nn2_reg[1]_0\(4)
    );
\tar_dat_nn1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(5),
      I1 => Q(0),
      I2 => DataOut(5),
      O => \arb_win_nn2_reg[1]_0\(5)
    );
\tar_dat_nn1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(6),
      I1 => Q(0),
      I2 => DataOut(6),
      O => \arb_win_nn2_reg[1]_0\(6)
    );
\tar_dat_nn1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(7),
      I1 => Q(0),
      I2 => DataOut(7),
      O => \arb_win_nn2_reg[1]_0\(7)
    );
\tar_dat_nn1[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(8),
      I1 => Q(0),
      I2 => DataOut(8),
      O => \arb_win_nn2_reg[1]_0\(8)
    );
\tar_dat_nn1[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \DataOut0_out__0\(9),
      I1 => Q(0),
      I2 => DataOut(9),
      O => \arb_win_nn2_reg[1]_0\(9)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xpm_cdc_single is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of xdma_0_xpm_cdc_single : entity is 4;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of xdma_0_xpm_cdc_single : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xpm_cdc_single : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of xdma_0_xpm_cdc_single : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of xdma_0_xpm_cdc_single : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of xdma_0_xpm_cdc_single : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of xdma_0_xpm_cdc_single : entity is "TRUE";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of xdma_0_xpm_cdc_single : entity is "true";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of xdma_0_xpm_cdc_single : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of xdma_0_xpm_cdc_single : entity is "SINGLE";
end xdma_0_xpm_cdc_single;

architecture STRUCTURE of xdma_0_xpm_cdc_single is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(3);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(1),
      Q => syncstages_ff(2),
      R => '0'
    );
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(2),
      Q => syncstages_ff(3),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xpm_cdc_single__parameterized0\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \xdma_0_xpm_cdc_single__parameterized0\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \xdma_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xpm_cdc_single__parameterized0\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \xdma_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \xdma_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \xdma_0_xpm_cdc_single__parameterized0\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \xdma_0_xpm_cdc_single__parameterized0\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \xdma_0_xpm_cdc_single__parameterized0\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \xdma_0_xpm_cdc_single__parameterized0\ : entity is "SINGLE";
end \xdma_0_xpm_cdc_single__parameterized0\;

architecture STRUCTURE of \xdma_0_xpm_cdc_single__parameterized0\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xpm_cdc_single__parameterized0__2\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is "TRUE";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is "true";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \xdma_0_xpm_cdc_single__parameterized0__2\ : entity is "SINGLE";
end \xdma_0_xpm_cdc_single__parameterized0__2\;

architecture STRUCTURE of \xdma_0_xpm_cdc_single__parameterized0__2\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_rx is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc_d : out STD_LOGIC;
    m_axis_rx_tvalid_reg : out STD_LOGIC;
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect_reg : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \trn_rbar_hit_prev_reg[0]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered : in STD_LOGIC;
    trn_reof : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    trn_in_packet_reg : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_rx : entity is "xdma_0_pcie2_ip_axi_basic_rx";
end xdma_0_xdma_0_pcie2_ip_axi_basic_rx;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_rx is
  signal \^q\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \^m_axis_rx_tvalid_reg\ : STD_LOGIC;
  signal new_pkt_len : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal null_mux_sel : STD_LOGIC;
  signal rx_null_gen_inst_n_0 : STD_LOGIC;
  signal rx_null_gen_inst_n_1 : STD_LOGIC;
  signal rx_null_gen_inst_n_2 : STD_LOGIC;
  signal rx_null_gen_inst_n_3 : STD_LOGIC;
  signal rx_null_gen_inst_n_4 : STD_LOGIC;
  signal rx_null_gen_inst_n_5 : STD_LOGIC;
  signal rx_null_gen_inst_n_6 : STD_LOGIC;
  signal rx_pipeline_inst_n_72 : STD_LOGIC;
  signal rx_pipeline_inst_n_73 : STD_LOGIC;
begin
  Q(63 downto 0) <= \^q\(63 downto 0);
  m_axis_rx_tuser(12 downto 0) <= \^m_axis_rx_tuser\(12 downto 0);
  m_axis_rx_tvalid_reg <= \^m_axis_rx_tvalid_reg\;
rx_null_gen_inst: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_rx_null_gen
     port map (
      CLK => CLK,
      D(1) => rx_null_gen_inst_n_0,
      D(0) => rx_null_gen_inst_n_1,
      Q(4 downto 3) => \^q\(30 downto 29),
      Q(2) => \^q\(15),
      Q(1 downto 0) => \^q\(1 downto 0),
      S(1) => rx_null_gen_inst_n_5,
      S(0) => rx_null_gen_inst_n_6,
      cur_state_reg_0 => rx_null_gen_inst_n_2,
      cur_state_reg_1 => \trn_rbar_hit_prev_reg[0]\,
      cur_state_reg_2 => \^m_axis_rx_tvalid_reg\,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(0) => \^m_axis_rx_tuser\(12),
      \m_axis_rx_tuser_reg[19]\ => rx_pipeline_inst_n_73,
      \m_axis_rx_tuser_reg[21]\ => rx_pipeline_inst_n_72,
      new_pkt_len(10 downto 0) => new_pkt_len(10 downto 0),
      null_mux_sel => null_mux_sel,
      \reg_pkt_len_counter_reg[0]_0\ => rx_null_gen_inst_n_4,
      \reg_tkeep[7]_i_7_0\ => rx_null_gen_inst_n_3
    );
rx_pipeline_inst: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_rx_pipeline
     port map (
      CLK => CLK,
      D(1) => rx_null_gen_inst_n_0,
      D(0) => rx_null_gen_inst_n_1,
      E(0) => E(0),
      Q(63 downto 0) => \^q\(63 downto 0),
      S(1) => rx_null_gen_inst_n_5,
      S(0) => rx_null_gen_inst_n_6,
      dsc_detect => dsc_detect,
      m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => \^m_axis_rx_tuser\(12 downto 0),
      m_axis_rx_tvalid_reg_0 => \^m_axis_rx_tvalid_reg\,
      new_pkt_len(10 downto 0) => new_pkt_len(10 downto 0),
      null_mux_sel => null_mux_sel,
      null_mux_sel_reg_0 => rx_null_gen_inst_n_4,
      reg_dsc_detect_reg_0 => reg_dsc_detect_reg,
      \reg_tkeep_reg[7]_0\ => rx_null_gen_inst_n_3,
      \reg_tkeep_reg[7]_1\ => rx_null_gen_inst_n_2,
      rsrc_rdy_filtered => rsrc_rdy_filtered,
      trn_in_packet => trn_in_packet,
      trn_in_packet_reg_0 => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      \trn_rbar_hit_prev_reg[0]_0\ => \trn_rbar_hit_prev_reg[0]\,
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_reof_prev_reg_0 => rx_pipeline_inst_n_72,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      \trn_rrem_prev_reg[0]_0\ => rx_pipeline_inst_n_73,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => trn_rsrc_dsc_d,
      trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_tx is
  port (
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_reg : out STD_LOGIC;
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    ppm_L1_thrtl : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    \throttle_ctl_pipeline.reg_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    ppm_L1_thrtl_reg : in STD_LOGIC;
    lnk_up_thrtl_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    tcfg_req_trig : in STD_LOGIC;
    tready_thrtl_i_3 : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_tx : entity is "xdma_0_pcie2_ip_axi_basic_tx";
end xdma_0_xdma_0_pcie2_ip_axi_basic_tx;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_tx is
  signal axi_in_packet : STD_LOGIC;
  signal reg_disable_trn : STD_LOGIC;
  signal reg_tsrc_rdy0 : STD_LOGIC;
  signal \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\ : STD_LOGIC;
  signal \^tready_thrtl_reg\ : STD_LOGIC;
begin
  tready_thrtl_reg <= \^tready_thrtl_reg\;
\thrtl_ctl_enabled.tx_thrl_ctl_inst\: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl
     port map (
      CLK => CLK,
      axi_in_packet => axi_in_packet,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      lnk_up_thrtl => lnk_up_thrtl,
      lnk_up_thrtl_reg_0 => lnk_up_thrtl_reg,
      \out\ => \out\,
      ppm_L1_thrtl => ppm_L1_thrtl,
      ppm_L1_thrtl_reg_0 => ppm_L1_thrtl_reg,
      ppm_L1_trig => ppm_L1_trig,
      reg_disable_trn => reg_disable_trn,
      reg_tcfg_gnt => reg_tcfg_gnt,
      reg_tsrc_rdy0 => reg_tsrc_rdy0,
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tlast_reg => \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => tbuf_av_min_trig,
      \tbuf_gap_cnt_reg[0]_0\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\,
      tcfg_req_trig => tcfg_req_trig,
      tready_thrtl_i_3_0 => tready_thrtl_i_3,
      tready_thrtl_reg_0 => \^tready_thrtl_reg\,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy
    );
tx_pipeline_inst: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_tx_pipeline
     port map (
      CLK => CLK,
      axi_in_packet => axi_in_packet,
      axi_in_packet_reg_0 => \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4\,
      \out\ => \out\,
      reg_disable_trn => reg_disable_trn,
      reg_tsrc_rdy0 => reg_tsrc_rdy0,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      \throttle_ctl_pipeline.reg_tdata_reg[63]_0\(63 downto 0) => \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0),
      \throttle_ctl_pipeline.reg_tkeep_reg[7]_0\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\,
      \thrtl_ctl_trn_flush.reg_disable_trn_reg_0\ => \^tready_thrtl_reg\,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_21
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_16 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_16 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_16;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_16 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_20
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_17 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_17 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_17;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_17 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_19
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_18 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_18 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_18;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_18 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(14 downto 0),
      wdata(14 downto 0) => wdata(14 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_22 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_22 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_22;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_22 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_29
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_23 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_23 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_23;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_23 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_28
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_24 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_24 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_24;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_24 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_27
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_25 is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_25 : entity is "xdma_0_pcie2_ip_pcie_bram_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_25;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_25 is
begin
\use_tdp.ramb36\: entity work.xdma_0_BRAM_TDP_MACRO_26
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(13 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(13 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1\(13 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(13 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_pipe_pipeline is
  port (
    pipe_rx1_valid : out STD_LOGIC;
    pipe_rx1_chanisaligned : out STD_LOGIC;
    pipe_rx1_phy_status : out STD_LOGIC;
    pipe_rx1_elec_idle : out STD_LOGIC;
    pipe_rx0_polarity_gt : out STD_LOGIC;
    pipe_rx1_polarity_gt : out STD_LOGIC;
    TXCHARDISPMODE : out STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_compliance_q_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx0_elec_idle_gt : out STD_LOGIC;
    pipe_tx1_elec_idle_gt : out STD_LOGIC;
    pipe_tx_rcvr_det_gt : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_deemph_gt : out STD_LOGIC;
    pipe_rx0_valid : out STD_LOGIC;
    pipe_rx0_chanisaligned : out STD_LOGIC;
    pipe_rx0_phy_status : out STD_LOGIC;
    pipe_rx0_elec_idle : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_valid_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_deemph_q_reg\ : in STD_LOGIC;
    pipe_rx1_chanisaligned_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : in STD_LOGIC;
    pipe_rx0_polarity : in STD_LOGIC;
    pipe_rx1_polarity : in STD_LOGIC;
    pipe_tx0_compliance : in STD_LOGIC;
    pipe_tx1_compliance : in STD_LOGIC;
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_tx1_elec_idle : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    pipe_rx0_valid_gt : in STD_LOGIC;
    pipe_rx0_chanisaligned_gt : in STD_LOGIC;
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_pipe_pipeline : entity is "xdma_0_pcie2_ip_pcie_pipe_pipeline";
end xdma_0_xdma_0_pcie2_ip_pcie_pipe_pipeline;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_pipe_pipeline is
begin
\pipe_2_lane.pipe_lane_1_i\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane
     port map (
      Q(1 downto 0) => Q(1 downto 0),
      SR(0) => SR(0),
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_elec_idle => pipe_rx1_elec_idle,
      pipe_rx1_phy_status => pipe_rx1_phy_status,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx1_valid_gt => pipe_rx1_valid_gt,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg_0\ => \pipe_stages_1.pipe_tx_deemph_q_reg\,
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\(1 downto 0),
      \pipe_stages_1.pipe_tx_compliance_q_reg_0\(0) => \pipe_stages_1.pipe_tx_compliance_q_reg\(0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_2\(15 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt
    );
pipe_lane_0_i: entity work.xdma_0_xdma_0_pcie2_ip_pcie_pipe_lane_14
     port map (
      SR(0) => SR(0),
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rxelecidle_q => gt_rxelecidle_q,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_elec_idle => pipe_rx0_elec_idle,
      pipe_rx0_phy_status => pipe_rx0_phy_status,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx0_valid_gt => pipe_rx0_valid_gt,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg_0\ => \pipe_stages_1.pipe_tx_deemph_q_reg\,
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt
    );
pipe_misc_i: entity work.xdma_0_xdma_0_pcie2_ip_pcie_pipe_misc
     port map (
      D(0) => D(0),
      SR(0) => SR(0),
      \pipe_stages_1.pipe_tx_deemph_q_reg_0\ => \pipe_stages_1.pipe_tx_deemph_q_reg\,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rate => pipe_tx_rate,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_eq is
  port (
    eq_rxeq_adapt_done_0 : out STD_LOGIC;
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rst_cpllreset : in STD_LOGIC;
    \fs_reg2_reg[5]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_eq : entity is "xdma_0_pcie2_ip_pipe_eq";
end xdma_0_xdma_0_pcie2_ip_pipe_eq;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_eq is
  signal \FSM_onehot_fsm_rx[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_4_n_0\ : STD_LOGIC;
  signal \^eq_rxeq_adapt_done_0\ : STD_LOGIC;
  signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal in10 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_adapt_done_i_2_n_0 : STD_LOGIC;
  signal rxeq_adapt_done_reg_i_2_n_0 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO";
  attribute async_reg of rxeq_control_reg1 : signal is "true";
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO";
  attribute async_reg of rxeq_control_reg2 : signal is "true";
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg1 : signal is "true";
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg2 : signal is "true";
  signal rxeq_new_txcoeff_req : STD_LOGIC;
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_3_n_0\ : STD_LOGIC;
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO";
  attribute async_reg of rxeq_preset_reg1 : signal is "true";
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO";
  attribute async_reg of rxeq_preset_reg2 : signal is "true";
  signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset[3]_i_3_n_0\ : STD_LOGIC;
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg1 : signal is "true";
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg2 : signal is "true";
  signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC;
  signal rxeq_user_en_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg1 : signal is "true";
  signal rxeq_user_en_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg2 : signal is "true";
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg1 : signal is "true";
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg2 : signal is "true";
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true";
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true";
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO";
  attribute async_reg of txeq_control_reg1 : signal is "true";
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO";
  attribute async_reg of txeq_control_reg2 : signal is "true";
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO";
  attribute async_reg of txeq_deemph_reg1 : signal is "true";
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO";
  attribute async_reg of txeq_deemph_reg2 : signal is "true";
  signal \txeq_preset[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_2_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_done_i_1_n_0 : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO";
  attribute async_reg of txeq_preset_reg1 : signal is "true";
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO";
  attribute async_reg of txeq_preset_reg2 : signal is "true";
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal txeq_txcoeff : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1\ : label is "soft_lutpair1842";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_4\ : label is "soft_lutpair1840";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1\ : label is "soft_lutpair1843";
  attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1\ : label is "soft_lutpair1842";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3\ : label is "soft_lutpair1843";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1\ : label is "soft_lutpair1844";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1\ : label is "soft_lutpair1849";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1\ : label is "soft_lutpair1849";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1\ : label is "soft_lutpair1844";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1\ : label is "soft_lutpair1845";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1\ : label is "soft_lutpair1845";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1\ : label is "soft_lutpair1846";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1\ : label is "soft_lutpair1846";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1\ : label is "soft_lutpair1847";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1\ : label is "soft_lutpair1847";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1\ : label is "soft_lutpair1848";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1\ : label is "soft_lutpair1848";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO";
  attribute SOFT_HLUTNM of \txeq_txcoeff[0]_i_1\ : label is "soft_lutpair1840";
  attribute SOFT_HLUTNM of \txeq_txcoeff[18]_i_3\ : label is "soft_lutpair1841";
  attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1\ : label is "soft_lutpair1841";
begin
  eq_rxeq_adapt_done_0 <= \^eq_rxeq_adapt_done_0\;
\FSM_onehot_fsm_rx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \FSM_onehot_fsm_rx[1]_i_1_n_0\
    );
\FSM_onehot_fsm_rx[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \FSM_onehot_fsm_rx[1]_i_2_n_0\
    );
\FSM_onehot_fsm_rx[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[3]_i_1_n_0\
    );
\FSM_onehot_fsm_rx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2ABA2AAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[4]_i_1_n_0\
    );
\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[3]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\FSM_sequential_fsm_tx[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C04FC043C04FF04F"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(0)
    );
\FSM_sequential_fsm_tx[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F703F7C3F7C0F70"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(1)
    );
\FSM_sequential_fsm_tx[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_tx[1]_i_2_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A8A8A8AAA8A8"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[2]_i_2_n_0\,
      I1 => \FSM_sequential_fsm_tx[2]_i_3_n_0\,
      I2 => fsm_tx(2),
      I3 => \FSM_sequential_fsm_tx[2]_i_4_n_0\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => \fsm_tx__0\(2)
    );
\FSM_sequential_fsm_tx[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7777FFF7"
    )
        port map (
      I0 => fsm_tx(1),
      I1 => fsm_tx(2),
      I2 => txeq_control_reg2(1),
      I3 => txeq_control_reg2(0),
      I4 => fsm_tx(0),
      O => \FSM_sequential_fsm_tx[2]_i_2_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F800080"
    )
        port map (
      I0 => txeq_control_reg2(1),
      I1 => txeq_control_reg2(0),
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => txeq_preset_done,
      O => \FSM_sequential_fsm_tx[2]_i_3_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => fsm_tx(0),
      I1 => fsm_tx(1),
      O => \FSM_sequential_fsm_tx[2]_i_4_n_0\
    );
\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(0),
      Q => fsm_tx(0),
      S => rst_cpllreset
    );
\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(1),
      Q => fsm_tx(1),
      R => rst_cpllreset
    );
\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(2),
      Q => fsm_tx(2),
      R => rst_cpllreset
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => rst_cpllreset
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rst_cpllreset
    );
\gtp_channel.gtpe2_channel_i_i_20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtp_channel.gtpe2_channel_i_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => gen3_reg2,
      O => TXPRECURSOR(0)
    );
\gtp_channel.gtpe2_channel_i_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtp_channel.gtpe2_channel_i_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtp_channel.gtpe2_channel_i_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => rxeq_adapt_done_i_2_n_0
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \^eq_rxeq_adapt_done_0\,
      R => rst_cpllreset
    );
rxeq_adapt_done_reg_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      O => rxeq_adapt_done_reg_i_2_n_0
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => rst_cpllreset
    );
\rxeq_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888FFF8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => rst_cpllreset
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => rst_cpllreset
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => rst_cpllreset
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => rst_cpllreset
    );
\rxeq_fs[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      O => \rxeq_fs[5]_i_1_n_0\
    );
\rxeq_fs[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_lf[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      O => \rxeq_lf[5]_i_1_n_0\
    );
\rxeq_lf[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => rst_cpllreset
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_new_txcoeff_req,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => rst_cpllreset
    );
\rxeq_preset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[0]\,
      O => \rxeq_preset[0]_i_1_n_0\
    );
\rxeq_preset[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[1]\,
      O => \rxeq_preset[1]_i_1_n_0\
    );
\rxeq_preset[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_1_n_0\
    );
\rxeq_preset[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0002"
    )
        port map (
      I0 => \rxeq_preset[2]_i_3_n_0\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I4 => rxeq_adapt_done_reg_i_2_n_0,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_2_n_0\
    );
\rxeq_preset[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_preset[2]_i_3_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => rst_cpllreset
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => rst_cpllreset
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => rst_cpllreset
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[0]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[1]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[2]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[2]\,
      R => rst_cpllreset
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q => rxeq_preset_valid,
      R => rst_cpllreset
    );
rxeq_scan_i: entity work.xdma_0_xdma_0_pcie2_ip_rxeq_scan_37
     port map (
      D(2) => rxeq_scan_i_n_2,
      D(1) => rxeq_scan_i_n_3,
      D(0) => rxeq_scan_i_n_4,
      \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\,
      \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\,
      \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\,
      Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      adapt_done_reg_0 => rxeq_scan_i_n_0,
      eq_rxeq_adapt_done_0 => \^eq_rxeq_adapt_done_0\,
      \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\,
      \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\,
      \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\,
      \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\,
      \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\,
      \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\,
      \fs_reg2_reg[5]_0\ => \fs_reg2_reg[5]\,
      \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\,
      \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\,
      \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\,
      \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\,
      \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\,
      \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\,
      new_txcoeff_done_reg_0 => rxeq_scan_i_n_1,
      new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\,
      \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\,
      \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\,
      rst_cpllreset => rst_cpllreset,
      rxeq_adapt_done_reg => rxeq_adapt_done_i_2_n_0,
      rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_i_2_n_0,
      rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0,
      rxeq_new_txcoeff_req => rxeq_new_txcoeff_req,
      rxeq_preset_valid => rxeq_preset_valid,
      \txcoeff_reg1_reg[17]_0\(17 downto 6) => in10(11 downto 0),
      \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\,
      \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\,
      \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\,
      \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\,
      \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\,
      \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\,
      \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\,
      \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\,
      \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\,
      \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\
    );
\rxeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(10),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(11),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(6),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(7),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(8),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(9),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(10),
      Q => in10(4),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(11),
      Q => in10(5),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(12),
      Q => in10(6),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(13),
      Q => in10(7),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(14),
      Q => in10(8),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(15),
      Q => in10(9),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(16),
      Q => in10(10),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(17),
      Q => in10(11),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(6),
      Q => in10(0),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(7),
      Q => in10(1),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(8),
      Q => in10(2),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(9),
      Q => in10(3),
      R => rst_cpllreset
    );
\rxeq_txpreset[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF044"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \rxeq_txpreset[3]_i_3_n_0\,
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_txpreset[3]_i_1_n_0\
    );
\rxeq_txpreset[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \rxeq_txpreset[3]_i_3_n_0\
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset_reg_n_0_[3]\,
      R => rst_cpllreset
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => rst_cpllreset
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => rst_cpllreset
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => rst_cpllreset
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => rst_cpllreset
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => rst_cpllreset
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => rst_cpllreset
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => rst_cpllreset
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => rst_cpllreset
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => rst_cpllreset
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => rst_cpllreset
    );
\txeq_preset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => rst_cpllreset,
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(0)
    );
\txeq_preset[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABBAF"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(10)
    );
\txeq_preset[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1811"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => rst_cpllreset,
      O => p_0_out(11)
    );
\txeq_preset[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01111510"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(12)
    );
\txeq_preset[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000010"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(13)
    );
\txeq_preset[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100100"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(14)
    );
\txeq_preset[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F1"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => rst_cpllreset,
      I3 => txeq_preset_reg2(3),
      O => p_0_out(15)
    );
\txeq_preset[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => rst_cpllreset,
      O => p_0_out(16)
    );
\txeq_preset[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      O => \txeq_preset[17]_i_1_n_0\
    );
\txeq_preset[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1091"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => rst_cpllreset,
      O => p_0_out(17)
    );
\txeq_preset[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(1)
    );
\txeq_preset[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      O => p_0_out(2)
    );
\txeq_preset[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00441140"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => \txeq_preset[3]_i_1_n_0\
    );
\txeq_preset[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAA3C00AAAA"
    )
        port map (
      I0 => \txeq_preset_reg_n_0_[7]\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \txeq_preset[7]_i_2_n_0\,
      I4 => \txeq_preset[17]_i_1_n_0\,
      I5 => rst_cpllreset,
      O => \txeq_preset[7]_i_1_n_0\
    );
\txeq_preset[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      O => \txeq_preset[7]_i_2_n_0\
    );
\txeq_preset[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABEAFAF"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(8)
    );
\txeq_preset[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CFCCCCFD"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(2),
      O => p_0_out(9)
    );
txeq_preset_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      O => txeq_preset_done_i_1_n_0
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_done_i_1_n_0,
      Q => txeq_preset_done,
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => rst_cpllreset
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(0),
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(10),
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(11),
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(12),
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(13),
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(14),
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(15),
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(16),
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(17),
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(1),
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(2),
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[3]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset[7]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(8),
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(9),
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45404040"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => \txeq_txcoeff[0]_i_2_n_0\,
      I2 => fsm_tx(1),
      I3 => fsm_tx(0),
      I4 => \txeq_txcoeff_reg_n_0_[6]\,
      O => \txeq_txcoeff[0]_i_1_n_0\
    );
\txeq_txcoeff[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[0]\,
      O => \txeq_txcoeff[0]_i_2_n_0\
    );
\txeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[10]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[16]\,
      O => \txeq_txcoeff[10]_i_1_n_0\
    );
\txeq_txcoeff[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[10]\,
      O => \txeq_txcoeff[10]_i_2_n_0\
    );
\txeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[11]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[17]\,
      O => \txeq_txcoeff[11]_i_1_n_0\
    );
\txeq_txcoeff[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[18]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[17]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[11]\,
      O => \txeq_txcoeff[11]_i_2_n_0\
    );
\txeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[12]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[18]\,
      O => \txeq_txcoeff[12]_i_1_n_0\
    );
\txeq_txcoeff[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[18]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[12]\,
      O => \txeq_txcoeff[12]_i_2_n_0\
    );
\txeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[13]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(0),
      O => \txeq_txcoeff[13]_i_1_n_0\
    );
\txeq_txcoeff[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(0),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[13]\,
      O => \txeq_txcoeff[13]_i_2_n_0\
    );
\txeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[14]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(1),
      O => \txeq_txcoeff[14]_i_1_n_0\
    );
\txeq_txcoeff[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(1),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[14]\,
      O => \txeq_txcoeff[14]_i_2_n_0\
    );
\txeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[15]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(2),
      O => \txeq_txcoeff[15]_i_1_n_0\
    );
\txeq_txcoeff[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(2),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[15]\,
      O => \txeq_txcoeff[15]_i_2_n_0\
    );
\txeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[16]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(3),
      O => \txeq_txcoeff[16]_i_1_n_0\
    );
\txeq_txcoeff[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(3),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[16]\,
      O => \txeq_txcoeff[16]_i_2_n_0\
    );
\txeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[17]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(4),
      O => \txeq_txcoeff[17]_i_1_n_0\
    );
\txeq_txcoeff[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(4),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[17]\,
      O => \txeq_txcoeff[17]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040FFF"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      O => txeq_txcoeff
    );
\txeq_txcoeff[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440F440044004400"
    )
        port map (
      I0 => fsm_tx(1),
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      I2 => \txeq_txcoeff[18]_i_3_n_0\,
      I3 => fsm_tx(2),
      I4 => txeq_deemph_reg2(5),
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[18]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      O => \txeq_txcoeff[18]_i_3_n_0\
    );
\txeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[1]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[1]_i_1_n_0\
    );
\txeq_txcoeff[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2_n_0\
    );
\txeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[1]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[2]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[8]\,
      O => \txeq_txcoeff[2]_i_1_n_0\
    );
\txeq_txcoeff[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[2]\,
      O => \txeq_txcoeff[2]_i_2_n_0\
    );
\txeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[2]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[3]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[9]\,
      O => \txeq_txcoeff[3]_i_1_n_0\
    );
\txeq_txcoeff[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2_n_0\
    );
\txeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[3]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[4]_i_2_n_0\,
      O => \txeq_txcoeff[4]_i_1_n_0\
    );
\txeq_txcoeff[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0E0A0A0A020A0A0"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[11]\,
      O => \txeq_txcoeff[4]_i_2_n_0\
    );
\txeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[4]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[5]_i_2_n_0\,
      O => \txeq_txcoeff[5]_i_1_n_0\
    );
\txeq_txcoeff[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0E0A0A0A020A0A0"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[12]\,
      O => \txeq_txcoeff[5]_i_2_n_0\
    );
\txeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[5]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[6]_i_2_n_0\,
      O => \txeq_txcoeff[6]_i_1_n_0\
    );
\txeq_txcoeff[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CACCCCCC00000000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => fsm_tx(1),
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[6]_i_2_n_0\
    );
\txeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[7]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[7]_i_1_n_0\
    );
\txeq_txcoeff[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[7]\,
      O => \txeq_txcoeff[7]_i_2_n_0\
    );
\txeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[8]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[14]\,
      O => \txeq_txcoeff[8]_i_1_n_0\
    );
\txeq_txcoeff[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[8]\,
      O => \txeq_txcoeff[8]_i_2_n_0\
    );
\txeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[9]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[15]\,
      O => \txeq_txcoeff[9]_i_1_n_0\
    );
\txeq_txcoeff[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[9]\,
      O => \txeq_txcoeff[9]_i_2_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000004000F000400"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => fsm_tx(2),
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[0]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[10]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[11]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[12]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[13]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[14]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[15]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[16]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[17]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[18]_i_2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[1]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[2]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[3]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[4]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[5]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[6]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[7]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[8]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[9]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_eq_34 is
  port (
    eq_rxeq_adapt_done_1 : out STD_LOGIC;
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    rst_cpllreset : in STD_LOGIC;
    \lf_reg2_reg[5]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_eq_34 : entity is "xdma_0_pcie2_ip_pipe_eq";
end xdma_0_xdma_0_pcie2_ip_pipe_eq_34;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_eq_34 is
  signal \FSM_onehot_fsm_rx[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \^eq_rxeq_adapt_done_1\ : STD_LOGIC;
  signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal in10 : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_adapt_done_i_2__0_n_0\ : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__0_n_0\ : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO";
  attribute async_reg of rxeq_control_reg1 : signal is "true";
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO";
  attribute async_reg of rxeq_control_reg2 : signal is "true";
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg1 : signal is "true";
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg2 : signal is "true";
  signal rxeq_new_txcoeff_req : STD_LOGIC;
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_3__0_n_0\ : STD_LOGIC;
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO";
  attribute async_reg of rxeq_preset_reg1 : signal is "true";
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO";
  attribute async_reg of rxeq_preset_reg2 : signal is "true";
  signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset[3]_i_3__0_n_0\ : STD_LOGIC;
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg1 : signal is "true";
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg2 : signal is "true";
  signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC;
  signal rxeq_user_en_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg1 : signal is "true";
  signal rxeq_user_en_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg2 : signal is "true";
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg1 : signal is "true";
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg2 : signal is "true";
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true";
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true";
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO";
  attribute async_reg of txeq_control_reg1 : signal is "true";
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO";
  attribute async_reg of txeq_control_reg2 : signal is "true";
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO";
  attribute async_reg of txeq_deemph_reg1 : signal is "true";
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO";
  attribute async_reg of txeq_deemph_reg2 : signal is "true";
  signal \txeq_preset[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_2__0_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal \txeq_preset_done_i_1__0_n_0\ : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO";
  attribute async_reg of txeq_preset_reg1 : signal is "true";
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO";
  attribute async_reg of txeq_preset_reg2 : signal is "true";
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal txeq_txcoeff : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__0_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1__0\ : label is "soft_lutpair1889";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2__0\ : label is "soft_lutpair1887";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1__0\ : label is "soft_lutpair1890";
  attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1__0\ : label is "soft_lutpair1889";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3__0\ : label is "soft_lutpair1890";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1__0\ : label is "soft_lutpair1891";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1__0\ : label is "soft_lutpair1896";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1__0\ : label is "soft_lutpair1896";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1__0\ : label is "soft_lutpair1891";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1__0\ : label is "soft_lutpair1892";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1__0\ : label is "soft_lutpair1892";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1__0\ : label is "soft_lutpair1893";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1__0\ : label is "soft_lutpair1893";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1__0\ : label is "soft_lutpair1894";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1__0\ : label is "soft_lutpair1894";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1__0\ : label is "soft_lutpair1895";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1__0\ : label is "soft_lutpair1895";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO";
  attribute SOFT_HLUTNM of \txeq_preset_done_i_1__0\ : label is "soft_lutpair1888";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO";
  attribute SOFT_HLUTNM of \txeq_txcoeff[18]_i_3__0\ : label is "soft_lutpair1887";
  attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1__0\ : label is "soft_lutpair1888";
begin
  eq_rxeq_adapt_done_1 <= \^eq_rxeq_adapt_done_1\;
\FSM_onehot_fsm_rx[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\
    );
\FSM_onehot_fsm_rx[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2ABA2AAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      S => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\FSM_sequential_fsm_tx[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C04FC043C04FF04F"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(0)
    );
\FSM_sequential_fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F703F7C3F7C0F70"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(1)
    );
\FSM_sequential_fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3A2A2A227F7F7F77"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      I5 => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\,
      O => \fsm_tx__0\(2)
    );
\FSM_sequential_fsm_tx[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFDFFF"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => txeq_preset_done,
      O => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\
    );
\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(0),
      Q => fsm_tx(0),
      S => rst_cpllreset
    );
\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(1),
      Q => fsm_tx(1),
      R => rst_cpllreset
    );
\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(2),
      Q => fsm_tx(2),
      R => rst_cpllreset
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => gen3_reg1,
      R => rst_cpllreset
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rst_cpllreset
    );
\gtp_channel.gtpe2_channel_i_i_22__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_23__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_24__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_25__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_26__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtp_channel.gtpe2_channel_i_i_27__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_28__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_29__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_30__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_31__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => gen3_reg2,
      O => TXPRECURSOR(0)
    );
\gtp_channel.gtpe2_channel_i_i_32__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtp_channel.gtpe2_channel_i_i_33__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtp_channel.gtpe2_channel_i_i_34__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtp_channel.gtpe2_channel_i_i_35__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtp_channel.gtpe2_channel_i_i_36__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtp_channel.gtpe2_channel_i_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtp_channel.gtpe2_channel_i_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
\rxeq_adapt_done_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \rxeq_adapt_done_i_2__0_n_0\
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \^eq_rxeq_adapt_done_1\,
      R => rst_cpllreset
    );
\rxeq_adapt_done_reg_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      O => \rxeq_adapt_done_reg_i_2__0_n_0\
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => rst_cpllreset
    );
\rxeq_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888FFF8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => rst_cpllreset
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => rst_cpllreset
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => rst_cpllreset
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => rst_cpllreset
    );
\rxeq_fs[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      O => \rxeq_fs[5]_i_1__0_n_0\
    );
\rxeq_fs[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_lf[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      O => \rxeq_lf[5]_i_1__0_n_0\
    );
\rxeq_lf[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => rst_cpllreset
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => rst_cpllreset
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => rst_cpllreset
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_new_txcoeff_req,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => rst_cpllreset
    );
\rxeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[0]\,
      O => \rxeq_preset[0]_i_1__0_n_0\
    );
\rxeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[1]\,
      O => \rxeq_preset[1]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0002"
    )
        port map (
      I0 => \rxeq_preset[2]_i_3__0_n_0\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I4 => \rxeq_adapt_done_reg_i_2__0_n_0\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_2__0_n_0\
    );
\rxeq_preset[2]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_preset[2]_i_3__0_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => rst_cpllreset
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => rst_cpllreset
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => rst_cpllreset
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => rst_cpllreset
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[0]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[1]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[2]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[2]\,
      R => rst_cpllreset
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q => rxeq_preset_valid,
      R => rst_cpllreset
    );
rxeq_scan_i: entity work.xdma_0_xdma_0_pcie2_ip_rxeq_scan
     port map (
      D(2) => rxeq_scan_i_n_2,
      D(1) => rxeq_scan_i_n_3,
      D(0) => rxeq_scan_i_n_4,
      \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\,
      \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\,
      \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\,
      Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      adapt_done_reg_0 => rxeq_scan_i_n_0,
      eq_rxeq_adapt_done_1 => \^eq_rxeq_adapt_done_1\,
      \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\,
      \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\,
      \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\,
      \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\,
      \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\,
      \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\,
      \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\,
      \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\,
      \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\,
      \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\,
      \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\,
      \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\,
      \lf_reg2_reg[5]_0\ => \lf_reg2_reg[5]\,
      new_txcoeff_done_reg_0 => rxeq_scan_i_n_1,
      new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\,
      \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\,
      \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\,
      rst_cpllreset => rst_cpllreset,
      rxeq_adapt_done_reg => \rxeq_adapt_done_i_2__0_n_0\,
      rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      rxeq_adapt_done_reg_reg_0 => \rxeq_adapt_done_reg_i_2__0_n_0\,
      rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0,
      rxeq_new_txcoeff_req => rxeq_new_txcoeff_req,
      rxeq_preset_valid => rxeq_preset_valid,
      \txcoeff_reg1_reg[17]_0\(17 downto 6) => in10(11 downto 0),
      \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\,
      \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\,
      \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\,
      \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\,
      \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\,
      \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\,
      \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\,
      \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\,
      \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\,
      \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\
    );
\rxeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(10),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(11),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(6),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(7),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(8),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => in10(9),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(10),
      Q => in10(4),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(11),
      Q => in10(5),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(12),
      Q => in10(6),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(13),
      Q => in10(7),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(14),
      Q => in10(8),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(15),
      Q => in10(9),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(16),
      Q => in10(10),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(17),
      Q => in10(11),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(6),
      Q => in10(0),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(7),
      Q => in10(1),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(8),
      Q => in10(2),
      R => rst_cpllreset
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(9),
      Q => in10(3),
      R => rst_cpllreset
    );
\rxeq_txpreset[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF044"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \rxeq_txpreset[3]_i_3__0_n_0\,
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_txpreset[3]_i_1__0_n_0\
    );
\rxeq_txpreset[3]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset[3]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \rxeq_txpreset[3]_i_3__0_n_0\
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset_reg_n_0_[3]\,
      R => rst_cpllreset
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => rst_cpllreset
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => rst_cpllreset
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => rst_cpllreset
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => rst_cpllreset
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => rst_cpllreset
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => rst_cpllreset
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => rst_cpllreset
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => rst_cpllreset
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => rst_cpllreset
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => rst_cpllreset
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => rst_cpllreset
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => rst_cpllreset
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => rst_cpllreset
    );
\txeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => rst_cpllreset,
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(0)
    );
\txeq_preset[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABBAF"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(10)
    );
\txeq_preset[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1811"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => rst_cpllreset,
      O => p_0_out(11)
    );
\txeq_preset[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01111510"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(12)
    );
\txeq_preset[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000010"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(13)
    );
\txeq_preset[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100100"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(14)
    );
\txeq_preset[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F1"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => rst_cpllreset,
      I3 => txeq_preset_reg2(3),
      O => p_0_out(15)
    );
\txeq_preset[16]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => rst_cpllreset,
      O => p_0_out(16)
    );
\txeq_preset[17]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      O => \txeq_preset[17]_i_1__0_n_0\
    );
\txeq_preset[17]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1091"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => rst_cpllreset,
      O => p_0_out(17)
    );
\txeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(1)
    );
\txeq_preset[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      O => p_0_out(2)
    );
\txeq_preset[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00441140"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => \txeq_preset[3]_i_1__0_n_0\
    );
\txeq_preset[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAA3C00AAAA"
    )
        port map (
      I0 => \txeq_preset_reg_n_0_[7]\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \txeq_preset[7]_i_2__0_n_0\,
      I4 => \txeq_preset[17]_i_1__0_n_0\,
      I5 => rst_cpllreset,
      O => \txeq_preset[7]_i_1__0_n_0\
    );
\txeq_preset[7]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      O => \txeq_preset[7]_i_2__0_n_0\
    );
\txeq_preset[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABEAFAF"
    )
        port map (
      I0 => rst_cpllreset,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(8)
    );
\txeq_preset[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CFCCCCFD"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => rst_cpllreset,
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(2),
      O => p_0_out(9)
    );
\txeq_preset_done_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      O => \txeq_preset_done_i_1__0_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset_done_i_1__0_n_0\,
      Q => txeq_preset_done,
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => rst_cpllreset
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => rst_cpllreset
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => rst_cpllreset
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(0),
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(10),
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(11),
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(12),
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(13),
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(14),
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(15),
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(16),
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(17),
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(1),
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(2),
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[3]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset[7]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(8),
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(9),
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45404040"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => \txeq_txcoeff[0]_i_2__0_n_0\,
      I2 => fsm_tx(1),
      I3 => fsm_tx(0),
      I4 => \txeq_txcoeff_reg_n_0_[6]\,
      O => \txeq_txcoeff[0]_i_1__0_n_0\
    );
\txeq_txcoeff[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[0]\,
      O => \txeq_txcoeff[0]_i_2__0_n_0\
    );
\txeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[10]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[16]\,
      O => \txeq_txcoeff[10]_i_1__0_n_0\
    );
\txeq_txcoeff[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[10]\,
      O => \txeq_txcoeff[10]_i_2__0_n_0\
    );
\txeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[11]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[17]\,
      O => \txeq_txcoeff[11]_i_1__0_n_0\
    );
\txeq_txcoeff[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[18]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[17]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[11]\,
      O => \txeq_txcoeff[11]_i_2__0_n_0\
    );
\txeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[12]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[18]\,
      O => \txeq_txcoeff[12]_i_1__0_n_0\
    );
\txeq_txcoeff[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[18]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[12]\,
      O => \txeq_txcoeff[12]_i_2__0_n_0\
    );
\txeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[13]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(0),
      O => \txeq_txcoeff[13]_i_1__0_n_0\
    );
\txeq_txcoeff[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(0),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[13]\,
      O => \txeq_txcoeff[13]_i_2__0_n_0\
    );
\txeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[14]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(1),
      O => \txeq_txcoeff[14]_i_1__0_n_0\
    );
\txeq_txcoeff[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(1),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[14]\,
      O => \txeq_txcoeff[14]_i_2__0_n_0\
    );
\txeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[15]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(2),
      O => \txeq_txcoeff[15]_i_1__0_n_0\
    );
\txeq_txcoeff[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(2),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[15]\,
      O => \txeq_txcoeff[15]_i_2__0_n_0\
    );
\txeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[16]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(3),
      O => \txeq_txcoeff[16]_i_1__0_n_0\
    );
\txeq_txcoeff[16]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(3),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[16]\,
      O => \txeq_txcoeff[16]_i_2__0_n_0\
    );
\txeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[17]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(4),
      O => \txeq_txcoeff[17]_i_1__0_n_0\
    );
\txeq_txcoeff[17]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(4),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[17]\,
      O => \txeq_txcoeff[17]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040FFF"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      O => txeq_txcoeff
    );
\txeq_txcoeff[18]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"440F440044004400"
    )
        port map (
      I0 => fsm_tx(1),
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      I2 => \txeq_txcoeff[18]_i_3__0_n_0\,
      I3 => fsm_tx(2),
      I4 => txeq_deemph_reg2(5),
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[18]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      O => \txeq_txcoeff[18]_i_3__0_n_0\
    );
\txeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[1]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[1]_i_1__0_n_0\
    );
\txeq_txcoeff[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__0_n_0\
    );
\txeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[1]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[2]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[8]\,
      O => \txeq_txcoeff[2]_i_1__0_n_0\
    );
\txeq_txcoeff[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[2]\,
      O => \txeq_txcoeff[2]_i_2__0_n_0\
    );
\txeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[2]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[3]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[9]\,
      O => \txeq_txcoeff[3]_i_1__0_n_0\
    );
\txeq_txcoeff[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__0_n_0\
    );
\txeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[3]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[4]_i_2__0_n_0\,
      O => \txeq_txcoeff[4]_i_1__0_n_0\
    );
\txeq_txcoeff[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CACCCCCC00000000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => fsm_tx(1),
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[4]_i_2__0_n_0\
    );
\txeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[4]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[5]_i_2__0_n_0\,
      O => \txeq_txcoeff[5]_i_1__0_n_0\
    );
\txeq_txcoeff[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CACCCCCC00000000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => fsm_tx(1),
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[5]_i_2__0_n_0\
    );
\txeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[5]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[6]_i_2__0_n_0\,
      O => \txeq_txcoeff[6]_i_1__0_n_0\
    );
\txeq_txcoeff[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CACCCCCC00000000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => fsm_tx(1),
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => fsm_tx(0),
      O => \txeq_txcoeff[6]_i_2__0_n_0\
    );
\txeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[7]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[7]_i_1__0_n_0\
    );
\txeq_txcoeff[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[7]\,
      O => \txeq_txcoeff[7]_i_2__0_n_0\
    );
\txeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[8]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[14]\,
      O => \txeq_txcoeff[8]_i_1__0_n_0\
    );
\txeq_txcoeff[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[8]\,
      O => \txeq_txcoeff[8]_i_2__0_n_0\
    );
\txeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[9]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[15]\,
      O => \txeq_txcoeff[9]_i_1__0_n_0\
    );
\txeq_txcoeff[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[9]\,
      O => \txeq_txcoeff[9]_i_2__0_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000004000F000400"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => fsm_tx(2),
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[0]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[10]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[11]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[12]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[13]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[14]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[15]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[16]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[17]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[18]_i_2__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[1]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[2]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[3]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[4]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[5]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[6]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[7]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[8]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => rst_cpllreset
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \lf_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[9]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => rst_cpllreset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_qpll_wrapper is
  port (
    cpllrst : out STD_LOGIC;
    qpll_drp_rdy : out STD_LOGIC;
    QRST_QPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk_0 : out STD_LOGIC;
    sys_clk_1 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    CLK : in STD_LOGIC;
    qpll_drp_en : in STD_LOGIC;
    qpll_drp_we : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    PLL0RESET0 : in STD_LOGIC;
    rdy_reg1_reg : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_qpll_wrapper : entity is "xdma_0_pcie2_ip_qpll_wrapper";
end xdma_0_xdma_0_pcie2_ip_qpll_wrapper;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_qpll_wrapper is
  signal cpllpd : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL0FBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL0REFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL1FBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL1LOCK_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL1OUTCLK_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL1OUTREFCLK_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_PLL1REFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR0_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR1_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtp_common.gtpe2_common_i_DMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_gtp_common.gtpe2_common_i_PMARSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtp_common.gtpe2_common_i\ : label is "PRIMITIVE";
begin
cpllPDInst: entity work.xdma_0_xdma_0_pcie2_ip_gtp_cpllpd_ovrd
     port map (
      cpllpd => cpllpd,
      cpllrst => cpllrst,
      gt_cpllpdrefclk => gt_cpllpdrefclk
    );
\gtp_common.gtpe2_common_i\: unisim.vcomponents.GTPE2_COMMON
    generic map(
      BIAS_CFG => X"0000000000050001",
      COMMON_CFG => X"00000000",
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK0_INVERTED => '0',
      IS_GTGREFCLK1_INVERTED => '0',
      IS_PLL0LOCKDETCLK_INVERTED => '0',
      IS_PLL1LOCKDETCLK_INVERTED => '0',
      PLL0_CFG => X"01F024C",
      PLL0_DMON_CFG => '0',
      PLL0_FBDIV => 5,
      PLL0_FBDIV_45 => 5,
      PLL0_INIT_CFG => X"00001E",
      PLL0_LOCK_CFG => X"1E8",
      PLL0_REFCLK_DIV => 1,
      PLL1_CFG => X"01F024C",
      PLL1_DMON_CFG => '0',
      PLL1_FBDIV => 5,
      PLL1_FBDIV_45 => 5,
      PLL1_INIT_CFG => X"00001E",
      PLL1_LOCK_CFG => X"1E8",
      PLL1_REFCLK_DIV => 1,
      PLL_CLKOUT_CFG => B"00000000",
      RSVD_ATTR0 => X"0000",
      RSVD_ATTR1 => X"0000",
      SIM_PLL0REFCLK_SEL => B"001",
      SIM_PLL1REFCLK_SEL => B"001",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_VERSION => "1.0"
    )
        port map (
      BGBYPASSB => '1',
      BGMONITORENB => '1',
      BGPDB => '1',
      BGRCALOVRD(4 downto 0) => B"11111",
      BGRCALOVRDENB => '1',
      DMONITOROUT(7 downto 0) => \NLW_gtp_common.gtpe2_common_i_DMONITOROUT_UNCONNECTED\(7 downto 0),
      DRPADDR(7) => Q(4),
      DRPADDR(6) => '0',
      DRPADDR(5) => Q(3),
      DRPADDR(4) => Q(3),
      DRPADDR(3) => Q(4),
      DRPADDR(2 downto 0) => Q(2 downto 0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => rdy_reg1_reg(15 downto 0),
      DRPDO(15 downto 0) => D(15 downto 0),
      DRPEN => qpll_drp_en,
      DRPRDY => qpll_drp_rdy,
      DRPWE => qpll_drp_we,
      GTEASTREFCLK0 => '0',
      GTEASTREFCLK1 => '0',
      GTGREFCLK0 => '0',
      GTGREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTWESTREFCLK0 => '0',
      GTWESTREFCLK1 => '0',
      PLL0FBCLKLOST => \NLW_gtp_common.gtpe2_common_i_PLL0FBCLKLOST_UNCONNECTED\,
      PLL0LOCK => QRST_QPLLLOCK(0),
      PLL0LOCKDETCLK => '0',
      PLL0LOCKEN => '1',
      PLL0OUTCLK => sys_clk_0,
      PLL0OUTREFCLK => sys_clk_1,
      PLL0PD => cpllpd,
      PLL0REFCLKLOST => \NLW_gtp_common.gtpe2_common_i_PLL0REFCLKLOST_UNCONNECTED\,
      PLL0REFCLKSEL(2 downto 0) => B"001",
      PLL0RESET => PLL0RESET0,
      PLL1FBCLKLOST => \NLW_gtp_common.gtpe2_common_i_PLL1FBCLKLOST_UNCONNECTED\,
      PLL1LOCK => \NLW_gtp_common.gtpe2_common_i_PLL1LOCK_UNCONNECTED\,
      PLL1LOCKDETCLK => '0',
      PLL1LOCKEN => '1',
      PLL1OUTCLK => \NLW_gtp_common.gtpe2_common_i_PLL1OUTCLK_UNCONNECTED\,
      PLL1OUTREFCLK => \NLW_gtp_common.gtpe2_common_i_PLL1OUTREFCLK_UNCONNECTED\,
      PLL1PD => '1',
      PLL1REFCLKLOST => \NLW_gtp_common.gtpe2_common_i_PLL1REFCLKLOST_UNCONNECTED\,
      PLL1REFCLKSEL(2 downto 0) => B"001",
      PLL1RESET => '1',
      PLLRSVD1(15 downto 0) => B"0000000000000000",
      PLLRSVD2(4 downto 0) => B"00000",
      PMARSVD(7 downto 0) => B"00000000",
      PMARSVDOUT(15 downto 0) => \NLW_gtp_common.gtpe2_common_i_PMARSVDOUT_UNCONNECTED\(15 downto 0),
      RCALENB => '1',
      REFCLKOUTMONITOR0 => \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR0_UNCONNECTED\,
      REFCLKOUTMONITOR1 => \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR1_UNCONNECTED\
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_axi_basic_top is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc_d : out STD_LOGIC;
    m_axis_rx_tvalid_reg : out STD_LOGIC;
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_reg : out STD_LOGIC;
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect : out STD_LOGIC;
    ppm_L1_thrtl : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    trn_tcfg_gnt : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \throttle_ctl_pipeline.reg_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered : in STD_LOGIC;
    trn_reof : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_in_packet_reg : in STD_LOGIC;
    ppm_L1_thrtl_reg : in STD_LOGIC;
    lnk_up_thrtl_reg : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    tcfg_req_trig : in STD_LOGIC;
    tready_thrtl_i_3 : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_axi_basic_top : entity is "xdma_0_pcie2_ip_axi_basic_top";
end xdma_0_xdma_0_pcie2_ip_axi_basic_top;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_axi_basic_top is
begin
rx_inst: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_rx
     port map (
      CLK => CLK,
      E(0) => E(0),
      Q(63 downto 0) => Q(63 downto 0),
      dsc_detect => dsc_detect,
      m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_reg => m_axis_rx_tvalid_reg,
      reg_dsc_detect_reg => reg_dsc_detect,
      rsrc_rdy_filtered => rsrc_rdy_filtered,
      trn_in_packet => trn_in_packet,
      trn_in_packet_reg => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      \trn_rbar_hit_prev_reg[0]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\,
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => trn_rsrc_dsc_d,
      trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0
    );
tx_inst: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_tx
     port map (
      CLK => CLK,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      lnk_up_thrtl => lnk_up_thrtl,
      lnk_up_thrtl_reg => lnk_up_thrtl_reg,
      \out\ => \out\,
      ppm_L1_thrtl => ppm_L1_thrtl,
      ppm_L1_thrtl_reg => ppm_L1_thrtl_reg,
      ppm_L1_trig => ppm_L1_trig,
      reg_tcfg_gnt => reg_tcfg_gnt,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => tbuf_av_min_trig,
      tcfg_req_trig => tcfg_req_trig,
      \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0) => \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 0),
      \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\,
      tready_thrtl_i_3 => tready_thrtl_i_3,
      tready_thrtl_reg => tready_thrtl_reg,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_common is
  port (
    cpllrst : out STD_LOGIC;
    QRST_QPLLLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk_0 : out STD_LOGIC;
    sys_clk_1 : out STD_LOGIC;
    QRST_DRP_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    CLK : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    PLL0RESET0 : in STD_LOGIC;
    rst_dclk_reset : in STD_LOGIC;
    QRST_DRP_START : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_common : entity is "xdma_0_pcie2_ip_gt_common";
end xdma_0_xdma_0_pcie2_ip_gt_common;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_common is
  signal \^qrst_qplllock\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal qpll_drp_addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpll_drp_di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_do : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_en : STD_LOGIC;
  signal qpll_drp_rdy : STD_LOGIC;
  signal qpll_drp_we : STD_LOGIC;
begin
  QRST_QPLLLOCK(0) <= \^qrst_qplllock\(0);
qpll_drp_i: entity work.xdma_0_xdma_0_pcie2_ip_qpll_drp
     port map (
      CLK => CLK,
      D(15 downto 0) => qpll_drp_do(15 downto 0),
      Q(4) => qpll_drp_addr(7),
      Q(3) => qpll_drp_addr(5),
      Q(2 downto 0) => qpll_drp_addr(2 downto 0),
      QRST_DRP_DONE(0) => QRST_DRP_DONE(0),
      QRST_DRP_START => QRST_DRP_START,
      QRST_QPLLLOCK(0) => \^qrst_qplllock\(0),
      \di_reg[15]_0\(15 downto 0) => qpll_drp_di(15 downto 0),
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we,
      rst_dclk_reset => rst_dclk_reset
    );
qpll_wrapper_i: entity work.xdma_0_xdma_0_pcie2_ip_qpll_wrapper
     port map (
      CLK => CLK,
      D(15 downto 0) => qpll_drp_do(15 downto 0),
      PLL0RESET0 => PLL0RESET0,
      Q(4) => qpll_drp_addr(7),
      Q(3) => qpll_drp_addr(5),
      Q(2 downto 0) => qpll_drp_addr(2 downto 0),
      QRST_QPLLLOCK(0) => \^qrst_qplllock\(0),
      cpllrst => cpllrst,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we,
      rdy_reg1_reg(15 downto 0) => qpll_drp_di(15 downto 0),
      sys_clk => sys_clk,
      sys_clk_0 => sys_clk_0,
      sys_clk_1 => sys_clk_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_brams_7x is
  port (
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_brams_7x : entity is "xdma_0_pcie2_ip_pcie_brams_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_brams_7x;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_brams_7x is
begin
\brams[0].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_22
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
\brams[1].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_23
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(35 downto 18),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(35 downto 18),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
\brams[2].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_24
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(53 downto 36),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(17 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(53 downto 36),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
\brams[3].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_25
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(13 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 54),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(13 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 54),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_brams_7x_15 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_brams_7x_15 : entity is "xdma_0_pcie2_ip_pcie_brams_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_brams_7x_15;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_brams_7x_15 is
begin
\brams[0].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
\brams[1].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_16
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(35 downto 18),
      wdata(17 downto 0) => wdata(35 downto 18)
    );
\brams[2].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_17
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(53 downto 36),
      wdata(17 downto 0) => wdata(53 downto 36)
    );
\brams[3].ram\: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_7x_18
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(68 downto 54),
      wdata(14 downto 0) => wdata(68 downto 54)
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_bram_top_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_bram_top_7x : entity is "xdma_0_pcie2_ip_pcie_bram_top_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_bram_top_7x;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_bram_top_7x is
begin
pcie_brams_rx: entity work.xdma_0_xdma_0_pcie2_ip_pcie_brams_7x
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0) => \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen
    );
pcie_brams_tx: entity work.xdma_0_xdma_0_pcie2_ip_pcie_brams_7x_15
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(68 downto 0) => rdata(68 downto 0),
      wdata(68 downto 0) => wdata(68 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pipe_wrapper is
  port (
    CLK : out STD_LOGIC;
    mmcm_i : out STD_LOGIC;
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_chanisaligned_gt : out STD_LOGIC;
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rx_data_wire_filter : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt_rx_data_k_wire_filter : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rx1_chanisaligned_gt : out STD_LOGIC;
    sys_rst_n_0 : out STD_LOGIC;
    mmcm_i_0 : out STD_LOGIC;
    rate_idle_reg2_reg : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_rxvalid_q_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rate_idle_reg2_reg_0 : out STD_LOGIC;
    rst_idle_reg2_reg : out STD_LOGIC;
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 1 downto 0 );
    sys_clk : in STD_LOGIC;
    pipe_tx0_elec_idle_gt : in STD_LOGIC;
    TXCHARDISPMODE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_polarity_gt : in STD_LOGIC;
    pipe_tx_deemph_gt : in STD_LOGIC;
    pipe_tx_rcvr_det_gt : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdy_reg1_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rdy_reg1_reg_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_elec_idle_gt : in STD_LOGIC;
    txcompliance_reg1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_polarity_gt : in STD_LOGIC;
    rdy_reg1_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdy_reg1_reg_3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    sys_rst_n : in STD_LOGIC;
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC;
    reg_clock_locked : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pipe_wrapper : entity is "xdma_0_pcie2_ip_pipe_wrapper";
end xdma_0_xdma_0_pcie2_ip_pipe_wrapper;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pipe_wrapper is
  signal \^clk\ : STD_LOGIC;
  signal DRP_START0 : STD_LOGIC;
  signal DRP_START00_out : STD_LOGIC;
  signal DRP_X160 : STD_LOGIC;
  signal DRP_X1602_out : STD_LOGIC;
  signal SYNC_TXSYNC_START0 : STD_LOGIC;
  signal SYNC_TXSYNC_START01_out : STD_LOGIC;
  signal drp_done_0 : STD_LOGIC;
  signal drp_done_1 : STD_LOGIC;
  signal drp_mux_addr_0 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal drp_mux_addr_9 : STD_LOGIC_VECTOR ( 4 to 4 );
  signal drp_mux_di_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drp_mux_di_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drp_mux_en_0 : STD_LOGIC;
  signal drp_mux_en_1 : STD_LOGIC;
  signal eq_rxeq_adapt_done_0 : STD_LOGIC;
  signal eq_rxeq_adapt_done_1 : STD_LOGIC;
  signal eq_txeq_maincursor_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal eq_txeq_maincursor_7 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal eq_txeq_postcursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_postcursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_precursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_precursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gt_cpllpdrefclk : STD_LOGIC;
  signal gt_phystatus_0 : STD_LOGIC;
  signal gt_phystatus_1 : STD_LOGIC;
  signal \^gt_rx_elec_idle_wire_filter\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gt_rxcdrlock_0 : STD_LOGIC;
  signal gt_rxcdrlock_1 : STD_LOGIC;
  signal \gt_rxchbondi[1]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gt_rxratedone_0 : STD_LOGIC;
  signal gt_rxratedone_1 : STD_LOGIC;
  signal gt_rxresetdone_0 : STD_LOGIC;
  signal gt_rxresetdone_1 : STD_LOGIC;
  signal gt_rxsyncout_0 : STD_LOGIC;
  signal gt_rxvalid_0 : STD_LOGIC;
  signal gt_rxvalid_1 : STD_LOGIC;
  signal gt_txratedone_0 : STD_LOGIC;
  signal gt_txratedone_1 : STD_LOGIC;
  signal gt_txresetdone_0 : STD_LOGIC;
  signal gt_txresetdone_1 : STD_LOGIC;
  signal gt_txsyncdone_0 : STD_LOGIC;
  signal gt_txsyncdone_1 : STD_LOGIC;
  signal gt_txsyncout_0 : STD_LOGIC;
  signal \gtp_pipe_reset.gtp_pipe_reset_i_n_0\ : STD_LOGIC;
  signal \gtp_pipe_reset.gtp_pipe_reset_i_n_11\ : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in4_in_1 : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in0_in : STD_LOGIC;
  signal p_1_in0_in_0 : STD_LOGIC;
  signal p_1_in5_in : STD_LOGIC;
  signal p_1_in5_in_2 : STD_LOGIC;
  signal \pipe_clock_int.pipe_clock_i_n_1\ : STD_LOGIC;
  signal \pipe_clock_int.pipe_clock_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_31\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_32\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_33\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_34\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_35\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_36\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_37\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_31\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_32\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_33\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_34\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_35\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_36\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_19\ : STD_LOGIC;
  signal qdrp_done : STD_LOGIC;
  signal \qpll_wrapper_i/PLL0RESET0\ : STD_LOGIC;
  signal \qpll_wrapper_i/cpllrst\ : STD_LOGIC;
  signal qrst_drp_start : STD_LOGIC;
  signal rate_done_0 : STD_LOGIC;
  signal rate_done_1 : STD_LOGIC;
  signal rate_idle_0 : STD_LOGIC;
  signal rate_idle_1 : STD_LOGIC;
  signal rate_rate_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_rate_3 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_txsync_start_0 : STD_LOGIC;
  signal rate_txsync_start_1 : STD_LOGIC;
  signal reset_n_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of reset_n_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of reset_n_reg1 : signal is "true";
  signal reset_n_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of reset_n_reg2 : signal is "NO";
  attribute async_reg of reset_n_reg2 : signal is "true";
  signal rst_cpllreset : STD_LOGIC;
  signal rst_dclk_reset : STD_LOGIC;
  signal rst_drp_start : STD_LOGIC;
  signal rst_drp_x16 : STD_LOGIC;
  signal rst_gtreset : STD_LOGIC;
  signal rst_rxusrclk_reset : STD_LOGIC;
  signal rst_userrdy : STD_LOGIC;
  signal rxdlysresetdone_1 : STD_LOGIC;
  signal rxsyncallin : STD_LOGIC;
  signal sync_txdlyen_0 : STD_LOGIC;
  signal sync_txsync_done_0 : STD_LOGIC;
  signal sync_txsync_done_1 : STD_LOGIC;
  signal \^sys_rst_n_0\ : STD_LOGIC;
  signal txdlysresetdone_1 : STD_LOGIC;
  signal txsyncallin : STD_LOGIC;
  signal user_eyescanreset_0 : STD_LOGIC;
  signal user_eyescanreset_1 : STD_LOGIC;
  signal user_oobclk_0 : STD_LOGIC;
  signal user_oobclk_1 : STD_LOGIC;
  signal user_resetdone : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal user_resetovrd_0 : STD_LOGIC;
  signal user_resetovrd_1 : STD_LOGIC;
  signal user_rxbufreset_0 : STD_LOGIC;
  signal user_rxbufreset_1 : STD_LOGIC;
  signal user_rxcdrfreqreset_0 : STD_LOGIC;
  signal user_rxcdrfreqreset_1 : STD_LOGIC;
  signal user_rxcdrlock_0 : STD_LOGIC;
  signal user_rxcdrlock_1 : STD_LOGIC;
  signal user_rxcdrreset_0 : STD_LOGIC;
  signal user_rxcdrreset_1 : STD_LOGIC;
  signal user_rxpcsreset_0 : STD_LOGIC;
  signal user_rxpcsreset_1 : STD_LOGIC;
  signal user_rxpmareset_0 : STD_LOGIC;
  signal user_rxpmareset_1 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of cpllpd_refclk_inst : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of reset_n_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of reset_n_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of reset_n_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of reset_n_reg2_reg : label is std.standard.true;
  attribute KEEP of reset_n_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of reset_n_reg2_reg : label is "NO";
begin
  CLK <= \^clk\;
  gt_rx_elec_idle_wire_filter(1 downto 0) <= \^gt_rx_elec_idle_wire_filter\(1 downto 0);
  sys_rst_n_0 <= \^sys_rst_n_0\;
cpllpd_refclk_inst: unisim.vcomponents.BUFG
     port map (
      I => sys_clk,
      O => gt_cpllpdrefclk
    );
\gtp_pipe_reset.gtp_pipe_reset_i\: entity work.xdma_0_xdma_0_pcie2_ip_gtp_pipe_reset
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      D(1 downto 0) => user_resetdone(1 downto 0),
      \FSM_onehot_fsm_reg[11]_0\ => SYNC_TXSYNC_START01_out,
      \FSM_onehot_fsm_reg[1]_0\(0) => \gtp_pipe_reset.gtp_pipe_reset_i_n_11\,
      PLL0RESET0 => \qpll_wrapper_i/PLL0RESET0\,
      Q(1) => rate_txsync_start_0,
      Q(0) => rate_idle_0,
      QRST_QPLLLOCK(0) => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\,
      SR(0) => \gtp_pipe_reset.gtp_pipe_reset_i_n_0\,
      SYNC_MMCM_LOCK => \pipe_clock_int.pipe_clock_i_n_3\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      \cfg_wait_cnt_reg[5]_0\ => \^clk\,
      cpllrst => \qpll_wrapper_i/cpllrst\,
      \drp_done_reg1_reg[1]_0\(1) => drp_done_1,
      \drp_done_reg1_reg[1]_0\(0) => drp_done_0,
      \out\ => reset_n_reg2,
      \phystatus_reg1_reg[1]_0\(1) => gt_phystatus_1,
      \phystatus_reg1_reg[1]_0\(0) => gt_phystatus_0,
      rst_cpllreset => rst_cpllreset,
      rst_dclk_reset => rst_dclk_reset,
      rst_drp_start => rst_drp_start,
      rst_drp_x16 => rst_drp_x16,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      \rxcdrlock_reg1_reg[1]_0\(1) => user_rxcdrlock_1,
      \rxcdrlock_reg1_reg[1]_0\(0) => user_rxcdrlock_0,
      \rxpmaresetdone_reg1_reg[1]_0\(1) => \pipe_lane[1].gt_wrapper_i_n_9\,
      \rxpmaresetdone_reg1_reg[1]_0\(0) => \pipe_lane[0].gt_wrapper_i_n_8\,
      rxusrclk_rst_reg2_reg_0(0) => rst_rxusrclk_reset,
      \txsync_done_reg1_reg[1]_0\(1) => sync_txsync_done_1,
      \txsync_done_reg1_reg[1]_0\(0) => sync_txsync_done_0,
      txsync_start_reg1_reg(1) => rate_txsync_start_1,
      txsync_start_reg1_reg(0) => rate_idle_1
    );
\pipe_clock_int.pipe_clock_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_clock
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      SYNC_MMCM_LOCK => \pipe_clock_int.pipe_clock_i_n_3\,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      mmcm_i_0 => mmcm_i,
      mmcm_i_1 => mmcm_i_0,
      mmcm_lock_reg1_reg => \pipe_lane[0].gt_wrapper_i_n_14\,
      \pclk_sel_reg1_reg[0]_0\ => \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      \pclk_sel_reg1_reg[1]_0\ => \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      pclk_sel_reg_0 => \^clk\
    );
\pipe_lane[0].gt_wrapper_i\: entity work.xdma_0_xdma_0_pcie2_ip_gt_wrapper
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      D(15) => \pipe_lane[0].gt_wrapper_i_n_21\,
      D(14) => \pipe_lane[0].gt_wrapper_i_n_22\,
      D(13) => \pipe_lane[0].gt_wrapper_i_n_23\,
      D(12) => \pipe_lane[0].gt_wrapper_i_n_24\,
      D(11) => \pipe_lane[0].gt_wrapper_i_n_25\,
      D(10) => \pipe_lane[0].gt_wrapper_i_n_26\,
      D(9) => \pipe_lane[0].gt_wrapper_i_n_27\,
      D(8) => \pipe_lane[0].gt_wrapper_i_n_28\,
      D(7) => \pipe_lane[0].gt_wrapper_i_n_29\,
      D(6) => \pipe_lane[0].gt_wrapper_i_n_30\,
      D(5) => \pipe_lane[0].gt_wrapper_i_n_31\,
      D(4) => \pipe_lane[0].gt_wrapper_i_n_32\,
      D(3) => \pipe_lane[0].gt_wrapper_i_n_33\,
      D(2) => \pipe_lane[0].gt_wrapper_i_n_34\,
      D(1) => \pipe_lane[0].gt_wrapper_i_n_35\,
      D(0) => \pipe_lane[0].gt_wrapper_i_n_36\,
      DRPADDR(0) => drp_mux_addr_0(4),
      DRPDI(15 downto 0) => drp_mux_di_0(15 downto 0),
      Q(2) => \pipe_lane[0].pipe_sync_i_n_4\,
      Q(1) => \pipe_lane[0].pipe_sync_i_n_5\,
      Q(0) => \pipe_lane[0].pipe_sync_i_n_6\,
      RXCHBONDO(3 downto 0) => \gt_rxchbondi[1]_0\(3 downto 0),
      RXRATE(0) => rate_rate_0(0),
      RXSTATUS(0) => \pipe_lane[0].gt_wrapper_i_n_37\,
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_7\,
      SYNC_RXSYNCDONE => \pipe_lane[0].gt_wrapper_i_n_11\,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXSYNCDONE => gt_txsyncdone_0,
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0),
      drp_mux_en_0 => drp_mux_en_0,
      gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0),
      gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(15 downto 0),
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      \gt_rx_status_q_reg[0]\ => \gt_rx_status_q_reg[0]\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_status_q_reg[2]\,
      gt_rxcdrlock_0 => gt_rxcdrlock_0,
      gt_rxratedone_0 => gt_rxratedone_0,
      gt_rxresetdone_0 => gt_rxresetdone_0,
      gt_rxsyncout_0 => gt_rxsyncout_0,
      gt_rxvalid_0 => gt_rxvalid_0,
      gt_rxvalid_q_reg(2 downto 0) => gt_rxvalid_q_reg_0(2 downto 0),
      gt_txratedone_0 => gt_txratedone_0,
      gt_txresetdone_0 => gt_txresetdone_0,
      gt_txsyncout_0 => gt_txsyncout_0,
      pci_exp_rxn(0) => pci_exp_rxn(0),
      pci_exp_rxp(0) => pci_exp_rxp(0),
      pci_exp_txn(0) => pci_exp_txn(0),
      pci_exp_txp(0) => pci_exp_txp(0),
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt,
      rdy_reg1_reg => \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1\,
      rdy_reg1_reg_0 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\,
      rdy_reg1_reg_1 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3\,
      rdy_reg1_reg_2 => \^clk\,
      rdy_reg1_reg_3(1 downto 0) => Q(1 downto 0),
      rdy_reg1_reg_4(2 downto 0) => rdy_reg1_reg(2 downto 0),
      rdy_reg1_reg_5(15 downto 0) => rdy_reg1_reg_0(15 downto 0),
      rdy_reg1_reg_6(1 downto 0) => rdy_reg1_reg_1(1 downto 0),
      \resetovrd.reset_reg[4]\ => \pipe_lane[0].gt_wrapper_i_n_0\,
      \resetovrd.reset_reg[4]_0\(0) => gt_phystatus_0,
      \resetovrd.reset_reg[4]_1\(0) => \pipe_lane[0].gt_wrapper_i_n_8\,
      \resetovrd.reset_reg[4]_2\ => \pipe_lane[0].gt_wrapper_i_n_14\,
      \resetovrd.reset_reg[4]_3\ => \pipe_lane[0].gt_wrapper_i_n_15\,
      \resetovrd.reset_reg[4]_4\ => \pipe_lane[0].gt_wrapper_i_n_16\,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      rxdlysresetdone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_6\,
      rxsyncallin => rxsyncallin,
      sync_txdlyen_0 => sync_txdlyen_0,
      txdlysresetdone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_14\,
      user_eyescanreset_0 => user_eyescanreset_0,
      user_oobclk_0 => user_oobclk_0,
      user_resetovrd_0 => user_resetovrd_0,
      user_rxbufreset_0 => user_rxbufreset_0,
      user_rxcdrfreqreset_0 => user_rxcdrfreqreset_0,
      user_rxcdrreset_0 => user_rxcdrreset_0,
      user_rxpcsreset_0 => user_rxpcsreset_0,
      user_rxpmareset_0 => user_rxpmareset_0
    );
\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i\: entity work.xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      D(15) => \pipe_lane[0].gt_wrapper_i_n_21\,
      D(14) => \pipe_lane[0].gt_wrapper_i_n_22\,
      D(13) => \pipe_lane[0].gt_wrapper_i_n_23\,
      D(12) => \pipe_lane[0].gt_wrapper_i_n_24\,
      D(11) => \pipe_lane[0].gt_wrapper_i_n_25\,
      D(10) => \pipe_lane[0].gt_wrapper_i_n_26\,
      D(9) => \pipe_lane[0].gt_wrapper_i_n_27\,
      D(8) => \pipe_lane[0].gt_wrapper_i_n_28\,
      D(7) => \pipe_lane[0].gt_wrapper_i_n_29\,
      D(6) => \pipe_lane[0].gt_wrapper_i_n_30\,
      D(5) => \pipe_lane[0].gt_wrapper_i_n_31\,
      D(4) => \pipe_lane[0].gt_wrapper_i_n_32\,
      D(3) => \pipe_lane[0].gt_wrapper_i_n_33\,
      D(2) => \pipe_lane[0].gt_wrapper_i_n_34\,
      D(1) => \pipe_lane[0].gt_wrapper_i_n_35\,
      D(0) => \pipe_lane[0].gt_wrapper_i_n_36\,
      DRPADDR(0) => drp_mux_addr_0(4),
      DRPDI(15 downto 0) => drp_mux_di_0(15 downto 0),
      DRP_START00_out => DRP_START00_out,
      DRP_X160 => DRP_X160,
      done_reg_0(0) => drp_done_0,
      drp_mux_en_0 => drp_mux_en_0,
      \fsm_reg[1]_0\ => \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1\,
      rdy_reg1_reg_0 => \pipe_lane[0].gt_wrapper_i_n_0\,
      rst_dclk_reset => rst_dclk_reset
    );
\pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i\: entity work.xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate
     port map (
      D(0) => D(0),
      DRP_START00_out => DRP_START00_out,
      DRP_X160 => DRP_X160,
      Q(2) => rate_txsync_start_0,
      Q(1) => rate_done_0,
      Q(0) => rate_idle_0,
      RXRATE(0) => rate_rate_0(0),
      drp_done_reg1_reg_0(0) => drp_done_0,
      gt_rxratedone_0 => gt_rxratedone_0,
      gt_txratedone_0 => gt_txratedone_0,
      pclk_sel_reg_0 => \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      phystatus_reg1_reg_0(0) => gt_phystatus_0,
      rst_cpllreset => rst_cpllreset,
      rst_drp_start => rst_drp_start,
      rst_drp_x16 => rst_drp_x16,
      rxpmaresetdone_reg1_reg_0(0) => \pipe_lane[0].gt_wrapper_i_n_8\,
      \txdata_wait_cnt_reg[0]_0\ => \^clk\,
      txsync_done_reg1_reg_0(0) => sync_txsync_done_0
    );
\pipe_lane[0].pipe_eq.pipe_eq_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_eq
     port map (
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0),
      eq_rxeq_adapt_done_0 => eq_rxeq_adapt_done_0,
      \fs_reg2_reg[5]\ => \^clk\,
      rst_cpllreset => rst_cpllreset
    );
\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i\: entity work.xdma_0_xdma_0_pcie2_ip_gt_common
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      PLL0RESET0 => \qpll_wrapper_i/PLL0RESET0\,
      QRST_DRP_DONE(0) => qdrp_done,
      QRST_DRP_START => qrst_drp_start,
      QRST_QPLLLOCK(0) => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\,
      cpllrst => \qpll_wrapper_i/cpllrst\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      rst_dclk_reset => rst_dclk_reset,
      sys_clk => sys_clk,
      sys_clk_0 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\,
      sys_clk_1 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3\
    );
\pipe_lane[0].pipe_sync_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_sync
     port map (
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[0].pipe_user_i_n_15\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => \pipe_lane[0].pipe_user_i_n_17\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_0_in4_in,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ => p_1_in5_in,
      Q(2) => \pipe_lane[0].pipe_sync_i_n_4\,
      Q(1) => \pipe_lane[0].pipe_sync_i_n_5\,
      Q(0) => \pipe_lane[0].pipe_sync_i_n_6\,
      SYNC_MMCM_LOCK => \pipe_clock_int.pipe_clock_i_n_3\,
      SYNC_RATE_IDLE => rate_idle_0,
      SYNC_RXCDRLOCK => user_rxcdrlock_0,
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_7\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[1].gt_wrapper_i_n_8\,
      SYNC_RXSYNCDONE => \pipe_lane[0].gt_wrapper_i_n_11\,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_15\,
      SYNC_TXSYNCDONE => gt_txsyncdone_0,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      \out\ => \pipe_lane[0].pipe_sync_i_n_1\,
      p_1_in => p_1_in,
      p_1_in0_in => p_1_in0_in,
      rst_cpllreset => rst_cpllreset,
      rxphaligndone_s_reg2_reg_0 => \^clk\,
      sync_txdlyen_0 => sync_txdlyen_0,
      txphinitdone_reg3_reg_0 => \pipe_lane[0].pipe_sync_i_n_3\,
      \txsync_fsm.txsync_done_reg_0\(0) => sync_txsync_done_0,
      \txsync_fsm.txsync_done_reg_1\ => \pipe_lane[0].pipe_user_i_n_16\
    );
\pipe_lane[0].pipe_user_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_user
     port map (
      D(0) => user_resetdone(0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[0].pipe_sync_i_n_3\,
      Q(1) => rate_done_0,
      Q(0) => rate_idle_0,
      RXSTATUS(0) => \pipe_lane[0].gt_wrapper_i_n_37\,
      SR(0) => rst_rxusrclk_reset,
      SYNC_RXCDRLOCK => user_rxcdrlock_0,
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      eq_rxeq_adapt_done_0 => eq_rxeq_adapt_done_0,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      gt_rx_phy_status_q_reg(0) => gt_phystatus_0,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0),
      gt_rxcdrlock_0 => gt_rxcdrlock_0,
      gt_rxresetdone_0 => gt_rxresetdone_0,
      gt_rxvalid_0 => gt_rxvalid_0,
      gt_rxvalid_q_reg => \gt_rx_status_q_reg[0]\,
      gt_txresetdone_0 => gt_txresetdone_0,
      \out\ => p_1_in5_in,
      p_1_in => p_1_in,
      p_1_in0_in => p_1_in0_in,
      pclk_sel_reg1_reg_0 => \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      rate_idle_reg2_reg_0 => rate_idle_reg2_reg,
      rst_cpllreset => rst_cpllreset,
      rst_idle_reg1_reg_0(0) => \gtp_pipe_reset.gtp_pipe_reset_i_n_11\,
      rst_idle_reg2_reg_0 => \pipe_lane[0].pipe_user_i_n_2\,
      \rxvalid_cnt_reg[3]_0\ => \^clk\,
      txcompliance_reg2_reg_0 => p_0_in4_in,
      txcompliance_reg2_reg_1 => \pipe_lane[0].pipe_user_i_n_15\,
      txcompliance_reg2_reg_2 => \pipe_lane[0].pipe_user_i_n_16\,
      txelecidle_reg2_reg_0 => \pipe_lane[0].pipe_user_i_n_17\,
      \txsync_fsm.txsync_done_reg\ => \pipe_lane[0].pipe_sync_i_n_1\,
      user_eyescanreset_0 => user_eyescanreset_0,
      user_oobclk_0 => user_oobclk_0,
      user_resetovrd_0 => user_resetovrd_0,
      user_rxbufreset_0 => user_rxbufreset_0,
      user_rxcdrfreqreset_0 => user_rxcdrfreqreset_0,
      user_rxcdrreset_0 => user_rxcdrreset_0,
      user_rxpcsreset_0 => user_rxpcsreset_0,
      user_rxpmareset_0 => user_rxpmareset_0
    );
\pipe_lane[1].gt_wrapper_i\: entity work.xdma_0_xdma_0_pcie2_ip_gt_wrapper_31
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      D(15) => \pipe_lane[1].gt_wrapper_i_n_20\,
      D(14) => \pipe_lane[1].gt_wrapper_i_n_21\,
      D(13) => \pipe_lane[1].gt_wrapper_i_n_22\,
      D(12) => \pipe_lane[1].gt_wrapper_i_n_23\,
      D(11) => \pipe_lane[1].gt_wrapper_i_n_24\,
      D(10) => \pipe_lane[1].gt_wrapper_i_n_25\,
      D(9) => \pipe_lane[1].gt_wrapper_i_n_26\,
      D(8) => \pipe_lane[1].gt_wrapper_i_n_27\,
      D(7) => \pipe_lane[1].gt_wrapper_i_n_28\,
      D(6) => \pipe_lane[1].gt_wrapper_i_n_29\,
      D(5) => \pipe_lane[1].gt_wrapper_i_n_30\,
      D(4) => \pipe_lane[1].gt_wrapper_i_n_31\,
      D(3) => \pipe_lane[1].gt_wrapper_i_n_32\,
      D(2) => \pipe_lane[1].gt_wrapper_i_n_33\,
      D(1) => \pipe_lane[1].gt_wrapper_i_n_34\,
      D(0) => \pipe_lane[1].gt_wrapper_i_n_35\,
      DRPADDR(0) => drp_mux_addr_9(4),
      DRPDI(15 downto 0) => drp_mux_di_16(15 downto 0),
      Q(2) => \pipe_lane[1].pipe_sync_i_n_2\,
      Q(1) => \pipe_lane[1].pipe_sync_i_n_3\,
      Q(0) => \pipe_lane[1].pipe_sync_i_n_4\,
      RXCHBONDO(3 downto 0) => \gt_rxchbondi[1]_0\(3 downto 0),
      RXRATE(0) => rate_rate_3(0),
      RXSTATUS(0) => \pipe_lane[1].gt_wrapper_i_n_36\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[1].gt_wrapper_i_n_8\,
      SYNC_RXSYNCDONE => \pipe_lane[1].gt_wrapper_i_n_12\,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXSYNCDONE => gt_txsyncdone_1,
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0),
      drp_mux_en_1 => drp_mux_en_1,
      gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(3 downto 2),
      gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(31 downto 16),
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      \gt_rx_status_q_reg[0]\ => \gt_rx_status_q_reg[0]_0\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_status_q_reg[2]\,
      gt_rxcdrlock_1 => gt_rxcdrlock_1,
      gt_rxratedone_1 => gt_rxratedone_1,
      gt_rxresetdone_1 => gt_rxresetdone_1,
      gt_rxsyncout_0 => gt_rxsyncout_0,
      gt_rxvalid_1 => gt_rxvalid_1,
      gt_rxvalid_q_reg(2 downto 0) => gt_rxvalid_q_reg(2 downto 0),
      gt_txratedone_1 => gt_txratedone_1,
      gt_txresetdone_1 => gt_txresetdone_1,
      gt_txsyncout_0 => gt_txsyncout_0,
      pci_exp_rxn(0) => pci_exp_rxn(1),
      pci_exp_rxp(0) => pci_exp_rxp(1),
      pci_exp_txn(0) => pci_exp_txn(1),
      pci_exp_txp(0) => pci_exp_txp(1),
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt,
      rdy_reg1_reg => \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1\,
      rdy_reg1_reg_0 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2\,
      rdy_reg1_reg_1 => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3\,
      rdy_reg1_reg_2 => \^clk\,
      rdy_reg1_reg_3(1 downto 0) => rdy_reg1_reg_2(1 downto 0),
      rdy_reg1_reg_4(2 downto 0) => rdy_reg1_reg(2 downto 0),
      rdy_reg1_reg_5(15 downto 0) => rdy_reg1_reg_3(15 downto 0),
      rdy_reg1_reg_6(0) => txcompliance_reg1_reg(0),
      rdy_reg1_reg_7(1 downto 0) => rdy_reg1_reg_4(1 downto 0),
      \resetovrd.reset_reg[4]\ => \pipe_lane[1].gt_wrapper_i_n_0\,
      \resetovrd.reset_reg[4]_0\(0) => gt_phystatus_1,
      \resetovrd.reset_reg[4]_1\ => \pipe_lane[1].gt_wrapper_i_n_6\,
      \resetovrd.reset_reg[4]_2\(0) => \pipe_lane[1].gt_wrapper_i_n_9\,
      \resetovrd.reset_reg[4]_3\ => \pipe_lane[1].gt_wrapper_i_n_14\,
      \resetovrd.reset_reg[4]_4\ => \pipe_lane[1].gt_wrapper_i_n_15\,
      \resetovrd.reset_reg[4]_5\ => \pipe_lane[1].gt_wrapper_i_n_16\,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      rxsyncallin => rxsyncallin,
      user_eyescanreset_1 => user_eyescanreset_1,
      user_oobclk_1 => user_oobclk_1,
      user_resetovrd_1 => user_resetovrd_1,
      user_rxbufreset_1 => user_rxbufreset_1,
      user_rxcdrfreqreset_1 => user_rxcdrfreqreset_1,
      user_rxcdrreset_1 => user_rxcdrreset_1,
      user_rxpcsreset_1 => user_rxpcsreset_1,
      user_rxpmareset_1 => user_rxpmareset_1
    );
\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i\: entity work.xdma_0_xdma_0_pcie2_ip_gtp_pipe_drp_32
     port map (
      CLK => \pipe_clock_int.pipe_clock_i_n_1\,
      D(15) => \pipe_lane[1].gt_wrapper_i_n_20\,
      D(14) => \pipe_lane[1].gt_wrapper_i_n_21\,
      D(13) => \pipe_lane[1].gt_wrapper_i_n_22\,
      D(12) => \pipe_lane[1].gt_wrapper_i_n_23\,
      D(11) => \pipe_lane[1].gt_wrapper_i_n_24\,
      D(10) => \pipe_lane[1].gt_wrapper_i_n_25\,
      D(9) => \pipe_lane[1].gt_wrapper_i_n_26\,
      D(8) => \pipe_lane[1].gt_wrapper_i_n_27\,
      D(7) => \pipe_lane[1].gt_wrapper_i_n_28\,
      D(6) => \pipe_lane[1].gt_wrapper_i_n_29\,
      D(5) => \pipe_lane[1].gt_wrapper_i_n_30\,
      D(4) => \pipe_lane[1].gt_wrapper_i_n_31\,
      D(3) => \pipe_lane[1].gt_wrapper_i_n_32\,
      D(2) => \pipe_lane[1].gt_wrapper_i_n_33\,
      D(1) => \pipe_lane[1].gt_wrapper_i_n_34\,
      D(0) => \pipe_lane[1].gt_wrapper_i_n_35\,
      DRPADDR(0) => drp_mux_addr_9(4),
      DRPDI(15 downto 0) => drp_mux_di_16(15 downto 0),
      DRP_START0 => DRP_START0,
      DRP_X1602_out => DRP_X1602_out,
      done_reg_0(0) => drp_done_1,
      drp_mux_en_1 => drp_mux_en_1,
      \fsm_reg[1]_0\ => \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1\,
      rdy_reg1_reg_0 => \pipe_lane[1].gt_wrapper_i_n_0\,
      rst_dclk_reset => rst_dclk_reset
    );
\pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i\: entity work.xdma_0_xdma_0_pcie2_ip_gtp_pipe_rate_33
     port map (
      D(0) => D(0),
      DRP_START0 => DRP_START0,
      DRP_X1602_out => DRP_X1602_out,
      Q(2) => rate_txsync_start_1,
      Q(1) => rate_done_1,
      Q(0) => rate_idle_1,
      RXRATE(0) => rate_rate_3(0),
      drp_done_reg1_reg_0(0) => drp_done_1,
      gt_rxratedone_1 => gt_rxratedone_1,
      gt_txratedone_1 => gt_txratedone_1,
      pclk_sel_reg_0 => \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      phystatus_reg1_reg_0(0) => gt_phystatus_1,
      rst_cpllreset => rst_cpllreset,
      rst_drp_start => rst_drp_start,
      rst_drp_x16 => rst_drp_x16,
      rxpmaresetdone_reg1_reg_0(0) => \pipe_lane[1].gt_wrapper_i_n_9\,
      \txdata_wait_cnt_reg[0]_0\ => \^clk\,
      txsync_done_reg1_reg_0(0) => sync_txsync_done_1
    );
\pipe_lane[1].pipe_eq.pipe_eq_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_eq_34
     port map (
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0),
      eq_rxeq_adapt_done_1 => eq_rxeq_adapt_done_1,
      \lf_reg2_reg[5]\ => \^clk\,
      rst_cpllreset => rst_cpllreset
    );
\pipe_lane[1].pipe_sync_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_sync_35
     port map (
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[1].pipe_user_i_n_18\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => \pipe_lane[1].pipe_user_i_n_19\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_1_in5_in_2,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ => p_0_in4_in_1,
      Q(2) => \pipe_lane[1].pipe_sync_i_n_2\,
      Q(1) => \pipe_lane[1].pipe_sync_i_n_3\,
      Q(0) => \pipe_lane[1].pipe_sync_i_n_4\,
      QRST_MMCM_LOCK => \pipe_clock_int.pipe_clock_i_n_3\,
      SYNC_RATE_IDLE => rate_idle_1,
      SYNC_RXCDRLOCK => user_rxcdrlock_1,
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_7\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[1].gt_wrapper_i_n_8\,
      SYNC_RXSYNCDONE => \pipe_lane[1].gt_wrapper_i_n_12\,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_15\,
      SYNC_TXSYNCDONE => gt_txsyncdone_1,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START01_out,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      \out\ => \pipe_lane[1].pipe_sync_i_n_1\,
      p_1_in0_in => p_1_in0_in_0,
      rst_cpllreset => rst_cpllreset,
      rxsyncdone_reg2_reg_0 => \^clk\,
      \txsync_fsm.txsync_done_reg_0\(0) => sync_txsync_done_1
    );
\pipe_lane[1].pipe_user_i\: entity work.xdma_0_xdma_0_pcie2_ip_pipe_user_36
     port map (
      D(0) => user_resetdone(1),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[1].pipe_sync_i_n_1\,
      Q(1) => rate_done_1,
      Q(0) => rate_idle_1,
      RXSTATUS(0) => \pipe_lane[1].gt_wrapper_i_n_36\,
      SR(0) => rst_rxusrclk_reset,
      SYNC_RXCDRLOCK => user_rxcdrlock_1,
      SYNC_RXPHALIGNDONE_M => \pipe_lane[0].gt_wrapper_i_n_7\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[1].gt_wrapper_i_n_8\,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_15\,
      eq_rxeq_adapt_done_1 => eq_rxeq_adapt_done_1,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      gt_rx_phy_status_q_reg(0) => gt_phystatus_1,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1),
      gt_rxcdrlock_1 => gt_rxcdrlock_1,
      gt_rxresetdone_1 => gt_rxresetdone_1,
      gt_rxvalid_1 => gt_rxvalid_1,
      gt_rxvalid_q_reg => \gt_rx_status_q_reg[0]_0\,
      gt_txresetdone_1 => gt_txresetdone_1,
      \out\ => p_1_in5_in_2,
      p_1_in0_in => p_1_in0_in_0,
      pclk_sel_reg1_reg_0 => \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0\,
      phy_rdy_n_int_reg => \pipe_lane[0].pipe_user_i_n_2\,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      rate_idle_reg2_reg_0 => rate_idle_reg2_reg_0,
      reg_clock_locked => reg_clock_locked,
      rst_cpllreset => rst_cpllreset,
      rst_idle_reg1_reg_0(0) => \gtp_pipe_reset.gtp_pipe_reset_i_n_11\,
      rst_idle_reg2_reg_0 => rst_idle_reg2_reg,
      rxsyncallin => rxsyncallin,
      \rxvalid_cnt_reg[3]_0\ => \^clk\,
      txcompliance_reg1_reg_0(0) => txcompliance_reg1_reg(0),
      txcompliance_reg2_reg_0 => p_0_in4_in_1,
      txcompliance_reg2_reg_1 => \pipe_lane[1].pipe_user_i_n_18\,
      txelecidle_reg2_reg_0 => \pipe_lane[1].pipe_user_i_n_19\,
      txphaligndone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_15\,
      txphaligndone_reg1_reg_0 => \pipe_lane[0].gt_wrapper_i_n_15\,
      txphinitdone_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_16\,
      txphinitdone_reg1_reg_0 => p_1_in5_in,
      txphinitdone_reg1_reg_1 => p_0_in4_in,
      txphinitdone_reg1_reg_2 => \pipe_lane[0].gt_wrapper_i_n_16\,
      user_eyescanreset_1 => user_eyescanreset_1,
      user_oobclk_1 => user_oobclk_1,
      user_resetovrd_1 => user_resetovrd_1,
      user_rxbufreset_1 => user_rxbufreset_1,
      user_rxcdrfreqreset_1 => user_rxcdrfreqreset_1,
      user_rxcdrreset_1 => user_rxcdrreset_1,
      user_rxpcsreset_1 => user_rxpcsreset_1,
      user_rxpmareset_1 => user_rxpmareset_1
    );
pl_phy_lnk_up_q_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst_n,
      O => \^sys_rst_n_0\
    );
\qpll_reset.qpll_reset_i\: entity work.xdma_0_xdma_0_pcie2_ip_qpll_reset
     port map (
      D(0) => D(0),
      Q(0) => qrst_drp_start,
      QRST_DRP_DONE(0) => qdrp_done,
      QRST_QPLLLOCK(0) => \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1\,
      SS(0) => \gtp_pipe_reset.gtp_pipe_reset_i_n_0\,
      SYNC_MMCM_LOCK => \pipe_clock_int.pipe_clock_i_n_3\,
      mmcm_lock_reg1_reg_0 => \^clk\
    );
reset_n_reg1_reg: unisim.vcomponents.FDCE
     port map (
      C => \^clk\,
      CE => '1',
      CLR => \^sys_rst_n_0\,
      D => '1',
      Q => reset_n_reg1
    );
reset_n_reg2_reg: unisim.vcomponents.FDCE
     port map (
      C => \^clk\,
      CE => '1',
      CLR => \^sys_rst_n_0\,
      D => reset_n_reg1,
      Q => reset_n_reg2
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_gt_top is
  port (
    pclk_sel_reg : out STD_LOGIC;
    CLK : out STD_LOGIC;
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_chanisaligned_gt : out STD_LOGIC;
    pipe_rx1_chanisaligned_gt : out STD_LOGIC;
    sys_rst_n_0 : out STD_LOGIC;
    pipe_rx0_valid_gt : out STD_LOGIC;
    phy_rdy_n : out STD_LOGIC;
    pipe_rx1_valid_gt : out STD_LOGIC;
    gt_rx_phy_status_q_reg : out STD_LOGIC;
    gt_rxelecidle_q_reg : out STD_LOGIC;
    gt_rx_phy_status_q : out STD_LOGIC;
    gt_rxelecidle_q : out STD_LOGIC;
    phy_rdy_n_int_reg_0 : out STD_LOGIC;
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    sys_clk : in STD_LOGIC;
    pipe_tx0_elec_idle_gt : in STD_LOGIC;
    TXCHARDISPMODE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_polarity_gt : in STD_LOGIC;
    pipe_tx_deemph_gt : in STD_LOGIC;
    pipe_tx_rcvr_det_gt : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdy_reg1_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    rdy_reg1_reg_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_elec_idle_gt : in STD_LOGIC;
    txcompliance_reg1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_polarity_gt : in STD_LOGIC;
    rdy_reg1_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdy_reg1_reg_3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rdy_reg1_reg_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    sys_rst_n : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_gt_top : entity is "xdma_0_pcie2_ip_gt_top";
end xdma_0_xdma_0_pcie2_ip_gt_top;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_gt_top is
  signal gt_rx_data_k_wire_filter : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gt_rx_data_wire_filter : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal gt_rx_elec_idle_wire_filter : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gt_rx_phy_status_wire_filter : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3\ : STD_LOGIC;
  signal \^pclk_sel_reg\ : STD_LOGIC;
  signal \^phy_rdy_n\ : STD_LOGIC;
  signal \^pipe_rx0_valid_gt\ : STD_LOGIC;
  signal \^pipe_rx1_valid_gt\ : STD_LOGIC;
  signal pipe_wrapper_i_n_47 : STD_LOGIC;
  signal pipe_wrapper_i_n_48 : STD_LOGIC;
  signal pipe_wrapper_i_n_49 : STD_LOGIC;
  signal pipe_wrapper_i_n_50 : STD_LOGIC;
  signal pipe_wrapper_i_n_51 : STD_LOGIC;
  signal pipe_wrapper_i_n_52 : STD_LOGIC;
  signal pipe_wrapper_i_n_53 : STD_LOGIC;
  signal pipe_wrapper_i_n_54 : STD_LOGIC;
  signal pipe_wrapper_i_n_55 : STD_LOGIC;
  signal pipe_wrapper_i_n_56 : STD_LOGIC;
  signal pl_ltssm_state_q : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal reg_clock_locked : STD_LOGIC;
begin
  pclk_sel_reg <= \^pclk_sel_reg\;
  phy_rdy_n <= \^phy_rdy_n\;
  pipe_rx0_valid_gt <= \^pipe_rx0_valid_gt\;
  pipe_rx1_valid_gt <= \^pipe_rx1_valid_gt\;
\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst\: entity work.xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x
     port map (
      CLK => \^pclk_sel_reg\,
      D(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0),
      SR(0) => \^phy_rdy_n\,
      SYNC_RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0),
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0),
      \gt_rx_status_q_reg[2]_1\(2) => pipe_wrapper_i_n_52,
      \gt_rx_status_q_reg[2]_1\(1) => pipe_wrapper_i_n_53,
      \gt_rx_status_q_reg[2]_1\(0) => pipe_wrapper_i_n_54,
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      \gt_rxdata_q_reg[15]_1\(15 downto 0) => gt_rx_data_wire_filter(15 downto 0),
      gt_rxelecidle_q => gt_rxelecidle_q,
      gt_rxvalid_q_reg_0 => \^pipe_rx0_valid_gt\,
      gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_48,
      gt_rxvalid_q_reg_2 => \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3\
    );
\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst\: entity work.xdma_0_xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30
     port map (
      CLK => \^pclk_sel_reg\,
      D(1 downto 0) => gt_rx_data_k_wire_filter(5 downto 4),
      Q(5 downto 0) => pl_ltssm_state_q(5 downto 0),
      SS(0) => \^phy_rdy_n\,
      SYNC_RXELECIDLE => gt_rx_elec_idle_wire_filter(1),
      gt_rx_phy_status_q_reg_0 => gt_rx_phy_status_q_reg,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1),
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0),
      \gt_rx_status_q_reg[2]_1\(2) => pipe_wrapper_i_n_49,
      \gt_rx_status_q_reg[2]_1\(1) => pipe_wrapper_i_n_50,
      \gt_rx_status_q_reg[2]_1\(0) => pipe_wrapper_i_n_51,
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => \gt_rxcharisk_q_reg[1]_0\(1 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0),
      \gt_rxdata_q_reg[15]_1\(15 downto 0) => gt_rx_data_wire_filter(47 downto 32),
      gt_rxelecidle_q_reg_0 => gt_rxelecidle_q_reg,
      gt_rxvalid_q_reg_0 => \^pipe_rx1_valid_gt\,
      gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_55,
      \pl_ltssm_state_q_reg[5]\ => \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3\
    );
pcie_block_i_i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^phy_rdy_n\,
      O => phy_rdy_n_int_reg_0
    );
phy_rdy_n_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      D => pipe_wrapper_i_n_56,
      Q => \^phy_rdy_n\,
      R => '0'
    );
pipe_wrapper_i: entity work.xdma_0_xdma_0_pcie2_ip_pipe_wrapper
     port map (
      CLK => \^pclk_sel_reg\,
      D(0) => D(0),
      Q(1 downto 0) => Q(1 downto 0),
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      gt_rx_data_k_wire_filter(3 downto 2) => gt_rx_data_k_wire_filter(5 downto 4),
      gt_rx_data_k_wire_filter(1 downto 0) => gt_rx_data_k_wire_filter(1 downto 0),
      gt_rx_data_wire_filter(31 downto 16) => gt_rx_data_wire_filter(47 downto 32),
      gt_rx_data_wire_filter(15 downto 0) => gt_rx_data_wire_filter(15 downto 0),
      gt_rx_elec_idle_wire_filter(1 downto 0) => gt_rx_elec_idle_wire_filter(1 downto 0),
      gt_rx_phy_status_wire_filter(1 downto 0) => gt_rx_phy_status_wire_filter(1 downto 0),
      \gt_rx_status_q_reg[0]\ => \^pipe_rx0_valid_gt\,
      \gt_rx_status_q_reg[0]_0\ => \^pipe_rx1_valid_gt\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3\,
      gt_rxvalid_q_reg(2) => pipe_wrapper_i_n_49,
      gt_rxvalid_q_reg(1) => pipe_wrapper_i_n_50,
      gt_rxvalid_q_reg(0) => pipe_wrapper_i_n_51,
      gt_rxvalid_q_reg_0(2) => pipe_wrapper_i_n_52,
      gt_rxvalid_q_reg_0(1) => pipe_wrapper_i_n_53,
      gt_rxvalid_q_reg_0(0) => pipe_wrapper_i_n_54,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      mmcm_i => CLK,
      mmcm_i_0 => pipe_wrapper_i_n_47,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt,
      rate_idle_reg2_reg => pipe_wrapper_i_n_48,
      rate_idle_reg2_reg_0 => pipe_wrapper_i_n_55,
      rdy_reg1_reg(2 downto 0) => rdy_reg1_reg(2 downto 0),
      rdy_reg1_reg_0(15 downto 0) => rdy_reg1_reg_0(15 downto 0),
      rdy_reg1_reg_1(1 downto 0) => rdy_reg1_reg_1(1 downto 0),
      rdy_reg1_reg_2(1 downto 0) => rdy_reg1_reg_2(1 downto 0),
      rdy_reg1_reg_3(15 downto 0) => rdy_reg1_reg_3(15 downto 0),
      rdy_reg1_reg_4(1 downto 0) => rdy_reg1_reg_4(1 downto 0),
      reg_clock_locked => reg_clock_locked,
      rst_idle_reg2_reg => pipe_wrapper_i_n_56,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      sys_rst_n_0 => sys_rst_n_0,
      txcompliance_reg1_reg(0) => txcompliance_reg1_reg(0)
    );
\pl_ltssm_state_q_reg[0]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(0),
      Q => pl_ltssm_state_q(0)
    );
\pl_ltssm_state_q_reg[1]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(1),
      Q => pl_ltssm_state_q(1)
    );
\pl_ltssm_state_q_reg[2]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(2),
      Q => pl_ltssm_state_q(2)
    );
\pl_ltssm_state_q_reg[3]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(3),
      Q => pl_ltssm_state_q(3)
    );
\pl_ltssm_state_q_reg[4]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(4),
      Q => pl_ltssm_state_q(4)
    );
\pl_ltssm_state_q_reg[5]\: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => pl_ltssm_state(5),
      Q => pl_ltssm_state_q(5)
    );
reg_clock_locked_reg: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_47,
      D => '1',
      Q => reg_clock_locked
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_7x is
  port (
    user_reset_int_reg : out STD_LOGIC;
    src_in : out STD_LOGIC;
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    trn_in_packet_reg : out STD_LOGIC;
    trn_reof : out STD_LOGIC;
    trn_rsof : out STD_LOGIC;
    trn_rsrc_dsc : out STD_LOGIC;
    ppm_L1_thrtl_reg : out STD_LOGIC;
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    dsc_detect : out STD_LOGIC;
    rsrc_rdy_filtered : out STD_LOGIC;
    trn_rsrc_dsc_prev0 : out STD_LOGIC;
    tcfg_req_trig : out STD_LOGIC;
    trn_tcfg_req : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : out STD_LOGIC;
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tbuf_av_min_trig : out STD_LOGIC;
    lnk_up_thrtl_reg : out STD_LOGIC;
    trn_tdst_rdy : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    pipe_rx0_polarity : out STD_LOGIC;
    pipe_rx1_polarity : out STD_LOGIC;
    pipe_tx0_compliance : out STD_LOGIC;
    pipe_tx0_elec_idle : out STD_LOGIC;
    pipe_tx1_compliance : out STD_LOGIC;
    pipe_tx1_elec_idle : out STD_LOGIC;
    pipe_tx_deemph : out STD_LOGIC;
    pipe_tx_rate : out STD_LOGIC;
    pipe_tx_rcvr_det : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    trn_recrc_err : out STD_LOGIC;
    trn_rerrfwd : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx_margin : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 );
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    trn_in_packet : in STD_LOGIC;
    trn_rdst_rdy : in STD_LOGIC;
    ppm_L1_trig : in STD_LOGIC;
    ppm_L1_thrtl : in STD_LOGIC;
    trn_rsrc_dsc_d : in STD_LOGIC;
    reg_dsc_detect : in STD_LOGIC;
    reg_tcfg_gnt : in STD_LOGIC;
    lnk_up_thrtl : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    clk_msien_reg : in STD_LOGIC;
    pipe_rx0_chanisaligned : in STD_LOGIC;
    pipe_rx0_elec_idle : in STD_LOGIC;
    pipe_rx0_phy_status : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    pipe_rx1_chanisaligned : in STD_LOGIC;
    pipe_rx1_elec_idle : in STD_LOGIC;
    pipe_rx1_phy_status : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    trn_tcfg_gnt : in STD_LOGIC;
    trn_teof : in STD_LOGIC;
    trn_tsof : in STD_LOGIC;
    trn_tsrc_rdy : in STD_LOGIC;
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    clk_msien_reg_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    clk_msien_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    clk_msien_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_trem : in STD_LOGIC_VECTOR ( 0 to 0 );
    clk_msien_reg_3 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    clk_msien_reg_4 : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_7x : entity is "xdma_0_pcie2_ip_pcie_7x";
end xdma_0_xdma_0_pcie2_ip_pcie_7x;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_7x is
  signal cfg_err_aer_headerlog_set_n : STD_LOGIC;
  signal cfg_err_cpl_rdy_n : STD_LOGIC;
  signal cfg_interrupt_rdy_n : STD_LOGIC;
  signal cfg_mgmt_rd_wr_done_n : STD_LOGIC;
  signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cfg_received_func_lvl_rst_n : STD_LOGIC;
  signal mim_rx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_rdata : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal mim_rx_ren : STD_LOGIC;
  signal mim_rx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_wdata : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal mim_rx_wen : STD_LOGIC;
  signal mim_tx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_rdata : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal mim_tx_ren : STD_LOGIC;
  signal mim_tx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_wdata : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal mim_tx_wen : STD_LOGIC;
  signal pcie_block_i_i_1_n_0 : STD_LOGIC;
  signal pcie_block_i_i_2_n_0 : STD_LOGIC;
  signal pcie_block_i_i_3_n_0 : STD_LOGIC;
  signal pcie_block_i_i_4_n_0 : STD_LOGIC;
  signal pcie_block_i_i_5_n_0 : STD_LOGIC;
  signal pcie_block_i_n_0 : STD_LOGIC;
  signal pcie_block_i_n_1 : STD_LOGIC;
  signal pcie_block_i_n_10 : STD_LOGIC;
  signal pcie_block_i_n_100 : STD_LOGIC;
  signal pcie_block_i_n_101 : STD_LOGIC;
  signal pcie_block_i_n_102 : STD_LOGIC;
  signal pcie_block_i_n_103 : STD_LOGIC;
  signal pcie_block_i_n_104 : STD_LOGIC;
  signal pcie_block_i_n_105 : STD_LOGIC;
  signal pcie_block_i_n_106 : STD_LOGIC;
  signal pcie_block_i_n_107 : STD_LOGIC;
  signal pcie_block_i_n_108 : STD_LOGIC;
  signal pcie_block_i_n_1097 : STD_LOGIC;
  signal pcie_block_i_n_1098 : STD_LOGIC;
  signal pcie_block_i_n_1099 : STD_LOGIC;
  signal pcie_block_i_n_11 : STD_LOGIC;
  signal pcie_block_i_n_1100 : STD_LOGIC;
  signal pcie_block_i_n_1101 : STD_LOGIC;
  signal pcie_block_i_n_1102 : STD_LOGIC;
  signal pcie_block_i_n_1103 : STD_LOGIC;
  signal pcie_block_i_n_1104 : STD_LOGIC;
  signal pcie_block_i_n_1105 : STD_LOGIC;
  signal pcie_block_i_n_1106 : STD_LOGIC;
  signal pcie_block_i_n_1107 : STD_LOGIC;
  signal pcie_block_i_n_1108 : STD_LOGIC;
  signal pcie_block_i_n_1109 : STD_LOGIC;
  signal pcie_block_i_n_1110 : STD_LOGIC;
  signal pcie_block_i_n_1111 : STD_LOGIC;
  signal pcie_block_i_n_1112 : STD_LOGIC;
  signal pcie_block_i_n_1113 : STD_LOGIC;
  signal pcie_block_i_n_1114 : STD_LOGIC;
  signal pcie_block_i_n_1115 : STD_LOGIC;
  signal pcie_block_i_n_1116 : STD_LOGIC;
  signal pcie_block_i_n_1117 : STD_LOGIC;
  signal pcie_block_i_n_1118 : STD_LOGIC;
  signal pcie_block_i_n_1119 : STD_LOGIC;
  signal pcie_block_i_n_1120 : STD_LOGIC;
  signal pcie_block_i_n_1121 : STD_LOGIC;
  signal pcie_block_i_n_1122 : STD_LOGIC;
  signal pcie_block_i_n_1123 : STD_LOGIC;
  signal pcie_block_i_n_1124 : STD_LOGIC;
  signal pcie_block_i_n_1125 : STD_LOGIC;
  signal pcie_block_i_n_1126 : STD_LOGIC;
  signal pcie_block_i_n_1135 : STD_LOGIC;
  signal pcie_block_i_n_1136 : STD_LOGIC;
  signal pcie_block_i_n_1137 : STD_LOGIC;
  signal pcie_block_i_n_1138 : STD_LOGIC;
  signal pcie_block_i_n_1139 : STD_LOGIC;
  signal pcie_block_i_n_1140 : STD_LOGIC;
  signal pcie_block_i_n_1141 : STD_LOGIC;
  signal pcie_block_i_n_1142 : STD_LOGIC;
  signal pcie_block_i_n_1143 : STD_LOGIC;
  signal pcie_block_i_n_12 : STD_LOGIC;
  signal pcie_block_i_n_13 : STD_LOGIC;
  signal pcie_block_i_n_14 : STD_LOGIC;
  signal pcie_block_i_n_140 : STD_LOGIC;
  signal pcie_block_i_n_141 : STD_LOGIC;
  signal pcie_block_i_n_142 : STD_LOGIC;
  signal pcie_block_i_n_143 : STD_LOGIC;
  signal pcie_block_i_n_144 : STD_LOGIC;
  signal pcie_block_i_n_145 : STD_LOGIC;
  signal pcie_block_i_n_146 : STD_LOGIC;
  signal pcie_block_i_n_147 : STD_LOGIC;
  signal pcie_block_i_n_148 : STD_LOGIC;
  signal pcie_block_i_n_149 : STD_LOGIC;
  signal pcie_block_i_n_15 : STD_LOGIC;
  signal pcie_block_i_n_150 : STD_LOGIC;
  signal pcie_block_i_n_153 : STD_LOGIC;
  signal pcie_block_i_n_155 : STD_LOGIC;
  signal pcie_block_i_n_156 : STD_LOGIC;
  signal pcie_block_i_n_157 : STD_LOGIC;
  signal pcie_block_i_n_158 : STD_LOGIC;
  signal pcie_block_i_n_159 : STD_LOGIC;
  signal pcie_block_i_n_16 : STD_LOGIC;
  signal pcie_block_i_n_160 : STD_LOGIC;
  signal pcie_block_i_n_169 : STD_LOGIC;
  signal pcie_block_i_n_17 : STD_LOGIC;
  signal pcie_block_i_n_170 : STD_LOGIC;
  signal pcie_block_i_n_172 : STD_LOGIC;
  signal pcie_block_i_n_173 : STD_LOGIC;
  signal pcie_block_i_n_174 : STD_LOGIC;
  signal pcie_block_i_n_175 : STD_LOGIC;
  signal pcie_block_i_n_176 : STD_LOGIC;
  signal pcie_block_i_n_177 : STD_LOGIC;
  signal pcie_block_i_n_178 : STD_LOGIC;
  signal pcie_block_i_n_179 : STD_LOGIC;
  signal pcie_block_i_n_18 : STD_LOGIC;
  signal pcie_block_i_n_180 : STD_LOGIC;
  signal pcie_block_i_n_181 : STD_LOGIC;
  signal pcie_block_i_n_182 : STD_LOGIC;
  signal pcie_block_i_n_183 : STD_LOGIC;
  signal pcie_block_i_n_184 : STD_LOGIC;
  signal pcie_block_i_n_185 : STD_LOGIC;
  signal pcie_block_i_n_186 : STD_LOGIC;
  signal pcie_block_i_n_187 : STD_LOGIC;
  signal pcie_block_i_n_188 : STD_LOGIC;
  signal pcie_block_i_n_189 : STD_LOGIC;
  signal pcie_block_i_n_19 : STD_LOGIC;
  signal pcie_block_i_n_190 : STD_LOGIC;
  signal pcie_block_i_n_191 : STD_LOGIC;
  signal pcie_block_i_n_192 : STD_LOGIC;
  signal pcie_block_i_n_193 : STD_LOGIC;
  signal pcie_block_i_n_194 : STD_LOGIC;
  signal pcie_block_i_n_195 : STD_LOGIC;
  signal pcie_block_i_n_196 : STD_LOGIC;
  signal pcie_block_i_n_197 : STD_LOGIC;
  signal pcie_block_i_n_198 : STD_LOGIC;
  signal pcie_block_i_n_199 : STD_LOGIC;
  signal pcie_block_i_n_2 : STD_LOGIC;
  signal pcie_block_i_n_20 : STD_LOGIC;
  signal pcie_block_i_n_200 : STD_LOGIC;
  signal pcie_block_i_n_201 : STD_LOGIC;
  signal pcie_block_i_n_202 : STD_LOGIC;
  signal pcie_block_i_n_203 : STD_LOGIC;
  signal pcie_block_i_n_204 : STD_LOGIC;
  signal pcie_block_i_n_205 : STD_LOGIC;
  signal pcie_block_i_n_206 : STD_LOGIC;
  signal pcie_block_i_n_207 : STD_LOGIC;
  signal pcie_block_i_n_208 : STD_LOGIC;
  signal pcie_block_i_n_209 : STD_LOGIC;
  signal pcie_block_i_n_21 : STD_LOGIC;
  signal pcie_block_i_n_210 : STD_LOGIC;
  signal pcie_block_i_n_211 : STD_LOGIC;
  signal pcie_block_i_n_212 : STD_LOGIC;
  signal pcie_block_i_n_213 : STD_LOGIC;
  signal pcie_block_i_n_214 : STD_LOGIC;
  signal pcie_block_i_n_215 : STD_LOGIC;
  signal pcie_block_i_n_216 : STD_LOGIC;
  signal pcie_block_i_n_217 : STD_LOGIC;
  signal pcie_block_i_n_218 : STD_LOGIC;
  signal pcie_block_i_n_219 : STD_LOGIC;
  signal pcie_block_i_n_22 : STD_LOGIC;
  signal pcie_block_i_n_220 : STD_LOGIC;
  signal pcie_block_i_n_221 : STD_LOGIC;
  signal pcie_block_i_n_222 : STD_LOGIC;
  signal pcie_block_i_n_223 : STD_LOGIC;
  signal pcie_block_i_n_224 : STD_LOGIC;
  signal pcie_block_i_n_225 : STD_LOGIC;
  signal pcie_block_i_n_226 : STD_LOGIC;
  signal pcie_block_i_n_227 : STD_LOGIC;
  signal pcie_block_i_n_228 : STD_LOGIC;
  signal pcie_block_i_n_229 : STD_LOGIC;
  signal pcie_block_i_n_23 : STD_LOGIC;
  signal pcie_block_i_n_230 : STD_LOGIC;
  signal pcie_block_i_n_231 : STD_LOGIC;
  signal pcie_block_i_n_24 : STD_LOGIC;
  signal pcie_block_i_n_25 : STD_LOGIC;
  signal pcie_block_i_n_26 : STD_LOGIC;
  signal pcie_block_i_n_27 : STD_LOGIC;
  signal pcie_block_i_n_28 : STD_LOGIC;
  signal pcie_block_i_n_29 : STD_LOGIC;
  signal pcie_block_i_n_3 : STD_LOGIC;
  signal pcie_block_i_n_30 : STD_LOGIC;
  signal pcie_block_i_n_31 : STD_LOGIC;
  signal pcie_block_i_n_32 : STD_LOGIC;
  signal pcie_block_i_n_33 : STD_LOGIC;
  signal pcie_block_i_n_34 : STD_LOGIC;
  signal pcie_block_i_n_38 : STD_LOGIC;
  signal pcie_block_i_n_39 : STD_LOGIC;
  signal pcie_block_i_n_4 : STD_LOGIC;
  signal pcie_block_i_n_41 : STD_LOGIC;
  signal pcie_block_i_n_42 : STD_LOGIC;
  signal pcie_block_i_n_428 : STD_LOGIC;
  signal pcie_block_i_n_429 : STD_LOGIC;
  signal pcie_block_i_n_43 : STD_LOGIC;
  signal pcie_block_i_n_430 : STD_LOGIC;
  signal pcie_block_i_n_431 : STD_LOGIC;
  signal pcie_block_i_n_432 : STD_LOGIC;
  signal pcie_block_i_n_433 : STD_LOGIC;
  signal pcie_block_i_n_434 : STD_LOGIC;
  signal pcie_block_i_n_435 : STD_LOGIC;
  signal pcie_block_i_n_436 : STD_LOGIC;
  signal pcie_block_i_n_437 : STD_LOGIC;
  signal pcie_block_i_n_438 : STD_LOGIC;
  signal pcie_block_i_n_439 : STD_LOGIC;
  signal pcie_block_i_n_44 : STD_LOGIC;
  signal pcie_block_i_n_440 : STD_LOGIC;
  signal pcie_block_i_n_441 : STD_LOGIC;
  signal pcie_block_i_n_442 : STD_LOGIC;
  signal pcie_block_i_n_443 : STD_LOGIC;
  signal pcie_block_i_n_45 : STD_LOGIC;
  signal pcie_block_i_n_46 : STD_LOGIC;
  signal pcie_block_i_n_47 : STD_LOGIC;
  signal pcie_block_i_n_48 : STD_LOGIC;
  signal pcie_block_i_n_49 : STD_LOGIC;
  signal pcie_block_i_n_5 : STD_LOGIC;
  signal pcie_block_i_n_50 : STD_LOGIC;
  signal pcie_block_i_n_51 : STD_LOGIC;
  signal pcie_block_i_n_52 : STD_LOGIC;
  signal pcie_block_i_n_53 : STD_LOGIC;
  signal pcie_block_i_n_55 : STD_LOGIC;
  signal pcie_block_i_n_56 : STD_LOGIC;
  signal pcie_block_i_n_57 : STD_LOGIC;
  signal pcie_block_i_n_572 : STD_LOGIC;
  signal pcie_block_i_n_573 : STD_LOGIC;
  signal pcie_block_i_n_574 : STD_LOGIC;
  signal pcie_block_i_n_575 : STD_LOGIC;
  signal pcie_block_i_n_576 : STD_LOGIC;
  signal pcie_block_i_n_577 : STD_LOGIC;
  signal pcie_block_i_n_58 : STD_LOGIC;
  signal pcie_block_i_n_59 : STD_LOGIC;
  signal pcie_block_i_n_6 : STD_LOGIC;
  signal pcie_block_i_n_60 : STD_LOGIC;
  signal pcie_block_i_n_61 : STD_LOGIC;
  signal pcie_block_i_n_610 : STD_LOGIC;
  signal pcie_block_i_n_611 : STD_LOGIC;
  signal pcie_block_i_n_612 : STD_LOGIC;
  signal pcie_block_i_n_613 : STD_LOGIC;
  signal pcie_block_i_n_614 : STD_LOGIC;
  signal pcie_block_i_n_615 : STD_LOGIC;
  signal pcie_block_i_n_616 : STD_LOGIC;
  signal pcie_block_i_n_617 : STD_LOGIC;
  signal pcie_block_i_n_618 : STD_LOGIC;
  signal pcie_block_i_n_619 : STD_LOGIC;
  signal pcie_block_i_n_62 : STD_LOGIC;
  signal pcie_block_i_n_63 : STD_LOGIC;
  signal pcie_block_i_n_637 : STD_LOGIC;
  signal pcie_block_i_n_638 : STD_LOGIC;
  signal pcie_block_i_n_639 : STD_LOGIC;
  signal pcie_block_i_n_64 : STD_LOGIC;
  signal pcie_block_i_n_640 : STD_LOGIC;
  signal pcie_block_i_n_641 : STD_LOGIC;
  signal pcie_block_i_n_642 : STD_LOGIC;
  signal pcie_block_i_n_65 : STD_LOGIC;
  signal pcie_block_i_n_66 : STD_LOGIC;
  signal pcie_block_i_n_67 : STD_LOGIC;
  signal pcie_block_i_n_675 : STD_LOGIC;
  signal pcie_block_i_n_676 : STD_LOGIC;
  signal pcie_block_i_n_677 : STD_LOGIC;
  signal pcie_block_i_n_678 : STD_LOGIC;
  signal pcie_block_i_n_679 : STD_LOGIC;
  signal pcie_block_i_n_680 : STD_LOGIC;
  signal pcie_block_i_n_681 : STD_LOGIC;
  signal pcie_block_i_n_682 : STD_LOGIC;
  signal pcie_block_i_n_687 : STD_LOGIC;
  signal pcie_block_i_n_688 : STD_LOGIC;
  signal pcie_block_i_n_689 : STD_LOGIC;
  signal pcie_block_i_n_69 : STD_LOGIC;
  signal pcie_block_i_n_690 : STD_LOGIC;
  signal pcie_block_i_n_691 : STD_LOGIC;
  signal pcie_block_i_n_7 : STD_LOGIC;
  signal pcie_block_i_n_70 : STD_LOGIC;
  signal pcie_block_i_n_704 : STD_LOGIC;
  signal pcie_block_i_n_705 : STD_LOGIC;
  signal pcie_block_i_n_706 : STD_LOGIC;
  signal pcie_block_i_n_707 : STD_LOGIC;
  signal pcie_block_i_n_708 : STD_LOGIC;
  signal pcie_block_i_n_709 : STD_LOGIC;
  signal pcie_block_i_n_71 : STD_LOGIC;
  signal pcie_block_i_n_710 : STD_LOGIC;
  signal pcie_block_i_n_711 : STD_LOGIC;
  signal pcie_block_i_n_712 : STD_LOGIC;
  signal pcie_block_i_n_713 : STD_LOGIC;
  signal pcie_block_i_n_714 : STD_LOGIC;
  signal pcie_block_i_n_715 : STD_LOGIC;
  signal pcie_block_i_n_716 : STD_LOGIC;
  signal pcie_block_i_n_717 : STD_LOGIC;
  signal pcie_block_i_n_718 : STD_LOGIC;
  signal pcie_block_i_n_719 : STD_LOGIC;
  signal pcie_block_i_n_72 : STD_LOGIC;
  signal pcie_block_i_n_720 : STD_LOGIC;
  signal pcie_block_i_n_721 : STD_LOGIC;
  signal pcie_block_i_n_722 : STD_LOGIC;
  signal pcie_block_i_n_723 : STD_LOGIC;
  signal pcie_block_i_n_724 : STD_LOGIC;
  signal pcie_block_i_n_725 : STD_LOGIC;
  signal pcie_block_i_n_726 : STD_LOGIC;
  signal pcie_block_i_n_727 : STD_LOGIC;
  signal pcie_block_i_n_728 : STD_LOGIC;
  signal pcie_block_i_n_729 : STD_LOGIC;
  signal pcie_block_i_n_73 : STD_LOGIC;
  signal pcie_block_i_n_730 : STD_LOGIC;
  signal pcie_block_i_n_731 : STD_LOGIC;
  signal pcie_block_i_n_732 : STD_LOGIC;
  signal pcie_block_i_n_733 : STD_LOGIC;
  signal pcie_block_i_n_734 : STD_LOGIC;
  signal pcie_block_i_n_735 : STD_LOGIC;
  signal pcie_block_i_n_736 : STD_LOGIC;
  signal pcie_block_i_n_737 : STD_LOGIC;
  signal pcie_block_i_n_738 : STD_LOGIC;
  signal pcie_block_i_n_739 : STD_LOGIC;
  signal pcie_block_i_n_74 : STD_LOGIC;
  signal pcie_block_i_n_740 : STD_LOGIC;
  signal pcie_block_i_n_741 : STD_LOGIC;
  signal pcie_block_i_n_742 : STD_LOGIC;
  signal pcie_block_i_n_743 : STD_LOGIC;
  signal pcie_block_i_n_744 : STD_LOGIC;
  signal pcie_block_i_n_745 : STD_LOGIC;
  signal pcie_block_i_n_746 : STD_LOGIC;
  signal pcie_block_i_n_747 : STD_LOGIC;
  signal pcie_block_i_n_748 : STD_LOGIC;
  signal pcie_block_i_n_749 : STD_LOGIC;
  signal pcie_block_i_n_75 : STD_LOGIC;
  signal pcie_block_i_n_750 : STD_LOGIC;
  signal pcie_block_i_n_751 : STD_LOGIC;
  signal pcie_block_i_n_752 : STD_LOGIC;
  signal pcie_block_i_n_753 : STD_LOGIC;
  signal pcie_block_i_n_754 : STD_LOGIC;
  signal pcie_block_i_n_755 : STD_LOGIC;
  signal pcie_block_i_n_756 : STD_LOGIC;
  signal pcie_block_i_n_757 : STD_LOGIC;
  signal pcie_block_i_n_758 : STD_LOGIC;
  signal pcie_block_i_n_759 : STD_LOGIC;
  signal pcie_block_i_n_76 : STD_LOGIC;
  signal pcie_block_i_n_760 : STD_LOGIC;
  signal pcie_block_i_n_761 : STD_LOGIC;
  signal pcie_block_i_n_762 : STD_LOGIC;
  signal pcie_block_i_n_763 : STD_LOGIC;
  signal pcie_block_i_n_764 : STD_LOGIC;
  signal pcie_block_i_n_765 : STD_LOGIC;
  signal pcie_block_i_n_766 : STD_LOGIC;
  signal pcie_block_i_n_767 : STD_LOGIC;
  signal pcie_block_i_n_768 : STD_LOGIC;
  signal pcie_block_i_n_769 : STD_LOGIC;
  signal pcie_block_i_n_77 : STD_LOGIC;
  signal pcie_block_i_n_770 : STD_LOGIC;
  signal pcie_block_i_n_771 : STD_LOGIC;
  signal pcie_block_i_n_772 : STD_LOGIC;
  signal pcie_block_i_n_773 : STD_LOGIC;
  signal pcie_block_i_n_774 : STD_LOGIC;
  signal pcie_block_i_n_775 : STD_LOGIC;
  signal pcie_block_i_n_776 : STD_LOGIC;
  signal pcie_block_i_n_777 : STD_LOGIC;
  signal pcie_block_i_n_778 : STD_LOGIC;
  signal pcie_block_i_n_779 : STD_LOGIC;
  signal pcie_block_i_n_78 : STD_LOGIC;
  signal pcie_block_i_n_780 : STD_LOGIC;
  signal pcie_block_i_n_781 : STD_LOGIC;
  signal pcie_block_i_n_782 : STD_LOGIC;
  signal pcie_block_i_n_783 : STD_LOGIC;
  signal pcie_block_i_n_784 : STD_LOGIC;
  signal pcie_block_i_n_785 : STD_LOGIC;
  signal pcie_block_i_n_786 : STD_LOGIC;
  signal pcie_block_i_n_787 : STD_LOGIC;
  signal pcie_block_i_n_788 : STD_LOGIC;
  signal pcie_block_i_n_789 : STD_LOGIC;
  signal pcie_block_i_n_79 : STD_LOGIC;
  signal pcie_block_i_n_790 : STD_LOGIC;
  signal pcie_block_i_n_791 : STD_LOGIC;
  signal pcie_block_i_n_792 : STD_LOGIC;
  signal pcie_block_i_n_793 : STD_LOGIC;
  signal pcie_block_i_n_794 : STD_LOGIC;
  signal pcie_block_i_n_795 : STD_LOGIC;
  signal pcie_block_i_n_796 : STD_LOGIC;
  signal pcie_block_i_n_797 : STD_LOGIC;
  signal pcie_block_i_n_798 : STD_LOGIC;
  signal pcie_block_i_n_799 : STD_LOGIC;
  signal pcie_block_i_n_8 : STD_LOGIC;
  signal pcie_block_i_n_80 : STD_LOGIC;
  signal pcie_block_i_n_800 : STD_LOGIC;
  signal pcie_block_i_n_801 : STD_LOGIC;
  signal pcie_block_i_n_802 : STD_LOGIC;
  signal pcie_block_i_n_803 : STD_LOGIC;
  signal pcie_block_i_n_804 : STD_LOGIC;
  signal pcie_block_i_n_805 : STD_LOGIC;
  signal pcie_block_i_n_806 : STD_LOGIC;
  signal pcie_block_i_n_807 : STD_LOGIC;
  signal pcie_block_i_n_808 : STD_LOGIC;
  signal pcie_block_i_n_809 : STD_LOGIC;
  signal pcie_block_i_n_81 : STD_LOGIC;
  signal pcie_block_i_n_810 : STD_LOGIC;
  signal pcie_block_i_n_811 : STD_LOGIC;
  signal pcie_block_i_n_812 : STD_LOGIC;
  signal pcie_block_i_n_813 : STD_LOGIC;
  signal pcie_block_i_n_814 : STD_LOGIC;
  signal pcie_block_i_n_815 : STD_LOGIC;
  signal pcie_block_i_n_816 : STD_LOGIC;
  signal pcie_block_i_n_817 : STD_LOGIC;
  signal pcie_block_i_n_818 : STD_LOGIC;
  signal pcie_block_i_n_819 : STD_LOGIC;
  signal pcie_block_i_n_82 : STD_LOGIC;
  signal pcie_block_i_n_820 : STD_LOGIC;
  signal pcie_block_i_n_821 : STD_LOGIC;
  signal pcie_block_i_n_822 : STD_LOGIC;
  signal pcie_block_i_n_823 : STD_LOGIC;
  signal pcie_block_i_n_824 : STD_LOGIC;
  signal pcie_block_i_n_825 : STD_LOGIC;
  signal pcie_block_i_n_826 : STD_LOGIC;
  signal pcie_block_i_n_827 : STD_LOGIC;
  signal pcie_block_i_n_828 : STD_LOGIC;
  signal pcie_block_i_n_829 : STD_LOGIC;
  signal pcie_block_i_n_83 : STD_LOGIC;
  signal pcie_block_i_n_830 : STD_LOGIC;
  signal pcie_block_i_n_831 : STD_LOGIC;
  signal pcie_block_i_n_832 : STD_LOGIC;
  signal pcie_block_i_n_833 : STD_LOGIC;
  signal pcie_block_i_n_834 : STD_LOGIC;
  signal pcie_block_i_n_835 : STD_LOGIC;
  signal pcie_block_i_n_836 : STD_LOGIC;
  signal pcie_block_i_n_837 : STD_LOGIC;
  signal pcie_block_i_n_838 : STD_LOGIC;
  signal pcie_block_i_n_839 : STD_LOGIC;
  signal pcie_block_i_n_84 : STD_LOGIC;
  signal pcie_block_i_n_840 : STD_LOGIC;
  signal pcie_block_i_n_841 : STD_LOGIC;
  signal pcie_block_i_n_842 : STD_LOGIC;
  signal pcie_block_i_n_843 : STD_LOGIC;
  signal pcie_block_i_n_844 : STD_LOGIC;
  signal pcie_block_i_n_845 : STD_LOGIC;
  signal pcie_block_i_n_846 : STD_LOGIC;
  signal pcie_block_i_n_847 : STD_LOGIC;
  signal pcie_block_i_n_848 : STD_LOGIC;
  signal pcie_block_i_n_849 : STD_LOGIC;
  signal pcie_block_i_n_85 : STD_LOGIC;
  signal pcie_block_i_n_850 : STD_LOGIC;
  signal pcie_block_i_n_851 : STD_LOGIC;
  signal pcie_block_i_n_852 : STD_LOGIC;
  signal pcie_block_i_n_853 : STD_LOGIC;
  signal pcie_block_i_n_854 : STD_LOGIC;
  signal pcie_block_i_n_855 : STD_LOGIC;
  signal pcie_block_i_n_856 : STD_LOGIC;
  signal pcie_block_i_n_857 : STD_LOGIC;
  signal pcie_block_i_n_858 : STD_LOGIC;
  signal pcie_block_i_n_859 : STD_LOGIC;
  signal pcie_block_i_n_86 : STD_LOGIC;
  signal pcie_block_i_n_860 : STD_LOGIC;
  signal pcie_block_i_n_861 : STD_LOGIC;
  signal pcie_block_i_n_862 : STD_LOGIC;
  signal pcie_block_i_n_863 : STD_LOGIC;
  signal pcie_block_i_n_864 : STD_LOGIC;
  signal pcie_block_i_n_865 : STD_LOGIC;
  signal pcie_block_i_n_866 : STD_LOGIC;
  signal pcie_block_i_n_867 : STD_LOGIC;
  signal pcie_block_i_n_868 : STD_LOGIC;
  signal pcie_block_i_n_869 : STD_LOGIC;
  signal pcie_block_i_n_87 : STD_LOGIC;
  signal pcie_block_i_n_870 : STD_LOGIC;
  signal pcie_block_i_n_871 : STD_LOGIC;
  signal pcie_block_i_n_872 : STD_LOGIC;
  signal pcie_block_i_n_873 : STD_LOGIC;
  signal pcie_block_i_n_874 : STD_LOGIC;
  signal pcie_block_i_n_875 : STD_LOGIC;
  signal pcie_block_i_n_876 : STD_LOGIC;
  signal pcie_block_i_n_877 : STD_LOGIC;
  signal pcie_block_i_n_878 : STD_LOGIC;
  signal pcie_block_i_n_879 : STD_LOGIC;
  signal pcie_block_i_n_88 : STD_LOGIC;
  signal pcie_block_i_n_880 : STD_LOGIC;
  signal pcie_block_i_n_881 : STD_LOGIC;
  signal pcie_block_i_n_882 : STD_LOGIC;
  signal pcie_block_i_n_883 : STD_LOGIC;
  signal pcie_block_i_n_884 : STD_LOGIC;
  signal pcie_block_i_n_885 : STD_LOGIC;
  signal pcie_block_i_n_886 : STD_LOGIC;
  signal pcie_block_i_n_887 : STD_LOGIC;
  signal pcie_block_i_n_888 : STD_LOGIC;
  signal pcie_block_i_n_889 : STD_LOGIC;
  signal pcie_block_i_n_89 : STD_LOGIC;
  signal pcie_block_i_n_890 : STD_LOGIC;
  signal pcie_block_i_n_891 : STD_LOGIC;
  signal pcie_block_i_n_892 : STD_LOGIC;
  signal pcie_block_i_n_893 : STD_LOGIC;
  signal pcie_block_i_n_894 : STD_LOGIC;
  signal pcie_block_i_n_895 : STD_LOGIC;
  signal pcie_block_i_n_896 : STD_LOGIC;
  signal pcie_block_i_n_897 : STD_LOGIC;
  signal pcie_block_i_n_898 : STD_LOGIC;
  signal pcie_block_i_n_899 : STD_LOGIC;
  signal pcie_block_i_n_90 : STD_LOGIC;
  signal pcie_block_i_n_900 : STD_LOGIC;
  signal pcie_block_i_n_901 : STD_LOGIC;
  signal pcie_block_i_n_902 : STD_LOGIC;
  signal pcie_block_i_n_903 : STD_LOGIC;
  signal pcie_block_i_n_904 : STD_LOGIC;
  signal pcie_block_i_n_905 : STD_LOGIC;
  signal pcie_block_i_n_906 : STD_LOGIC;
  signal pcie_block_i_n_907 : STD_LOGIC;
  signal pcie_block_i_n_908 : STD_LOGIC;
  signal pcie_block_i_n_909 : STD_LOGIC;
  signal pcie_block_i_n_91 : STD_LOGIC;
  signal pcie_block_i_n_910 : STD_LOGIC;
  signal pcie_block_i_n_911 : STD_LOGIC;
  signal pcie_block_i_n_912 : STD_LOGIC;
  signal pcie_block_i_n_913 : STD_LOGIC;
  signal pcie_block_i_n_914 : STD_LOGIC;
  signal pcie_block_i_n_915 : STD_LOGIC;
  signal pcie_block_i_n_916 : STD_LOGIC;
  signal pcie_block_i_n_917 : STD_LOGIC;
  signal pcie_block_i_n_918 : STD_LOGIC;
  signal pcie_block_i_n_919 : STD_LOGIC;
  signal pcie_block_i_n_92 : STD_LOGIC;
  signal pcie_block_i_n_920 : STD_LOGIC;
  signal pcie_block_i_n_921 : STD_LOGIC;
  signal pcie_block_i_n_922 : STD_LOGIC;
  signal pcie_block_i_n_923 : STD_LOGIC;
  signal pcie_block_i_n_924 : STD_LOGIC;
  signal pcie_block_i_n_925 : STD_LOGIC;
  signal pcie_block_i_n_926 : STD_LOGIC;
  signal pcie_block_i_n_927 : STD_LOGIC;
  signal pcie_block_i_n_928 : STD_LOGIC;
  signal pcie_block_i_n_929 : STD_LOGIC;
  signal pcie_block_i_n_93 : STD_LOGIC;
  signal pcie_block_i_n_930 : STD_LOGIC;
  signal pcie_block_i_n_931 : STD_LOGIC;
  signal pcie_block_i_n_932 : STD_LOGIC;
  signal pcie_block_i_n_933 : STD_LOGIC;
  signal pcie_block_i_n_934 : STD_LOGIC;
  signal pcie_block_i_n_935 : STD_LOGIC;
  signal pcie_block_i_n_936 : STD_LOGIC;
  signal pcie_block_i_n_937 : STD_LOGIC;
  signal pcie_block_i_n_938 : STD_LOGIC;
  signal pcie_block_i_n_939 : STD_LOGIC;
  signal pcie_block_i_n_94 : STD_LOGIC;
  signal pcie_block_i_n_940 : STD_LOGIC;
  signal pcie_block_i_n_941 : STD_LOGIC;
  signal pcie_block_i_n_942 : STD_LOGIC;
  signal pcie_block_i_n_943 : STD_LOGIC;
  signal pcie_block_i_n_944 : STD_LOGIC;
  signal pcie_block_i_n_945 : STD_LOGIC;
  signal pcie_block_i_n_946 : STD_LOGIC;
  signal pcie_block_i_n_947 : STD_LOGIC;
  signal pcie_block_i_n_948 : STD_LOGIC;
  signal pcie_block_i_n_949 : STD_LOGIC;
  signal pcie_block_i_n_95 : STD_LOGIC;
  signal pcie_block_i_n_950 : STD_LOGIC;
  signal pcie_block_i_n_951 : STD_LOGIC;
  signal pcie_block_i_n_952 : STD_LOGIC;
  signal pcie_block_i_n_953 : STD_LOGIC;
  signal pcie_block_i_n_954 : STD_LOGIC;
  signal pcie_block_i_n_955 : STD_LOGIC;
  signal pcie_block_i_n_956 : STD_LOGIC;
  signal pcie_block_i_n_957 : STD_LOGIC;
  signal pcie_block_i_n_958 : STD_LOGIC;
  signal pcie_block_i_n_959 : STD_LOGIC;
  signal pcie_block_i_n_96 : STD_LOGIC;
  signal pcie_block_i_n_97 : STD_LOGIC;
  signal pcie_block_i_n_98 : STD_LOGIC;
  signal pcie_block_i_n_99 : STD_LOGIC;
  signal pipe_rx2_polarity : STD_LOGIC;
  signal pipe_rx3_polarity : STD_LOGIC;
  signal pipe_rx4_polarity : STD_LOGIC;
  signal pipe_rx5_polarity : STD_LOGIC;
  signal pipe_rx6_polarity : STD_LOGIC;
  signal pipe_rx7_polarity : STD_LOGIC;
  signal pipe_tx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_compliance : STD_LOGIC;
  signal pipe_tx2_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx2_elec_idle : STD_LOGIC;
  signal pipe_tx2_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_compliance : STD_LOGIC;
  signal pipe_tx3_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx3_elec_idle : STD_LOGIC;
  signal pipe_tx3_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_compliance : STD_LOGIC;
  signal pipe_tx4_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx4_elec_idle : STD_LOGIC;
  signal pipe_tx4_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_compliance : STD_LOGIC;
  signal pipe_tx5_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx5_elec_idle : STD_LOGIC;
  signal pipe_tx5_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_compliance : STD_LOGIC;
  signal pipe_tx6_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx6_elec_idle : STD_LOGIC;
  signal pipe_tx6_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_compliance : STD_LOGIC;
  signal pipe_tx7_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx7_elec_idle : STD_LOGIC;
  signal pipe_tx7_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pl_phy_lnk_up_n : STD_LOGIC;
  signal trn_rd : STD_LOGIC_VECTOR ( 127 downto 64 );
  signal \^trn_reof\ : STD_LOGIC;
  signal trn_rrem : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^trn_rsof\ : STD_LOGIC;
  signal \^trn_rsrc_dsc\ : STD_LOGIC;
  signal trn_rsrc_rdy : STD_LOGIC;
  signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^trn_tcfg_req\ : STD_LOGIC;
  signal \^trn_tdst_rdy\ : STD_LOGIC;
  signal user_rst_n : STD_LOGIC;
  signal NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute box_type : string;
  attribute box_type of pcie_block_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of trn_rsrc_dsc_prev_i_1 : label is "soft_lutpair1954";
  attribute SOFT_HLUTNM of trn_rsrc_rdy_prev_i_1 : label is "soft_lutpair1954";
begin
  cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0);
  trn_reof <= \^trn_reof\;
  trn_rsof <= \^trn_rsof\;
  trn_rsrc_dsc <= \^trn_rsrc_dsc\;
  trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0);
  trn_tcfg_req <= \^trn_tcfg_req\;
  trn_tdst_rdy <= \^trn_tdst_rdy\;
\cfg_bus_number_d[7]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pcie_block_i_n_55,
      O => E(0)
    );
cfg_interrupt_rdy_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_rdy_n,
      O => cfg_interrupt_rdy
    );
cfg_mgmt_rd_wr_done_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_wr_done_n,
      O => cfg_mgmt_rd_wr_done
    );
lnk_up_thrtl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \^trn_tdst_rdy\,
      I1 => lnk_up_thrtl,
      I2 => \out\,
      O => lnk_up_thrtl_reg
    );
m_axis_rx_tvalid_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000027000000"
    )
        port map (
      I0 => \^trn_reof\,
      I1 => trn_rdst_rdy,
      I2 => \^trn_rsof\,
      I3 => \^trn_rsrc_dsc\,
      I4 => trn_in_packet,
      I5 => trn_rsrc_dsc_d,
      O => dsc_detect
    );
pcie_block_i: unisim.vcomponents.PCIE_2_1
    generic map(
      AER_BASE_PTR => X"000",
      AER_CAP_ECRC_CHECK_CAPABLE => "FALSE",
      AER_CAP_ECRC_GEN_CAPABLE => "FALSE",
      AER_CAP_ID => X"0001",
      AER_CAP_MULTIHEADER => "FALSE",
      AER_CAP_NEXTPTR => X"000",
      AER_CAP_ON => "FALSE",
      AER_CAP_OPTIONAL_ERR_SUPPORT => X"000000",
      AER_CAP_PERMIT_ROOTERR_UPDATE => "FALSE",
      AER_CAP_VERSION => X"1",
      ALLOW_X8_GEN2 => "FALSE",
      BAR0 => X"FFFF0000",
      BAR1 => X"FFF00000",
      BAR2 => X"00000000",
      BAR3 => X"00000000",
      BAR4 => X"00000000",
      BAR5 => X"00000000",
      CAPABILITIES_PTR => X"40",
      CARDBUS_CIS_POINTER => X"00000000",
      CFG_ECRC_ERR_CPLSTAT => 0,
      CLASS_CODE => X"070001",
      CMD_INTX_IMPLEMENTED => "TRUE",
      CPL_TIMEOUT_DISABLE_SUPPORTED => "FALSE",
      CPL_TIMEOUT_RANGES_SUPPORTED => X"2",
      CRM_MODULE_RSTS => X"00",
      DEV_CAP2_ARI_FORWARDING_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => "FALSE",
      DEV_CAP2_CAS128_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => "FALSE",
      DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => "FALSE",
      DEV_CAP2_LTR_MECHANISM_SUPPORTED => "FALSE",
      DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => X"0",
      DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => "FALSE",
      DEV_CAP2_TPH_COMPLETER_SUPPORTED => X"0",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => "TRUE",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => "TRUE",
      DEV_CAP_ENDPOINT_L0S_LATENCY => 0,
      DEV_CAP_ENDPOINT_L1_LATENCY => 7,
      DEV_CAP_EXT_TAG_SUPPORTED => "TRUE",
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => "FALSE",
      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => 0,
      DEV_CAP_ROLE_BASED_ERROR => "TRUE",
      DEV_CAP_RSVD_14_12 => 0,
      DEV_CAP_RSVD_17_16 => 0,
      DEV_CAP_RSVD_31_29 => 0,
      DEV_CONTROL_AUX_POWER_SUPPORTED => "FALSE",
      DEV_CONTROL_EXT_TAG_DEFAULT => "FALSE",
      DISABLE_ASPM_L1_TIMER => "FALSE",
      DISABLE_BAR_FILTERING => "FALSE",
      DISABLE_ERR_MSG => "FALSE",
      DISABLE_ID_CHECK => "FALSE",
      DISABLE_LANE_REVERSAL => "TRUE",
      DISABLE_LOCKED_FILTER => "FALSE",
      DISABLE_PPM_FILTER => "FALSE",
      DISABLE_RX_POISONED_RESP => "FALSE",
      DISABLE_RX_TC_FILTER => "FALSE",
      DISABLE_SCRAMBLING => "FALSE",
      DNSTREAM_LINK_NUM => X"00",
      DSN_BASE_PTR => X"100",
      DSN_CAP_ID => X"0003",
      DSN_CAP_NEXTPTR => X"000",
      DSN_CAP_ON => "TRUE",
      DSN_CAP_VERSION => X"1",
      ENABLE_MSG_ROUTE => X"000",
      ENABLE_RX_TD_ECRC_TRIM => "FALSE",
      ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => "FALSE",
      ENTER_RVRY_EI_L0 => "TRUE",
      EXIT_LOOPBACK_ON_EI => "TRUE",
      EXPANSION_ROM => X"00000000",
      EXT_CFG_CAP_PTR => X"3F",
      EXT_CFG_XP_CAP_PTR => X"3FF",
      HEADER_TYPE => X"00",
      INFER_EI => X"00",
      INTERRUPT_PIN => X"01",
      INTERRUPT_STAT_AUTO => "TRUE",
      IS_SWITCH => "FALSE",
      LAST_CONFIG_DWORD => X"3FF",
      LINK_CAP_ASPM_OPTIONALITY => "FALSE",
      LINK_CAP_ASPM_SUPPORT => 1,
      LINK_CAP_CLOCK_POWER_MANAGEMENT => "FALSE",
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => "FALSE",
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => "FALSE",
      LINK_CAP_MAX_LINK_SPEED => X"2",
      LINK_CAP_MAX_LINK_WIDTH => X"02",
      LINK_CAP_RSVD_23 => 0,
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => "FALSE",
      LINK_CONTROL_RCB => 0,
      LINK_CTRL2_DEEMPHASIS => "FALSE",
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => "FALSE",
      LINK_CTRL2_TARGET_LINK_SPEED => X"2",
      LINK_STATUS_SLOT_CLOCK_CONFIG => "TRUE",
      LL_ACK_TIMEOUT => X"0000",
      LL_ACK_TIMEOUT_EN => "FALSE",
      LL_ACK_TIMEOUT_FUNC => 0,
      LL_REPLAY_TIMEOUT => X"0000",
      LL_REPLAY_TIMEOUT_EN => "FALSE",
      LL_REPLAY_TIMEOUT_FUNC => 1,
      LTSSM_MAX_LINK_WIDTH => X"02",
      MPS_FORCE => "FALSE",
      MSIX_BASE_PTR => X"9C",
      MSIX_CAP_ID => X"11",
      MSIX_CAP_NEXTPTR => X"00",
      MSIX_CAP_ON => "FALSE",
      MSIX_CAP_PBA_BIR => 0,
      MSIX_CAP_PBA_OFFSET => X"00000000",
      MSIX_CAP_TABLE_BIR => 0,
      MSIX_CAP_TABLE_OFFSET => X"00000000",
      MSIX_CAP_TABLE_SIZE => X"000",
      MSI_BASE_PTR => X"48",
      MSI_CAP_64_BIT_ADDR_CAPABLE => "TRUE",
      MSI_CAP_ID => X"05",
      MSI_CAP_MULTIMSGCAP => 0,
      MSI_CAP_MULTIMSG_EXTENSION => 0,
      MSI_CAP_NEXTPTR => X"60",
      MSI_CAP_ON => "TRUE",
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE => "FALSE",
      N_FTS_COMCLK_GEN1 => 255,
      N_FTS_COMCLK_GEN2 => 255,
      N_FTS_GEN1 => 255,
      N_FTS_GEN2 => 255,
      PCIE_BASE_PTR => X"60",
      PCIE_CAP_CAPABILITY_ID => X"10",
      PCIE_CAP_CAPABILITY_VERSION => X"2",
      PCIE_CAP_DEVICE_PORT_TYPE => X"0",
      PCIE_CAP_NEXTPTR => X"00",
      PCIE_CAP_ON => "TRUE",
      PCIE_CAP_RSVD_15_14 => 0,
      PCIE_CAP_SLOT_IMPLEMENTED => "FALSE",
      PCIE_REVISION => 2,
      PL_AUTO_CONFIG => 0,
      PL_FAST_TRAIN => "TRUE",
      PM_ASPML0S_TIMEOUT => X"0000",
      PM_ASPML0S_TIMEOUT_EN => "FALSE",
      PM_ASPML0S_TIMEOUT_FUNC => 0,
      PM_ASPM_FASTEXIT => "FALSE",
      PM_BASE_PTR => X"40",
      PM_CAP_AUXCURRENT => 0,
      PM_CAP_D1SUPPORT => "FALSE",
      PM_CAP_D2SUPPORT => "FALSE",
      PM_CAP_DSI => "FALSE",
      PM_CAP_ID => X"01",
      PM_CAP_NEXTPTR => X"48",
      PM_CAP_ON => "TRUE",
      PM_CAP_PMESUPPORT => X"0F",
      PM_CAP_PME_CLOCK => "FALSE",
      PM_CAP_RSVD_04 => 0,
      PM_CAP_VERSION => 3,
      PM_CSR_B2B3 => "FALSE",
      PM_CSR_BPCCEN => "FALSE",
      PM_CSR_NOSOFTRST => "TRUE",
      PM_DATA0 => X"00",
      PM_DATA1 => X"00",
      PM_DATA2 => X"00",
      PM_DATA3 => X"00",
      PM_DATA4 => X"00",
      PM_DATA5 => X"00",
      PM_DATA6 => X"00",
      PM_DATA7 => X"00",
      PM_DATA_SCALE0 => X"0",
      PM_DATA_SCALE1 => X"0",
      PM_DATA_SCALE2 => X"0",
      PM_DATA_SCALE3 => X"0",
      PM_DATA_SCALE4 => X"0",
      PM_DATA_SCALE5 => X"0",
      PM_DATA_SCALE6 => X"0",
      PM_DATA_SCALE7 => X"0",
      PM_MF => "FALSE",
      RBAR_BASE_PTR => X"000",
      RBAR_CAP_CONTROL_ENCODEDBAR0 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR1 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR2 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR3 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR4 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR5 => X"00",
      RBAR_CAP_ID => X"0015",
      RBAR_CAP_INDEX0 => X"0",
      RBAR_CAP_INDEX1 => X"0",
      RBAR_CAP_INDEX2 => X"0",
      RBAR_CAP_INDEX3 => X"0",
      RBAR_CAP_INDEX4 => X"0",
      RBAR_CAP_INDEX5 => X"0",
      RBAR_CAP_NEXTPTR => X"000",
      RBAR_CAP_ON => "FALSE",
      RBAR_CAP_SUP0 => X"00000001",
      RBAR_CAP_SUP1 => X"00000001",
      RBAR_CAP_SUP2 => X"00000001",
      RBAR_CAP_SUP3 => X"00000001",
      RBAR_CAP_SUP4 => X"00000001",
      RBAR_CAP_SUP5 => X"00000001",
      RBAR_CAP_VERSION => X"1",
      RBAR_NUM => X"0",
      RECRC_CHK => 0,
      RECRC_CHK_TRIM => "FALSE",
      ROOT_CAP_CRS_SW_VISIBILITY => "FALSE",
      RP_AUTO_SPD => X"1",
      RP_AUTO_SPD_LOOPCNT => X"1F",
      SELECT_DLL_IF => "FALSE",
      SIM_VERSION => "1.0",
      SLOT_CAP_ATT_BUTTON_PRESENT => "FALSE",
      SLOT_CAP_ATT_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_ELEC_INTERLOCK_PRESENT => "FALSE",
      SLOT_CAP_HOTPLUG_CAPABLE => "FALSE",
      SLOT_CAP_HOTPLUG_SURPRISE => "FALSE",
      SLOT_CAP_MRL_SENSOR_PRESENT => "FALSE",
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => "FALSE",
      SLOT_CAP_PHYSICAL_SLOT_NUM => X"0000",
      SLOT_CAP_POWER_CONTROLLER_PRESENT => "FALSE",
      SLOT_CAP_POWER_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE => 0,
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE => X"00",
      SPARE_BIT0 => 0,
      SPARE_BIT1 => 0,
      SPARE_BIT2 => 0,
      SPARE_BIT3 => 0,
      SPARE_BIT4 => 0,
      SPARE_BIT5 => 0,
      SPARE_BIT6 => 0,
      SPARE_BIT7 => 0,
      SPARE_BIT8 => 0,
      SPARE_BYTE0 => X"00",
      SPARE_BYTE1 => X"00",
      SPARE_BYTE2 => X"00",
      SPARE_BYTE3 => X"00",
      SPARE_WORD0 => X"00000000",
      SPARE_WORD1 => X"00000000",
      SPARE_WORD2 => X"00000000",
      SPARE_WORD3 => X"00000000",
      SSL_MESSAGE_AUTO => "FALSE",
      TECRC_EP_INV => "FALSE",
      TL_RBYPASS => "FALSE",
      TL_RX_RAM_RADDR_LATENCY => 0,
      TL_RX_RAM_RDATA_LATENCY => 2,
      TL_RX_RAM_WRITE_LATENCY => 0,
      TL_TFC_DISABLE => "FALSE",
      TL_TX_CHECKS_DISABLE => "FALSE",
      TL_TX_RAM_RADDR_LATENCY => 0,
      TL_TX_RAM_RDATA_LATENCY => 2,
      TL_TX_RAM_WRITE_LATENCY => 0,
      TRN_DW => "FALSE",
      TRN_NP_FC => "TRUE",
      UPCONFIG_CAPABLE => "TRUE",
      UPSTREAM_FACING => "TRUE",
      UR_ATOMIC => "FALSE",
      UR_CFG1 => "TRUE",
      UR_INV_REQ => "TRUE",
      UR_PRS_RESPONSE => "TRUE",
      USER_CLK2_DIV2 => "FALSE",
      USER_CLK_FREQ => 2,
      USE_RID_PINS => "FALSE",
      VC0_CPL_INFINITE => "TRUE",
      VC0_RX_RAM_LIMIT => X"07FF",
      VC0_TOTAL_CREDITS_CD => 461,
      VC0_TOTAL_CREDITS_CH => 36,
      VC0_TOTAL_CREDITS_NPD => 24,
      VC0_TOTAL_CREDITS_NPH => 12,
      VC0_TOTAL_CREDITS_PD => 437,
      VC0_TOTAL_CREDITS_PH => 32,
      VC0_TX_LASTPACKET => 29,
      VC_BASE_PTR => X"000",
      VC_CAP_ID => X"0002",
      VC_CAP_NEXTPTR => X"000",
      VC_CAP_ON => "FALSE",
      VC_CAP_REJECT_SNOOP_TRANSACTIONS => "FALSE",
      VC_CAP_VERSION => X"1",
      VSEC_BASE_PTR => X"000",
      VSEC_CAP_HDR_ID => X"1234",
      VSEC_CAP_HDR_LENGTH => X"018",
      VSEC_CAP_HDR_REVISION => X"1",
      VSEC_CAP_ID => X"000B",
      VSEC_CAP_IS_LINK_VISIBLE => "TRUE",
      VSEC_CAP_NEXTPTR => X"000",
      VSEC_CAP_ON => "FALSE",
      VSEC_CAP_VERSION => X"1"
    )
        port map (
      CFGAERECRCCHECKEN => pcie_block_i_n_0,
      CFGAERECRCGENEN => pcie_block_i_n_1,
      CFGAERINTERRUPTMSGNUM(4 downto 0) => B"00000",
      CFGAERROOTERRCORRERRRECEIVED => pcie_block_i_n_2,
      CFGAERROOTERRCORRERRREPORTINGEN => pcie_block_i_n_3,
      CFGAERROOTERRFATALERRRECEIVED => pcie_block_i_n_4,
      CFGAERROOTERRFATALERRREPORTINGEN => pcie_block_i_n_5,
      CFGAERROOTERRNONFATALERRRECEIVED => pcie_block_i_n_6,
      CFGAERROOTERRNONFATALERRREPORTINGEN => pcie_block_i_n_7,
      CFGBRIDGESERREN => pcie_block_i_n_8,
      CFGCOMMANDBUSMASTERENABLE => cfg_command(0),
      CFGCOMMANDINTERRUPTDISABLE => pcie_block_i_n_10,
      CFGCOMMANDIOENABLE => pcie_block_i_n_11,
      CFGCOMMANDMEMENABLE => pcie_block_i_n_12,
      CFGCOMMANDSERREN => pcie_block_i_n_13,
      CFGDEVCONTROL2ARIFORWARDEN => pcie_block_i_n_14,
      CFGDEVCONTROL2ATOMICEGRESSBLOCK => pcie_block_i_n_15,
      CFGDEVCONTROL2ATOMICREQUESTEREN => pcie_block_i_n_16,
      CFGDEVCONTROL2CPLTIMEOUTDIS => pcie_block_i_n_17,
      CFGDEVCONTROL2CPLTIMEOUTVAL(3) => pcie_block_i_n_675,
      CFGDEVCONTROL2CPLTIMEOUTVAL(2) => pcie_block_i_n_676,
      CFGDEVCONTROL2CPLTIMEOUTVAL(1) => pcie_block_i_n_677,
      CFGDEVCONTROL2CPLTIMEOUTVAL(0) => pcie_block_i_n_678,
      CFGDEVCONTROL2IDOCPLEN => pcie_block_i_n_18,
      CFGDEVCONTROL2IDOREQEN => pcie_block_i_n_19,
      CFGDEVCONTROL2LTREN => pcie_block_i_n_20,
      CFGDEVCONTROL2TLPPREFIXBLOCK => pcie_block_i_n_21,
      CFGDEVCONTROLAUXPOWEREN => pcie_block_i_n_22,
      CFGDEVCONTROLCORRERRREPORTINGEN => pcie_block_i_n_23,
      CFGDEVCONTROLENABLERO => pcie_block_i_n_24,
      CFGDEVCONTROLEXTTAGEN => pcie_block_i_n_25,
      CFGDEVCONTROLFATALERRREPORTINGEN => pcie_block_i_n_26,
      CFGDEVCONTROLMAXPAYLOAD(2 downto 0) => cfg_dcommand(2 downto 0),
      CFGDEVCONTROLMAXREADREQ(2 downto 0) => cfg_dcommand(5 downto 3),
      CFGDEVCONTROLNONFATALREPORTINGEN => pcie_block_i_n_27,
      CFGDEVCONTROLNOSNOOPEN => pcie_block_i_n_28,
      CFGDEVCONTROLPHANTOMEN => pcie_block_i_n_29,
      CFGDEVCONTROLURERRREPORTINGEN => pcie_block_i_n_30,
      CFGDEVID(15 downto 0) => B"0111000000100010",
      CFGDEVSTATUSCORRERRDETECTED => pcie_block_i_n_31,
      CFGDEVSTATUSFATALERRDETECTED => pcie_block_i_n_32,
      CFGDEVSTATUSNONFATALERRDETECTED => pcie_block_i_n_33,
      CFGDEVSTATUSURDETECTED => pcie_block_i_n_34,
      CFGDSBUSNUMBER(7 downto 0) => B"00000000",
      CFGDSDEVICENUMBER(4 downto 0) => B"00000",
      CFGDSFUNCTIONNUMBER(2 downto 0) => B"000",
      CFGDSN(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      CFGERRACSN => '1',
      CFGERRAERHEADERLOG(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      CFGERRAERHEADERLOGSETN => cfg_err_aer_headerlog_set_n,
      CFGERRATOMICEGRESSBLOCKEDN => '1',
      CFGERRCORN => '1',
      CFGERRCPLABORTN => '1',
      CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
      CFGERRCPLTIMEOUTN => '1',
      CFGERRCPLUNEXPECTN => '1',
      CFGERRECRCN => '1',
      CFGERRINTERNALCORN => '1',
      CFGERRINTERNALUNCORN => '1',
      CFGERRLOCKEDN => '1',
      CFGERRMALFORMEDN => '1',
      CFGERRMCBLOCKEDN => '1',
      CFGERRNORECOVERYN => '1',
      CFGERRPOISONEDN => '1',
      CFGERRPOSTEDN => '1',
      CFGERRTLPCPLHEADER(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      CFGERRURN => '1',
      CFGFORCECOMMONCLOCKOFF => '0',
      CFGFORCEEXTENDEDSYNCON => '0',
      CFGFORCEMPS(2 downto 0) => B"000",
      CFGINTERRUPTASSERTN => pcie_block_i_i_1_n_0,
      CFGINTERRUPTDI(7 downto 5) => B"000",
      CFGINTERRUPTDI(4 downto 0) => cfg_interrupt_di(4 downto 0),
      CFGINTERRUPTDO(7) => pcie_block_i_n_1111,
      CFGINTERRUPTDO(6) => pcie_block_i_n_1112,
      CFGINTERRUPTDO(5) => pcie_block_i_n_1113,
      CFGINTERRUPTDO(4) => pcie_block_i_n_1114,
      CFGINTERRUPTDO(3) => pcie_block_i_n_1115,
      CFGINTERRUPTDO(2) => pcie_block_i_n_1116,
      CFGINTERRUPTDO(1) => pcie_block_i_n_1117,
      CFGINTERRUPTDO(0) => pcie_block_i_n_1118,
      CFGINTERRUPTMMENABLE(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
      CFGINTERRUPTMSIXENABLE => pcie_block_i_n_38,
      CFGINTERRUPTMSIXFM => pcie_block_i_n_39,
      CFGINTERRUPTN => pcie_block_i_i_2_n_0,
      CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
      CFGINTERRUPTSTATN => '1',
      CFGLINKCONTROLASPMCONTROL(1) => pcie_block_i_n_572,
      CFGLINKCONTROLASPMCONTROL(0) => pcie_block_i_n_573,
      CFGLINKCONTROLAUTOBANDWIDTHINTEN => pcie_block_i_n_41,
      CFGLINKCONTROLBANDWIDTHINTEN => pcie_block_i_n_42,
      CFGLINKCONTROLCLOCKPMEN => pcie_block_i_n_43,
      CFGLINKCONTROLCOMMONCLOCK => pcie_block_i_n_44,
      CFGLINKCONTROLEXTENDEDSYNC => pcie_block_i_n_45,
      CFGLINKCONTROLHWAUTOWIDTHDIS => pcie_block_i_n_46,
      CFGLINKCONTROLLINKDISABLE => pcie_block_i_n_47,
      CFGLINKCONTROLRCB => pcie_block_i_n_48,
      CFGLINKCONTROLRETRAINLINK => pcie_block_i_n_49,
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS => pcie_block_i_n_50,
      CFGLINKSTATUSBANDWIDTHSTATUS => pcie_block_i_n_51,
      CFGLINKSTATUSCURRENTSPEED(1) => pcie_block_i_n_574,
      CFGLINKSTATUSCURRENTSPEED(0) => pcie_block_i_n_575,
      CFGLINKSTATUSDLLACTIVE => pcie_block_i_n_52,
      CFGLINKSTATUSLINKTRAINING => pcie_block_i_n_53,
      CFGLINKSTATUSNEGOTIATEDWIDTH(3) => pcie_block_i_n_679,
      CFGLINKSTATUSNEGOTIATEDWIDTH(2) => pcie_block_i_n_680,
      CFGLINKSTATUSNEGOTIATEDWIDTH(1) => pcie_block_i_n_681,
      CFGLINKSTATUSNEGOTIATEDWIDTH(0) => pcie_block_i_n_682,
      CFGMGMTBYTEENN(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      CFGMGMTDI(31 downto 0) => cfg_mgmt_di(31 downto 0),
      CFGMGMTDO(31 downto 0) => cfg_mgmt_do(31 downto 0),
      CFGMGMTDWADDR(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      CFGMGMTRDENN => pcie_block_i_i_3_n_0,
      CFGMGMTRDWRDONEN => cfg_mgmt_rd_wr_done_n,
      CFGMGMTWRENN => pcie_block_i_i_4_n_0,
      CFGMGMTWRREADONLYN => pcie_block_i_i_5_n_0,
      CFGMGMTWRRW1CASRWN => '1',
      CFGMSGDATA(15 downto 0) => cfg_msg_data(15 downto 0),
      CFGMSGRECEIVED => pcie_block_i_n_55,
      CFGMSGRECEIVEDASSERTINTA => pcie_block_i_n_56,
      CFGMSGRECEIVEDASSERTINTB => pcie_block_i_n_57,
      CFGMSGRECEIVEDASSERTINTC => pcie_block_i_n_58,
      CFGMSGRECEIVEDASSERTINTD => pcie_block_i_n_59,
      CFGMSGRECEIVEDDEASSERTINTA => pcie_block_i_n_60,
      CFGMSGRECEIVEDDEASSERTINTB => pcie_block_i_n_61,
      CFGMSGRECEIVEDDEASSERTINTC => pcie_block_i_n_62,
      CFGMSGRECEIVEDDEASSERTINTD => pcie_block_i_n_63,
      CFGMSGRECEIVEDERRCOR => pcie_block_i_n_64,
      CFGMSGRECEIVEDERRFATAL => pcie_block_i_n_65,
      CFGMSGRECEIVEDERRNONFATAL => pcie_block_i_n_66,
      CFGMSGRECEIVEDPMASNAK => pcie_block_i_n_67,
      CFGMSGRECEIVEDPMETO => cfg_to_turnoff,
      CFGMSGRECEIVEDPMETOACK => pcie_block_i_n_69,
      CFGMSGRECEIVEDPMPME => pcie_block_i_n_70,
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT => pcie_block_i_n_71,
      CFGMSGRECEIVEDUNLOCK => pcie_block_i_n_72,
      CFGPCIECAPINTERRUPTMSGNUM(4 downto 0) => B"00000",
      CFGPCIELINKSTATE(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      CFGPMCSRPMEEN => pcie_block_i_n_73,
      CFGPMCSRPMESTATUS => pcie_block_i_n_74,
      CFGPMCSRPOWERSTATE(1) => pcie_block_i_n_576,
      CFGPMCSRPOWERSTATE(0) => pcie_block_i_n_577,
      CFGPMFORCESTATE(1 downto 0) => B"00",
      CFGPMFORCESTATEENN => '1',
      CFGPMHALTASPML0SN => '1',
      CFGPMHALTASPML1N => '1',
      CFGPMRCVASREQL1N => pcie_block_i_n_75,
      CFGPMRCVENTERL1N => pcie_block_i_n_76,
      CFGPMRCVENTERL23N => pcie_block_i_n_77,
      CFGPMRCVREQACKN => pcie_block_i_n_78,
      CFGPMSENDPMETON => '1',
      CFGPMTURNOFFOKN => '0',
      CFGPMWAKEN => '1',
      CFGPORTNUMBER(7 downto 0) => B"00000000",
      CFGREVID(7 downto 0) => B"00000000",
      CFGROOTCONTROLPMEINTEN => pcie_block_i_n_79,
      CFGROOTCONTROLSYSERRCORRERREN => pcie_block_i_n_80,
      CFGROOTCONTROLSYSERRFATALERREN => pcie_block_i_n_81,
      CFGROOTCONTROLSYSERRNONFATALERREN => pcie_block_i_n_82,
      CFGSLOTCONTROLELECTROMECHILCTLPULSE => pcie_block_i_n_83,
      CFGSUBSYSID(15 downto 0) => B"0000000000000111",
      CFGSUBSYSVENDID(15 downto 0) => B"0001000011101110",
      CFGTRANSACTION => pcie_block_i_n_84,
      CFGTRANSACTIONADDR(6) => pcie_block_i_n_1097,
      CFGTRANSACTIONADDR(5) => pcie_block_i_n_1098,
      CFGTRANSACTIONADDR(4) => pcie_block_i_n_1099,
      CFGTRANSACTIONADDR(3) => pcie_block_i_n_1100,
      CFGTRANSACTIONADDR(2) => pcie_block_i_n_1101,
      CFGTRANSACTIONADDR(1) => pcie_block_i_n_1102,
      CFGTRANSACTIONADDR(0) => pcie_block_i_n_1103,
      CFGTRANSACTIONTYPE => pcie_block_i_n_85,
      CFGTRNPENDINGN => '1',
      CFGVCTCVCMAP(6) => pcie_block_i_n_1104,
      CFGVCTCVCMAP(5) => pcie_block_i_n_1105,
      CFGVCTCVCMAP(4) => pcie_block_i_n_1106,
      CFGVCTCVCMAP(3) => pcie_block_i_n_1107,
      CFGVCTCVCMAP(2) => pcie_block_i_n_1108,
      CFGVCTCVCMAP(1) => pcie_block_i_n_1109,
      CFGVCTCVCMAP(0) => pcie_block_i_n_1110,
      CFGVENDID(15 downto 0) => B"0001000011101110",
      CMRSTN => '1',
      CMSTICKYRSTN => '1',
      DBGMODE(1 downto 0) => B"00",
      DBGSCLRA => pcie_block_i_n_86,
      DBGSCLRB => pcie_block_i_n_87,
      DBGSCLRC => pcie_block_i_n_88,
      DBGSCLRD => pcie_block_i_n_89,
      DBGSCLRE => pcie_block_i_n_90,
      DBGSCLRF => pcie_block_i_n_91,
      DBGSCLRG => pcie_block_i_n_92,
      DBGSCLRH => pcie_block_i_n_93,
      DBGSCLRI => pcie_block_i_n_94,
      DBGSCLRJ => pcie_block_i_n_95,
      DBGSCLRK => pcie_block_i_n_96,
      DBGSUBMODE => '0',
      DBGVECA(63) => pcie_block_i_n_704,
      DBGVECA(62) => pcie_block_i_n_705,
      DBGVECA(61) => pcie_block_i_n_706,
      DBGVECA(60) => pcie_block_i_n_707,
      DBGVECA(59) => pcie_block_i_n_708,
      DBGVECA(58) => pcie_block_i_n_709,
      DBGVECA(57) => pcie_block_i_n_710,
      DBGVECA(56) => pcie_block_i_n_711,
      DBGVECA(55) => pcie_block_i_n_712,
      DBGVECA(54) => pcie_block_i_n_713,
      DBGVECA(53) => pcie_block_i_n_714,
      DBGVECA(52) => pcie_block_i_n_715,
      DBGVECA(51) => pcie_block_i_n_716,
      DBGVECA(50) => pcie_block_i_n_717,
      DBGVECA(49) => pcie_block_i_n_718,
      DBGVECA(48) => pcie_block_i_n_719,
      DBGVECA(47) => pcie_block_i_n_720,
      DBGVECA(46) => pcie_block_i_n_721,
      DBGVECA(45) => pcie_block_i_n_722,
      DBGVECA(44) => pcie_block_i_n_723,
      DBGVECA(43) => pcie_block_i_n_724,
      DBGVECA(42) => pcie_block_i_n_725,
      DBGVECA(41) => pcie_block_i_n_726,
      DBGVECA(40) => pcie_block_i_n_727,
      DBGVECA(39) => pcie_block_i_n_728,
      DBGVECA(38) => pcie_block_i_n_729,
      DBGVECA(37) => pcie_block_i_n_730,
      DBGVECA(36) => pcie_block_i_n_731,
      DBGVECA(35) => pcie_block_i_n_732,
      DBGVECA(34) => pcie_block_i_n_733,
      DBGVECA(33) => pcie_block_i_n_734,
      DBGVECA(32) => pcie_block_i_n_735,
      DBGVECA(31) => pcie_block_i_n_736,
      DBGVECA(30) => pcie_block_i_n_737,
      DBGVECA(29) => pcie_block_i_n_738,
      DBGVECA(28) => pcie_block_i_n_739,
      DBGVECA(27) => pcie_block_i_n_740,
      DBGVECA(26) => pcie_block_i_n_741,
      DBGVECA(25) => pcie_block_i_n_742,
      DBGVECA(24) => pcie_block_i_n_743,
      DBGVECA(23) => pcie_block_i_n_744,
      DBGVECA(22) => pcie_block_i_n_745,
      DBGVECA(21) => pcie_block_i_n_746,
      DBGVECA(20) => pcie_block_i_n_747,
      DBGVECA(19) => pcie_block_i_n_748,
      DBGVECA(18) => pcie_block_i_n_749,
      DBGVECA(17) => pcie_block_i_n_750,
      DBGVECA(16) => pcie_block_i_n_751,
      DBGVECA(15) => pcie_block_i_n_752,
      DBGVECA(14) => pcie_block_i_n_753,
      DBGVECA(13) => pcie_block_i_n_754,
      DBGVECA(12) => pcie_block_i_n_755,
      DBGVECA(11) => pcie_block_i_n_756,
      DBGVECA(10) => pcie_block_i_n_757,
      DBGVECA(9) => pcie_block_i_n_758,
      DBGVECA(8) => pcie_block_i_n_759,
      DBGVECA(7) => pcie_block_i_n_760,
      DBGVECA(6) => pcie_block_i_n_761,
      DBGVECA(5) => pcie_block_i_n_762,
      DBGVECA(4) => pcie_block_i_n_763,
      DBGVECA(3) => pcie_block_i_n_764,
      DBGVECA(2) => pcie_block_i_n_765,
      DBGVECA(1) => pcie_block_i_n_766,
      DBGVECA(0) => pcie_block_i_n_767,
      DBGVECB(63) => pcie_block_i_n_768,
      DBGVECB(62) => pcie_block_i_n_769,
      DBGVECB(61) => pcie_block_i_n_770,
      DBGVECB(60) => pcie_block_i_n_771,
      DBGVECB(59) => pcie_block_i_n_772,
      DBGVECB(58) => pcie_block_i_n_773,
      DBGVECB(57) => pcie_block_i_n_774,
      DBGVECB(56) => pcie_block_i_n_775,
      DBGVECB(55) => pcie_block_i_n_776,
      DBGVECB(54) => pcie_block_i_n_777,
      DBGVECB(53) => pcie_block_i_n_778,
      DBGVECB(52) => pcie_block_i_n_779,
      DBGVECB(51) => pcie_block_i_n_780,
      DBGVECB(50) => pcie_block_i_n_781,
      DBGVECB(49) => pcie_block_i_n_782,
      DBGVECB(48) => pcie_block_i_n_783,
      DBGVECB(47) => pcie_block_i_n_784,
      DBGVECB(46) => pcie_block_i_n_785,
      DBGVECB(45) => pcie_block_i_n_786,
      DBGVECB(44) => pcie_block_i_n_787,
      DBGVECB(43) => pcie_block_i_n_788,
      DBGVECB(42) => pcie_block_i_n_789,
      DBGVECB(41) => pcie_block_i_n_790,
      DBGVECB(40) => pcie_block_i_n_791,
      DBGVECB(39) => pcie_block_i_n_792,
      DBGVECB(38) => pcie_block_i_n_793,
      DBGVECB(37) => pcie_block_i_n_794,
      DBGVECB(36) => pcie_block_i_n_795,
      DBGVECB(35) => pcie_block_i_n_796,
      DBGVECB(34) => pcie_block_i_n_797,
      DBGVECB(33) => pcie_block_i_n_798,
      DBGVECB(32) => pcie_block_i_n_799,
      DBGVECB(31) => pcie_block_i_n_800,
      DBGVECB(30) => pcie_block_i_n_801,
      DBGVECB(29) => pcie_block_i_n_802,
      DBGVECB(28) => pcie_block_i_n_803,
      DBGVECB(27) => pcie_block_i_n_804,
      DBGVECB(26) => pcie_block_i_n_805,
      DBGVECB(25) => pcie_block_i_n_806,
      DBGVECB(24) => pcie_block_i_n_807,
      DBGVECB(23) => pcie_block_i_n_808,
      DBGVECB(22) => pcie_block_i_n_809,
      DBGVECB(21) => pcie_block_i_n_810,
      DBGVECB(20) => pcie_block_i_n_811,
      DBGVECB(19) => pcie_block_i_n_812,
      DBGVECB(18) => pcie_block_i_n_813,
      DBGVECB(17) => pcie_block_i_n_814,
      DBGVECB(16) => pcie_block_i_n_815,
      DBGVECB(15) => pcie_block_i_n_816,
      DBGVECB(14) => pcie_block_i_n_817,
      DBGVECB(13) => pcie_block_i_n_818,
      DBGVECB(12) => pcie_block_i_n_819,
      DBGVECB(11) => pcie_block_i_n_820,
      DBGVECB(10) => pcie_block_i_n_821,
      DBGVECB(9) => pcie_block_i_n_822,
      DBGVECB(8) => pcie_block_i_n_823,
      DBGVECB(7) => pcie_block_i_n_824,
      DBGVECB(6) => pcie_block_i_n_825,
      DBGVECB(5) => pcie_block_i_n_826,
      DBGVECB(4) => pcie_block_i_n_827,
      DBGVECB(3) => pcie_block_i_n_828,
      DBGVECB(2) => pcie_block_i_n_829,
      DBGVECB(1) => pcie_block_i_n_830,
      DBGVECB(0) => pcie_block_i_n_831,
      DBGVECC(11) => pcie_block_i_n_172,
      DBGVECC(10) => pcie_block_i_n_173,
      DBGVECC(9) => pcie_block_i_n_174,
      DBGVECC(8) => pcie_block_i_n_175,
      DBGVECC(7) => pcie_block_i_n_176,
      DBGVECC(6) => pcie_block_i_n_177,
      DBGVECC(5) => pcie_block_i_n_178,
      DBGVECC(4) => pcie_block_i_n_179,
      DBGVECC(3) => pcie_block_i_n_180,
      DBGVECC(2) => pcie_block_i_n_181,
      DBGVECC(1) => pcie_block_i_n_182,
      DBGVECC(0) => pcie_block_i_n_183,
      DLRSTN => '1',
      DRPADDR(8 downto 0) => B"000000000",
      DRPCLK => '1',
      DRPDI(15 downto 0) => B"0000000000000000",
      DRPDO(15) => pcie_block_i_n_428,
      DRPDO(14) => pcie_block_i_n_429,
      DRPDO(13) => pcie_block_i_n_430,
      DRPDO(12) => pcie_block_i_n_431,
      DRPDO(11) => pcie_block_i_n_432,
      DRPDO(10) => pcie_block_i_n_433,
      DRPDO(9) => pcie_block_i_n_434,
      DRPDO(8) => pcie_block_i_n_435,
      DRPDO(7) => pcie_block_i_n_436,
      DRPDO(6) => pcie_block_i_n_437,
      DRPDO(5) => pcie_block_i_n_438,
      DRPDO(4) => pcie_block_i_n_439,
      DRPDO(3) => pcie_block_i_n_440,
      DRPDO(2) => pcie_block_i_n_441,
      DRPDO(1) => pcie_block_i_n_442,
      DRPDO(0) => pcie_block_i_n_443,
      DRPEN => '0',
      DRPRDY => pcie_block_i_n_97,
      DRPWE => '0',
      FUNCLVLRSTN => '1',
      LL2BADDLLPERR => pcie_block_i_n_98,
      LL2BADTLPERR => pcie_block_i_n_99,
      LL2LINKSTATUS(4) => pcie_block_i_n_687,
      LL2LINKSTATUS(3) => pcie_block_i_n_688,
      LL2LINKSTATUS(2) => pcie_block_i_n_689,
      LL2LINKSTATUS(1) => pcie_block_i_n_690,
      LL2LINKSTATUS(0) => pcie_block_i_n_691,
      LL2PROTOCOLERR => pcie_block_i_n_100,
      LL2RECEIVERERR => pcie_block_i_n_101,
      LL2REPLAYROERR => pcie_block_i_n_102,
      LL2REPLAYTOERR => pcie_block_i_n_103,
      LL2SENDASREQL1 => '0',
      LL2SENDENTERL1 => '0',
      LL2SENDENTERL23 => '0',
      LL2SENDPMACK => '0',
      LL2SUSPENDNOW => '0',
      LL2SUSPENDOK => pcie_block_i_n_104,
      LL2TFCINIT1SEQ => pcie_block_i_n_105,
      LL2TFCINIT2SEQ => pcie_block_i_n_106,
      LL2TLPRCV => '0',
      LL2TXIDLE => pcie_block_i_n_107,
      LNKCLKEN => pcie_block_i_n_108,
      MIMRXRADDR(12 downto 0) => mim_rx_raddr(12 downto 0),
      MIMRXRDATA(67 downto 0) => mim_rx_rdata(67 downto 0),
      MIMRXREN => mim_rx_ren,
      MIMRXWADDR(12 downto 0) => mim_rx_waddr(12 downto 0),
      MIMRXWDATA(67 downto 0) => mim_rx_wdata(67 downto 0),
      MIMRXWEN => mim_rx_wen,
      MIMTXRADDR(12 downto 0) => mim_tx_raddr(12 downto 0),
      MIMTXRDATA(68 downto 0) => mim_tx_rdata(68 downto 0),
      MIMTXREN => mim_tx_ren,
      MIMTXWADDR(12 downto 0) => mim_tx_waddr(12 downto 0),
      MIMTXWDATA(68 downto 0) => mim_tx_wdata(68 downto 0),
      MIMTXWEN => mim_tx_wen,
      PIPECLK => clk_msien_reg,
      PIPERX0CHANISALIGNED => pipe_rx0_chanisaligned,
      PIPERX0CHARISK(1 downto 0) => clk_msien_reg_1(1 downto 0),
      PIPERX0DATA(15 downto 0) => Q(15 downto 0),
      PIPERX0ELECIDLE => pipe_rx0_elec_idle,
      PIPERX0PHYSTATUS => pipe_rx0_phy_status,
      PIPERX0POLARITY => pipe_rx0_polarity,
      PIPERX0STATUS(2 downto 0) => clk_msien_reg_3(2 downto 0),
      PIPERX0VALID => pipe_rx0_valid,
      PIPERX1CHANISALIGNED => pipe_rx1_chanisaligned,
      PIPERX1CHARISK(1 downto 0) => clk_msien_reg_2(1 downto 0),
      PIPERX1DATA(15 downto 0) => clk_msien_reg_0(15 downto 0),
      PIPERX1ELECIDLE => pipe_rx1_elec_idle,
      PIPERX1PHYSTATUS => pipe_rx1_phy_status,
      PIPERX1POLARITY => pipe_rx1_polarity,
      PIPERX1STATUS(2 downto 0) => clk_msien_reg_4(2 downto 0),
      PIPERX1VALID => pipe_rx1_valid,
      PIPERX2CHANISALIGNED => '0',
      PIPERX2CHARISK(1 downto 0) => B"00",
      PIPERX2DATA(15 downto 0) => B"0000000000000000",
      PIPERX2ELECIDLE => '1',
      PIPERX2PHYSTATUS => '0',
      PIPERX2POLARITY => pipe_rx2_polarity,
      PIPERX2STATUS(2 downto 0) => B"000",
      PIPERX2VALID => '0',
      PIPERX3CHANISALIGNED => '0',
      PIPERX3CHARISK(1 downto 0) => B"00",
      PIPERX3DATA(15 downto 0) => B"0000000000000000",
      PIPERX3ELECIDLE => '1',
      PIPERX3PHYSTATUS => '0',
      PIPERX3POLARITY => pipe_rx3_polarity,
      PIPERX3STATUS(2 downto 0) => B"000",
      PIPERX3VALID => '0',
      PIPERX4CHANISALIGNED => '0',
      PIPERX4CHARISK(1 downto 0) => B"00",
      PIPERX4DATA(15 downto 0) => B"0000000000000000",
      PIPERX4ELECIDLE => '1',
      PIPERX4PHYSTATUS => '0',
      PIPERX4POLARITY => pipe_rx4_polarity,
      PIPERX4STATUS(2 downto 0) => B"000",
      PIPERX4VALID => '0',
      PIPERX5CHANISALIGNED => '0',
      PIPERX5CHARISK(1 downto 0) => B"00",
      PIPERX5DATA(15 downto 0) => B"0000000000000000",
      PIPERX5ELECIDLE => '1',
      PIPERX5PHYSTATUS => '0',
      PIPERX5POLARITY => pipe_rx5_polarity,
      PIPERX5STATUS(2 downto 0) => B"000",
      PIPERX5VALID => '0',
      PIPERX6CHANISALIGNED => '0',
      PIPERX6CHARISK(1 downto 0) => B"00",
      PIPERX6DATA(15 downto 0) => B"0000000000000000",
      PIPERX6ELECIDLE => '1',
      PIPERX6PHYSTATUS => '0',
      PIPERX6POLARITY => pipe_rx6_polarity,
      PIPERX6STATUS(2 downto 0) => B"000",
      PIPERX6VALID => '0',
      PIPERX7CHANISALIGNED => '0',
      PIPERX7CHARISK(1 downto 0) => B"00",
      PIPERX7DATA(15 downto 0) => B"0000000000000000",
      PIPERX7ELECIDLE => '1',
      PIPERX7PHYSTATUS => '0',
      PIPERX7POLARITY => pipe_rx7_polarity,
      PIPERX7STATUS(2 downto 0) => B"000",
      PIPERX7VALID => '0',
      PIPETX0CHARISK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      PIPETX0COMPLIANCE => pipe_tx0_compliance,
      PIPETX0DATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      PIPETX0ELECIDLE => pipe_tx0_elec_idle,
      PIPETX0POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      PIPETX1CHARISK(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      PIPETX1COMPLIANCE => pipe_tx1_compliance,
      PIPETX1DATA(15 downto 0) => pipe_tx1_data(15 downto 0),
      PIPETX1ELECIDLE => pipe_tx1_elec_idle,
      PIPETX1POWERDOWN(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      PIPETX2CHARISK(1 downto 0) => pipe_tx2_char_is_k(1 downto 0),
      PIPETX2COMPLIANCE => pipe_tx2_compliance,
      PIPETX2DATA(15 downto 0) => pipe_tx2_data(15 downto 0),
      PIPETX2ELECIDLE => pipe_tx2_elec_idle,
      PIPETX2POWERDOWN(1 downto 0) => pipe_tx2_powerdown(1 downto 0),
      PIPETX3CHARISK(1 downto 0) => pipe_tx3_char_is_k(1 downto 0),
      PIPETX3COMPLIANCE => pipe_tx3_compliance,
      PIPETX3DATA(15 downto 0) => pipe_tx3_data(15 downto 0),
      PIPETX3ELECIDLE => pipe_tx3_elec_idle,
      PIPETX3POWERDOWN(1 downto 0) => pipe_tx3_powerdown(1 downto 0),
      PIPETX4CHARISK(1 downto 0) => pipe_tx4_char_is_k(1 downto 0),
      PIPETX4COMPLIANCE => pipe_tx4_compliance,
      PIPETX4DATA(15 downto 0) => pipe_tx4_data(15 downto 0),
      PIPETX4ELECIDLE => pipe_tx4_elec_idle,
      PIPETX4POWERDOWN(1 downto 0) => pipe_tx4_powerdown(1 downto 0),
      PIPETX5CHARISK(1 downto 0) => pipe_tx5_char_is_k(1 downto 0),
      PIPETX5COMPLIANCE => pipe_tx5_compliance,
      PIPETX5DATA(15 downto 0) => pipe_tx5_data(15 downto 0),
      PIPETX5ELECIDLE => pipe_tx5_elec_idle,
      PIPETX5POWERDOWN(1 downto 0) => pipe_tx5_powerdown(1 downto 0),
      PIPETX6CHARISK(1 downto 0) => pipe_tx6_char_is_k(1 downto 0),
      PIPETX6COMPLIANCE => pipe_tx6_compliance,
      PIPETX6DATA(15 downto 0) => pipe_tx6_data(15 downto 0),
      PIPETX6ELECIDLE => pipe_tx6_elec_idle,
      PIPETX6POWERDOWN(1 downto 0) => pipe_tx6_powerdown(1 downto 0),
      PIPETX7CHARISK(1 downto 0) => pipe_tx7_char_is_k(1 downto 0),
      PIPETX7COMPLIANCE => pipe_tx7_compliance,
      PIPETX7DATA(15 downto 0) => pipe_tx7_data(15 downto 0),
      PIPETX7ELECIDLE => pipe_tx7_elec_idle,
      PIPETX7POWERDOWN(1 downto 0) => pipe_tx7_powerdown(1 downto 0),
      PIPETXDEEMPH => pipe_tx_deemph,
      PIPETXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0),
      PIPETXRATE => pipe_tx_rate,
      PIPETXRCVRDET => pipe_tx_rcvr_det,
      PIPETXRESET => pcie_block_i_n_140,
      PL2DIRECTEDLSTATE(4 downto 0) => B"00000",
      PL2L0REQ => pcie_block_i_n_141,
      PL2LINKUP => pcie_block_i_n_142,
      PL2RECEIVERERR => pcie_block_i_n_143,
      PL2RECOVERY => pcie_block_i_n_144,
      PL2RXELECIDLE => pcie_block_i_n_145,
      PL2RXPMSTATE(1) => pcie_block_i_n_610,
      PL2RXPMSTATE(0) => pcie_block_i_n_611,
      PL2SUSPENDOK => pcie_block_i_n_146,
      PLDBGMODE(2 downto 0) => B"000",
      PLDBGVEC(11) => pcie_block_i_n_184,
      PLDBGVEC(10) => pcie_block_i_n_185,
      PLDBGVEC(9) => pcie_block_i_n_186,
      PLDBGVEC(8) => pcie_block_i_n_187,
      PLDBGVEC(7) => pcie_block_i_n_188,
      PLDBGVEC(6) => pcie_block_i_n_189,
      PLDBGVEC(5) => pcie_block_i_n_190,
      PLDBGVEC(4) => pcie_block_i_n_191,
      PLDBGVEC(3) => pcie_block_i_n_192,
      PLDBGVEC(2) => pcie_block_i_n_193,
      PLDBGVEC(1) => pcie_block_i_n_194,
      PLDBGVEC(0) => pcie_block_i_n_195,
      PLDIRECTEDCHANGEDONE => pcie_block_i_n_147,
      PLDIRECTEDLINKAUTON => '0',
      PLDIRECTEDLINKCHANGE(1 downto 0) => B"00",
      PLDIRECTEDLINKSPEED => '0',
      PLDIRECTEDLINKWIDTH(1 downto 0) => B"00",
      PLDIRECTEDLTSSMNEW(5 downto 0) => B"000000",
      PLDIRECTEDLTSSMNEWVLD => '0',
      PLDIRECTEDLTSSMSTALL => '0',
      PLDOWNSTREAMDEEMPHSOURCE => '0',
      PLINITIALLINKWIDTH(2) => pcie_block_i_n_637,
      PLINITIALLINKWIDTH(1) => pcie_block_i_n_638,
      PLINITIALLINKWIDTH(0) => pcie_block_i_n_639,
      PLLANEREVERSALMODE(1) => pcie_block_i_n_612,
      PLLANEREVERSALMODE(0) => pcie_block_i_n_613,
      PLLINKGEN2CAP => pcie_block_i_n_148,
      PLLINKPARTNERGEN2SUPPORTED => pcie_block_i_n_149,
      PLLINKUPCFGCAP => pcie_block_i_n_150,
      PLLTSSMSTATE(5 downto 0) => pl_ltssm_state(5 downto 0),
      PLPHYLNKUPN => pl_phy_lnk_up_n,
      PLRECEIVEDHOTRST => pl_received_hot_rst,
      PLRSTN => '1',
      PLRXPMSTATE(1) => pcie_block_i_n_614,
      PLRXPMSTATE(0) => pcie_block_i_n_615,
      PLSELLNKRATE => pcie_block_i_n_153,
      PLSELLNKWIDTH(1) => pcie_block_i_n_616,
      PLSELLNKWIDTH(0) => pcie_block_i_n_617,
      PLTRANSMITHOTRST => '0',
      PLTXPMSTATE(2) => pcie_block_i_n_640,
      PLTXPMSTATE(1) => pcie_block_i_n_641,
      PLTXPMSTATE(0) => pcie_block_i_n_642,
      PLUPSTREAMPREFERDEEMPH => '0',
      RECEIVEDFUNCLVLRSTN => cfg_received_func_lvl_rst_n,
      SYSRSTN => sys_rst_n,
      TL2ASPMSUSPENDCREDITCHECK => '0',
      TL2ASPMSUSPENDCREDITCHECKOK => pcie_block_i_n_155,
      TL2ASPMSUSPENDREQ => pcie_block_i_n_156,
      TL2ERRFCPE => pcie_block_i_n_157,
      TL2ERRHDR(63) => pcie_block_i_n_832,
      TL2ERRHDR(62) => pcie_block_i_n_833,
      TL2ERRHDR(61) => pcie_block_i_n_834,
      TL2ERRHDR(60) => pcie_block_i_n_835,
      TL2ERRHDR(59) => pcie_block_i_n_836,
      TL2ERRHDR(58) => pcie_block_i_n_837,
      TL2ERRHDR(57) => pcie_block_i_n_838,
      TL2ERRHDR(56) => pcie_block_i_n_839,
      TL2ERRHDR(55) => pcie_block_i_n_840,
      TL2ERRHDR(54) => pcie_block_i_n_841,
      TL2ERRHDR(53) => pcie_block_i_n_842,
      TL2ERRHDR(52) => pcie_block_i_n_843,
      TL2ERRHDR(51) => pcie_block_i_n_844,
      TL2ERRHDR(50) => pcie_block_i_n_845,
      TL2ERRHDR(49) => pcie_block_i_n_846,
      TL2ERRHDR(48) => pcie_block_i_n_847,
      TL2ERRHDR(47) => pcie_block_i_n_848,
      TL2ERRHDR(46) => pcie_block_i_n_849,
      TL2ERRHDR(45) => pcie_block_i_n_850,
      TL2ERRHDR(44) => pcie_block_i_n_851,
      TL2ERRHDR(43) => pcie_block_i_n_852,
      TL2ERRHDR(42) => pcie_block_i_n_853,
      TL2ERRHDR(41) => pcie_block_i_n_854,
      TL2ERRHDR(40) => pcie_block_i_n_855,
      TL2ERRHDR(39) => pcie_block_i_n_856,
      TL2ERRHDR(38) => pcie_block_i_n_857,
      TL2ERRHDR(37) => pcie_block_i_n_858,
      TL2ERRHDR(36) => pcie_block_i_n_859,
      TL2ERRHDR(35) => pcie_block_i_n_860,
      TL2ERRHDR(34) => pcie_block_i_n_861,
      TL2ERRHDR(33) => pcie_block_i_n_862,
      TL2ERRHDR(32) => pcie_block_i_n_863,
      TL2ERRHDR(31) => pcie_block_i_n_864,
      TL2ERRHDR(30) => pcie_block_i_n_865,
      TL2ERRHDR(29) => pcie_block_i_n_866,
      TL2ERRHDR(28) => pcie_block_i_n_867,
      TL2ERRHDR(27) => pcie_block_i_n_868,
      TL2ERRHDR(26) => pcie_block_i_n_869,
      TL2ERRHDR(25) => pcie_block_i_n_870,
      TL2ERRHDR(24) => pcie_block_i_n_871,
      TL2ERRHDR(23) => pcie_block_i_n_872,
      TL2ERRHDR(22) => pcie_block_i_n_873,
      TL2ERRHDR(21) => pcie_block_i_n_874,
      TL2ERRHDR(20) => pcie_block_i_n_875,
      TL2ERRHDR(19) => pcie_block_i_n_876,
      TL2ERRHDR(18) => pcie_block_i_n_877,
      TL2ERRHDR(17) => pcie_block_i_n_878,
      TL2ERRHDR(16) => pcie_block_i_n_879,
      TL2ERRHDR(15) => pcie_block_i_n_880,
      TL2ERRHDR(14) => pcie_block_i_n_881,
      TL2ERRHDR(13) => pcie_block_i_n_882,
      TL2ERRHDR(12) => pcie_block_i_n_883,
      TL2ERRHDR(11) => pcie_block_i_n_884,
      TL2ERRHDR(10) => pcie_block_i_n_885,
      TL2ERRHDR(9) => pcie_block_i_n_886,
      TL2ERRHDR(8) => pcie_block_i_n_887,
      TL2ERRHDR(7) => pcie_block_i_n_888,
      TL2ERRHDR(6) => pcie_block_i_n_889,
      TL2ERRHDR(5) => pcie_block_i_n_890,
      TL2ERRHDR(4) => pcie_block_i_n_891,
      TL2ERRHDR(3) => pcie_block_i_n_892,
      TL2ERRHDR(2) => pcie_block_i_n_893,
      TL2ERRHDR(1) => pcie_block_i_n_894,
      TL2ERRHDR(0) => pcie_block_i_n_895,
      TL2ERRMALFORMED => pcie_block_i_n_158,
      TL2ERRRXOVERFLOW => pcie_block_i_n_159,
      TL2PPMSUSPENDOK => pcie_block_i_n_160,
      TL2PPMSUSPENDREQ => '0',
      TLRSTN => '1',
      TRNFCCPLD(11) => pcie_block_i_n_196,
      TRNFCCPLD(10) => pcie_block_i_n_197,
      TRNFCCPLD(9) => pcie_block_i_n_198,
      TRNFCCPLD(8) => pcie_block_i_n_199,
      TRNFCCPLD(7) => pcie_block_i_n_200,
      TRNFCCPLD(6) => pcie_block_i_n_201,
      TRNFCCPLD(5) => pcie_block_i_n_202,
      TRNFCCPLD(4) => pcie_block_i_n_203,
      TRNFCCPLD(3) => pcie_block_i_n_204,
      TRNFCCPLD(2) => pcie_block_i_n_205,
      TRNFCCPLD(1) => pcie_block_i_n_206,
      TRNFCCPLD(0) => pcie_block_i_n_207,
      TRNFCCPLH(7) => pcie_block_i_n_1119,
      TRNFCCPLH(6) => pcie_block_i_n_1120,
      TRNFCCPLH(5) => pcie_block_i_n_1121,
      TRNFCCPLH(4) => pcie_block_i_n_1122,
      TRNFCCPLH(3) => pcie_block_i_n_1123,
      TRNFCCPLH(2) => pcie_block_i_n_1124,
      TRNFCCPLH(1) => pcie_block_i_n_1125,
      TRNFCCPLH(0) => pcie_block_i_n_1126,
      TRNFCNPD(11) => pcie_block_i_n_208,
      TRNFCNPD(10) => pcie_block_i_n_209,
      TRNFCNPD(9) => pcie_block_i_n_210,
      TRNFCNPD(8) => pcie_block_i_n_211,
      TRNFCNPD(7) => pcie_block_i_n_212,
      TRNFCNPD(6) => pcie_block_i_n_213,
      TRNFCNPD(5) => pcie_block_i_n_214,
      TRNFCNPD(4) => pcie_block_i_n_215,
      TRNFCNPD(3) => pcie_block_i_n_216,
      TRNFCNPD(2) => pcie_block_i_n_217,
      TRNFCNPD(1) => pcie_block_i_n_218,
      TRNFCNPD(0) => pcie_block_i_n_219,
      TRNFCNPH(7 downto 0) => fc_nph(7 downto 0),
      TRNFCPD(11) => pcie_block_i_n_220,
      TRNFCPD(10) => pcie_block_i_n_221,
      TRNFCPD(9) => pcie_block_i_n_222,
      TRNFCPD(8) => pcie_block_i_n_223,
      TRNFCPD(7) => pcie_block_i_n_224,
      TRNFCPD(6) => pcie_block_i_n_225,
      TRNFCPD(5) => pcie_block_i_n_226,
      TRNFCPD(4) => pcie_block_i_n_227,
      TRNFCPD(3) => pcie_block_i_n_228,
      TRNFCPD(2) => pcie_block_i_n_229,
      TRNFCPD(1) => pcie_block_i_n_230,
      TRNFCPD(0) => pcie_block_i_n_231,
      TRNFCPH(7) => pcie_block_i_n_1135,
      TRNFCPH(6) => pcie_block_i_n_1136,
      TRNFCPH(5) => pcie_block_i_n_1137,
      TRNFCPH(4) => pcie_block_i_n_1138,
      TRNFCPH(3) => pcie_block_i_n_1139,
      TRNFCPH(2) => pcie_block_i_n_1140,
      TRNFCPH(1) => pcie_block_i_n_1141,
      TRNFCPH(0) => pcie_block_i_n_1142,
      TRNFCSEL(2 downto 1) => B"10",
      TRNFCSEL(0) => fc_sel(0),
      TRNLNKUP => trn_lnk_up,
      TRNRBARHIT(7) => pcie_block_i_n_1143,
      TRNRBARHIT(6 downto 0) => trn_rbar_hit(6 downto 0),
      TRNRD(127 downto 64) => trn_rd(127 downto 64),
      TRNRD(63 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(63 downto 0),
      TRNRDLLPDATA(63) => pcie_block_i_n_896,
      TRNRDLLPDATA(62) => pcie_block_i_n_897,
      TRNRDLLPDATA(61) => pcie_block_i_n_898,
      TRNRDLLPDATA(60) => pcie_block_i_n_899,
      TRNRDLLPDATA(59) => pcie_block_i_n_900,
      TRNRDLLPDATA(58) => pcie_block_i_n_901,
      TRNRDLLPDATA(57) => pcie_block_i_n_902,
      TRNRDLLPDATA(56) => pcie_block_i_n_903,
      TRNRDLLPDATA(55) => pcie_block_i_n_904,
      TRNRDLLPDATA(54) => pcie_block_i_n_905,
      TRNRDLLPDATA(53) => pcie_block_i_n_906,
      TRNRDLLPDATA(52) => pcie_block_i_n_907,
      TRNRDLLPDATA(51) => pcie_block_i_n_908,
      TRNRDLLPDATA(50) => pcie_block_i_n_909,
      TRNRDLLPDATA(49) => pcie_block_i_n_910,
      TRNRDLLPDATA(48) => pcie_block_i_n_911,
      TRNRDLLPDATA(47) => pcie_block_i_n_912,
      TRNRDLLPDATA(46) => pcie_block_i_n_913,
      TRNRDLLPDATA(45) => pcie_block_i_n_914,
      TRNRDLLPDATA(44) => pcie_block_i_n_915,
      TRNRDLLPDATA(43) => pcie_block_i_n_916,
      TRNRDLLPDATA(42) => pcie_block_i_n_917,
      TRNRDLLPDATA(41) => pcie_block_i_n_918,
      TRNRDLLPDATA(40) => pcie_block_i_n_919,
      TRNRDLLPDATA(39) => pcie_block_i_n_920,
      TRNRDLLPDATA(38) => pcie_block_i_n_921,
      TRNRDLLPDATA(37) => pcie_block_i_n_922,
      TRNRDLLPDATA(36) => pcie_block_i_n_923,
      TRNRDLLPDATA(35) => pcie_block_i_n_924,
      TRNRDLLPDATA(34) => pcie_block_i_n_925,
      TRNRDLLPDATA(33) => pcie_block_i_n_926,
      TRNRDLLPDATA(32) => pcie_block_i_n_927,
      TRNRDLLPDATA(31) => pcie_block_i_n_928,
      TRNRDLLPDATA(30) => pcie_block_i_n_929,
      TRNRDLLPDATA(29) => pcie_block_i_n_930,
      TRNRDLLPDATA(28) => pcie_block_i_n_931,
      TRNRDLLPDATA(27) => pcie_block_i_n_932,
      TRNRDLLPDATA(26) => pcie_block_i_n_933,
      TRNRDLLPDATA(25) => pcie_block_i_n_934,
      TRNRDLLPDATA(24) => pcie_block_i_n_935,
      TRNRDLLPDATA(23) => pcie_block_i_n_936,
      TRNRDLLPDATA(22) => pcie_block_i_n_937,
      TRNRDLLPDATA(21) => pcie_block_i_n_938,
      TRNRDLLPDATA(20) => pcie_block_i_n_939,
      TRNRDLLPDATA(19) => pcie_block_i_n_940,
      TRNRDLLPDATA(18) => pcie_block_i_n_941,
      TRNRDLLPDATA(17) => pcie_block_i_n_942,
      TRNRDLLPDATA(16) => pcie_block_i_n_943,
      TRNRDLLPDATA(15) => pcie_block_i_n_944,
      TRNRDLLPDATA(14) => pcie_block_i_n_945,
      TRNRDLLPDATA(13) => pcie_block_i_n_946,
      TRNRDLLPDATA(12) => pcie_block_i_n_947,
      TRNRDLLPDATA(11) => pcie_block_i_n_948,
      TRNRDLLPDATA(10) => pcie_block_i_n_949,
      TRNRDLLPDATA(9) => pcie_block_i_n_950,
      TRNRDLLPDATA(8) => pcie_block_i_n_951,
      TRNRDLLPDATA(7) => pcie_block_i_n_952,
      TRNRDLLPDATA(6) => pcie_block_i_n_953,
      TRNRDLLPDATA(5) => pcie_block_i_n_954,
      TRNRDLLPDATA(4) => pcie_block_i_n_955,
      TRNRDLLPDATA(3) => pcie_block_i_n_956,
      TRNRDLLPDATA(2) => pcie_block_i_n_957,
      TRNRDLLPDATA(1) => pcie_block_i_n_958,
      TRNRDLLPDATA(0) => pcie_block_i_n_959,
      TRNRDLLPSRCRDY(1) => pcie_block_i_n_618,
      TRNRDLLPSRCRDY(0) => pcie_block_i_n_619,
      TRNRDSTRDY => trn_rdst_rdy,
      TRNRECRCERR => trn_recrc_err,
      TRNREOF => \^trn_reof\,
      TRNRERRFWD => trn_rerrfwd,
      TRNRFCPRET => '1',
      TRNRNPOK => '0',
      TRNRNPREQ => rx_np_req,
      TRNRREM(1) => trn_rrem(1),
      TRNRREM(0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      TRNRSOF => \^trn_rsof\,
      TRNRSRCDSC => \^trn_rsrc_dsc\,
      TRNRSRCRDY => trn_rsrc_rdy,
      TRNTBUFAV(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      TRNTCFGGNT => trn_tcfg_gnt,
      TRNTCFGREQ => \^trn_tcfg_req\,
      TRNTD(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TRNTD(63 downto 0) => trn_td(63 downto 0),
      TRNTDLLPDATA(31 downto 0) => B"00000000000000000000000000000000",
      TRNTDLLPDSTRDY => pcie_block_i_n_169,
      TRNTDLLPSRCRDY => '0',
      TRNTDSTRDY(3 downto 1) => NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED(3 downto 1),
      TRNTDSTRDY(0) => \^trn_tdst_rdy\,
      TRNTECRCGEN => '0',
      TRNTEOF => trn_teof,
      TRNTERRDROP => pcie_block_i_n_170,
      TRNTERRFWD => '0',
      TRNTREM(1) => '0',
      TRNTREM(0) => trn_trem(0),
      TRNTSOF => trn_tsof,
      TRNTSRCDSC => '0',
      TRNTSRCRDY => trn_tsrc_rdy,
      TRNTSTR => '0',
      USERCLK => CLK,
      USERCLK2 => CLK,
      USERRSTN => user_rst_n
    );
pcie_block_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_assert,
      O => pcie_block_i_i_1_n_0
    );
pcie_block_i_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt,
      O => pcie_block_i_i_2_n_0
    );
pcie_block_i_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_en,
      O => pcie_block_i_i_3_n_0
    );
pcie_block_i_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_en,
      O => pcie_block_i_i_4_n_0
    );
pcie_block_i_i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_readonly,
      O => pcie_block_i_i_5_n_0
    );
pcie_bram_top: entity work.xdma_0_xdma_0_pcie2_ip_pcie_bram_top_7x
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => mim_rx_raddr(10 downto 0),
      MIMRXWADDR(10 downto 0) => mim_rx_waddr(10 downto 0),
      MIMTXRADDR(10 downto 0) => mim_tx_raddr(10 downto 0),
      MIMTXWADDR(10 downto 0) => mim_tx_waddr(10 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl\(67 downto 0) => mim_rx_rdata(67 downto 0),
      \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0\(67 downto 0) => mim_rx_wdata(67 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(68 downto 0) => mim_tx_rdata(68 downto 0),
      wdata(68 downto 0) => mim_tx_wdata(68 downto 0)
    );
phy_lnk_up_cdc_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pl_phy_lnk_up_n,
      O => src_in
    );
ppm_L1_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEAAAA"
    )
        port map (
      I0 => ppm_L1_trig,
      I1 => \^cfg_pcie_link_state\(0),
      I2 => \^cfg_pcie_link_state\(2),
      I3 => \^cfg_pcie_link_state\(1),
      I4 => ppm_L1_thrtl,
      O => ppm_L1_thrtl_reg
    );
tbuf_av_min_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^trn_tbuf_av\(5),
      I1 => \^trn_tbuf_av\(4),
      I2 => \^trn_tbuf_av\(3),
      I3 => \^trn_tbuf_av\(2),
      I4 => \^trn_tbuf_av\(1),
      O => tbuf_av_min_trig
    );
tready_thrtl_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^trn_tcfg_req\,
      I1 => reg_tcfg_gnt,
      O => tcfg_req_trig
    );
tready_thrtl_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => \^trn_tbuf_av\(5),
      I1 => \^trn_tbuf_av\(4),
      I2 => \^trn_tbuf_av\(3),
      I3 => \^trn_tbuf_av\(2),
      I4 => \^trn_tbuf_av\(0),
      I5 => \^trn_tbuf_av\(1),
      O => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\
    );
trn_in_packet_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AEAA2AAA"
    )
        port map (
      I0 => trn_in_packet,
      I1 => trn_rdst_rdy,
      I2 => \^trn_reof\,
      I3 => trn_rsrc_rdy,
      I4 => \^trn_rsof\,
      I5 => \^trn_rsrc_dsc\,
      O => trn_in_packet_reg
    );
trn_rsrc_dsc_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^trn_rsrc_dsc\,
      I1 => reg_dsc_detect,
      O => trn_rsrc_dsc_prev0
    );
trn_rsrc_rdy_prev_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => trn_rsrc_rdy,
      I1 => \^trn_rsof\,
      I2 => \^trn_rsrc_dsc\,
      I3 => trn_in_packet,
      O => rsrc_rdy_filtered
    );
user_reset_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => bridge_reset_int,
      I1 => pl_phy_lnk_up,
      I2 => user_rst_n,
      O => user_reset_int_reg
    );
end STRUCTURE;
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie_top is
  port (
    m_axis_rx_tvalid_reg : out STD_LOGIC;
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    tready_thrtl_reg : out STD_LOGIC;
    pipe_rx0_polarity_gt : out STD_LOGIC;
    pipe_rx1_polarity_gt : out STD_LOGIC;
    TXCHARDISPMODE : out STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_compliance_q_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx0_elec_idle_gt : out STD_LOGIC;
    pipe_tx1_elec_idle_gt : out STD_LOGIC;
    pipe_tx_rcvr_det_gt : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_deemph_gt : out STD_LOGIC;
    user_reset_int_reg : out STD_LOGIC;
    src_in : out STD_LOGIC;
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    cfg_dcommand : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \throttle_ctl_pipeline.reg_tkeep_reg[7]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_valid_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_deemph_q_reg\ : in STD_LOGIC;
    pipe_rx1_chanisaligned_gt : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : in STD_LOGIC;
    pipe_rx0_valid_gt : in STD_LOGIC;
    pipe_rx0_chanisaligned_gt : in STD_LOGIC;
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_rst_n : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie_top : entity is "xdma_0_pcie2_ip_pcie_top";
end xdma_0_xdma_0_pcie2_ip_pcie_top;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie_top is
  signal pcie_7x_i_n_10 : STD_LOGIC;
  signal pcie_7x_i_n_108 : STD_LOGIC;
  signal pcie_7x_i_n_109 : STD_LOGIC;
  signal pcie_7x_i_n_11 : STD_LOGIC;
  signal pcie_7x_i_n_110 : STD_LOGIC;
  signal pcie_7x_i_n_111 : STD_LOGIC;
  signal pcie_7x_i_n_112 : STD_LOGIC;
  signal pcie_7x_i_n_113 : STD_LOGIC;
  signal pcie_7x_i_n_114 : STD_LOGIC;
  signal pcie_7x_i_n_115 : STD_LOGIC;
  signal pcie_7x_i_n_116 : STD_LOGIC;
  signal pcie_7x_i_n_117 : STD_LOGIC;
  signal pcie_7x_i_n_118 : STD_LOGIC;
  signal pcie_7x_i_n_119 : STD_LOGIC;
  signal pcie_7x_i_n_12 : STD_LOGIC;
  signal pcie_7x_i_n_120 : STD_LOGIC;
  signal pcie_7x_i_n_121 : STD_LOGIC;
  signal pcie_7x_i_n_122 : STD_LOGIC;
  signal pcie_7x_i_n_123 : STD_LOGIC;
  signal pcie_7x_i_n_17 : STD_LOGIC;
  signal pcie_7x_i_n_18 : STD_LOGIC;
  signal pcie_7x_i_n_19 : STD_LOGIC;
  signal pcie_7x_i_n_20 : STD_LOGIC;
  signal pcie_7x_i_n_21 : STD_LOGIC;
  signal pcie_7x_i_n_22 : STD_LOGIC;
  signal pcie_7x_i_n_23 : STD_LOGIC;
  signal pcie_7x_i_n_24 : STD_LOGIC;
  signal pcie_7x_i_n_26 : STD_LOGIC;
  signal pcie_7x_i_n_4 : STD_LOGIC;
  signal pcie_7x_i_n_5 : STD_LOGIC;
  signal pcie_7x_i_n_9 : STD_LOGIC;
  signal pipe_rx0_chanisaligned : STD_LOGIC;
  signal pipe_rx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx0_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx0_elec_idle : STD_LOGIC;
  signal pipe_rx0_phy_status : STD_LOGIC;
  signal pipe_rx0_polarity : STD_LOGIC;
  signal pipe_rx0_status : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx0_valid : STD_LOGIC;
  signal pipe_rx1_chanisaligned : STD_LOGIC;
  signal pipe_rx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx1_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx1_elec_idle : STD_LOGIC;
  signal pipe_rx1_phy_status : STD_LOGIC;
  signal pipe_rx1_polarity : STD_LOGIC;
  signal pipe_rx1_status : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx1_valid : STD_LOGIC;
  signal pipe_tx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx0_compliance : STD_LOGIC;
  signal pipe_tx0_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx0_elec_idle : STD_LOGIC;
  signal pipe_tx0_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_compliance : STD_LOGIC;
  signal pipe_tx1_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx1_elec_idle : STD_LOGIC;
  signal pipe_tx1_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx_deemph : STD_LOGIC;
  signal pipe_tx_margin : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_tx_rate : STD_LOGIC;
  signal pipe_tx_rcvr_det : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/dsc_detect\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/reg_dsc_detect\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_in_packet\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\ : STD_LOGIC;
  signal trn_rbar_hit : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy : STD_LOGIC;
  signal trn_recrc_err : STD_LOGIC;
  signal trn_reof : STD_LOGIC;
  signal trn_rerrfwd : STD_LOGIC;
  signal trn_rrem : STD_LOGIC_VECTOR ( 0 to 0 );
  signal trn_rsof : STD_LOGIC;
  signal trn_rsrc_dsc : STD_LOGIC;
  signal trn_tcfg_gnt : STD_LOGIC;
  signal trn_td : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_tdst_rdy : STD_LOGIC;
  signal trn_teof : STD_LOGIC;
  signal trn_trem : STD_LOGIC;
  signal trn_tsof : STD_LOGIC;
  signal trn_tsrc_rdy : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\ : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\ : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\ : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\ : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\ : STD_LOGIC;
  signal \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\ : STD_LOGIC;
  signal \tx_inst/tx_pipeline_inst/reg_disable_trn2\ : STD_LOGIC;
begin
axi_basic_top: entity work.xdma_0_xdma_0_pcie2_ip_axi_basic_top
     port map (
      CLK => CLK,
      E(0) => trn_rdst_rdy,
      Q(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      cfg_pcie_link_state(2) => pcie_7x_i_n_10,
      cfg_pcie_link_state(1) => pcie_7x_i_n_11,
      cfg_pcie_link_state(0) => pcie_7x_i_n_12,
      dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\,
      lnk_up_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\,
      lnk_up_thrtl_reg => pcie_7x_i_n_26,
      m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_reg => m_axis_rx_tvalid_reg,
      \out\ => \out\,
      ppm_L1_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\,
      ppm_L1_thrtl_reg => pcie_7x_i_n_9,
      ppm_L1_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\,
      reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\,
      reg_tcfg_gnt => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\,
      rsrc_rdy_filtered => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      tcfg_req_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\,
      \throttle_ctl_pipeline.reg_tdata_reg[63]\(63 downto 32) => trn_td(31 downto 0),
      \throttle_ctl_pipeline.reg_tdata_reg[63]\(31 downto 0) => trn_td(63 downto 32),
      \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \throttle_ctl_pipeline.reg_tkeep_reg[7]\,
      tready_thrtl_i_3 => pcie_7x_i_n_18,
      tready_thrtl_reg => tready_thrtl_reg,
      trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\,
      trn_in_packet_reg => pcie_7x_i_n_5,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\,
      trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\,
      trn_tbuf_av(5) => pcie_7x_i_n_19,
      trn_tbuf_av(4) => pcie_7x_i_n_20,
      trn_tbuf_av(3) => pcie_7x_i_n_21,
      trn_tbuf_av(2) => pcie_7x_i_n_22,
      trn_tbuf_av(1) => pcie_7x_i_n_23,
      trn_tbuf_av(0) => pcie_7x_i_n_24,
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => pcie_7x_i_n_17,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy
    );
\cfg_bus_number_d[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \out\,
      O => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_115,
      Q => cfg_bus_number(0),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_114,
      Q => cfg_bus_number(1),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_113,
      Q => cfg_bus_number(2),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_112,
      Q => cfg_bus_number(3),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_111,
      Q => cfg_bus_number(4),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_110,
      Q => cfg_bus_number(5),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_109,
      Q => cfg_bus_number(6),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_bus_number_d_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_108,
      Q => cfg_bus_number(7),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_device_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_120,
      Q => cfg_device_number(0),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_device_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_119,
      Q => cfg_device_number(1),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_device_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_118,
      Q => cfg_device_number(2),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_device_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_117,
      Q => cfg_device_number(3),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_device_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_116,
      Q => cfg_device_number(4),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_function_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_123,
      Q => cfg_function_number(0),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_function_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_122,
      Q => cfg_function_number(1),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
\cfg_function_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_4,
      D => pcie_7x_i_n_121,
      Q => cfg_function_number(2),
      R => \tx_inst/tx_pipeline_inst/reg_disable_trn2\
    );
pcie_7x_i: entity work.xdma_0_xdma_0_pcie2_ip_pcie_7x
     port map (
      CLK => CLK,
      E(0) => pcie_7x_i_n_4,
      Q(15 downto 0) => pipe_rx0_data(15 downto 0),
      bridge_reset_int => bridge_reset_int,
      cfg_command(0) => cfg_command(0),
      cfg_dcommand(5 downto 0) => cfg_dcommand(5 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(4 downto 0) => cfg_interrupt_di(4 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_msg_data(15) => pcie_7x_i_n_108,
      cfg_msg_data(14) => pcie_7x_i_n_109,
      cfg_msg_data(13) => pcie_7x_i_n_110,
      cfg_msg_data(12) => pcie_7x_i_n_111,
      cfg_msg_data(11) => pcie_7x_i_n_112,
      cfg_msg_data(10) => pcie_7x_i_n_113,
      cfg_msg_data(9) => pcie_7x_i_n_114,
      cfg_msg_data(8) => pcie_7x_i_n_115,
      cfg_msg_data(7) => pcie_7x_i_n_116,
      cfg_msg_data(6) => pcie_7x_i_n_117,
      cfg_msg_data(5) => pcie_7x_i_n_118,
      cfg_msg_data(4) => pcie_7x_i_n_119,
      cfg_msg_data(3) => pcie_7x_i_n_120,
      cfg_msg_data(2) => pcie_7x_i_n_121,
      cfg_msg_data(1) => pcie_7x_i_n_122,
      cfg_msg_data(0) => pcie_7x_i_n_123,
      cfg_pcie_link_state(2) => pcie_7x_i_n_10,
      cfg_pcie_link_state(1) => pcie_7x_i_n_11,
      cfg_pcie_link_state(0) => pcie_7x_i_n_12,
      cfg_to_turnoff => cfg_to_turnoff,
      clk_msien_reg => \pipe_stages_1.pipe_tx_deemph_q_reg\,
      clk_msien_reg_0(15 downto 0) => pipe_rx1_data(15 downto 0),
      clk_msien_reg_1(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      clk_msien_reg_2(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      clk_msien_reg_3(2 downto 0) => pipe_rx0_status(2 downto 0),
      clk_msien_reg_4(2 downto 0) => pipe_rx1_status(2 downto 0),
      dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\,
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_sel(0) => fc_sel(0),
      lnk_up_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl\,
      lnk_up_thrtl_reg => pcie_7x_i_n_26,
      \out\ => \out\,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_elec_idle => pipe_rx0_elec_idle,
      pipe_rx0_phy_status => pipe_rx0_phy_status,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_elec_idle => pipe_rx1_elec_idle,
      pipe_rx1_phy_status => pipe_rx1_phy_status,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rx1_valid => pipe_rx1_valid,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ => pcie_7x_i_n_18,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(63 downto 0) => trn_rd(63 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0) => trn_rrem(0),
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rate => pipe_tx_rate,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => pl_received_hot_rst,
      ppm_L1_thrtl => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl\,
      ppm_L1_thrtl_reg => pcie_7x_i_n_9,
      ppm_L1_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig\,
      reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\,
      reg_tcfg_gnt => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt\,
      rsrc_rdy_filtered => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered\,
      rx_np_req => rx_np_req,
      src_in => src_in,
      sys_rst_n => sys_rst_n,
      tbuf_av_min_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      tcfg_req_trig => \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig\,
      trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\,
      trn_in_packet_reg => pcie_7x_i_n_5,
      trn_lnk_up => trn_lnk_up,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rdst_rdy => trn_rdst_rdy,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\,
      trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\,
      trn_tbuf_av(5) => pcie_7x_i_n_19,
      trn_tbuf_av(4) => pcie_7x_i_n_20,
      trn_tbuf_av(3) => pcie_7x_i_n_21,
      trn_tbuf_av(2) => pcie_7x_i_n_22,
      trn_tbuf_av(1) => pcie_7x_i_n_23,
      trn_tbuf_av(0) => pcie_7x_i_n_24,
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => pcie_7x_i_n_17,
      trn_td(63 downto 0) => trn_td(63 downto 0),
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      user_reset_int_reg => user_reset_int_reg
    );
pcie_pipe_pipeline_i: entity work.xdma_0_xdma_0_pcie2_ip_pcie_pipe_pipeline
     port map (
      D(0) => D(0),
      Q(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      SR(0) => SR(0),
      TXCHARDISPMODE(0) => TXCHARDISPMODE(0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rxelecidle_q => gt_rxelecidle_q,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_elec_idle => pipe_rx0_elec_idle,
      pipe_rx0_phy_status => pipe_rx0_phy_status,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx0_valid_gt => pipe_rx0_valid_gt,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_elec_idle => pipe_rx1_elec_idle,
      pipe_rx1_phy_status => pipe_rx1_phy_status,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx1_valid_gt => pipe_rx1_valid_gt,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx1_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx0_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => pipe_rx1_status(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => pipe_rx0_status(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0) => Q(1 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2\(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_tx_compliance_q_reg\(0) => \pipe_stages_1.pipe_tx_compliance_q_reg\(0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_1\(15 downto 0) => pipe_tx0_data(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_2\(15 downto 0) => pipe_tx1_data(15 downto 0),
      \pipe_stages_1.pipe_tx_deemph_q_reg\ => \pipe_stages_1.pipe_tx_deemph_q_reg\,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_0\(2 downto 0) => pipe_tx_margin(2 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1\(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2\(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rate => pipe_tx_rate,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_pcie2_fifo_generator_tgt_brdg is
  port (
    s_aclk : in STD_LOGIC;
    s_aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tlast : in STD_LOGIC;
    s_axis_tuser : in STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_tlast : out STD_LOGIC;
    m_axis_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    axis_prog_full : out STD_LOGIC
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0_pcie2_fifo_generator_tgt_brdg : entity is "pcie2_fifo_generator_tgt_brdg,fifo_generator_v13_1_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_pcie2_fifo_generator_tgt_brdg : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_pcie2_fifo_generator_tgt_brdg : entity is "pcie2_fifo_generator_tgt_brdg";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0_pcie2_fifo_generator_tgt_brdg : entity is "fifo_generator_v13_1_4,Vivado 2020.2";
end xdma_0_pcie2_fifo_generator_tgt_brdg;

architecture STRUCTURE of xdma_0_pcie2_fifo_generator_tgt_brdg is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axis_tuser\ : STD_LOGIC_VECTOR ( 6 downto 2 );
  signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_dout_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute C_ADD_NGC_CONSTRAINT : integer;
  attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
  attribute C_APPLICATION_TYPE_AXIS : integer;
  attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
  attribute C_APPLICATION_TYPE_RACH : integer;
  attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_RDCH : integer;
  attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WACH : integer;
  attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WDCH : integer;
  attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WRCH : integer;
  attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
  attribute C_AXIS_TDATA_WIDTH : integer;
  attribute C_AXIS_TDATA_WIDTH of U0 : label is 64;
  attribute C_AXIS_TDEST_WIDTH : integer;
  attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
  attribute C_AXIS_TID_WIDTH : integer;
  attribute C_AXIS_TID_WIDTH of U0 : label is 1;
  attribute C_AXIS_TKEEP_WIDTH : integer;
  attribute C_AXIS_TKEEP_WIDTH of U0 : label is 8;
  attribute C_AXIS_TSTRB_WIDTH : integer;
  attribute C_AXIS_TSTRB_WIDTH of U0 : label is 8;
  attribute C_AXIS_TUSER_WIDTH : integer;
  attribute C_AXIS_TUSER_WIDTH of U0 : label is 22;
  attribute C_AXIS_TYPE : integer;
  attribute C_AXIS_TYPE of U0 : label is 0;
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
  attribute C_AXI_ARUSER_WIDTH : integer;
  attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_AWUSER_WIDTH : integer;
  attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_BUSER_WIDTH : integer;
  attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_DATA_WIDTH : integer;
  attribute C_AXI_DATA_WIDTH of U0 : label is 64;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 1;
  attribute C_AXI_LEN_WIDTH : integer;
  attribute C_AXI_LEN_WIDTH of U0 : label is 8;
  attribute C_AXI_LOCK_WIDTH : integer;
  attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
  attribute C_AXI_RUSER_WIDTH : integer;
  attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_AXI_WUSER_WIDTH : integer;
  attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
  attribute C_COMMON_CLOCK : integer;
  attribute C_COMMON_CLOCK of U0 : label is 1;
  attribute C_COUNT_TYPE : integer;
  attribute C_COUNT_TYPE of U0 : label is 0;
  attribute C_DATA_COUNT_WIDTH : integer;
  attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_DEFAULT_VALUE : string;
  attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
  attribute C_DIN_WIDTH : integer;
  attribute C_DIN_WIDTH of U0 : label is 18;
  attribute C_DIN_WIDTH_AXIS : integer;
  attribute C_DIN_WIDTH_AXIS of U0 : label is 95;
  attribute C_DIN_WIDTH_RACH : integer;
  attribute C_DIN_WIDTH_RACH of U0 : label is 32;
  attribute C_DIN_WIDTH_RDCH : integer;
  attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
  attribute C_DIN_WIDTH_WACH : integer;
  attribute C_DIN_WIDTH_WACH of U0 : label is 32;
  attribute C_DIN_WIDTH_WDCH : integer;
  attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
  attribute C_DIN_WIDTH_WRCH : integer;
  attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
  attribute C_DOUT_RST_VAL : string;
  attribute C_DOUT_RST_VAL of U0 : label is "0";
  attribute C_DOUT_WIDTH : integer;
  attribute C_DOUT_WIDTH of U0 : label is 18;
  attribute C_ENABLE_RLOCS : integer;
  attribute C_ENABLE_RLOCS of U0 : label is 0;
  attribute C_ENABLE_RST_SYNC : integer;
  attribute C_ENABLE_RST_SYNC of U0 : label is 1;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE : integer;
  attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
  attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_RACH : integer;
  attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
  attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WACH : integer;
  attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
  attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
  attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_FULL_FLAGS_RST_VAL : integer;
  attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
  attribute C_HAS_ALMOST_EMPTY : integer;
  attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
  attribute C_HAS_ALMOST_FULL : integer;
  attribute C_HAS_ALMOST_FULL of U0 : label is 0;
  attribute C_HAS_AXIS_TDATA : integer;
  attribute C_HAS_AXIS_TDATA of U0 : label is 1;
  attribute C_HAS_AXIS_TDEST : integer;
  attribute C_HAS_AXIS_TDEST of U0 : label is 0;
  attribute C_HAS_AXIS_TID : integer;
  attribute C_HAS_AXIS_TID of U0 : label is 0;
  attribute C_HAS_AXIS_TKEEP : integer;
  attribute C_HAS_AXIS_TKEEP of U0 : label is 1;
  attribute C_HAS_AXIS_TLAST : integer;
  attribute C_HAS_AXIS_TLAST of U0 : label is 1;
  attribute C_HAS_AXIS_TREADY : integer;
  attribute C_HAS_AXIS_TREADY of U0 : label is 1;
  attribute C_HAS_AXIS_TSTRB : integer;
  attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
  attribute C_HAS_AXIS_TUSER : integer;
  attribute C_HAS_AXIS_TUSER of U0 : label is 1;
  attribute C_HAS_AXI_ARUSER : integer;
  attribute C_HAS_AXI_ARUSER of U0 : label is 0;
  attribute C_HAS_AXI_AWUSER : integer;
  attribute C_HAS_AXI_AWUSER of U0 : label is 0;
  attribute C_HAS_AXI_BUSER : integer;
  attribute C_HAS_AXI_BUSER of U0 : label is 0;
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_AXI_RD_CHANNEL : integer;
  attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
  attribute C_HAS_AXI_RUSER : integer;
  attribute C_HAS_AXI_RUSER of U0 : label is 0;
  attribute C_HAS_AXI_WR_CHANNEL : integer;
  attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
  attribute C_HAS_AXI_WUSER : integer;
  attribute C_HAS_AXI_WUSER of U0 : label is 0;
  attribute C_HAS_BACKUP : integer;
  attribute C_HAS_BACKUP of U0 : label is 0;
  attribute C_HAS_DATA_COUNT : integer;
  attribute C_HAS_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_AXIS : integer;
  attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_RACH : integer;
  attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_RDCH : integer;
  attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WACH : integer;
  attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WDCH : integer;
  attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WRCH : integer;
  attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
  attribute C_HAS_INT_CLK : integer;
  attribute C_HAS_INT_CLK of U0 : label is 0;
  attribute C_HAS_MASTER_CE : integer;
  attribute C_HAS_MASTER_CE of U0 : label is 0;
  attribute C_HAS_MEMINIT_FILE : integer;
  attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
  attribute C_HAS_OVERFLOW : integer;
  attribute C_HAS_OVERFLOW of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_AXIS : integer;
  attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_RACH : integer;
  attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_RDCH : integer;
  attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WACH : integer;
  attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WDCH : integer;
  attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WRCH : integer;
  attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
  attribute C_HAS_RD_DATA_COUNT : integer;
  attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_RD_RST : integer;
  attribute C_HAS_RD_RST of U0 : label is 0;
  attribute C_HAS_RST : integer;
  attribute C_HAS_RST of U0 : label is 1;
  attribute C_HAS_SLAVE_CE : integer;
  attribute C_HAS_SLAVE_CE of U0 : label is 0;
  attribute C_HAS_SRST : integer;
  attribute C_HAS_SRST of U0 : label is 0;
  attribute C_HAS_UNDERFLOW : integer;
  attribute C_HAS_UNDERFLOW of U0 : label is 0;
  attribute C_HAS_VALID : integer;
  attribute C_HAS_VALID of U0 : label is 0;
  attribute C_HAS_WR_ACK : integer;
  attribute C_HAS_WR_ACK of U0 : label is 0;
  attribute C_HAS_WR_DATA_COUNT : integer;
  attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_WR_RST : integer;
  attribute C_HAS_WR_RST of U0 : label is 0;
  attribute C_IMPLEMENTATION_TYPE : integer;
  attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
  attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
  attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 2;
  attribute C_IMPLEMENTATION_TYPE_RACH : integer;
  attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 2;
  attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
  attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
  attribute C_IMPLEMENTATION_TYPE_WACH : integer;
  attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 2;
  attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
  attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
  attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
  attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 2;
  attribute C_INIT_WR_PNTR_VAL : integer;
  attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 1;
  attribute C_MEMORY_TYPE : integer;
  attribute C_MEMORY_TYPE of U0 : label is 1;
  attribute C_MIF_FILE_NAME : string;
  attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
  attribute C_MSGON_VAL : integer;
  attribute C_MSGON_VAL of U0 : label is 1;
  attribute C_OPTIMIZATION_MODE : integer;
  attribute C_OPTIMIZATION_MODE of U0 : label is 0;
  attribute C_OVERFLOW_LOW : integer;
  attribute C_OVERFLOW_LOW of U0 : label is 0;
  attribute C_POWER_SAVING_MODE : integer;
  attribute C_POWER_SAVING_MODE of U0 : label is 0;
  attribute C_PRELOAD_LATENCY : integer;
  attribute C_PRELOAD_LATENCY of U0 : label is 1;
  attribute C_PRELOAD_REGS : integer;
  attribute C_PRELOAD_REGS of U0 : label is 0;
  attribute C_PRIM_FIFO_TYPE : string;
  attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx4";
  attribute C_PRIM_FIFO_TYPE_AXIS : string;
  attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "512x72";
  attribute C_PRIM_FIFO_TYPE_RACH : string;
  attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
  attribute C_PRIM_FIFO_TYPE_RDCH : string;
  attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
  attribute C_PRIM_FIFO_TYPE_WACH : string;
  attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
  attribute C_PRIM_FIFO_TYPE_WDCH : string;
  attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
  attribute C_PRIM_FIFO_TYPE_WRCH : string;
  attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
  attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
  attribute C_PROG_EMPTY_TYPE : integer;
  attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_AXIS : integer;
  attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_RACH : integer;
  attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_RDCH : integer;
  attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WACH : integer;
  attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WDCH : integer;
  attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WRCH : integer;
  attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 9;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
  attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
  attribute C_PROG_FULL_TYPE : integer;
  attribute C_PROG_FULL_TYPE of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_AXIS : integer;
  attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 1;
  attribute C_PROG_FULL_TYPE_RACH : integer;
  attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_RDCH : integer;
  attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WACH : integer;
  attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WDCH : integer;
  attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WRCH : integer;
  attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
  attribute C_RACH_TYPE : integer;
  attribute C_RACH_TYPE of U0 : label is 0;
  attribute C_RDCH_TYPE : integer;
  attribute C_RDCH_TYPE of U0 : label is 0;
  attribute C_RD_DATA_COUNT_WIDTH : integer;
  attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_RD_DEPTH : integer;
  attribute C_RD_DEPTH of U0 : label is 1024;
  attribute C_RD_FREQ : integer;
  attribute C_RD_FREQ of U0 : label is 1;
  attribute C_RD_PNTR_WIDTH : integer;
  attribute C_RD_PNTR_WIDTH of U0 : label is 10;
  attribute C_REG_SLICE_MODE_AXIS : integer;
  attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
  attribute C_REG_SLICE_MODE_RACH : integer;
  attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_RDCH : integer;
  attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WACH : integer;
  attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WDCH : integer;
  attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WRCH : integer;
  attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
  attribute C_SELECT_XPM : integer;
  attribute C_SELECT_XPM of U0 : label is 0;
  attribute C_SYNCHRONIZER_STAGE : integer;
  attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
  attribute C_UNDERFLOW_LOW : integer;
  attribute C_UNDERFLOW_LOW of U0 : label is 0;
  attribute C_USE_COMMON_OVERFLOW : integer;
  attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
  attribute C_USE_COMMON_UNDERFLOW : integer;
  attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
  attribute C_USE_DEFAULT_SETTINGS : integer;
  attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
  attribute C_USE_DOUT_RST : integer;
  attribute C_USE_DOUT_RST of U0 : label is 1;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_ECC_AXIS : integer;
  attribute C_USE_ECC_AXIS of U0 : label is 0;
  attribute C_USE_ECC_RACH : integer;
  attribute C_USE_ECC_RACH of U0 : label is 0;
  attribute C_USE_ECC_RDCH : integer;
  attribute C_USE_ECC_RDCH of U0 : label is 0;
  attribute C_USE_ECC_WACH : integer;
  attribute C_USE_ECC_WACH of U0 : label is 0;
  attribute C_USE_ECC_WDCH : integer;
  attribute C_USE_ECC_WDCH of U0 : label is 0;
  attribute C_USE_ECC_WRCH : integer;
  attribute C_USE_ECC_WRCH of U0 : label is 0;
  attribute C_USE_EMBEDDED_REG : integer;
  attribute C_USE_EMBEDDED_REG of U0 : label is 0;
  attribute C_USE_FIFO16_FLAGS : integer;
  attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
  attribute C_USE_FWFT_DATA_COUNT : integer;
  attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
  attribute C_USE_PIPELINE_REG : integer;
  attribute C_USE_PIPELINE_REG of U0 : label is 0;
  attribute C_VALID_LOW : integer;
  attribute C_VALID_LOW of U0 : label is 0;
  attribute C_WACH_TYPE : integer;
  attribute C_WACH_TYPE of U0 : label is 0;
  attribute C_WDCH_TYPE : integer;
  attribute C_WDCH_TYPE of U0 : label is 0;
  attribute C_WRCH_TYPE : integer;
  attribute C_WRCH_TYPE of U0 : label is 0;
  attribute C_WR_ACK_LOW : integer;
  attribute C_WR_ACK_LOW of U0 : label is 0;
  attribute C_WR_DATA_COUNT_WIDTH : integer;
  attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_WR_DEPTH : integer;
  attribute C_WR_DEPTH of U0 : label is 1024;
  attribute C_WR_DEPTH_AXIS : integer;
  attribute C_WR_DEPTH_AXIS of U0 : label is 16;
  attribute C_WR_DEPTH_RACH : integer;
  attribute C_WR_DEPTH_RACH of U0 : label is 16;
  attribute C_WR_DEPTH_RDCH : integer;
  attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
  attribute C_WR_DEPTH_WACH : integer;
  attribute C_WR_DEPTH_WACH of U0 : label is 16;
  attribute C_WR_DEPTH_WDCH : integer;
  attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
  attribute C_WR_DEPTH_WRCH : integer;
  attribute C_WR_DEPTH_WRCH of U0 : label is 16;
  attribute C_WR_FREQ : integer;
  attribute C_WR_FREQ of U0 : label is 1;
  attribute C_WR_PNTR_WIDTH : integer;
  attribute C_WR_PNTR_WIDTH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_AXIS : integer;
  attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 4;
  attribute C_WR_PNTR_WIDTH_RACH : integer;
  attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
  attribute C_WR_PNTR_WIDTH_RDCH : integer;
  attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_WACH : integer;
  attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
  attribute C_WR_PNTR_WIDTH_WDCH : integer;
  attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_WRCH : integer;
  attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
  attribute C_WR_RESPONSE_LATENCY : integer;
  attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of m_axis_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
  attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
  attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of m_axis_tvalid : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_aclk : signal is "xilinx.com:signal:clock:1.0 slave_aclk CLK";
  attribute X_INTERFACE_PARAMETER of s_aclk : signal is "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_aresetn : signal is "xilinx.com:signal:reset:1.0 slave_aresetn RST";
  attribute X_INTERFACE_PARAMETER of s_aresetn : signal is "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_axis_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
  attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
  attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
  attribute X_INTERFACE_PARAMETER of s_axis_tvalid : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
  attribute X_INTERFACE_INFO of m_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
  attribute X_INTERFACE_INFO of m_axis_tuser : signal is "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
  attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
  attribute X_INTERFACE_INFO of s_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
  attribute X_INTERFACE_INFO of s_axis_tuser : signal is "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
begin
  axis_prog_full <= \<const0>\;
  m_axis_tkeep(7) <= \<const0>\;
  m_axis_tkeep(6) <= \<const0>\;
  m_axis_tkeep(5) <= \<const0>\;
  m_axis_tkeep(4) <= \<const0>\;
  m_axis_tkeep(3) <= \<const0>\;
  m_axis_tkeep(2) <= \<const0>\;
  m_axis_tkeep(1) <= \<const0>\;
  m_axis_tkeep(0) <= \<const0>\;
  m_axis_tuser(21) <= \<const0>\;
  m_axis_tuser(20) <= \<const0>\;
  m_axis_tuser(19) <= \<const0>\;
  m_axis_tuser(18) <= \<const0>\;
  m_axis_tuser(17) <= \<const0>\;
  m_axis_tuser(16) <= \<const0>\;
  m_axis_tuser(15) <= \<const0>\;
  m_axis_tuser(14) <= \<const0>\;
  m_axis_tuser(13) <= \<const0>\;
  m_axis_tuser(12) <= \<const0>\;
  m_axis_tuser(11) <= \<const0>\;
  m_axis_tuser(10) <= \<const0>\;
  m_axis_tuser(9) <= \<const0>\;
  m_axis_tuser(8) <= \<const0>\;
  m_axis_tuser(7) <= \<const0>\;
  m_axis_tuser(6 downto 2) <= \^m_axis_tuser\(6 downto 2);
  m_axis_tuser(1) <= \<const0>\;
  m_axis_tuser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\xdma_0_fifo_generator_v13_1_4__parameterized1\
     port map (
      almost_empty => NLW_U0_almost_empty_UNCONNECTED,
      almost_full => NLW_U0_almost_full_UNCONNECTED,
      axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
      axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
      axi_ar_injectdbiterr => '0',
      axi_ar_injectsbiterr => '0',
      axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
      axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
      axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
      axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
      axi_ar_prog_full_thresh(3 downto 0) => B"0000",
      axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
      axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
      axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
      axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
      axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
      axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
      axi_aw_injectdbiterr => '0',
      axi_aw_injectsbiterr => '0',
      axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
      axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
      axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
      axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
      axi_aw_prog_full_thresh(3 downto 0) => B"0000",
      axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
      axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
      axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
      axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
      axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
      axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
      axi_b_injectdbiterr => '0',
      axi_b_injectsbiterr => '0',
      axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
      axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
      axi_b_prog_empty_thresh(3 downto 0) => B"0000",
      axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
      axi_b_prog_full_thresh(3 downto 0) => B"0000",
      axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
      axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
      axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
      axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
      axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
      axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
      axi_r_injectdbiterr => '0',
      axi_r_injectsbiterr => '0',
      axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
      axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
      axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
      axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
      axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
      axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
      axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
      axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
      axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
      axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
      axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
      axi_w_injectdbiterr => '0',
      axi_w_injectsbiterr => '0',
      axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
      axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
      axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
      axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
      axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
      axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
      axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
      axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
      axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
      axis_data_count(4 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(4 downto 0),
      axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
      axis_injectdbiterr => '0',
      axis_injectsbiterr => '0',
      axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
      axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
      axis_prog_empty_thresh(3 downto 0) => B"0000",
      axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
      axis_prog_full_thresh(3 downto 0) => B"0000",
      axis_rd_data_count(4 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(4 downto 0),
      axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
      axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
      axis_wr_data_count(4 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(4 downto 0),
      backup => '0',
      backup_marker => '0',
      clk => '0',
      data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      din(17 downto 0) => B"000000000000000000",
      dout(17 downto 0) => NLW_U0_dout_UNCONNECTED(17 downto 0),
      empty => NLW_U0_empty_UNCONNECTED,
      full => NLW_U0_full_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      int_clk => '0',
      m_aclk => '0',
      m_aclk_en => '0',
      m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
      m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
      m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
      m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
      m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
      m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
      m_axi_arready => '0',
      m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
      m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
      m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
      m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
      m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
      m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
      m_axi_awready => '0',
      m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
      m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
      m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
      m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
      m_axi_bid(0) => '0',
      m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
      m_axi_bresp(1 downto 0) => B"00",
      m_axi_buser(0) => '0',
      m_axi_bvalid => '0',
      m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rid(0) => '0',
      m_axi_rlast => '0',
      m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
      m_axi_rresp(1 downto 0) => B"00",
      m_axi_ruser(0) => '0',
      m_axi_rvalid => '0',
      m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
      m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
      m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
      m_axi_wready => '0',
      m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
      m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
      m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
      m_axis_tdata(63 downto 0) => m_axis_tdata(63 downto 0),
      m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
      m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
      m_axis_tkeep(7 downto 0) => NLW_U0_m_axis_tkeep_UNCONNECTED(7 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tready => m_axis_tready,
      m_axis_tstrb(7 downto 0) => NLW_U0_m_axis_tstrb_UNCONNECTED(7 downto 0),
      m_axis_tuser(21 downto 7) => NLW_U0_m_axis_tuser_UNCONNECTED(21 downto 7),
      m_axis_tuser(6 downto 2) => \^m_axis_tuser\(6 downto 2),
      m_axis_tuser(1 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(1 downto 0),
      m_axis_tvalid => m_axis_tvalid,
      overflow => NLW_U0_overflow_UNCONNECTED,
      prog_empty => NLW_U0_prog_empty_UNCONNECTED,
      prog_empty_thresh(9 downto 0) => B"0000000000",
      prog_empty_thresh_assert(9 downto 0) => B"0000000000",
      prog_empty_thresh_negate(9 downto 0) => B"0000000000",
      prog_full => NLW_U0_prog_full_UNCONNECTED,
      prog_full_thresh(9 downto 0) => B"0000000000",
      prog_full_thresh_assert(9 downto 0) => B"0000000000",
      prog_full_thresh_negate(9 downto 0) => B"0000000000",
      rd_clk => '0',
      rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
      rd_en => '0',
      rd_rst => '0',
      rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
      rst => '0',
      s_aclk => s_aclk,
      s_aclk_en => '0',
      s_aresetn => s_aresetn,
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arcache(3 downto 0) => B"0000",
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arlock(0) => '0',
      s_axi_arprot(2 downto 0) => B"000",
      s_axi_arqos(3 downto 0) => B"0000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arregion(3 downto 0) => B"0000",
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_aruser(0) => '0',
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awregion(3 downto 0) => B"0000",
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(0) => '0',
      s_axi_awvalid => '0',
      s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wid(0) => '0',
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wuser(0) => '0',
      s_axi_wvalid => '0',
      s_axis_tdata(63 downto 0) => s_axis_tdata(63 downto 0),
      s_axis_tdest(0) => '0',
      s_axis_tid(0) => '0',
      s_axis_tkeep(7) => s_axis_tkeep(7),
      s_axis_tkeep(6 downto 0) => B"0000000",
      s_axis_tlast => s_axis_tlast,
      s_axis_tready => s_axis_tready,
      s_axis_tstrb(7 downto 0) => B"00000000",
      s_axis_tuser(21 downto 9) => B"0000000000000",
      s_axis_tuser(8 downto 0) => s_axis_tuser(8 downto 0),
      s_axis_tvalid => s_axis_tvalid,
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      sleep => '0',
      srst => '0',
      underflow => NLW_U0_underflow_UNCONNECTED,
      valid => NLW_U0_valid_UNCONNECTED,
      wr_ack => NLW_U0_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
      wr_en => '0',
      wr_rst => '0',
      wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_core_top is
  port (
    pl_phy_lnk_up : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    cfg_dcommand : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_lnk_up : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    s_axis_tx_tready : out STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_sel : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    sys_rst_n : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_core_top : entity is "xdma_0_pcie2_ip_core_top";
end xdma_0_xdma_0_pcie2_ip_core_top;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_core_top is
  signal \_inferred__0/store_ltssm_inferred_i_2_n_0\ : STD_LOGIC;
  signal \_inferred__0/store_ltssm_inferred_i_3_n_0\ : STD_LOGIC;
  signal bridge_reset_int : STD_LOGIC;
  signal gt_rx_phy_status_q : STD_LOGIC;
  signal gt_rxelecidle_q : STD_LOGIC;
  signal gt_top_i_n_0 : STD_LOGIC;
  signal gt_top_i_n_12 : STD_LOGIC;
  signal gt_top_i_n_13 : STD_LOGIC;
  signal gt_top_i_n_16 : STD_LOGIC;
  signal gt_top_i_n_49 : STD_LOGIC;
  signal gt_top_i_n_50 : STD_LOGIC;
  signal gt_top_i_n_51 : STD_LOGIC;
  signal gt_top_i_n_52 : STD_LOGIC;
  signal gt_top_i_n_53 : STD_LOGIC;
  signal gt_top_i_n_54 : STD_LOGIC;
  signal gt_top_i_n_8 : STD_LOGIC;
  signal \^int_userclk1_out\ : STD_LOGIC;
  signal \ltssm_reg1_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[3]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[4]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[5]_srl2_n_0\ : STD_LOGIC;
  signal ltssm_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal pcie_block_i_i_10_n_0 : STD_LOGIC;
  signal pcie_block_i_i_11_n_0 : STD_LOGIC;
  signal pcie_block_i_i_12_n_0 : STD_LOGIC;
  signal pcie_block_i_i_9_n_0 : STD_LOGIC;
  signal pcie_top_i_n_13 : STD_LOGIC;
  signal pcie_top_i_n_199 : STD_LOGIC;
  signal pcie_top_i_n_200 : STD_LOGIC;
  signal pcie_top_i_n_201 : STD_LOGIC;
  signal pcie_top_i_n_202 : STD_LOGIC;
  signal pcie_top_i_n_203 : STD_LOGIC;
  signal pcie_top_i_n_204 : STD_LOGIC;
  signal phy_rdy_n : STD_LOGIC;
  signal pipe_rx0_chanisaligned_gt : STD_LOGIC;
  signal pipe_rx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx0_polarity_gt : STD_LOGIC;
  signal pipe_rx0_valid_gt : STD_LOGIC;
  signal pipe_rx1_chanisaligned_gt : STD_LOGIC;
  signal pipe_rx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx1_polarity_gt : STD_LOGIC;
  signal pipe_rx1_valid_gt : STD_LOGIC;
  signal pipe_tx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx0_compliance_gt : STD_LOGIC;
  signal pipe_tx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx0_elec_idle_gt : STD_LOGIC;
  signal pipe_tx0_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_compliance_gt : STD_LOGIC;
  signal pipe_tx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx1_elec_idle_gt : STD_LOGIC;
  signal pipe_tx1_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx_deemph_gt : STD_LOGIC;
  signal pipe_tx_margin_gt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_tx_rate_gt : STD_LOGIC;
  signal pipe_tx_rcvr_det_gt : STD_LOGIC;
  signal \^pl_phy_lnk_up\ : STD_LOGIC;
  signal pl_phy_lnk_up_sync : STD_LOGIC;
  signal pl_phy_lnk_up_wire : STD_LOGIC;
  signal pl_received_hot_rst_q_reg_n_0 : STD_LOGIC;
  signal pl_received_hot_rst_sync : STD_LOGIC;
  signal pl_received_hot_rst_wire : STD_LOGIC;
  signal store_ltssm : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of store_ltssm : signal is std.standard.true;
  signal sys_or_hot_rst : STD_LOGIC;
  signal trn_lnk_up : STD_LOGIC;
  signal user_lnk_up_int : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of user_lnk_up_int : signal is "true";
  attribute async_reg : string;
  attribute async_reg of user_lnk_up_int : signal is "true";
  signal user_lnk_up_mux : STD_LOGIC;
  attribute async_reg of user_lnk_up_mux : signal is "true";
  signal \^user_reset_out\ : STD_LOGIC;
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of phy_lnk_up_cdc : label is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of phy_lnk_up_cdc : label is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of phy_lnk_up_cdc : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of phy_lnk_up_cdc : label is 0;
  attribute VERSION : integer;
  attribute VERSION of phy_lnk_up_cdc : label is 0;
  attribute XPM_CDC : string;
  attribute XPM_CDC of phy_lnk_up_cdc : label is "SINGLE";
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of phy_lnk_up_cdc : label is "TRUE";
  attribute DEST_SYNC_FF of pl_received_hot_rst_cdc : label is 2;
  attribute INIT_SYNC_FF of pl_received_hot_rst_cdc : label is 0;
  attribute SIM_ASSERT_CHK of pl_received_hot_rst_cdc : label is 0;
  attribute SRC_INPUT_REG of pl_received_hot_rst_cdc : label is 0;
  attribute VERSION of pl_received_hot_rst_cdc : label is 0;
  attribute XPM_CDC of pl_received_hot_rst_cdc : label is "SINGLE";
  attribute XPM_MODULE of pl_received_hot_rst_cdc : label is "TRUE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of user_lnk_up_int_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of user_lnk_up_int_reg : label is "yes";
  attribute ASYNC_REG_boolean of user_lnk_up_mux_reg : label is std.standard.true;
  attribute KEEP of user_lnk_up_mux_reg : label is "yes";
begin
  int_userclk1_out <= \^int_userclk1_out\;
  pl_phy_lnk_up <= \^pl_phy_lnk_up\;
  user_lnk_up <= user_lnk_up_int;
  user_reset_out <= \^user_reset_out\;
\_inferred__0/store_ltssm_inferred_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \_inferred__0/store_ltssm_inferred_i_2_n_0\,
      I1 => \_inferred__0/store_ltssm_inferred_i_3_n_0\,
      O => store_ltssm
    );
\_inferred__0/store_ltssm_inferred_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => ltssm_reg2(0),
      I1 => pcie_top_i_n_204,
      I2 => pcie_top_i_n_202,
      I3 => ltssm_reg2(2),
      I4 => pcie_top_i_n_203,
      I5 => ltssm_reg2(1),
      O => \_inferred__0/store_ltssm_inferred_i_2_n_0\
    );
\_inferred__0/store_ltssm_inferred_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => ltssm_reg2(3),
      I1 => pcie_top_i_n_201,
      I2 => pcie_top_i_n_199,
      I3 => ltssm_reg2(5),
      I4 => pcie_top_i_n_200,
      I5 => ltssm_reg2(4),
      O => \_inferred__0/store_ltssm_inferred_i_3_n_0\
    );
gt_top_i: entity work.xdma_0_xdma_0_pcie2_ip_gt_top
     port map (
      CLK => \^int_userclk1_out\,
      D(0) => pipe_tx_rate_gt,
      Q(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0),
      TXCHARDISPMODE(0) => pipe_tx0_compliance_gt,
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rx_phy_status_q_reg => gt_top_i_n_12,
      \gt_rx_status_q_reg[2]\(2) => gt_top_i_n_49,
      \gt_rx_status_q_reg[2]\(1) => gt_top_i_n_50,
      \gt_rx_status_q_reg[2]\(0) => gt_top_i_n_51,
      \gt_rx_status_q_reg[2]_0\(2) => gt_top_i_n_52,
      \gt_rx_status_q_reg[2]_0\(1) => gt_top_i_n_53,
      \gt_rx_status_q_reg[2]_0\(0) => gt_top_i_n_54,
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0),
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => pipe_rx0_data_gt(15 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => pipe_rx1_data_gt(15 downto 0),
      gt_rxelecidle_q => gt_rxelecidle_q,
      gt_rxelecidle_q_reg => gt_top_i_n_13,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pclk_sel_reg => gt_top_i_n_0,
      phy_rdy_n => phy_rdy_n,
      phy_rdy_n_int_reg_0 => gt_top_i_n_16,
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_rx0_valid_gt => pipe_rx0_valid_gt,
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_rx1_valid_gt => pipe_rx1_valid_gt,
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt,
      pl_ltssm_state(5) => pcie_top_i_n_199,
      pl_ltssm_state(4) => pcie_top_i_n_200,
      pl_ltssm_state(3) => pcie_top_i_n_201,
      pl_ltssm_state(2) => pcie_top_i_n_202,
      pl_ltssm_state(1) => pcie_top_i_n_203,
      pl_ltssm_state(0) => pcie_top_i_n_204,
      rdy_reg1_reg(2 downto 0) => pipe_tx_margin_gt(2 downto 0),
      rdy_reg1_reg_0(15 downto 0) => pipe_tx0_data_gt(15 downto 0),
      rdy_reg1_reg_1(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0),
      rdy_reg1_reg_2(1 downto 0) => pipe_tx1_powerdown_gt(1 downto 0),
      rdy_reg1_reg_3(15 downto 0) => pipe_tx1_data_gt(15 downto 0),
      rdy_reg1_reg_4(1 downto 0) => pipe_tx1_char_is_k_gt(1 downto 0),
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      sys_rst_n_0 => gt_top_i_n_8,
      txcompliance_reg1_reg(0) => pipe_tx1_compliance_gt
    );
\ltssm_reg1_reg[0]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_204,
      Q => \ltssm_reg1_reg[0]_srl2_n_0\
    );
\ltssm_reg1_reg[1]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_203,
      Q => \ltssm_reg1_reg[1]_srl2_n_0\
    );
\ltssm_reg1_reg[2]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_202,
      Q => \ltssm_reg1_reg[2]_srl2_n_0\
    );
\ltssm_reg1_reg[3]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_201,
      Q => \ltssm_reg1_reg[3]_srl2_n_0\
    );
\ltssm_reg1_reg[4]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_200,
      Q => \ltssm_reg1_reg[4]_srl2_n_0\
    );
\ltssm_reg1_reg[5]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => gt_top_i_n_0,
      D => pcie_top_i_n_199,
      Q => \ltssm_reg1_reg[5]_srl2_n_0\
    );
\ltssm_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[0]_srl2_n_0\,
      Q => ltssm_reg2(0),
      R => '0'
    );
\ltssm_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[1]_srl2_n_0\,
      Q => ltssm_reg2(1),
      R => '0'
    );
\ltssm_reg2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[2]_srl2_n_0\,
      Q => ltssm_reg2(2),
      R => '0'
    );
\ltssm_reg2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[3]_srl2_n_0\,
      Q => ltssm_reg2(3),
      R => '0'
    );
\ltssm_reg2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[4]_srl2_n_0\,
      Q => ltssm_reg2(4),
      R => '0'
    );
\ltssm_reg2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_top_i_n_0,
      CE => '1',
      D => \ltssm_reg1_reg[5]_srl2_n_0\,
      Q => ltssm_reg2(5),
      R => '0'
    );
pcie_block_i_i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(2),
      O => pcie_block_i_i_10_n_0
    );
pcie_block_i_i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(1),
      O => pcie_block_i_i_11_n_0
    );
pcie_block_i_i_12: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(0),
      O => pcie_block_i_i_12_n_0
    );
pcie_block_i_i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(3),
      O => pcie_block_i_i_9_n_0
    );
pcie_top_i: entity work.xdma_0_xdma_0_pcie2_ip_pcie_top
     port map (
      CLK => \^int_userclk1_out\,
      D(0) => pipe_tx_rate_gt,
      Q(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0),
      SR(0) => phy_rdy_n,
      TXCHARDISPMODE(0) => pipe_tx0_compliance_gt,
      bridge_reset_int => bridge_reset_int,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(0) => cfg_command(0),
      cfg_dcommand(5 downto 0) => cfg_dcommand(5 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(4 downto 0) => cfg_interrupt_di(4 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_mgmt_byte_en_n(3) => pcie_block_i_i_9_n_0,
      cfg_mgmt_byte_en_n(2) => pcie_block_i_i_10_n_0,
      cfg_mgmt_byte_en_n(1) => pcie_block_i_i_11_n_0,
      cfg_mgmt_byte_en_n(0) => pcie_block_i_i_12_n_0,
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_to_turnoff => cfg_to_turnoff,
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_sel(0) => fc_sel(0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rxelecidle_q => gt_rxelecidle_q,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_reg => m_axis_rx_tvalid,
      \out\ => user_lnk_up_int,
      pipe_rx0_chanisaligned_gt => pipe_rx0_chanisaligned_gt,
      pipe_rx0_polarity_gt => pipe_rx0_polarity_gt,
      pipe_rx0_valid_gt => pipe_rx0_valid_gt,
      pipe_rx1_chanisaligned_gt => pipe_rx1_chanisaligned_gt,
      pipe_rx1_polarity_gt => pipe_rx1_polarity_gt,
      pipe_rx1_valid_gt => pipe_rx1_valid_gt,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx1_data_gt(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx0_data_gt(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => gt_top_i_n_13,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => gt_top_i_n_12,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2) => gt_top_i_n_49,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(1) => gt_top_i_n_50,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(0) => gt_top_i_n_51,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2) => gt_top_i_n_52,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1) => gt_top_i_n_53,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0) => gt_top_i_n_54,
      \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\(1 downto 0) => pipe_tx1_char_is_k_gt(1 downto 0),
      \pipe_stages_1.pipe_tx_compliance_q_reg\(0) => pipe_tx1_compliance_gt,
      \pipe_stages_1.pipe_tx_data_q_reg[15]\(15 downto 0) => pipe_tx0_data_gt(15 downto 0),
      \pipe_stages_1.pipe_tx_data_q_reg[15]_0\(15 downto 0) => pipe_tx1_data_gt(15 downto 0),
      \pipe_stages_1.pipe_tx_deemph_q_reg\ => gt_top_i_n_0,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => pipe_tx_margin_gt(2 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]\(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0),
      \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0\(1 downto 0) => pipe_tx1_powerdown_gt(1 downto 0),
      pipe_tx0_elec_idle_gt => pipe_tx0_elec_idle_gt,
      pipe_tx1_elec_idle_gt => pipe_tx1_elec_idle_gt,
      pipe_tx_deemph_gt => pipe_tx_deemph_gt,
      pipe_tx_rcvr_det_gt => pipe_tx_rcvr_det_gt,
      pl_ltssm_state(5) => pcie_top_i_n_199,
      pl_ltssm_state(4) => pcie_top_i_n_200,
      pl_ltssm_state(3) => pcie_top_i_n_201,
      pl_ltssm_state(2) => pcie_top_i_n_202,
      pl_ltssm_state(1) => pcie_top_i_n_203,
      pl_ltssm_state(0) => pcie_top_i_n_204,
      pl_phy_lnk_up => \^pl_phy_lnk_up\,
      pl_received_hot_rst => pl_received_hot_rst_wire,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      src_in => pl_phy_lnk_up_wire,
      sys_rst_n => gt_top_i_n_16,
      \throttle_ctl_pipeline.reg_tkeep_reg[7]\ => \^user_reset_out\,
      tready_thrtl_reg => s_axis_tx_tready,
      trn_lnk_up => trn_lnk_up,
      user_reset_int_reg => pcie_top_i_n_13
    );
phy_lnk_up_cdc: entity work.\xdma_0_xpm_cdc_single__parameterized0__2\
     port map (
      dest_clk => \^int_userclk1_out\,
      dest_out => pl_phy_lnk_up_sync,
      src_clk => '0',
      src_in => pl_phy_lnk_up_wire
    );
pl_phy_lnk_up_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pl_phy_lnk_up_sync,
      Q => \^pl_phy_lnk_up\,
      R => gt_top_i_n_8
    );
pl_received_hot_rst_cdc: entity work.\xdma_0_xpm_cdc_single__parameterized0\
     port map (
      dest_clk => \^int_userclk1_out\,
      dest_out => pl_received_hot_rst_sync,
      src_clk => '0',
      src_in => pl_received_hot_rst_wire
    );
pl_received_hot_rst_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pl_received_hot_rst_sync,
      Q => pl_received_hot_rst_q_reg_n_0,
      R => gt_top_i_n_8
    );
user_lnk_up_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => trn_lnk_up,
      Q => user_lnk_up_int,
      R => gt_top_i_n_8
    );
user_lnk_up_mux_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => user_lnk_up_int,
      Q => user_lnk_up_mux,
      R => gt_top_i_n_8
    );
user_reset_int_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pcie_top_i_n_13,
      PRE => sys_or_hot_rst,
      Q => bridge_reset_int
    );
user_reset_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => pl_received_hot_rst_q_reg_n_0,
      I1 => sys_rst_n,
      O => sys_or_hot_rst
    );
user_reset_out_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => bridge_reset_int,
      PRE => sys_or_hot_rst,
      Q => \^user_reset_out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 71 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be : entity is "xdma_v4_1_8_blk_mem_64_noreg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be : entity is "xdma_v4_1_8_blk_mem_64_noreg_be";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be : entity is "blk_mem_gen_v8_4_4,Vivado 2020.2";
end xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 1;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "1";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     7.638025 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "xdma_v4_1_8_blk_mem_64_noreg_be.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 72;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 72;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 1;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 1;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 8;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 8;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 72;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 72;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute X_INTERFACE_INFO of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.\xdma_0_blk_mem_gen_v8_4_4__parameterized1\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(71) => '0',
      dina(70 downto 63) => dina(70 downto 63),
      dina(62) => '0',
      dina(61 downto 54) => dina(61 downto 54),
      dina(53) => '0',
      dina(52 downto 45) => dina(52 downto 45),
      dina(44) => '0',
      dina(43 downto 36) => dina(43 downto 36),
      dina(35) => '0',
      dina(34 downto 27) => dina(34 downto 27),
      dina(26) => '0',
      dina(25 downto 18) => dina(25 downto 18),
      dina(17) => '0',
      dina(16 downto 9) => dina(16 downto 9),
      dina(8) => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(71 downto 0) => NLW_U0_douta_UNCONNECTED(71 downto 0),
      doutb(71 downto 0) => doutb(71 downto 0),
      eccpipece => '0',
      ena => '1',
      enb => '1',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(71 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(71 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(7) => wea(7),
      wea(6 downto 0) => B"0000000",
      web(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 71 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ : entity is "xdma_v4_1_8_blk_mem_64_noreg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ : entity is "xdma_v4_1_8_blk_mem_64_noreg_be";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ : entity is "blk_mem_gen_v8_4_4,Vivado 2020.2";
end \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 70 downto 0 );
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 1;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "1";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     7.638025 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "xdma_v4_1_8_blk_mem_64_noreg_be.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 72;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 72;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 1;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 1;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 8;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 8;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 72;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 72;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute X_INTERFACE_INFO of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
  doutb(71) <= \<const0>\;
  doutb(70 downto 63) <= \^doutb\(70 downto 63);
  doutb(62) <= \<const0>\;
  doutb(61 downto 54) <= \^doutb\(61 downto 54);
  doutb(53) <= \<const0>\;
  doutb(52 downto 45) <= \^doutb\(52 downto 45);
  doutb(44) <= \<const0>\;
  doutb(43 downto 36) <= \^doutb\(43 downto 36);
  doutb(35) <= \<const0>\;
  doutb(34 downto 27) <= \^doutb\(34 downto 27);
  doutb(26) <= \<const0>\;
  doutb(25 downto 18) <= \^doutb\(25 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16 downto 9) <= \^doutb\(16 downto 9);
  doutb(8) <= \<const0>\;
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\xdma_0_blk_mem_gen_v8_4_4__parameterized1__2\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(71) => '0',
      dina(70 downto 63) => dina(70 downto 63),
      dina(62) => '0',
      dina(61 downto 54) => dina(61 downto 54),
      dina(53) => '0',
      dina(52 downto 45) => dina(52 downto 45),
      dina(44) => '0',
      dina(43 downto 36) => dina(43 downto 36),
      dina(35) => '0',
      dina(34 downto 27) => dina(34 downto 27),
      dina(26) => '0',
      dina(25 downto 18) => dina(25 downto 18),
      dina(17) => '0',
      dina(16 downto 9) => dina(16 downto 9),
      dina(8) => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(71 downto 0) => NLW_U0_douta_UNCONNECTED(71 downto 0),
      doutb(71) => NLW_U0_doutb_UNCONNECTED(71),
      doutb(70 downto 63) => \^doutb\(70 downto 63),
      doutb(62) => NLW_U0_doutb_UNCONNECTED(62),
      doutb(61 downto 54) => \^doutb\(61 downto 54),
      doutb(53) => NLW_U0_doutb_UNCONNECTED(53),
      doutb(52 downto 45) => \^doutb\(52 downto 45),
      doutb(44) => NLW_U0_doutb_UNCONNECTED(44),
      doutb(43 downto 36) => \^doutb\(43 downto 36),
      doutb(35) => NLW_U0_doutb_UNCONNECTED(35),
      doutb(34 downto 27) => \^doutb\(34 downto 27),
      doutb(26) => NLW_U0_doutb_UNCONNECTED(26),
      doutb(25 downto 18) => \^doutb\(25 downto 18),
      doutb(17) => NLW_U0_doutb_UNCONNECTED(17),
      doutb(16 downto 9) => \^doutb\(16 downto 9),
      doutb(8) => NLW_U0_doutb_UNCONNECTED(8),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      eccpipece => '0',
      ena => '1',
      enb => '1',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(71 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(71 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(7) => wea(7),
      wea(6 downto 0) => B"0000000",
      web(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_v4_1_8_blk_mem_64_reg_be is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 71 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0_xdma_v4_1_8_blk_mem_64_reg_be : entity is "xdma_v4_1_8_blk_mem_64_reg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_xdma_v4_1_8_blk_mem_64_reg_be : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_v4_1_8_blk_mem_64_reg_be : entity is "xdma_v4_1_8_blk_mem_64_reg_be";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0_xdma_v4_1_8_blk_mem_64_reg_be : entity is "blk_mem_gen_v8_4_4,Vivado 2020.2";
end xdma_0_xdma_v4_1_8_blk_mem_64_reg_be;

architecture STRUCTURE of xdma_0_xdma_v4_1_8_blk_mem_64_reg_be is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 70 downto 0 );
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 1;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "1";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     7.638025 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "xdma_v4_1_8_blk_mem_64_reg_be.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 72;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 72;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 1;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 1;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 8;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 8;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 72;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 72;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute X_INTERFACE_INFO of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
  doutb(71) <= \<const0>\;
  doutb(70 downto 63) <= \^doutb\(70 downto 63);
  doutb(62) <= \<const0>\;
  doutb(61 downto 54) <= \^doutb\(61 downto 54);
  doutb(53) <= \<const0>\;
  doutb(52 downto 45) <= \^doutb\(52 downto 45);
  doutb(44) <= \<const0>\;
  doutb(43 downto 36) <= \^doutb\(43 downto 36);
  doutb(35) <= \<const0>\;
  doutb(34 downto 27) <= \^doutb\(34 downto 27);
  doutb(26) <= \<const0>\;
  doutb(25 downto 18) <= \^doutb\(25 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16 downto 9) <= \^doutb\(16 downto 9);
  doutb(8) <= \<const0>\;
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.xdma_0_blk_mem_gen_v8_4_4
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(71 downto 0) => dina(71 downto 0),
      dinb(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(71 downto 0) => NLW_U0_douta_UNCONNECTED(71 downto 0),
      doutb(71) => NLW_U0_doutb_UNCONNECTED(71),
      doutb(70 downto 63) => \^doutb\(70 downto 63),
      doutb(62) => NLW_U0_doutb_UNCONNECTED(62),
      doutb(61 downto 54) => \^doutb\(61 downto 54),
      doutb(53) => NLW_U0_doutb_UNCONNECTED(53),
      doutb(52 downto 45) => \^doutb\(52 downto 45),
      doutb(44) => NLW_U0_doutb_UNCONNECTED(44),
      doutb(43 downto 36) => \^doutb\(43 downto 36),
      doutb(35) => NLW_U0_doutb_UNCONNECTED(35),
      doutb(34 downto 27) => \^doutb\(34 downto 27),
      doutb(26) => NLW_U0_doutb_UNCONNECTED(26),
      doutb(25 downto 18) => \^doutb\(25 downto 18),
      doutb(17) => NLW_U0_doutb_UNCONNECTED(17),
      doutb(16 downto 9) => \^doutb\(16 downto 9),
      doutb(8) => NLW_U0_doutb_UNCONNECTED(8),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      eccpipece => '0',
      ena => '1',
      enb => '1',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(71 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(71 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(7) => wea(7),
      wea(6 downto 0) => B"0000000",
      web(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ is
  port (
    clka : in STD_LOGIC;
    ena : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 71 downto 0 );
    clkb : in STD_LOGIC;
    enb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 71 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ : entity is "xdma_v4_1_8_blk_mem_64_reg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ : entity is "xdma_v4_1_8_blk_mem_64_reg_be";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ : entity is "blk_mem_gen_v8_4_4,Vivado 2020.2";
end \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\ is
  signal \<const0>\ : STD_LOGIC;
  signal \^doutb\ : STD_LOGIC_VECTOR ( 70 downto 0 );
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 8 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 9;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 9;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 1;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "1";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     7.638025 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 1;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 1;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "xdma_v4_1_8_blk_mem_64_reg_be.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 512;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 512;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 72;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 72;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 1;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 1;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 8;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 8;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 512;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 512;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 72;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 72;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute DowngradeIPIdentifiedWarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
  attribute X_INTERFACE_INFO of enb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
  doutb(71) <= \<const0>\;
  doutb(70 downto 63) <= \^doutb\(70 downto 63);
  doutb(62) <= \<const0>\;
  doutb(61 downto 54) <= \^doutb\(61 downto 54);
  doutb(53) <= \<const0>\;
  doutb(52 downto 45) <= \^doutb\(52 downto 45);
  doutb(44) <= \<const0>\;
  doutb(43 downto 36) <= \^doutb\(43 downto 36);
  doutb(35) <= \<const0>\;
  doutb(34 downto 27) <= \^doutb\(34 downto 27);
  doutb(26) <= \<const0>\;
  doutb(25 downto 18) <= \^doutb\(25 downto 18);
  doutb(17) <= \<const0>\;
  doutb(16 downto 9) <= \^doutb\(16 downto 9);
  doutb(8) <= \<const0>\;
  doutb(7 downto 0) <= \^doutb\(7 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.\xdma_0_blk_mem_gen_v8_4_4__11\
     port map (
      addra(8 downto 0) => addra(8 downto 0),
      addrb(8 downto 0) => addrb(8 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(71) => '0',
      dina(70 downto 63) => dina(70 downto 63),
      dina(62) => '0',
      dina(61 downto 54) => dina(61 downto 54),
      dina(53) => '0',
      dina(52 downto 45) => dina(52 downto 45),
      dina(44) => '0',
      dina(43 downto 36) => dina(43 downto 36),
      dina(35) => '0',
      dina(34 downto 27) => dina(34 downto 27),
      dina(26) => '0',
      dina(25 downto 18) => dina(25 downto 18),
      dina(17) => '0',
      dina(16 downto 9) => dina(16 downto 9),
      dina(8) => '0',
      dina(7 downto 0) => dina(7 downto 0),
      dinb(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      douta(71 downto 0) => NLW_U0_douta_UNCONNECTED(71 downto 0),
      doutb(71) => NLW_U0_doutb_UNCONNECTED(71),
      doutb(70 downto 63) => \^doutb\(70 downto 63),
      doutb(62) => NLW_U0_doutb_UNCONNECTED(62),
      doutb(61 downto 54) => \^doutb\(61 downto 54),
      doutb(53) => NLW_U0_doutb_UNCONNECTED(53),
      doutb(52 downto 45) => \^doutb\(52 downto 45),
      doutb(44) => NLW_U0_doutb_UNCONNECTED(44),
      doutb(43 downto 36) => \^doutb\(43 downto 36),
      doutb(35) => NLW_U0_doutb_UNCONNECTED(35),
      doutb(34 downto 27) => \^doutb\(34 downto 27),
      doutb(26) => NLW_U0_doutb_UNCONNECTED(26),
      doutb(25 downto 18) => \^doutb\(25 downto 18),
      doutb(17) => NLW_U0_doutb_UNCONNECTED(17),
      doutb(16 downto 9) => \^doutb\(16 downto 9),
      doutb(8) => NLW_U0_doutb_UNCONNECTED(8),
      doutb(7 downto 0) => \^doutb\(7 downto 0),
      eccpipece => '0',
      ena => '1',
      enb => '1',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
      s_axi_rdata(71 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(71 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(71 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(7) => wea(7),
      wea(6 downto 0) => B"0000000",
      web(7 downto 0) => B"00000000"
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip_pcie2_top is
  port (
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_out_slave : out STD_LOGIC;
    int_pipe_rxusrclk_out : out STD_LOGIC;
    int_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_dclk_out : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    int_userclk2_out : out STD_LOGIC;
    int_oobclk_out : out STD_LOGIC;
    int_mmcm_lock_out : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_in : in STD_LOGIC;
    pipe_rxusrclk_in : in STD_LOGIC;
    pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_dclk_in : in STD_LOGIC;
    pipe_userclk1_in : in STD_LOGIC;
    pipe_userclk2_in : in STD_LOGIC;
    pipe_oobclk_in : in STD_LOGIC;
    pipe_mmcm_lock_in : in STD_LOGIC;
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_gen3_out : out STD_LOGIC;
    qpll_drp_crscode : in STD_LOGIC_VECTOR ( 11 downto 0 );
    qpll_drp_fsm : in STD_LOGIC_VECTOR ( 17 downto 0 );
    qpll_drp_done : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_reset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplllock : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutrefclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplld : out STD_LOGIC;
    qpll_qpllreset : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_clk : out STD_LOGIC;
    qpll_drp_rst_n : out STD_LOGIC;
    qpll_drp_ovrd : out STD_LOGIC;
    qpll_drp_gen3 : out STD_LOGIC;
    qpll_drp_start : out STD_LOGIC;
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_err_drop : out STD_LOGIC;
    tx_cfg_req : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_acs : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_directed_change_done : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_rdy : out STD_LOGIC;
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    startup_eos_in : in STD_LOGIC;
    startup_cfgclk : out STD_LOGIC;
    startup_cfgmclk : out STD_LOGIC;
    startup_eos : out STD_LOGIC;
    startup_preq : out STD_LOGIC;
    startup_clk : in STD_LOGIC;
    startup_gsr : in STD_LOGIC;
    startup_gts : in STD_LOGIC;
    startup_keyclearb : in STD_LOGIC;
    startup_pack : in STD_LOGIC;
    startup_usrcclko : in STD_LOGIC;
    startup_usrcclkts : in STD_LOGIC;
    startup_usrdoneo : in STD_LOGIC;
    startup_usrdonets : in STD_LOGIC;
    icap_clk : in STD_LOGIC;
    icap_csib : in STD_LOGIC;
    icap_rdwrb : in STD_LOGIC;
    icap_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    icap_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_txprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_txprbsforceerr : in STD_LOGIC;
    pipe_rxprbscntreset : in STD_LOGIC;
    pipe_loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    pipe_sync_fsm_tx : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_drp_fsm : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_rst_idle : out STD_LOGIC;
    pipe_qrst_idle : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 29 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qpll_lock : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxpmaresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxsyncdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drpclk : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    common_commands_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rx_0_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_1_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_2_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_3_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_4_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_5_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_6_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_7_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    common_commands_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_tx_0_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_1_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_2_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_3_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_4_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_5_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_6_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_7_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC
  );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 64;
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "yes";
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 2;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "xdma_0_pcie2_ip_pcie2_top";
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute REDUCE_OOB_FREQ : string;
  attribute REDUCE_OOB_FREQ of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FFFF0000";
  attribute bar_1 : string;
  attribute bar_1 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FFF00000";
  attribute bar_2 : string;
  attribute bar_2 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_component_name : string;
  attribute c_component_name of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "xdma_0_pcie2_ip";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "461";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "36";
  attribute c_fc_npd : string;
  attribute c_fc_npd of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "24";
  attribute c_fc_nph : string;
  attribute c_fc_nph of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "12";
  attribute c_fc_pd : string;
  attribute c_fc_pd of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "437";
  attribute c_fc_ph : string;
  attribute c_fc_ph of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "32";
  attribute c_gen1 : string;
  attribute c_gen1 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "1'b1";
  attribute c_header_type : string;
  attribute c_header_type of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_msi : string;
  attribute c_msi of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rcb : string;
  attribute c_rcb of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "NONE";
  attribute cap_ver : string;
  attribute cap_ver of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
  attribute class_code : string;
  attribute class_code of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "070001";
  attribute cmps : string;
  attribute cmps of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute cost_table : integer;
  attribute cost_table of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 1;
  attribute d1_sup : string;
  attribute d1_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute d2_sup : string;
  attribute d2_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute dev_id : string;
  attribute dev_id of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "7022";
  attribute dev_port_type : string;
  attribute dev_port_type of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute dsi : string;
  attribute dsi of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute int_pin : string;
  attribute int_pin of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "1";
  attribute intx : string;
  attribute intx of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "2";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "000010";
  attribute mps : string;
  attribute mps of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is 2;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pme_sup : string;
  attribute pme_sup of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute rev_id : string;
  attribute rev_id of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00";
  attribute slot_clk : string;
  attribute slot_clk of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "10EE";
  attribute ven_id : string;
  attribute ven_id of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of xdma_0_xdma_0_pcie2_ip_pcie2_top : entity is "00000000";
end xdma_0_xdma_0_pcie2_ip_pcie2_top;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip_pcie2_top is
  signal \<const0>\ : STD_LOGIC;
  signal \^cfg_command\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 5 );
  signal \^m_axis_rx_tkeep\ : STD_LOGIC_VECTOR ( 6 to 6 );
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 );
begin
  cfg_aer_ecrc_check_en <= \<const0>\;
  cfg_aer_ecrc_gen_en <= \<const0>\;
  cfg_aer_rooterr_corr_err_received <= \<const0>\;
  cfg_aer_rooterr_corr_err_reporting_en <= \<const0>\;
  cfg_aer_rooterr_fatal_err_received <= \<const0>\;
  cfg_aer_rooterr_fatal_err_reporting_en <= \<const0>\;
  cfg_aer_rooterr_non_fatal_err_received <= \<const0>\;
  cfg_aer_rooterr_non_fatal_err_reporting_en <= \<const0>\;
  cfg_bridge_serr_en <= \<const0>\;
  cfg_command(15) <= \<const0>\;
  cfg_command(14) <= \<const0>\;
  cfg_command(13) <= \<const0>\;
  cfg_command(12) <= \<const0>\;
  cfg_command(11) <= \<const0>\;
  cfg_command(10) <= \<const0>\;
  cfg_command(9) <= \<const0>\;
  cfg_command(8) <= \<const0>\;
  cfg_command(7) <= \<const0>\;
  cfg_command(6) <= \<const0>\;
  cfg_command(5) <= \<const0>\;
  cfg_command(4) <= \<const0>\;
  cfg_command(3) <= \<const0>\;
  cfg_command(2) <= \^cfg_command\(2);
  cfg_command(1) <= \<const0>\;
  cfg_command(0) <= \<const0>\;
  cfg_dcommand(15) <= \<const0>\;
  cfg_dcommand(14 downto 12) <= \^cfg_dcommand\(14 downto 12);
  cfg_dcommand(11) <= \<const0>\;
  cfg_dcommand(10) <= \<const0>\;
  cfg_dcommand(9) <= \<const0>\;
  cfg_dcommand(8) <= \<const0>\;
  cfg_dcommand(7 downto 5) <= \^cfg_dcommand\(7 downto 5);
  cfg_dcommand(4) <= \<const0>\;
  cfg_dcommand(3) <= \<const0>\;
  cfg_dcommand(2) <= \<const0>\;
  cfg_dcommand(1) <= \<const0>\;
  cfg_dcommand(0) <= \<const0>\;
  cfg_dcommand2(15) <= \<const0>\;
  cfg_dcommand2(14) <= \<const0>\;
  cfg_dcommand2(13) <= \<const0>\;
  cfg_dcommand2(12) <= \<const0>\;
  cfg_dcommand2(11) <= \<const0>\;
  cfg_dcommand2(10) <= \<const0>\;
  cfg_dcommand2(9) <= \<const0>\;
  cfg_dcommand2(8) <= \<const0>\;
  cfg_dcommand2(7) <= \<const0>\;
  cfg_dcommand2(6) <= \<const0>\;
  cfg_dcommand2(5) <= \<const0>\;
  cfg_dcommand2(4) <= \<const0>\;
  cfg_dcommand2(3) <= \<const0>\;
  cfg_dcommand2(2) <= \<const0>\;
  cfg_dcommand2(1) <= \<const0>\;
  cfg_dcommand2(0) <= \<const0>\;
  cfg_dstatus(15) <= \<const0>\;
  cfg_dstatus(14) <= \<const0>\;
  cfg_dstatus(13) <= \<const0>\;
  cfg_dstatus(12) <= \<const0>\;
  cfg_dstatus(11) <= \<const0>\;
  cfg_dstatus(10) <= \<const0>\;
  cfg_dstatus(9) <= \<const0>\;
  cfg_dstatus(8) <= \<const0>\;
  cfg_dstatus(7) <= \<const0>\;
  cfg_dstatus(6) <= \<const0>\;
  cfg_dstatus(5) <= \<const0>\;
  cfg_dstatus(4) <= \<const0>\;
  cfg_dstatus(3) <= \<const0>\;
  cfg_dstatus(2) <= \<const0>\;
  cfg_dstatus(1) <= \<const0>\;
  cfg_dstatus(0) <= \<const0>\;
  cfg_err_aer_headerlog_set <= \<const0>\;
  cfg_err_cpl_rdy <= \<const0>\;
  cfg_interrupt_do(7) <= \<const0>\;
  cfg_interrupt_do(6) <= \<const0>\;
  cfg_interrupt_do(5) <= \<const0>\;
  cfg_interrupt_do(4) <= \<const0>\;
  cfg_interrupt_do(3) <= \<const0>\;
  cfg_interrupt_do(2) <= \<const0>\;
  cfg_interrupt_do(1) <= \<const0>\;
  cfg_interrupt_do(0) <= \<const0>\;
  cfg_interrupt_msixenable <= \<const0>\;
  cfg_interrupt_msixfm <= \<const0>\;
  cfg_lcommand(15) <= \<const0>\;
  cfg_lcommand(14) <= \<const0>\;
  cfg_lcommand(13) <= \<const0>\;
  cfg_lcommand(12) <= \<const0>\;
  cfg_lcommand(11) <= \<const0>\;
  cfg_lcommand(10) <= \<const0>\;
  cfg_lcommand(9) <= \<const0>\;
  cfg_lcommand(8) <= \<const0>\;
  cfg_lcommand(7) <= \<const0>\;
  cfg_lcommand(6) <= \<const0>\;
  cfg_lcommand(5) <= \<const0>\;
  cfg_lcommand(4) <= \<const0>\;
  cfg_lcommand(3) <= \<const0>\;
  cfg_lcommand(2) <= \<const0>\;
  cfg_lcommand(1) <= \<const0>\;
  cfg_lcommand(0) <= \<const0>\;
  cfg_lstatus(15) <= \<const0>\;
  cfg_lstatus(14) <= \<const0>\;
  cfg_lstatus(13) <= \<const0>\;
  cfg_lstatus(12) <= \<const0>\;
  cfg_lstatus(11) <= \<const0>\;
  cfg_lstatus(10) <= \<const0>\;
  cfg_lstatus(9) <= \<const0>\;
  cfg_lstatus(8) <= \<const0>\;
  cfg_lstatus(7) <= \<const0>\;
  cfg_lstatus(6) <= \<const0>\;
  cfg_lstatus(5) <= \<const0>\;
  cfg_lstatus(4) <= \<const0>\;
  cfg_lstatus(3) <= \<const0>\;
  cfg_lstatus(2) <= \<const0>\;
  cfg_lstatus(1) <= \<const0>\;
  cfg_lstatus(0) <= \<const0>\;
  cfg_msg_data(15) <= \<const0>\;
  cfg_msg_data(14) <= \<const0>\;
  cfg_msg_data(13) <= \<const0>\;
  cfg_msg_data(12) <= \<const0>\;
  cfg_msg_data(11) <= \<const0>\;
  cfg_msg_data(10) <= \<const0>\;
  cfg_msg_data(9) <= \<const0>\;
  cfg_msg_data(8) <= \<const0>\;
  cfg_msg_data(7) <= \<const0>\;
  cfg_msg_data(6) <= \<const0>\;
  cfg_msg_data(5) <= \<const0>\;
  cfg_msg_data(4) <= \<const0>\;
  cfg_msg_data(3) <= \<const0>\;
  cfg_msg_data(2) <= \<const0>\;
  cfg_msg_data(1) <= \<const0>\;
  cfg_msg_data(0) <= \<const0>\;
  cfg_msg_received <= \<const0>\;
  cfg_msg_received_assert_int_a <= \<const0>\;
  cfg_msg_received_assert_int_b <= \<const0>\;
  cfg_msg_received_assert_int_c <= \<const0>\;
  cfg_msg_received_assert_int_d <= \<const0>\;
  cfg_msg_received_deassert_int_a <= \<const0>\;
  cfg_msg_received_deassert_int_b <= \<const0>\;
  cfg_msg_received_deassert_int_c <= \<const0>\;
  cfg_msg_received_deassert_int_d <= \<const0>\;
  cfg_msg_received_err_cor <= \<const0>\;
  cfg_msg_received_err_fatal <= \<const0>\;
  cfg_msg_received_err_non_fatal <= \<const0>\;
  cfg_msg_received_pm_as_nak <= \<const0>\;
  cfg_msg_received_pm_pme <= \<const0>\;
  cfg_msg_received_pme_to_ack <= \<const0>\;
  cfg_msg_received_setslotpowerlimit <= \<const0>\;
  cfg_pcie_link_state(2) <= \<const0>\;
  cfg_pcie_link_state(1) <= \<const0>\;
  cfg_pcie_link_state(0) <= \<const0>\;
  cfg_pmcsr_pme_en <= \<const0>\;
  cfg_pmcsr_pme_status <= \<const0>\;
  cfg_pmcsr_powerstate(1) <= \<const0>\;
  cfg_pmcsr_powerstate(0) <= \<const0>\;
  cfg_received_func_lvl_rst <= \<const0>\;
  cfg_root_control_pme_int_en <= \<const0>\;
  cfg_root_control_syserr_corr_err_en <= \<const0>\;
  cfg_root_control_syserr_fatal_err_en <= \<const0>\;
  cfg_root_control_syserr_non_fatal_err_en <= \<const0>\;
  cfg_slot_control_electromech_il_ctl_pulse <= \<const0>\;
  cfg_status(15) <= \<const0>\;
  cfg_status(14) <= \<const0>\;
  cfg_status(13) <= \<const0>\;
  cfg_status(12) <= \<const0>\;
  cfg_status(11) <= \<const0>\;
  cfg_status(10) <= \<const0>\;
  cfg_status(9) <= \<const0>\;
  cfg_status(8) <= \<const0>\;
  cfg_status(7) <= \<const0>\;
  cfg_status(6) <= \<const0>\;
  cfg_status(5) <= \<const0>\;
  cfg_status(4) <= \<const0>\;
  cfg_status(3) <= \<const0>\;
  cfg_status(2) <= \<const0>\;
  cfg_status(1) <= \<const0>\;
  cfg_status(0) <= \<const0>\;
  cfg_vc_tcvc_map(6) <= \<const0>\;
  cfg_vc_tcvc_map(5) <= \<const0>\;
  cfg_vc_tcvc_map(4) <= \<const0>\;
  cfg_vc_tcvc_map(3) <= \<const0>\;
  cfg_vc_tcvc_map(2) <= \<const0>\;
  cfg_vc_tcvc_map(1) <= \<const0>\;
  cfg_vc_tcvc_map(0) <= \<const0>\;
  common_commands_out(11) <= \<const0>\;
  common_commands_out(10) <= \<const0>\;
  common_commands_out(9) <= \<const0>\;
  common_commands_out(8) <= \<const0>\;
  common_commands_out(7) <= \<const0>\;
  common_commands_out(6) <= \<const0>\;
  common_commands_out(5) <= \<const0>\;
  common_commands_out(4) <= \<const0>\;
  common_commands_out(3) <= \<const0>\;
  common_commands_out(2) <= \<const0>\;
  common_commands_out(1) <= \<const0>\;
  common_commands_out(0) <= \<const0>\;
  ext_ch_gt_drpclk <= \<const0>\;
  ext_ch_gt_drpdo(31) <= \<const0>\;
  ext_ch_gt_drpdo(30) <= \<const0>\;
  ext_ch_gt_drpdo(29) <= \<const0>\;
  ext_ch_gt_drpdo(28) <= \<const0>\;
  ext_ch_gt_drpdo(27) <= \<const0>\;
  ext_ch_gt_drpdo(26) <= \<const0>\;
  ext_ch_gt_drpdo(25) <= \<const0>\;
  ext_ch_gt_drpdo(24) <= \<const0>\;
  ext_ch_gt_drpdo(23) <= \<const0>\;
  ext_ch_gt_drpdo(22) <= \<const0>\;
  ext_ch_gt_drpdo(21) <= \<const0>\;
  ext_ch_gt_drpdo(20) <= \<const0>\;
  ext_ch_gt_drpdo(19) <= \<const0>\;
  ext_ch_gt_drpdo(18) <= \<const0>\;
  ext_ch_gt_drpdo(17) <= \<const0>\;
  ext_ch_gt_drpdo(16) <= \<const0>\;
  ext_ch_gt_drpdo(15) <= \<const0>\;
  ext_ch_gt_drpdo(14) <= \<const0>\;
  ext_ch_gt_drpdo(13) <= \<const0>\;
  ext_ch_gt_drpdo(12) <= \<const0>\;
  ext_ch_gt_drpdo(11) <= \<const0>\;
  ext_ch_gt_drpdo(10) <= \<const0>\;
  ext_ch_gt_drpdo(9) <= \<const0>\;
  ext_ch_gt_drpdo(8) <= \<const0>\;
  ext_ch_gt_drpdo(7) <= \<const0>\;
  ext_ch_gt_drpdo(6) <= \<const0>\;
  ext_ch_gt_drpdo(5) <= \<const0>\;
  ext_ch_gt_drpdo(4) <= \<const0>\;
  ext_ch_gt_drpdo(3) <= \<const0>\;
  ext_ch_gt_drpdo(2) <= \<const0>\;
  ext_ch_gt_drpdo(1) <= \<const0>\;
  ext_ch_gt_drpdo(0) <= \<const0>\;
  ext_ch_gt_drprdy(1) <= \<const0>\;
  ext_ch_gt_drprdy(0) <= \<const0>\;
  fc_cpld(11) <= \<const0>\;
  fc_cpld(10) <= \<const0>\;
  fc_cpld(9) <= \<const0>\;
  fc_cpld(8) <= \<const0>\;
  fc_cpld(7) <= \<const0>\;
  fc_cpld(6) <= \<const0>\;
  fc_cpld(5) <= \<const0>\;
  fc_cpld(4) <= \<const0>\;
  fc_cpld(3) <= \<const0>\;
  fc_cpld(2) <= \<const0>\;
  fc_cpld(1) <= \<const0>\;
  fc_cpld(0) <= \<const0>\;
  fc_cplh(7) <= \<const0>\;
  fc_cplh(6) <= \<const0>\;
  fc_cplh(5) <= \<const0>\;
  fc_cplh(4) <= \<const0>\;
  fc_cplh(3) <= \<const0>\;
  fc_cplh(2) <= \<const0>\;
  fc_cplh(1) <= \<const0>\;
  fc_cplh(0) <= \<const0>\;
  fc_npd(11) <= \<const0>\;
  fc_npd(10) <= \<const0>\;
  fc_npd(9) <= \<const0>\;
  fc_npd(8) <= \<const0>\;
  fc_npd(7) <= \<const0>\;
  fc_npd(6) <= \<const0>\;
  fc_npd(5) <= \<const0>\;
  fc_npd(4) <= \<const0>\;
  fc_npd(3) <= \<const0>\;
  fc_npd(2) <= \<const0>\;
  fc_npd(1) <= \<const0>\;
  fc_npd(0) <= \<const0>\;
  fc_pd(11) <= \<const0>\;
  fc_pd(10) <= \<const0>\;
  fc_pd(9) <= \<const0>\;
  fc_pd(8) <= \<const0>\;
  fc_pd(7) <= \<const0>\;
  fc_pd(6) <= \<const0>\;
  fc_pd(5) <= \<const0>\;
  fc_pd(4) <= \<const0>\;
  fc_pd(3) <= \<const0>\;
  fc_pd(2) <= \<const0>\;
  fc_pd(1) <= \<const0>\;
  fc_pd(0) <= \<const0>\;
  fc_ph(7) <= \<const0>\;
  fc_ph(6) <= \<const0>\;
  fc_ph(5) <= \<const0>\;
  fc_ph(4) <= \<const0>\;
  fc_ph(3) <= \<const0>\;
  fc_ph(2) <= \<const0>\;
  fc_ph(1) <= \<const0>\;
  fc_ph(0) <= \<const0>\;
  gt_ch_drp_rdy(1) <= \<const0>\;
  gt_ch_drp_rdy(0) <= \<const0>\;
  icap_o(31) <= \<const0>\;
  icap_o(30) <= \<const0>\;
  icap_o(29) <= \<const0>\;
  icap_o(28) <= \<const0>\;
  icap_o(27) <= \<const0>\;
  icap_o(26) <= \<const0>\;
  icap_o(25) <= \<const0>\;
  icap_o(24) <= \<const0>\;
  icap_o(23) <= \<const0>\;
  icap_o(22) <= \<const0>\;
  icap_o(21) <= \<const0>\;
  icap_o(20) <= \<const0>\;
  icap_o(19) <= \<const0>\;
  icap_o(18) <= \<const0>\;
  icap_o(17) <= \<const0>\;
  icap_o(16) <= \<const0>\;
  icap_o(15) <= \<const0>\;
  icap_o(14) <= \<const0>\;
  icap_o(13) <= \<const0>\;
  icap_o(12) <= \<const0>\;
  icap_o(11) <= \<const0>\;
  icap_o(10) <= \<const0>\;
  icap_o(9) <= \<const0>\;
  icap_o(8) <= \<const0>\;
  icap_o(7) <= \<const0>\;
  icap_o(6) <= \<const0>\;
  icap_o(5) <= \<const0>\;
  icap_o(4) <= \<const0>\;
  icap_o(3) <= \<const0>\;
  icap_o(2) <= \<const0>\;
  icap_o(1) <= \<const0>\;
  icap_o(0) <= \<const0>\;
  int_dclk_out <= \<const0>\;
  int_mmcm_lock_out <= \<const0>\;
  int_oobclk_out <= \<const0>\;
  int_pclk_out_slave <= \<const0>\;
  int_pipe_rxusrclk_out <= \<const0>\;
  int_qplllock_out(1) <= \<const0>\;
  int_qplllock_out(0) <= \<const0>\;
  int_qplloutclk_out(1) <= \<const0>\;
  int_qplloutclk_out(0) <= \<const0>\;
  int_qplloutrefclk_out(1) <= \<const0>\;
  int_qplloutrefclk_out(0) <= \<const0>\;
  int_rxoutclk_out(1) <= \<const0>\;
  int_rxoutclk_out(0) <= \<const0>\;
  int_userclk1_out <= \<const0>\;
  int_userclk2_out <= \<const0>\;
  m_axis_rx_tkeep(7) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(6) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(5) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(4) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(3) <= \<const0>\;
  m_axis_rx_tkeep(2) <= \<const0>\;
  m_axis_rx_tkeep(1) <= \<const0>\;
  m_axis_rx_tkeep(0) <= \<const0>\;
  m_axis_rx_tuser(21) <= \^m_axis_rx_tuser\(21);
  m_axis_rx_tuser(20) <= \<const0>\;
  m_axis_rx_tuser(19) <= \^m_axis_rx_tuser\(19);
  m_axis_rx_tuser(18) <= \^m_axis_rx_tuser\(17);
  m_axis_rx_tuser(17) <= \^m_axis_rx_tuser\(17);
  m_axis_rx_tuser(16) <= \<const0>\;
  m_axis_rx_tuser(15) <= \<const0>\;
  m_axis_rx_tuser(14) <= \^m_axis_rx_tuser\(14);
  m_axis_rx_tuser(13) <= \<const0>\;
  m_axis_rx_tuser(12) <= \<const0>\;
  m_axis_rx_tuser(11) <= \<const0>\;
  m_axis_rx_tuser(10) <= \<const0>\;
  m_axis_rx_tuser(9) <= \<const0>\;
  m_axis_rx_tuser(8 downto 0) <= \^m_axis_rx_tuser\(8 downto 0);
  pcie_drp_do(15) <= \<const0>\;
  pcie_drp_do(14) <= \<const0>\;
  pcie_drp_do(13) <= \<const0>\;
  pcie_drp_do(12) <= \<const0>\;
  pcie_drp_do(11) <= \<const0>\;
  pcie_drp_do(10) <= \<const0>\;
  pcie_drp_do(9) <= \<const0>\;
  pcie_drp_do(8) <= \<const0>\;
  pcie_drp_do(7) <= \<const0>\;
  pcie_drp_do(6) <= \<const0>\;
  pcie_drp_do(5) <= \<const0>\;
  pcie_drp_do(4) <= \<const0>\;
  pcie_drp_do(3) <= \<const0>\;
  pcie_drp_do(2) <= \<const0>\;
  pcie_drp_do(1) <= \<const0>\;
  pcie_drp_do(0) <= \<const0>\;
  pcie_drp_rdy <= \<const0>\;
  pipe_cpll_lock(1) <= \<const0>\;
  pipe_cpll_lock(0) <= \<const0>\;
  pipe_debug(31) <= \<const0>\;
  pipe_debug(30) <= \<const0>\;
  pipe_debug(29) <= \<const0>\;
  pipe_debug(28) <= \<const0>\;
  pipe_debug(27) <= \<const0>\;
  pipe_debug(26) <= \<const0>\;
  pipe_debug(25) <= \<const0>\;
  pipe_debug(24) <= \<const0>\;
  pipe_debug(23) <= \<const0>\;
  pipe_debug(22) <= \<const0>\;
  pipe_debug(21) <= \<const0>\;
  pipe_debug(20) <= \<const0>\;
  pipe_debug(19) <= \<const0>\;
  pipe_debug(18) <= \<const0>\;
  pipe_debug(17) <= \<const0>\;
  pipe_debug(16) <= \<const0>\;
  pipe_debug(15) <= \<const0>\;
  pipe_debug(14) <= \<const0>\;
  pipe_debug(13) <= \<const0>\;
  pipe_debug(12) <= \<const0>\;
  pipe_debug(11) <= \<const0>\;
  pipe_debug(10) <= \<const0>\;
  pipe_debug(9) <= \<const0>\;
  pipe_debug(8) <= \<const0>\;
  pipe_debug(7) <= \<const0>\;
  pipe_debug(6) <= \<const0>\;
  pipe_debug(5) <= \<const0>\;
  pipe_debug(4) <= \<const0>\;
  pipe_debug(3) <= \<const0>\;
  pipe_debug(2) <= \<const0>\;
  pipe_debug(1) <= \<const0>\;
  pipe_debug(0) <= \<const0>\;
  pipe_debug_0(1) <= \<const0>\;
  pipe_debug_0(0) <= \<const0>\;
  pipe_debug_1(1) <= \<const0>\;
  pipe_debug_1(0) <= \<const0>\;
  pipe_debug_2(1) <= \<const0>\;
  pipe_debug_2(0) <= \<const0>\;
  pipe_debug_3(1) <= \<const0>\;
  pipe_debug_3(0) <= \<const0>\;
  pipe_debug_4(1) <= \<const0>\;
  pipe_debug_4(0) <= \<const0>\;
  pipe_debug_5(1) <= \<const0>\;
  pipe_debug_5(0) <= \<const0>\;
  pipe_debug_6(1) <= \<const0>\;
  pipe_debug_6(0) <= \<const0>\;
  pipe_debug_7(1) <= \<const0>\;
  pipe_debug_7(0) <= \<const0>\;
  pipe_debug_8(1) <= \<const0>\;
  pipe_debug_8(0) <= \<const0>\;
  pipe_debug_9(1) <= \<const0>\;
  pipe_debug_9(0) <= \<const0>\;
  pipe_dmonitorout(29) <= \<const0>\;
  pipe_dmonitorout(28) <= \<const0>\;
  pipe_dmonitorout(27) <= \<const0>\;
  pipe_dmonitorout(26) <= \<const0>\;
  pipe_dmonitorout(25) <= \<const0>\;
  pipe_dmonitorout(24) <= \<const0>\;
  pipe_dmonitorout(23) <= \<const0>\;
  pipe_dmonitorout(22) <= \<const0>\;
  pipe_dmonitorout(21) <= \<const0>\;
  pipe_dmonitorout(20) <= \<const0>\;
  pipe_dmonitorout(19) <= \<const0>\;
  pipe_dmonitorout(18) <= \<const0>\;
  pipe_dmonitorout(17) <= \<const0>\;
  pipe_dmonitorout(16) <= \<const0>\;
  pipe_dmonitorout(15) <= \<const0>\;
  pipe_dmonitorout(14) <= \<const0>\;
  pipe_dmonitorout(13) <= \<const0>\;
  pipe_dmonitorout(12) <= \<const0>\;
  pipe_dmonitorout(11) <= \<const0>\;
  pipe_dmonitorout(10) <= \<const0>\;
  pipe_dmonitorout(9) <= \<const0>\;
  pipe_dmonitorout(8) <= \<const0>\;
  pipe_dmonitorout(7) <= \<const0>\;
  pipe_dmonitorout(6) <= \<const0>\;
  pipe_dmonitorout(5) <= \<const0>\;
  pipe_dmonitorout(4) <= \<const0>\;
  pipe_dmonitorout(3) <= \<const0>\;
  pipe_dmonitorout(2) <= \<const0>\;
  pipe_dmonitorout(1) <= \<const0>\;
  pipe_dmonitorout(0) <= \<const0>\;
  pipe_drp_fsm(13) <= \<const0>\;
  pipe_drp_fsm(12) <= \<const0>\;
  pipe_drp_fsm(11) <= \<const0>\;
  pipe_drp_fsm(10) <= \<const0>\;
  pipe_drp_fsm(9) <= \<const0>\;
  pipe_drp_fsm(8) <= \<const0>\;
  pipe_drp_fsm(7) <= \<const0>\;
  pipe_drp_fsm(6) <= \<const0>\;
  pipe_drp_fsm(5) <= \<const0>\;
  pipe_drp_fsm(4) <= \<const0>\;
  pipe_drp_fsm(3) <= \<const0>\;
  pipe_drp_fsm(2) <= \<const0>\;
  pipe_drp_fsm(1) <= \<const0>\;
  pipe_drp_fsm(0) <= \<const0>\;
  pipe_eyescandataerror(1) <= \<const0>\;
  pipe_eyescandataerror(0) <= \<const0>\;
  pipe_gen3_out <= \<const0>\;
  pipe_pclk_sel_out(1) <= \<const0>\;
  pipe_pclk_sel_out(0) <= \<const0>\;
  pipe_qpll_lock(0) <= \<const0>\;
  pipe_qrst_fsm(11) <= \<const0>\;
  pipe_qrst_fsm(10) <= \<const0>\;
  pipe_qrst_fsm(9) <= \<const0>\;
  pipe_qrst_fsm(8) <= \<const0>\;
  pipe_qrst_fsm(7) <= \<const0>\;
  pipe_qrst_fsm(6) <= \<const0>\;
  pipe_qrst_fsm(5) <= \<const0>\;
  pipe_qrst_fsm(4) <= \<const0>\;
  pipe_qrst_fsm(3) <= \<const0>\;
  pipe_qrst_fsm(2) <= \<const0>\;
  pipe_qrst_fsm(1) <= \<const0>\;
  pipe_qrst_fsm(0) <= \<const0>\;
  pipe_qrst_idle <= \<const0>\;
  pipe_rate_fsm(9) <= \<const0>\;
  pipe_rate_fsm(8) <= \<const0>\;
  pipe_rate_fsm(7) <= \<const0>\;
  pipe_rate_fsm(6) <= \<const0>\;
  pipe_rate_fsm(5) <= \<const0>\;
  pipe_rate_fsm(4) <= \<const0>\;
  pipe_rate_fsm(3) <= \<const0>\;
  pipe_rate_fsm(2) <= \<const0>\;
  pipe_rate_fsm(1) <= \<const0>\;
  pipe_rate_fsm(0) <= \<const0>\;
  pipe_rate_idle <= \<const0>\;
  pipe_rst_fsm(4) <= \<const0>\;
  pipe_rst_fsm(3) <= \<const0>\;
  pipe_rst_fsm(2) <= \<const0>\;
  pipe_rst_fsm(1) <= \<const0>\;
  pipe_rst_fsm(0) <= \<const0>\;
  pipe_rst_idle <= \<const0>\;
  pipe_rxbufstatus(5) <= \<const0>\;
  pipe_rxbufstatus(4) <= \<const0>\;
  pipe_rxbufstatus(3) <= \<const0>\;
  pipe_rxbufstatus(2) <= \<const0>\;
  pipe_rxbufstatus(1) <= \<const0>\;
  pipe_rxbufstatus(0) <= \<const0>\;
  pipe_rxcommadet(1) <= \<const0>\;
  pipe_rxcommadet(0) <= \<const0>\;
  pipe_rxdisperr(15) <= \<const0>\;
  pipe_rxdisperr(14) <= \<const0>\;
  pipe_rxdisperr(13) <= \<const0>\;
  pipe_rxdisperr(12) <= \<const0>\;
  pipe_rxdisperr(11) <= \<const0>\;
  pipe_rxdisperr(10) <= \<const0>\;
  pipe_rxdisperr(9) <= \<const0>\;
  pipe_rxdisperr(8) <= \<const0>\;
  pipe_rxdisperr(7) <= \<const0>\;
  pipe_rxdisperr(6) <= \<const0>\;
  pipe_rxdisperr(5) <= \<const0>\;
  pipe_rxdisperr(4) <= \<const0>\;
  pipe_rxdisperr(3) <= \<const0>\;
  pipe_rxdisperr(2) <= \<const0>\;
  pipe_rxdisperr(1) <= \<const0>\;
  pipe_rxdisperr(0) <= \<const0>\;
  pipe_rxdlysresetdone(1) <= \<const0>\;
  pipe_rxdlysresetdone(0) <= \<const0>\;
  pipe_rxnotintable(15) <= \<const0>\;
  pipe_rxnotintable(14) <= \<const0>\;
  pipe_rxnotintable(13) <= \<const0>\;
  pipe_rxnotintable(12) <= \<const0>\;
  pipe_rxnotintable(11) <= \<const0>\;
  pipe_rxnotintable(10) <= \<const0>\;
  pipe_rxnotintable(9) <= \<const0>\;
  pipe_rxnotintable(8) <= \<const0>\;
  pipe_rxnotintable(7) <= \<const0>\;
  pipe_rxnotintable(6) <= \<const0>\;
  pipe_rxnotintable(5) <= \<const0>\;
  pipe_rxnotintable(4) <= \<const0>\;
  pipe_rxnotintable(3) <= \<const0>\;
  pipe_rxnotintable(2) <= \<const0>\;
  pipe_rxnotintable(1) <= \<const0>\;
  pipe_rxnotintable(0) <= \<const0>\;
  pipe_rxoutclk_out(1) <= \<const0>\;
  pipe_rxoutclk_out(0) <= \<const0>\;
  pipe_rxphaligndone(1) <= \<const0>\;
  pipe_rxphaligndone(0) <= \<const0>\;
  pipe_rxpmaresetdone(1) <= \<const0>\;
  pipe_rxpmaresetdone(0) <= \<const0>\;
  pipe_rxprbserr(1) <= \<const0>\;
  pipe_rxprbserr(0) <= \<const0>\;
  pipe_rxstatus(5) <= \<const0>\;
  pipe_rxstatus(4) <= \<const0>\;
  pipe_rxstatus(3) <= \<const0>\;
  pipe_rxstatus(2) <= \<const0>\;
  pipe_rxstatus(1) <= \<const0>\;
  pipe_rxstatus(0) <= \<const0>\;
  pipe_rxsyncdone(1) <= \<const0>\;
  pipe_rxsyncdone(0) <= \<const0>\;
  pipe_sync_fsm_rx(13) <= \<const0>\;
  pipe_sync_fsm_rx(12) <= \<const0>\;
  pipe_sync_fsm_rx(11) <= \<const0>\;
  pipe_sync_fsm_rx(10) <= \<const0>\;
  pipe_sync_fsm_rx(9) <= \<const0>\;
  pipe_sync_fsm_rx(8) <= \<const0>\;
  pipe_sync_fsm_rx(7) <= \<const0>\;
  pipe_sync_fsm_rx(6) <= \<const0>\;
  pipe_sync_fsm_rx(5) <= \<const0>\;
  pipe_sync_fsm_rx(4) <= \<const0>\;
  pipe_sync_fsm_rx(3) <= \<const0>\;
  pipe_sync_fsm_rx(2) <= \<const0>\;
  pipe_sync_fsm_rx(1) <= \<const0>\;
  pipe_sync_fsm_rx(0) <= \<const0>\;
  pipe_sync_fsm_tx(11) <= \<const0>\;
  pipe_sync_fsm_tx(10) <= \<const0>\;
  pipe_sync_fsm_tx(9) <= \<const0>\;
  pipe_sync_fsm_tx(8) <= \<const0>\;
  pipe_sync_fsm_tx(7) <= \<const0>\;
  pipe_sync_fsm_tx(6) <= \<const0>\;
  pipe_sync_fsm_tx(5) <= \<const0>\;
  pipe_sync_fsm_tx(4) <= \<const0>\;
  pipe_sync_fsm_tx(3) <= \<const0>\;
  pipe_sync_fsm_tx(2) <= \<const0>\;
  pipe_sync_fsm_tx(1) <= \<const0>\;
  pipe_sync_fsm_tx(0) <= \<const0>\;
  pipe_tx_0_sigs(24) <= \<const0>\;
  pipe_tx_0_sigs(23) <= \<const0>\;
  pipe_tx_0_sigs(22) <= \<const0>\;
  pipe_tx_0_sigs(21) <= \<const0>\;
  pipe_tx_0_sigs(20) <= \<const0>\;
  pipe_tx_0_sigs(19) <= \<const0>\;
  pipe_tx_0_sigs(18) <= \<const0>\;
  pipe_tx_0_sigs(17) <= \<const0>\;
  pipe_tx_0_sigs(16) <= \<const0>\;
  pipe_tx_0_sigs(15) <= \<const0>\;
  pipe_tx_0_sigs(14) <= \<const0>\;
  pipe_tx_0_sigs(13) <= \<const0>\;
  pipe_tx_0_sigs(12) <= \<const0>\;
  pipe_tx_0_sigs(11) <= \<const0>\;
  pipe_tx_0_sigs(10) <= \<const0>\;
  pipe_tx_0_sigs(9) <= \<const0>\;
  pipe_tx_0_sigs(8) <= \<const0>\;
  pipe_tx_0_sigs(7) <= \<const0>\;
  pipe_tx_0_sigs(6) <= \<const0>\;
  pipe_tx_0_sigs(5) <= \<const0>\;
  pipe_tx_0_sigs(4) <= \<const0>\;
  pipe_tx_0_sigs(3) <= \<const0>\;
  pipe_tx_0_sigs(2) <= \<const0>\;
  pipe_tx_0_sigs(1) <= \<const0>\;
  pipe_tx_0_sigs(0) <= \<const0>\;
  pipe_tx_1_sigs(24) <= \<const0>\;
  pipe_tx_1_sigs(23) <= \<const0>\;
  pipe_tx_1_sigs(22) <= \<const0>\;
  pipe_tx_1_sigs(21) <= \<const0>\;
  pipe_tx_1_sigs(20) <= \<const0>\;
  pipe_tx_1_sigs(19) <= \<const0>\;
  pipe_tx_1_sigs(18) <= \<const0>\;
  pipe_tx_1_sigs(17) <= \<const0>\;
  pipe_tx_1_sigs(16) <= \<const0>\;
  pipe_tx_1_sigs(15) <= \<const0>\;
  pipe_tx_1_sigs(14) <= \<const0>\;
  pipe_tx_1_sigs(13) <= \<const0>\;
  pipe_tx_1_sigs(12) <= \<const0>\;
  pipe_tx_1_sigs(11) <= \<const0>\;
  pipe_tx_1_sigs(10) <= \<const0>\;
  pipe_tx_1_sigs(9) <= \<const0>\;
  pipe_tx_1_sigs(8) <= \<const0>\;
  pipe_tx_1_sigs(7) <= \<const0>\;
  pipe_tx_1_sigs(6) <= \<const0>\;
  pipe_tx_1_sigs(5) <= \<const0>\;
  pipe_tx_1_sigs(4) <= \<const0>\;
  pipe_tx_1_sigs(3) <= \<const0>\;
  pipe_tx_1_sigs(2) <= \<const0>\;
  pipe_tx_1_sigs(1) <= \<const0>\;
  pipe_tx_1_sigs(0) <= \<const0>\;
  pipe_tx_2_sigs(24) <= \<const0>\;
  pipe_tx_2_sigs(23) <= \<const0>\;
  pipe_tx_2_sigs(22) <= \<const0>\;
  pipe_tx_2_sigs(21) <= \<const0>\;
  pipe_tx_2_sigs(20) <= \<const0>\;
  pipe_tx_2_sigs(19) <= \<const0>\;
  pipe_tx_2_sigs(18) <= \<const0>\;
  pipe_tx_2_sigs(17) <= \<const0>\;
  pipe_tx_2_sigs(16) <= \<const0>\;
  pipe_tx_2_sigs(15) <= \<const0>\;
  pipe_tx_2_sigs(14) <= \<const0>\;
  pipe_tx_2_sigs(13) <= \<const0>\;
  pipe_tx_2_sigs(12) <= \<const0>\;
  pipe_tx_2_sigs(11) <= \<const0>\;
  pipe_tx_2_sigs(10) <= \<const0>\;
  pipe_tx_2_sigs(9) <= \<const0>\;
  pipe_tx_2_sigs(8) <= \<const0>\;
  pipe_tx_2_sigs(7) <= \<const0>\;
  pipe_tx_2_sigs(6) <= \<const0>\;
  pipe_tx_2_sigs(5) <= \<const0>\;
  pipe_tx_2_sigs(4) <= \<const0>\;
  pipe_tx_2_sigs(3) <= \<const0>\;
  pipe_tx_2_sigs(2) <= \<const0>\;
  pipe_tx_2_sigs(1) <= \<const0>\;
  pipe_tx_2_sigs(0) <= \<const0>\;
  pipe_tx_3_sigs(24) <= \<const0>\;
  pipe_tx_3_sigs(23) <= \<const0>\;
  pipe_tx_3_sigs(22) <= \<const0>\;
  pipe_tx_3_sigs(21) <= \<const0>\;
  pipe_tx_3_sigs(20) <= \<const0>\;
  pipe_tx_3_sigs(19) <= \<const0>\;
  pipe_tx_3_sigs(18) <= \<const0>\;
  pipe_tx_3_sigs(17) <= \<const0>\;
  pipe_tx_3_sigs(16) <= \<const0>\;
  pipe_tx_3_sigs(15) <= \<const0>\;
  pipe_tx_3_sigs(14) <= \<const0>\;
  pipe_tx_3_sigs(13) <= \<const0>\;
  pipe_tx_3_sigs(12) <= \<const0>\;
  pipe_tx_3_sigs(11) <= \<const0>\;
  pipe_tx_3_sigs(10) <= \<const0>\;
  pipe_tx_3_sigs(9) <= \<const0>\;
  pipe_tx_3_sigs(8) <= \<const0>\;
  pipe_tx_3_sigs(7) <= \<const0>\;
  pipe_tx_3_sigs(6) <= \<const0>\;
  pipe_tx_3_sigs(5) <= \<const0>\;
  pipe_tx_3_sigs(4) <= \<const0>\;
  pipe_tx_3_sigs(3) <= \<const0>\;
  pipe_tx_3_sigs(2) <= \<const0>\;
  pipe_tx_3_sigs(1) <= \<const0>\;
  pipe_tx_3_sigs(0) <= \<const0>\;
  pipe_tx_4_sigs(24) <= \<const0>\;
  pipe_tx_4_sigs(23) <= \<const0>\;
  pipe_tx_4_sigs(22) <= \<const0>\;
  pipe_tx_4_sigs(21) <= \<const0>\;
  pipe_tx_4_sigs(20) <= \<const0>\;
  pipe_tx_4_sigs(19) <= \<const0>\;
  pipe_tx_4_sigs(18) <= \<const0>\;
  pipe_tx_4_sigs(17) <= \<const0>\;
  pipe_tx_4_sigs(16) <= \<const0>\;
  pipe_tx_4_sigs(15) <= \<const0>\;
  pipe_tx_4_sigs(14) <= \<const0>\;
  pipe_tx_4_sigs(13) <= \<const0>\;
  pipe_tx_4_sigs(12) <= \<const0>\;
  pipe_tx_4_sigs(11) <= \<const0>\;
  pipe_tx_4_sigs(10) <= \<const0>\;
  pipe_tx_4_sigs(9) <= \<const0>\;
  pipe_tx_4_sigs(8) <= \<const0>\;
  pipe_tx_4_sigs(7) <= \<const0>\;
  pipe_tx_4_sigs(6) <= \<const0>\;
  pipe_tx_4_sigs(5) <= \<const0>\;
  pipe_tx_4_sigs(4) <= \<const0>\;
  pipe_tx_4_sigs(3) <= \<const0>\;
  pipe_tx_4_sigs(2) <= \<const0>\;
  pipe_tx_4_sigs(1) <= \<const0>\;
  pipe_tx_4_sigs(0) <= \<const0>\;
  pipe_tx_5_sigs(24) <= \<const0>\;
  pipe_tx_5_sigs(23) <= \<const0>\;
  pipe_tx_5_sigs(22) <= \<const0>\;
  pipe_tx_5_sigs(21) <= \<const0>\;
  pipe_tx_5_sigs(20) <= \<const0>\;
  pipe_tx_5_sigs(19) <= \<const0>\;
  pipe_tx_5_sigs(18) <= \<const0>\;
  pipe_tx_5_sigs(17) <= \<const0>\;
  pipe_tx_5_sigs(16) <= \<const0>\;
  pipe_tx_5_sigs(15) <= \<const0>\;
  pipe_tx_5_sigs(14) <= \<const0>\;
  pipe_tx_5_sigs(13) <= \<const0>\;
  pipe_tx_5_sigs(12) <= \<const0>\;
  pipe_tx_5_sigs(11) <= \<const0>\;
  pipe_tx_5_sigs(10) <= \<const0>\;
  pipe_tx_5_sigs(9) <= \<const0>\;
  pipe_tx_5_sigs(8) <= \<const0>\;
  pipe_tx_5_sigs(7) <= \<const0>\;
  pipe_tx_5_sigs(6) <= \<const0>\;
  pipe_tx_5_sigs(5) <= \<const0>\;
  pipe_tx_5_sigs(4) <= \<const0>\;
  pipe_tx_5_sigs(3) <= \<const0>\;
  pipe_tx_5_sigs(2) <= \<const0>\;
  pipe_tx_5_sigs(1) <= \<const0>\;
  pipe_tx_5_sigs(0) <= \<const0>\;
  pipe_tx_6_sigs(24) <= \<const0>\;
  pipe_tx_6_sigs(23) <= \<const0>\;
  pipe_tx_6_sigs(22) <= \<const0>\;
  pipe_tx_6_sigs(21) <= \<const0>\;
  pipe_tx_6_sigs(20) <= \<const0>\;
  pipe_tx_6_sigs(19) <= \<const0>\;
  pipe_tx_6_sigs(18) <= \<const0>\;
  pipe_tx_6_sigs(17) <= \<const0>\;
  pipe_tx_6_sigs(16) <= \<const0>\;
  pipe_tx_6_sigs(15) <= \<const0>\;
  pipe_tx_6_sigs(14) <= \<const0>\;
  pipe_tx_6_sigs(13) <= \<const0>\;
  pipe_tx_6_sigs(12) <= \<const0>\;
  pipe_tx_6_sigs(11) <= \<const0>\;
  pipe_tx_6_sigs(10) <= \<const0>\;
  pipe_tx_6_sigs(9) <= \<const0>\;
  pipe_tx_6_sigs(8) <= \<const0>\;
  pipe_tx_6_sigs(7) <= \<const0>\;
  pipe_tx_6_sigs(6) <= \<const0>\;
  pipe_tx_6_sigs(5) <= \<const0>\;
  pipe_tx_6_sigs(4) <= \<const0>\;
  pipe_tx_6_sigs(3) <= \<const0>\;
  pipe_tx_6_sigs(2) <= \<const0>\;
  pipe_tx_6_sigs(1) <= \<const0>\;
  pipe_tx_6_sigs(0) <= \<const0>\;
  pipe_tx_7_sigs(24) <= \<const0>\;
  pipe_tx_7_sigs(23) <= \<const0>\;
  pipe_tx_7_sigs(22) <= \<const0>\;
  pipe_tx_7_sigs(21) <= \<const0>\;
  pipe_tx_7_sigs(20) <= \<const0>\;
  pipe_tx_7_sigs(19) <= \<const0>\;
  pipe_tx_7_sigs(18) <= \<const0>\;
  pipe_tx_7_sigs(17) <= \<const0>\;
  pipe_tx_7_sigs(16) <= \<const0>\;
  pipe_tx_7_sigs(15) <= \<const0>\;
  pipe_tx_7_sigs(14) <= \<const0>\;
  pipe_tx_7_sigs(13) <= \<const0>\;
  pipe_tx_7_sigs(12) <= \<const0>\;
  pipe_tx_7_sigs(11) <= \<const0>\;
  pipe_tx_7_sigs(10) <= \<const0>\;
  pipe_tx_7_sigs(9) <= \<const0>\;
  pipe_tx_7_sigs(8) <= \<const0>\;
  pipe_tx_7_sigs(7) <= \<const0>\;
  pipe_tx_7_sigs(6) <= \<const0>\;
  pipe_tx_7_sigs(5) <= \<const0>\;
  pipe_tx_7_sigs(4) <= \<const0>\;
  pipe_tx_7_sigs(3) <= \<const0>\;
  pipe_tx_7_sigs(2) <= \<const0>\;
  pipe_tx_7_sigs(1) <= \<const0>\;
  pipe_tx_7_sigs(0) <= \<const0>\;
  pipe_txdlysresetdone(1) <= \<const0>\;
  pipe_txdlysresetdone(0) <= \<const0>\;
  pipe_txoutclk_out <= \<const0>\;
  pipe_txphaligndone(1) <= \<const0>\;
  pipe_txphaligndone(0) <= \<const0>\;
  pipe_txphinitdone(1) <= \<const0>\;
  pipe_txphinitdone(0) <= \<const0>\;
  pl_directed_change_done <= \<const0>\;
  pl_initial_link_width(2) <= \<const0>\;
  pl_initial_link_width(1) <= \<const0>\;
  pl_initial_link_width(0) <= \<const0>\;
  pl_lane_reversal_mode(1) <= \<const0>\;
  pl_lane_reversal_mode(0) <= \<const0>\;
  pl_link_gen2_cap <= \<const0>\;
  pl_link_partner_gen2_supported <= \<const0>\;
  pl_link_upcfg_cap <= \<const0>\;
  pl_ltssm_state(5) <= \<const0>\;
  pl_ltssm_state(4) <= \<const0>\;
  pl_ltssm_state(3) <= \<const0>\;
  pl_ltssm_state(2) <= \<const0>\;
  pl_ltssm_state(1) <= \<const0>\;
  pl_ltssm_state(0) <= \<const0>\;
  pl_received_hot_rst <= \<const0>\;
  pl_rx_pm_state(1) <= \<const0>\;
  pl_rx_pm_state(0) <= \<const0>\;
  pl_sel_lnk_rate <= \<const0>\;
  pl_sel_lnk_width(1) <= \<const0>\;
  pl_sel_lnk_width(0) <= \<const0>\;
  pl_tx_pm_state(2) <= \<const0>\;
  pl_tx_pm_state(1) <= \<const0>\;
  pl_tx_pm_state(0) <= \<const0>\;
  qpll_drp_clk <= \<const0>\;
  qpll_drp_gen3 <= \<const0>\;
  qpll_drp_ovrd <= \<const0>\;
  qpll_drp_rst_n <= \<const0>\;
  qpll_drp_start <= \<const0>\;
  qpll_qplld <= \<const0>\;
  qpll_qpllreset(1) <= \<const0>\;
  qpll_qpllreset(0) <= \<const0>\;
  startup_cfgclk <= \<const0>\;
  startup_cfgmclk <= \<const0>\;
  startup_eos <= \<const0>\;
  startup_preq <= \<const0>\;
  tx_buf_av(5) <= \<const0>\;
  tx_buf_av(4) <= \<const0>\;
  tx_buf_av(3) <= \<const0>\;
  tx_buf_av(2) <= \<const0>\;
  tx_buf_av(1) <= \<const0>\;
  tx_buf_av(0) <= \<const0>\;
  tx_cfg_req <= \<const0>\;
  tx_err_drop <= \<const0>\;
  user_app_rdy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.xdma_0_xdma_0_pcie2_ip_core_top
     port map (
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(0) => \^cfg_command\(2),
      cfg_dcommand(5 downto 3) => \^cfg_dcommand\(14 downto 12),
      cfg_dcommand(2 downto 0) => \^cfg_dcommand\(7 downto 5),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(4 downto 0) => cfg_interrupt_di(4 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_to_turnoff => cfg_to_turnoff,
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_sel(0) => fc_sel(0),
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      int_userclk1_out => user_clk_out,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(0) => \^m_axis_rx_tkeep\(6),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12) => \^m_axis_rx_tuser\(21),
      m_axis_rx_tuser(11) => \^m_axis_rx_tuser\(19),
      m_axis_rx_tuser(10) => \^m_axis_rx_tuser\(17),
      m_axis_rx_tuser(9) => \^m_axis_rx_tuser\(14),
      m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser\(8 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(7),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0\ is
  port (
    \mi_h2c_rd_brg_dat\\.rdat\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC;
    \mi_h2c_rd_brg_dat\\.wen\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mi_h2c_rd_brg_dat\\.wadr\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \mi_h2c_rd_brg_dat\\.wdat\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \mi_h2c_rd_brg_dat\\.radr\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0\ : entity is "xdma_v4_1_8_dma_bram_wrap";
end \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0\ is
  signal \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 71 downto 8 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \genblk1[0].u_buffermem\ : label is "xdma_v4_1_8_blk_mem_64_noreg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \genblk1[0].u_buffermem\ : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \genblk1[0].u_buffermem\ : label is "blk_mem_gen_v8_4_4,Vivado 2020.2";
begin
\genblk1[0].u_buffermem\: entity work.\xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be__2\
     port map (
      addra(8 downto 0) => \mi_h2c_rd_brg_dat\\.wadr\(8 downto 0),
      addrb(8 downto 0) => \mi_h2c_rd_brg_dat\\.radr\(8 downto 0),
      clka => user_clk,
      clkb => '0',
      dina(71) => '0',
      dina(70 downto 63) => \mi_h2c_rd_brg_dat\\.wdat\(63 downto 56),
      dina(62) => '0',
      dina(61 downto 54) => \mi_h2c_rd_brg_dat\\.wdat\(55 downto 48),
      dina(53) => '0',
      dina(52 downto 45) => \mi_h2c_rd_brg_dat\\.wdat\(47 downto 40),
      dina(44) => '0',
      dina(43 downto 36) => \mi_h2c_rd_brg_dat\\.wdat\(39 downto 32),
      dina(35) => '0',
      dina(34 downto 27) => \mi_h2c_rd_brg_dat\\.wdat\(31 downto 24),
      dina(26) => '0',
      dina(25 downto 18) => \mi_h2c_rd_brg_dat\\.wdat\(23 downto 16),
      dina(17) => '0',
      dina(16 downto 9) => \mi_h2c_rd_brg_dat\\.wdat\(15 downto 8),
      dina(8) => '0',
      dina(7 downto 0) => \mi_h2c_rd_brg_dat\\.wdat\(7 downto 0),
      doutb(71) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(71),
      doutb(70 downto 63) => \mi_h2c_rd_brg_dat\\.rdat\(63 downto 56),
      doutb(62) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(62),
      doutb(61 downto 54) => \mi_h2c_rd_brg_dat\\.rdat\(55 downto 48),
      doutb(53) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(53),
      doutb(52 downto 45) => \mi_h2c_rd_brg_dat\\.rdat\(47 downto 40),
      doutb(44) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(44),
      doutb(43 downto 36) => \mi_h2c_rd_brg_dat\\.rdat\(39 downto 32),
      doutb(35) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(35),
      doutb(34 downto 27) => \mi_h2c_rd_brg_dat\\.rdat\(31 downto 24),
      doutb(26) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(26),
      doutb(25 downto 18) => \mi_h2c_rd_brg_dat\\.rdat\(23 downto 16),
      doutb(17) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(17),
      doutb(16 downto 9) => \mi_h2c_rd_brg_dat\\.rdat\(15 downto 8),
      doutb(8) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(8),
      doutb(7 downto 0) => \mi_h2c_rd_brg_dat\\.rdat\(7 downto 0),
      ena => '1',
      enb => '1',
      wea(7) => \mi_h2c_rd_brg_dat\\.wen\(0),
      wea(6 downto 0) => B"0000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0__xdcDup__1\ is
  port (
    doutb : out STD_LOGIC_VECTOR ( 71 downto 0 );
    user_clk : in STD_LOGIC;
    \mi_h2c_wr_brg_dat\\.wen\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mi_h2c_wr_brg_dat\\.wadr\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \mi_h2c_wr_brg_dat\\.wdat\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \mi_h2c_wr_brg_dat\\.radr\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0__xdcDup__1\ : entity is "xdma_v4_1_8_dma_bram_wrap";
end \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0__xdcDup__1\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_dma_bram_wrap__parameterized0__xdcDup__1\ is
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \genblk1[0].u_buffermem\ : label is "xdma_v4_1_8_blk_mem_64_noreg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \genblk1[0].u_buffermem\ : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \genblk1[0].u_buffermem\ : label is "blk_mem_gen_v8_4_4,Vivado 2020.2";
begin
\genblk1[0].u_buffermem\: entity work.xdma_0_xdma_v4_1_8_blk_mem_64_noreg_be
     port map (
      addra(8 downto 0) => \mi_h2c_wr_brg_dat\\.wadr\(8 downto 0),
      addrb(8 downto 0) => \mi_h2c_wr_brg_dat\\.radr\(8 downto 0),
      clka => user_clk,
      clkb => '0',
      dina(71) => '0',
      dina(70 downto 63) => \mi_h2c_wr_brg_dat\\.wdat\(63 downto 56),
      dina(62) => '0',
      dina(61 downto 54) => \mi_h2c_wr_brg_dat\\.wdat\(55 downto 48),
      dina(53) => '0',
      dina(52 downto 45) => \mi_h2c_wr_brg_dat\\.wdat\(47 downto 40),
      dina(44) => '0',
      dina(43 downto 36) => \mi_h2c_wr_brg_dat\\.wdat\(39 downto 32),
      dina(35) => '0',
      dina(34 downto 27) => \mi_h2c_wr_brg_dat\\.wdat\(31 downto 24),
      dina(26) => '0',
      dina(25 downto 18) => \mi_h2c_wr_brg_dat\\.wdat\(23 downto 16),
      dina(17) => '0',
      dina(16 downto 9) => \mi_h2c_wr_brg_dat\\.wdat\(15 downto 8),
      dina(8) => '0',
      dina(7 downto 0) => \mi_h2c_wr_brg_dat\\.wdat\(7 downto 0),
      doutb(71 downto 0) => doutb(71 downto 0),
      ena => '1',
      enb => '1',
      wea(7) => \mi_h2c_wr_brg_dat\\.wen\(0),
      wea(6 downto 0) => B"0000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__1\ is
  port (
    \mi_h2c0_dat\\.rdat\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC;
    \mi_h2c0_dat\\.wen\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mi_h2c0_dat\\.wadr\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 71 downto 0 );
    \mi_h2c0_dat\\.radr\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__1\ : entity is "xdma_v4_1_8_dma_bram_wrap";
end \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__1\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__1\ is
  signal \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 71 downto 8 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \genblk1[0].u_buffermem\ : label is "xdma_v4_1_8_blk_mem_64_reg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \genblk1[0].u_buffermem\ : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \genblk1[0].u_buffermem\ : label is "blk_mem_gen_v8_4_4,Vivado 2020.2";
begin
\genblk1[0].u_buffermem\: entity work.xdma_0_xdma_v4_1_8_blk_mem_64_reg_be
     port map (
      addra(8 downto 0) => \mi_h2c0_dat\\.wadr\(8 downto 0),
      addrb(8 downto 0) => \mi_h2c0_dat\\.radr\(8 downto 0),
      clka => user_clk,
      clkb => '0',
      dina(71 downto 0) => dina(71 downto 0),
      doutb(71) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(71),
      doutb(70 downto 63) => \mi_h2c0_dat\\.rdat\(63 downto 56),
      doutb(62) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(62),
      doutb(61 downto 54) => \mi_h2c0_dat\\.rdat\(55 downto 48),
      doutb(53) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(53),
      doutb(52 downto 45) => \mi_h2c0_dat\\.rdat\(47 downto 40),
      doutb(44) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(44),
      doutb(43 downto 36) => \mi_h2c0_dat\\.rdat\(39 downto 32),
      doutb(35) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(35),
      doutb(34 downto 27) => \mi_h2c0_dat\\.rdat\(31 downto 24),
      doutb(26) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(26),
      doutb(25 downto 18) => \mi_h2c0_dat\\.rdat\(23 downto 16),
      doutb(17) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(17),
      doutb(16 downto 9) => \mi_h2c0_dat\\.rdat\(15 downto 8),
      doutb(8) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(8),
      doutb(7 downto 0) => \mi_h2c0_dat\\.rdat\(7 downto 0),
      ena => '1',
      enb => '1',
      wea(7) => \mi_h2c0_dat\\.wen\(0),
      wea(6 downto 0) => B"0000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__5\ is
  port (
    \mi_c2h0_dat\\.rdat\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC;
    \mi_c2h0_dat\\.wen\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \mi_c2h0_dat\\.wadr\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \mi_c2h0_dat\\.wdat\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \mi_c2h0_dat\\.radr\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__5\ : entity is "xdma_v4_1_8_dma_bram_wrap";
end \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__5\;

architecture STRUCTURE of \xdma_0_xdma_v4_1_8_dma_bram_wrap__xdcDup__5\ is
  signal \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 71 downto 8 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of \genblk1[0].u_buffermem\ : label is "xdma_v4_1_8_blk_mem_64_reg_be,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of \genblk1[0].u_buffermem\ : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of \genblk1[0].u_buffermem\ : label is "blk_mem_gen_v8_4_4,Vivado 2020.2";
begin
\genblk1[0].u_buffermem\: entity work.\xdma_0_xdma_v4_1_8_blk_mem_64_reg_be__11\
     port map (
      addra(8 downto 0) => \mi_c2h0_dat\\.wadr\(8 downto 0),
      addrb(8 downto 0) => \mi_c2h0_dat\\.radr\(8 downto 0),
      clka => user_clk,
      clkb => '0',
      dina(71) => '0',
      dina(70 downto 63) => \mi_c2h0_dat\\.wdat\(63 downto 56),
      dina(62) => '0',
      dina(61 downto 54) => \mi_c2h0_dat\\.wdat\(55 downto 48),
      dina(53) => '0',
      dina(52 downto 45) => \mi_c2h0_dat\\.wdat\(47 downto 40),
      dina(44) => '0',
      dina(43 downto 36) => \mi_c2h0_dat\\.wdat\(39 downto 32),
      dina(35) => '0',
      dina(34 downto 27) => \mi_c2h0_dat\\.wdat\(31 downto 24),
      dina(26) => '0',
      dina(25 downto 18) => \mi_c2h0_dat\\.wdat\(23 downto 16),
      dina(17) => '0',
      dina(16 downto 9) => \mi_c2h0_dat\\.wdat\(15 downto 8),
      dina(8) => '0',
      dina(7 downto 0) => \mi_c2h0_dat\\.wdat\(7 downto 0),
      doutb(71) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(71),
      doutb(70 downto 63) => \mi_c2h0_dat\\.rdat\(63 downto 56),
      doutb(62) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(62),
      doutb(61 downto 54) => \mi_c2h0_dat\\.rdat\(55 downto 48),
      doutb(53) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(53),
      doutb(52 downto 45) => \mi_c2h0_dat\\.rdat\(47 downto 40),
      doutb(44) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(44),
      doutb(43 downto 36) => \mi_c2h0_dat\\.rdat\(39 downto 32),
      doutb(35) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(35),
      doutb(34 downto 27) => \mi_c2h0_dat\\.rdat\(31 downto 24),
      doutb(26) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(26),
      doutb(25 downto 18) => \mi_c2h0_dat\\.rdat\(23 downto 16),
      doutb(17) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(17),
      doutb(16 downto 9) => \mi_c2h0_dat\\.rdat\(15 downto 8),
      doutb(8) => \NLW_genblk1[0].u_buffermem_doutb_UNCONNECTED\(8),
      doutb(7 downto 0) => \mi_c2h0_dat\\.rdat\(7 downto 0),
      ena => '1',
      enb => '1',
      wea(7) => \mi_c2h0_dat\\.wen\(0),
      wea(6 downto 0) => B"0000000"
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_ip is
  port (
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_acs : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_directed_change_done : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0_xdma_0_pcie2_ip : entity is "xdma_0_pcie2_ip,xdma_0_pcie2_ip_pcie2_top,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_xdma_0_pcie2_ip : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_ip : entity is "xdma_0_pcie2_ip";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0_xdma_0_pcie2_ip : entity is "xdma_0_pcie2_ip_pcie2_top,Vivado 2020.2";
end xdma_0_xdma_0_pcie2_ip;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_ip is
  signal \<const0>\ : STD_LOGIC;
  signal \^cfg_command\ : STD_LOGIC_VECTOR ( 2 to 2 );
  signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 5 );
  signal \^m_axis_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal NLW_inst_cfg_aer_ecrc_check_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_ecrc_gen_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_corr_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_fatal_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_bridge_serr_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_aer_headerlog_set_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_cpl_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msixenable_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msixfm_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_assert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_assert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_assert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_assert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_deassert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_deassert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_deassert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_deassert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_err_cor_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_err_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_err_non_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_pm_as_nak_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_pm_pme_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_pme_to_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_received_setslotpowerlimit_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_pmcsr_pme_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_pmcsr_pme_status_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_received_func_lvl_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_root_control_pme_int_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_root_control_syserr_corr_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_root_control_syserr_fatal_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_ch_gt_drpclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_dclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_mmcm_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_oobclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_pclk_out_slave_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_userclk1_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_userclk2_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie_drp_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_gen3_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_qrst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_rate_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_txoutclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_directed_change_done_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_link_gen2_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_link_partner_gen2_supported_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_link_upcfg_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_received_hot_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pl_sel_lnk_rate_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_gen3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_ovrd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_rst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_start_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_qplld_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_cfgclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_cfgmclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_eos_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_preq_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_tx_cfg_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_tx_err_drop_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_user_app_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_command_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_dcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_dcommand2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_dstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_interrupt_do_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_lcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_lstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_msg_data_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_pcie_link_state_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_pmcsr_powerstate_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cfg_status_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_cfg_vc_tcvc_map_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_inst_common_commands_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_ext_ch_gt_drpdo_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_ext_ch_gt_drprdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_fc_cpld_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_fc_cplh_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_fc_npd_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_fc_pd_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_fc_ph_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_gt_ch_drp_rdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_icap_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_int_qplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_qplloutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_qplloutrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axis_rx_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axis_rx_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 9 );
  signal NLW_inst_pcie_drp_do_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_cpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_pipe_debug_0_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_1_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_2_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_3_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_4_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_5_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_6_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_7_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_8_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_9_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_inst_pipe_drp_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_pipe_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_pclk_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_qpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_pipe_qrst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_pipe_rate_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_pipe_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_pipe_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_pipe_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxdisperr_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxnotintable_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_pipe_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_sync_fsm_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_pipe_sync_fsm_tx_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_pipe_tx_0_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_1_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_2_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_3_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_4_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_5_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_6_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_tx_7_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_inst_pipe_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pl_initial_link_width_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_pl_lane_reversal_mode_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pl_ltssm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_pl_rx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pl_sel_lnk_width_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pl_tx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_qpll_qpllreset_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_tx_buf_av_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of inst : label is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of inst : label is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of inst : label is "TRUE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of inst : label is "TRUE";
  attribute CLASS_CODE : string;
  attribute CLASS_CODE of inst : label is "070001";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of inst : label is 64;
  attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of inst : label is "FALSE";
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of inst : label is "TRUE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of inst : label is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of inst : label is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of inst : label is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of inst : label is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of inst : label is 2;
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of inst : label is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of inst : label is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of inst : label is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of inst : label is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of inst : label is "TRUE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of inst : label is "TRUE";
  attribute REDUCE_OOB_FREQ : string;
  attribute REDUCE_OOB_FREQ of inst : label is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of inst : label is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of inst : label is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of inst : label is "FFFF0000";
  attribute bar_1 : string;
  attribute bar_1 of inst : label is "FFF00000";
  attribute bar_2 : string;
  attribute bar_2 of inst : label is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of inst : label is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of inst : label is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of inst : label is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of inst : label is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of inst : label is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of inst : label is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of inst : label is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of inst : label is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of inst : label is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of inst : label is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of inst : label is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of inst : label is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of inst : label is "TRUE";
  attribute c_component_name : string;
  attribute c_component_name of inst : label is "xdma_0_pcie2_ip";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of inst : label is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of inst : label is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of inst : label is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of inst : label is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of inst : label is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of inst : label is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of inst : label is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of inst : label is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of inst : label is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of inst : label is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of inst : label is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of inst : label is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of inst : label is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of inst : label is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of inst : label is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of inst : label is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of inst : label is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of inst : label is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of inst : label is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of inst : label is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of inst : label is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of inst : label is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of inst : label is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of inst : label is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of inst : label is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of inst : label is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of inst : label is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of inst : label is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of inst : label is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of inst : label is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of inst : label is "461";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of inst : label is "36";
  attribute c_fc_npd : string;
  attribute c_fc_npd of inst : label is "24";
  attribute c_fc_nph : string;
  attribute c_fc_nph of inst : label is "12";
  attribute c_fc_pd : string;
  attribute c_fc_pd of inst : label is "437";
  attribute c_fc_ph : string;
  attribute c_fc_ph of inst : label is "32";
  attribute c_gen1 : string;
  attribute c_gen1 of inst : label is "1'b1";
  attribute c_header_type : string;
  attribute c_header_type of inst : label is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of inst : label is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of inst : label is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of inst : label is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of inst : label is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of inst : label is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of inst : label is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of inst : label is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of inst : label is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of inst : label is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of inst : label is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of inst : label is "FALSE";
  attribute c_msi : string;
  attribute c_msi of inst : label is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of inst : label is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of inst : label is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of inst : label is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of inst : label is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of inst : label is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of inst : label is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of inst : label is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of inst : label is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of inst : label is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of inst : label is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of inst : label is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of inst : label is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of inst : label is "0";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of inst : label is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of inst : label is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of inst : label is "FALSE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of inst : label is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of inst : label is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of inst : label is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of inst : label is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of inst : label is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of inst : label is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of inst : label is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of inst : label is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of inst : label is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of inst : label is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of inst : label is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of inst : label is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of inst : label is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of inst : label is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of inst : label is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of inst : label is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of inst : label is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of inst : label is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of inst : label is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of inst : label is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of inst : label is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of inst : label is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of inst : label is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of inst : label is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of inst : label is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of inst : label is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of inst : label is "0";
  attribute c_rcb : string;
  attribute c_rcb of inst : label is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of inst : label is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of inst : label is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of inst : label is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of inst : label is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of inst : label is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of inst : label is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of inst : label is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of inst : label is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of inst : label is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of inst : label is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of inst : label is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of inst : label is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of inst : label is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of inst : label is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of inst : label is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of inst : label is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of inst : label is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of inst : label is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of inst : label is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of inst : label is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of inst : label is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of inst : label is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of inst : label is "2";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of inst : label is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of inst : label is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of inst : label is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of inst : label is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of inst : label is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of inst : label is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of inst : label is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of inst : label is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of inst : label is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of inst : label is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of inst : label is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of inst : label is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of inst : label is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of inst : label is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of inst : label is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of inst : label is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of inst : label is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of inst : label is "NONE";
  attribute cap_ver : string;
  attribute cap_ver of inst : label is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of inst : label is "00000000";
  attribute cmps : string;
  attribute cmps of inst : label is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of inst : label is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of inst : label is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of inst : label is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of inst : label is "0";
  attribute cost_table : integer;
  attribute cost_table of inst : label is 1;
  attribute d1_sup : string;
  attribute d1_sup of inst : label is "0";
  attribute d2_sup : string;
  attribute d2_sup of inst : label is "0";
  attribute dev_id : string;
  attribute dev_id of inst : label is "7022";
  attribute dev_port_type : string;
  attribute dev_port_type of inst : label is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of inst : label is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of inst : label is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of inst : label is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of inst : label is "0";
  attribute dsi : string;
  attribute dsi of inst : label is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of inst : label is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of inst : label is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of inst : label is "TRUE";
  attribute int_pin : string;
  attribute int_pin of inst : label is "1";
  attribute intx : string;
  attribute intx of inst : label is "TRUE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of inst : label is "2";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of inst : label is "000010";
  attribute mps : string;
  attribute mps of inst : label is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of inst : label is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of inst : label is 2;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of inst : label is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of inst : label is "00";
  attribute pme_sup : string;
  attribute pme_sup of inst : label is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of inst : label is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of inst : label is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of inst : label is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of inst : label is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of inst : label is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of inst : label is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of inst : label is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of inst : label is "00";
  attribute rev_id : string;
  attribute rev_id of inst : label is "00";
  attribute slot_clk : string;
  attribute slot_clk of inst : label is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of inst : label is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of inst : label is "10EE";
  attribute ven_id : string;
  attribute ven_id of inst : label is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of inst : label is "00000000";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of cfg_aer_ecrc_check_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en";
  attribute X_INTERFACE_INFO of cfg_aer_ecrc_gen_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_corr_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_corr_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_non_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received";
  attribute X_INTERFACE_INFO of cfg_aer_rooterr_non_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en";
  attribute X_INTERFACE_INFO of cfg_bridge_serr_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en";
  attribute X_INTERFACE_INFO of cfg_err_acs : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs";
  attribute X_INTERFACE_INFO of cfg_err_aer_headerlog_set : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set";
  attribute X_INTERFACE_INFO of cfg_err_atomic_egress_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked";
  attribute X_INTERFACE_INFO of cfg_err_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor";
  attribute X_INTERFACE_INFO of cfg_err_cpl_abort : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort";
  attribute X_INTERFACE_INFO of cfg_err_cpl_rdy : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy";
  attribute X_INTERFACE_INFO of cfg_err_cpl_timeout : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout";
  attribute X_INTERFACE_INFO of cfg_err_cpl_unexpect : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect";
  attribute X_INTERFACE_INFO of cfg_err_ecrc : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc";
  attribute X_INTERFACE_INFO of cfg_err_internal_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor";
  attribute X_INTERFACE_INFO of cfg_err_internal_uncor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor";
  attribute X_INTERFACE_INFO of cfg_err_locked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked";
  attribute X_INTERFACE_INFO of cfg_err_malformed : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed";
  attribute X_INTERFACE_INFO of cfg_err_mc_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked";
  attribute X_INTERFACE_INFO of cfg_err_norecovery : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery";
  attribute X_INTERFACE_INFO of cfg_err_poisoned : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned";
  attribute X_INTERFACE_INFO of cfg_err_posted : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted";
  attribute X_INTERFACE_INFO of cfg_err_ur : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur";
  attribute X_INTERFACE_INFO of cfg_interrupt : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt";
  attribute X_INTERFACE_INFO of cfg_interrupt_assert : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert";
  attribute X_INTERFACE_INFO of cfg_interrupt_msienable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable";
  attribute X_INTERFACE_INFO of cfg_interrupt_msixenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable";
  attribute X_INTERFACE_INFO of cfg_interrupt_msixfm : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm";
  attribute X_INTERFACE_INFO of cfg_interrupt_rdy : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy";
  attribute X_INTERFACE_INFO of cfg_interrupt_stat : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat";
  attribute X_INTERFACE_INFO of cfg_mgmt_rd_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN";
  attribute X_INTERFACE_INFO of cfg_mgmt_rd_wr_done : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE";
  attribute X_INTERFACE_INFO of cfg_mgmt_wr_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN";
  attribute X_INTERFACE_INFO of cfg_mgmt_wr_readonly : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY";
  attribute X_INTERFACE_INFO of cfg_mgmt_wr_rw1c_as_rw : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS";
  attribute X_INTERFACE_INFO of cfg_msg_received : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received";
  attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_a : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a";
  attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_b : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b";
  attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_c : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c";
  attribute X_INTERFACE_INFO of cfg_msg_received_assert_int_d : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d";
  attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_a : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a";
  attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_b : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b";
  attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_c : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c";
  attribute X_INTERFACE_INFO of cfg_msg_received_deassert_int_d : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d";
  attribute X_INTERFACE_INFO of cfg_msg_received_err_cor : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor";
  attribute X_INTERFACE_INFO of cfg_msg_received_err_fatal : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal";
  attribute X_INTERFACE_INFO of cfg_msg_received_err_non_fatal : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal";
  attribute X_INTERFACE_INFO of cfg_msg_received_pm_as_nak : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak";
  attribute X_INTERFACE_INFO of cfg_msg_received_pm_pme : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme";
  attribute X_INTERFACE_INFO of cfg_msg_received_pme_to_ack : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack";
  attribute X_INTERFACE_INFO of cfg_msg_received_setslotpowerlimit : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit";
  attribute X_INTERFACE_INFO of cfg_pm_force_state_en : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en";
  attribute X_INTERFACE_INFO of cfg_pm_halt_aspm_l0s : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s";
  attribute X_INTERFACE_INFO of cfg_pm_halt_aspm_l1 : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1";
  attribute X_INTERFACE_INFO of cfg_pm_send_pme_to : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to";
  attribute X_INTERFACE_INFO of cfg_pm_wake : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake";
  attribute X_INTERFACE_INFO of cfg_pmcsr_pme_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en";
  attribute X_INTERFACE_INFO of cfg_pmcsr_pme_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status";
  attribute X_INTERFACE_INFO of cfg_received_func_lvl_rst : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst";
  attribute X_INTERFACE_INFO of cfg_root_control_pme_int_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en";
  attribute X_INTERFACE_INFO of cfg_root_control_syserr_corr_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en";
  attribute X_INTERFACE_INFO of cfg_root_control_syserr_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en";
  attribute X_INTERFACE_INFO of cfg_root_control_syserr_non_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en";
  attribute X_INTERFACE_INFO of cfg_slot_control_electromech_il_ctl_pulse : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse";
  attribute X_INTERFACE_INFO of cfg_to_turnoff : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff";
  attribute X_INTERFACE_INFO of cfg_trn_pending : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending";
  attribute X_INTERFACE_INFO of cfg_turnoff_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok";
  attribute X_INTERFACE_INFO of m_axis_rx_tlast : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TLAST";
  attribute X_INTERFACE_INFO of m_axis_rx_tready : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TREADY";
  attribute X_INTERFACE_INFO of m_axis_rx_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TVALID";
  attribute X_INTERFACE_INFO of pl_directed_change_done : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done";
  attribute X_INTERFACE_INFO of pl_directed_link_auton : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton";
  attribute X_INTERFACE_INFO of pl_directed_link_speed : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed";
  attribute X_INTERFACE_INFO of pl_downstream_deemph_source : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source";
  attribute X_INTERFACE_INFO of pl_link_gen2_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap";
  attribute X_INTERFACE_INFO of pl_link_partner_gen2_supported : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported";
  attribute X_INTERFACE_INFO of pl_link_upcfg_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap";
  attribute X_INTERFACE_INFO of pl_phy_lnk_up : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up";
  attribute X_INTERFACE_INFO of pl_received_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst";
  attribute X_INTERFACE_INFO of pl_sel_lnk_rate : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate";
  attribute X_INTERFACE_INFO of pl_transmit_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst";
  attribute X_INTERFACE_INFO of pl_upstream_prefer_deemph : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph";
  attribute X_INTERFACE_INFO of rx_np_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok";
  attribute X_INTERFACE_INFO of rx_np_req : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req";
  attribute X_INTERFACE_INFO of s_axis_tx_tlast : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TLAST";
  attribute X_INTERFACE_INFO of s_axis_tx_tready : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TREADY";
  attribute X_INTERFACE_INFO of s_axis_tx_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TVALID";
  attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of sys_rst_n : signal is "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST";
  attribute X_INTERFACE_PARAMETER of sys_rst_n : signal is "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of tx_cfg_gnt : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt";
  attribute X_INTERFACE_INFO of tx_cfg_req : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req";
  attribute X_INTERFACE_INFO of tx_err_drop : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop";
  attribute X_INTERFACE_INFO of user_clk_out : signal is "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK";
  attribute X_INTERFACE_PARAMETER of user_clk_out : signal is "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of user_reset_out : signal is "xilinx.com:signal:reset:1.0 RST.user_reset_out RST";
  attribute X_INTERFACE_PARAMETER of user_reset_out : signal is "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of cfg_aer_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum";
  attribute X_INTERFACE_INFO of cfg_bus_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number";
  attribute X_INTERFACE_INFO of cfg_command : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command";
  attribute X_INTERFACE_INFO of cfg_dcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand";
  attribute X_INTERFACE_INFO of cfg_dcommand2 : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2";
  attribute X_INTERFACE_INFO of cfg_device_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number";
  attribute X_INTERFACE_INFO of cfg_ds_bus_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number";
  attribute X_INTERFACE_INFO of cfg_ds_device_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number";
  attribute X_INTERFACE_INFO of cfg_ds_function_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number";
  attribute X_INTERFACE_INFO of cfg_dsn : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn";
  attribute X_INTERFACE_INFO of cfg_dstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus";
  attribute X_INTERFACE_INFO of cfg_err_aer_headerlog : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog";
  attribute X_INTERFACE_INFO of cfg_err_tlp_cpl_header : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header";
  attribute X_INTERFACE_INFO of cfg_function_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number";
  attribute X_INTERFACE_INFO of cfg_interrupt_di : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data";
  attribute X_INTERFACE_INFO of cfg_interrupt_do : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data";
  attribute X_INTERFACE_INFO of cfg_interrupt_mmenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable";
  attribute X_INTERFACE_INFO of cfg_lcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand";
  attribute X_INTERFACE_INFO of cfg_lstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus";
  attribute X_INTERFACE_INFO of cfg_mgmt_byte_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN";
  attribute X_INTERFACE_INFO of cfg_mgmt_di : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA";
  attribute X_INTERFACE_INFO of cfg_mgmt_do : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA";
  attribute X_INTERFACE_INFO of cfg_mgmt_dwaddr : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR";
  attribute X_INTERFACE_INFO of cfg_msg_data : signal is "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data";
  attribute X_INTERFACE_INFO of cfg_pcie_link_state : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state";
  attribute X_INTERFACE_INFO of cfg_pciecap_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum";
  attribute X_INTERFACE_INFO of cfg_pm_force_state : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state";
  attribute X_INTERFACE_INFO of cfg_pmcsr_powerstate : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate";
  attribute X_INTERFACE_INFO of cfg_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status";
  attribute X_INTERFACE_INFO of cfg_vc_tcvc_map : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map";
  attribute X_INTERFACE_INFO of fc_cpld : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD";
  attribute X_INTERFACE_INFO of fc_cplh : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH";
  attribute X_INTERFACE_INFO of fc_npd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD";
  attribute X_INTERFACE_INFO of fc_nph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH";
  attribute X_INTERFACE_INFO of fc_pd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD";
  attribute X_INTERFACE_INFO of fc_ph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH";
  attribute X_INTERFACE_INFO of fc_sel : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL";
  attribute X_INTERFACE_INFO of m_axis_rx_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TDATA";
  attribute X_INTERFACE_INFO of m_axis_rx_tkeep : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP";
  attribute X_INTERFACE_INFO of m_axis_rx_tuser : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TUSER";
  attribute X_INTERFACE_PARAMETER of m_axis_rx_tuser : signal is "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of pci_exp_rxn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn";
  attribute X_INTERFACE_INFO of pci_exp_rxp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp";
  attribute X_INTERFACE_INFO of pci_exp_txn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn";
  attribute X_INTERFACE_INFO of pci_exp_txp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp";
  attribute X_INTERFACE_INFO of pl_directed_link_change : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change";
  attribute X_INTERFACE_INFO of pl_directed_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width";
  attribute X_INTERFACE_INFO of pl_initial_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width";
  attribute X_INTERFACE_INFO of pl_lane_reversal_mode : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode";
  attribute X_INTERFACE_INFO of pl_ltssm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state";
  attribute X_INTERFACE_INFO of pl_rx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state";
  attribute X_INTERFACE_INFO of pl_sel_lnk_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width";
  attribute X_INTERFACE_INFO of pl_tx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state";
  attribute X_INTERFACE_INFO of s_axis_tx_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TDATA";
  attribute X_INTERFACE_INFO of s_axis_tx_tkeep : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP";
  attribute X_INTERFACE_INFO of s_axis_tx_tuser : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TUSER";
  attribute X_INTERFACE_PARAMETER of s_axis_tx_tuser : signal is "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of tx_buf_av : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av";
begin
  cfg_aer_ecrc_check_en <= \<const0>\;
  cfg_aer_ecrc_gen_en <= \<const0>\;
  cfg_aer_rooterr_corr_err_received <= \<const0>\;
  cfg_aer_rooterr_corr_err_reporting_en <= \<const0>\;
  cfg_aer_rooterr_fatal_err_received <= \<const0>\;
  cfg_aer_rooterr_fatal_err_reporting_en <= \<const0>\;
  cfg_aer_rooterr_non_fatal_err_received <= \<const0>\;
  cfg_aer_rooterr_non_fatal_err_reporting_en <= \<const0>\;
  cfg_bridge_serr_en <= \<const0>\;
  cfg_command(15) <= \<const0>\;
  cfg_command(14) <= \<const0>\;
  cfg_command(13) <= \<const0>\;
  cfg_command(12) <= \<const0>\;
  cfg_command(11) <= \<const0>\;
  cfg_command(10) <= \<const0>\;
  cfg_command(9) <= \<const0>\;
  cfg_command(8) <= \<const0>\;
  cfg_command(7) <= \<const0>\;
  cfg_command(6) <= \<const0>\;
  cfg_command(5) <= \<const0>\;
  cfg_command(4) <= \<const0>\;
  cfg_command(3) <= \<const0>\;
  cfg_command(2) <= \^cfg_command\(2);
  cfg_command(1) <= \<const0>\;
  cfg_command(0) <= \<const0>\;
  cfg_dcommand(15) <= \<const0>\;
  cfg_dcommand(14 downto 12) <= \^cfg_dcommand\(14 downto 12);
  cfg_dcommand(11) <= \<const0>\;
  cfg_dcommand(10) <= \<const0>\;
  cfg_dcommand(9) <= \<const0>\;
  cfg_dcommand(8) <= \<const0>\;
  cfg_dcommand(7 downto 5) <= \^cfg_dcommand\(7 downto 5);
  cfg_dcommand(4) <= \<const0>\;
  cfg_dcommand(3) <= \<const0>\;
  cfg_dcommand(2) <= \<const0>\;
  cfg_dcommand(1) <= \<const0>\;
  cfg_dcommand(0) <= \<const0>\;
  cfg_dcommand2(15) <= \<const0>\;
  cfg_dcommand2(14) <= \<const0>\;
  cfg_dcommand2(13) <= \<const0>\;
  cfg_dcommand2(12) <= \<const0>\;
  cfg_dcommand2(11) <= \<const0>\;
  cfg_dcommand2(10) <= \<const0>\;
  cfg_dcommand2(9) <= \<const0>\;
  cfg_dcommand2(8) <= \<const0>\;
  cfg_dcommand2(7) <= \<const0>\;
  cfg_dcommand2(6) <= \<const0>\;
  cfg_dcommand2(5) <= \<const0>\;
  cfg_dcommand2(4) <= \<const0>\;
  cfg_dcommand2(3) <= \<const0>\;
  cfg_dcommand2(2) <= \<const0>\;
  cfg_dcommand2(1) <= \<const0>\;
  cfg_dcommand2(0) <= \<const0>\;
  cfg_dstatus(15) <= \<const0>\;
  cfg_dstatus(14) <= \<const0>\;
  cfg_dstatus(13) <= \<const0>\;
  cfg_dstatus(12) <= \<const0>\;
  cfg_dstatus(11) <= \<const0>\;
  cfg_dstatus(10) <= \<const0>\;
  cfg_dstatus(9) <= \<const0>\;
  cfg_dstatus(8) <= \<const0>\;
  cfg_dstatus(7) <= \<const0>\;
  cfg_dstatus(6) <= \<const0>\;
  cfg_dstatus(5) <= \<const0>\;
  cfg_dstatus(4) <= \<const0>\;
  cfg_dstatus(3) <= \<const0>\;
  cfg_dstatus(2) <= \<const0>\;
  cfg_dstatus(1) <= \<const0>\;
  cfg_dstatus(0) <= \<const0>\;
  cfg_err_aer_headerlog_set <= \<const0>\;
  cfg_err_cpl_rdy <= \<const0>\;
  cfg_interrupt_do(7) <= \<const0>\;
  cfg_interrupt_do(6) <= \<const0>\;
  cfg_interrupt_do(5) <= \<const0>\;
  cfg_interrupt_do(4) <= \<const0>\;
  cfg_interrupt_do(3) <= \<const0>\;
  cfg_interrupt_do(2) <= \<const0>\;
  cfg_interrupt_do(1) <= \<const0>\;
  cfg_interrupt_do(0) <= \<const0>\;
  cfg_interrupt_msixenable <= \<const0>\;
  cfg_interrupt_msixfm <= \<const0>\;
  cfg_lcommand(15) <= \<const0>\;
  cfg_lcommand(14) <= \<const0>\;
  cfg_lcommand(13) <= \<const0>\;
  cfg_lcommand(12) <= \<const0>\;
  cfg_lcommand(11) <= \<const0>\;
  cfg_lcommand(10) <= \<const0>\;
  cfg_lcommand(9) <= \<const0>\;
  cfg_lcommand(8) <= \<const0>\;
  cfg_lcommand(7) <= \<const0>\;
  cfg_lcommand(6) <= \<const0>\;
  cfg_lcommand(5) <= \<const0>\;
  cfg_lcommand(4) <= \<const0>\;
  cfg_lcommand(3) <= \<const0>\;
  cfg_lcommand(2) <= \<const0>\;
  cfg_lcommand(1) <= \<const0>\;
  cfg_lcommand(0) <= \<const0>\;
  cfg_lstatus(15) <= \<const0>\;
  cfg_lstatus(14) <= \<const0>\;
  cfg_lstatus(13) <= \<const0>\;
  cfg_lstatus(12) <= \<const0>\;
  cfg_lstatus(11) <= \<const0>\;
  cfg_lstatus(10) <= \<const0>\;
  cfg_lstatus(9) <= \<const0>\;
  cfg_lstatus(8) <= \<const0>\;
  cfg_lstatus(7) <= \<const0>\;
  cfg_lstatus(6) <= \<const0>\;
  cfg_lstatus(5) <= \<const0>\;
  cfg_lstatus(4) <= \<const0>\;
  cfg_lstatus(3) <= \<const0>\;
  cfg_lstatus(2) <= \<const0>\;
  cfg_lstatus(1) <= \<const0>\;
  cfg_lstatus(0) <= \<const0>\;
  cfg_msg_data(15) <= \<const0>\;
  cfg_msg_data(14) <= \<const0>\;
  cfg_msg_data(13) <= \<const0>\;
  cfg_msg_data(12) <= \<const0>\;
  cfg_msg_data(11) <= \<const0>\;
  cfg_msg_data(10) <= \<const0>\;
  cfg_msg_data(9) <= \<const0>\;
  cfg_msg_data(8) <= \<const0>\;
  cfg_msg_data(7) <= \<const0>\;
  cfg_msg_data(6) <= \<const0>\;
  cfg_msg_data(5) <= \<const0>\;
  cfg_msg_data(4) <= \<const0>\;
  cfg_msg_data(3) <= \<const0>\;
  cfg_msg_data(2) <= \<const0>\;
  cfg_msg_data(1) <= \<const0>\;
  cfg_msg_data(0) <= \<const0>\;
  cfg_msg_received <= \<const0>\;
  cfg_msg_received_assert_int_a <= \<const0>\;
  cfg_msg_received_assert_int_b <= \<const0>\;
  cfg_msg_received_assert_int_c <= \<const0>\;
  cfg_msg_received_assert_int_d <= \<const0>\;
  cfg_msg_received_deassert_int_a <= \<const0>\;
  cfg_msg_received_deassert_int_b <= \<const0>\;
  cfg_msg_received_deassert_int_c <= \<const0>\;
  cfg_msg_received_deassert_int_d <= \<const0>\;
  cfg_msg_received_err_cor <= \<const0>\;
  cfg_msg_received_err_fatal <= \<const0>\;
  cfg_msg_received_err_non_fatal <= \<const0>\;
  cfg_msg_received_pm_as_nak <= \<const0>\;
  cfg_msg_received_pm_pme <= \<const0>\;
  cfg_msg_received_pme_to_ack <= \<const0>\;
  cfg_msg_received_setslotpowerlimit <= \<const0>\;
  cfg_pcie_link_state(2) <= \<const0>\;
  cfg_pcie_link_state(1) <= \<const0>\;
  cfg_pcie_link_state(0) <= \<const0>\;
  cfg_pmcsr_pme_en <= \<const0>\;
  cfg_pmcsr_pme_status <= \<const0>\;
  cfg_pmcsr_powerstate(1) <= \<const0>\;
  cfg_pmcsr_powerstate(0) <= \<const0>\;
  cfg_received_func_lvl_rst <= \<const0>\;
  cfg_root_control_pme_int_en <= \<const0>\;
  cfg_root_control_syserr_corr_err_en <= \<const0>\;
  cfg_root_control_syserr_fatal_err_en <= \<const0>\;
  cfg_root_control_syserr_non_fatal_err_en <= \<const0>\;
  cfg_slot_control_electromech_il_ctl_pulse <= \<const0>\;
  cfg_status(15) <= \<const0>\;
  cfg_status(14) <= \<const0>\;
  cfg_status(13) <= \<const0>\;
  cfg_status(12) <= \<const0>\;
  cfg_status(11) <= \<const0>\;
  cfg_status(10) <= \<const0>\;
  cfg_status(9) <= \<const0>\;
  cfg_status(8) <= \<const0>\;
  cfg_status(7) <= \<const0>\;
  cfg_status(6) <= \<const0>\;
  cfg_status(5) <= \<const0>\;
  cfg_status(4) <= \<const0>\;
  cfg_status(3) <= \<const0>\;
  cfg_status(2) <= \<const0>\;
  cfg_status(1) <= \<const0>\;
  cfg_status(0) <= \<const0>\;
  cfg_vc_tcvc_map(6) <= \<const0>\;
  cfg_vc_tcvc_map(5) <= \<const0>\;
  cfg_vc_tcvc_map(4) <= \<const0>\;
  cfg_vc_tcvc_map(3) <= \<const0>\;
  cfg_vc_tcvc_map(2) <= \<const0>\;
  cfg_vc_tcvc_map(1) <= \<const0>\;
  cfg_vc_tcvc_map(0) <= \<const0>\;
  fc_cpld(11) <= \<const0>\;
  fc_cpld(10) <= \<const0>\;
  fc_cpld(9) <= \<const0>\;
  fc_cpld(8) <= \<const0>\;
  fc_cpld(7) <= \<const0>\;
  fc_cpld(6) <= \<const0>\;
  fc_cpld(5) <= \<const0>\;
  fc_cpld(4) <= \<const0>\;
  fc_cpld(3) <= \<const0>\;
  fc_cpld(2) <= \<const0>\;
  fc_cpld(1) <= \<const0>\;
  fc_cpld(0) <= \<const0>\;
  fc_cplh(7) <= \<const0>\;
  fc_cplh(6) <= \<const0>\;
  fc_cplh(5) <= \<const0>\;
  fc_cplh(4) <= \<const0>\;
  fc_cplh(3) <= \<const0>\;
  fc_cplh(2) <= \<const0>\;
  fc_cplh(1) <= \<const0>\;
  fc_cplh(0) <= \<const0>\;
  fc_npd(11) <= \<const0>\;
  fc_npd(10) <= \<const0>\;
  fc_npd(9) <= \<const0>\;
  fc_npd(8) <= \<const0>\;
  fc_npd(7) <= \<const0>\;
  fc_npd(6) <= \<const0>\;
  fc_npd(5) <= \<const0>\;
  fc_npd(4) <= \<const0>\;
  fc_npd(3) <= \<const0>\;
  fc_npd(2) <= \<const0>\;
  fc_npd(1) <= \<const0>\;
  fc_npd(0) <= \<const0>\;
  fc_pd(11) <= \<const0>\;
  fc_pd(10) <= \<const0>\;
  fc_pd(9) <= \<const0>\;
  fc_pd(8) <= \<const0>\;
  fc_pd(7) <= \<const0>\;
  fc_pd(6) <= \<const0>\;
  fc_pd(5) <= \<const0>\;
  fc_pd(4) <= \<const0>\;
  fc_pd(3) <= \<const0>\;
  fc_pd(2) <= \<const0>\;
  fc_pd(1) <= \<const0>\;
  fc_pd(0) <= \<const0>\;
  fc_ph(7) <= \<const0>\;
  fc_ph(6) <= \<const0>\;
  fc_ph(5) <= \<const0>\;
  fc_ph(4) <= \<const0>\;
  fc_ph(3) <= \<const0>\;
  fc_ph(2) <= \<const0>\;
  fc_ph(1) <= \<const0>\;
  fc_ph(0) <= \<const0>\;
  m_axis_rx_tkeep(7 downto 4) <= \^m_axis_rx_tkeep\(7 downto 4);
  m_axis_rx_tkeep(3) <= \<const0>\;
  m_axis_rx_tkeep(2) <= \<const0>\;
  m_axis_rx_tkeep(1) <= \<const0>\;
  m_axis_rx_tkeep(0) <= \<const0>\;
  m_axis_rx_tuser(21) <= \^m_axis_rx_tuser\(21);
  m_axis_rx_tuser(20) <= \<const0>\;
  m_axis_rx_tuser(19 downto 17) <= \^m_axis_rx_tuser\(19 downto 17);
  m_axis_rx_tuser(16) <= \<const0>\;
  m_axis_rx_tuser(15) <= \<const0>\;
  m_axis_rx_tuser(14) <= \^m_axis_rx_tuser\(14);
  m_axis_rx_tuser(13) <= \<const0>\;
  m_axis_rx_tuser(12) <= \<const0>\;
  m_axis_rx_tuser(11) <= \<const0>\;
  m_axis_rx_tuser(10) <= \<const0>\;
  m_axis_rx_tuser(9) <= \<const0>\;
  m_axis_rx_tuser(8 downto 0) <= \^m_axis_rx_tuser\(8 downto 0);
  pl_directed_change_done <= \<const0>\;
  pl_initial_link_width(2) <= \<const0>\;
  pl_initial_link_width(1) <= \<const0>\;
  pl_initial_link_width(0) <= \<const0>\;
  pl_lane_reversal_mode(1) <= \<const0>\;
  pl_lane_reversal_mode(0) <= \<const0>\;
  pl_link_gen2_cap <= \<const0>\;
  pl_link_partner_gen2_supported <= \<const0>\;
  pl_link_upcfg_cap <= \<const0>\;
  pl_ltssm_state(5) <= \<const0>\;
  pl_ltssm_state(4) <= \<const0>\;
  pl_ltssm_state(3) <= \<const0>\;
  pl_ltssm_state(2) <= \<const0>\;
  pl_ltssm_state(1) <= \<const0>\;
  pl_ltssm_state(0) <= \<const0>\;
  pl_received_hot_rst <= \<const0>\;
  pl_rx_pm_state(1) <= \<const0>\;
  pl_rx_pm_state(0) <= \<const0>\;
  pl_sel_lnk_rate <= \<const0>\;
  pl_sel_lnk_width(1) <= \<const0>\;
  pl_sel_lnk_width(0) <= \<const0>\;
  pl_tx_pm_state(2) <= \<const0>\;
  pl_tx_pm_state(1) <= \<const0>\;
  pl_tx_pm_state(0) <= \<const0>\;
  tx_buf_av(5) <= \<const0>\;
  tx_buf_av(4) <= \<const0>\;
  tx_buf_av(3) <= \<const0>\;
  tx_buf_av(2) <= \<const0>\;
  tx_buf_av(1) <= \<const0>\;
  tx_buf_av(0) <= \<const0>\;
  tx_cfg_req <= \<const0>\;
  tx_err_drop <= \<const0>\;
  user_app_rdy <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.xdma_0_xdma_0_pcie2_ip_pcie2_top
     port map (
      cfg_aer_ecrc_check_en => NLW_inst_cfg_aer_ecrc_check_en_UNCONNECTED,
      cfg_aer_ecrc_gen_en => NLW_inst_cfg_aer_ecrc_gen_en_UNCONNECTED,
      cfg_aer_interrupt_msgnum(4 downto 0) => B"00000",
      cfg_aer_rooterr_corr_err_received => NLW_inst_cfg_aer_rooterr_corr_err_received_UNCONNECTED,
      cfg_aer_rooterr_corr_err_reporting_en => NLW_inst_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED,
      cfg_aer_rooterr_fatal_err_received => NLW_inst_cfg_aer_rooterr_fatal_err_received_UNCONNECTED,
      cfg_aer_rooterr_fatal_err_reporting_en => NLW_inst_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED,
      cfg_aer_rooterr_non_fatal_err_received => NLW_inst_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED,
      cfg_aer_rooterr_non_fatal_err_reporting_en => NLW_inst_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED,
      cfg_bridge_serr_en => NLW_inst_cfg_bridge_serr_en_UNCONNECTED,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(15 downto 3) => NLW_inst_cfg_command_UNCONNECTED(15 downto 3),
      cfg_command(2) => \^cfg_command\(2),
      cfg_command(1 downto 0) => NLW_inst_cfg_command_UNCONNECTED(1 downto 0),
      cfg_dcommand(15) => NLW_inst_cfg_dcommand_UNCONNECTED(15),
      cfg_dcommand(14 downto 12) => \^cfg_dcommand\(14 downto 12),
      cfg_dcommand(11 downto 8) => NLW_inst_cfg_dcommand_UNCONNECTED(11 downto 8),
      cfg_dcommand(7 downto 5) => \^cfg_dcommand\(7 downto 5),
      cfg_dcommand(4 downto 0) => NLW_inst_cfg_dcommand_UNCONNECTED(4 downto 0),
      cfg_dcommand2(15 downto 0) => NLW_inst_cfg_dcommand2_UNCONNECTED(15 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => B"00000000",
      cfg_ds_device_number(4 downto 0) => B"00000",
      cfg_ds_function_number(2 downto 0) => B"000",
      cfg_dsn(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      cfg_dstatus(15 downto 0) => NLW_inst_cfg_dstatus_UNCONNECTED(15 downto 0),
      cfg_err_acs => '0',
      cfg_err_aer_headerlog(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      cfg_err_aer_headerlog_set => NLW_inst_cfg_err_aer_headerlog_set_UNCONNECTED,
      cfg_err_atomic_egress_blocked => '0',
      cfg_err_cor => '0',
      cfg_err_cpl_abort => '0',
      cfg_err_cpl_rdy => NLW_inst_cfg_err_cpl_rdy_UNCONNECTED,
      cfg_err_cpl_timeout => '0',
      cfg_err_cpl_unexpect => '0',
      cfg_err_ecrc => '0',
      cfg_err_internal_cor => '0',
      cfg_err_internal_uncor => '0',
      cfg_err_locked => '0',
      cfg_err_malformed => '0',
      cfg_err_mc_blocked => '0',
      cfg_err_norecovery => '0',
      cfg_err_poisoned => '0',
      cfg_err_posted => '0',
      cfg_err_tlp_cpl_header(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      cfg_err_ur => '0',
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 5) => B"000",
      cfg_interrupt_di(4 downto 0) => cfg_interrupt_di(4 downto 0),
      cfg_interrupt_do(7 downto 0) => NLW_inst_cfg_interrupt_do_UNCONNECTED(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => NLW_inst_cfg_interrupt_msixenable_UNCONNECTED,
      cfg_interrupt_msixfm => NLW_inst_cfg_interrupt_msixfm_UNCONNECTED,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => '0',
      cfg_lcommand(15 downto 0) => NLW_inst_cfg_lcommand_UNCONNECTED(15 downto 0),
      cfg_lstatus(15 downto 0) => NLW_inst_cfg_lstatus_UNCONNECTED(15 downto 0),
      cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => '0',
      cfg_msg_data(15 downto 0) => NLW_inst_cfg_msg_data_UNCONNECTED(15 downto 0),
      cfg_msg_received => NLW_inst_cfg_msg_received_UNCONNECTED,
      cfg_msg_received_assert_int_a => NLW_inst_cfg_msg_received_assert_int_a_UNCONNECTED,
      cfg_msg_received_assert_int_b => NLW_inst_cfg_msg_received_assert_int_b_UNCONNECTED,
      cfg_msg_received_assert_int_c => NLW_inst_cfg_msg_received_assert_int_c_UNCONNECTED,
      cfg_msg_received_assert_int_d => NLW_inst_cfg_msg_received_assert_int_d_UNCONNECTED,
      cfg_msg_received_deassert_int_a => NLW_inst_cfg_msg_received_deassert_int_a_UNCONNECTED,
      cfg_msg_received_deassert_int_b => NLW_inst_cfg_msg_received_deassert_int_b_UNCONNECTED,
      cfg_msg_received_deassert_int_c => NLW_inst_cfg_msg_received_deassert_int_c_UNCONNECTED,
      cfg_msg_received_deassert_int_d => NLW_inst_cfg_msg_received_deassert_int_d_UNCONNECTED,
      cfg_msg_received_err_cor => NLW_inst_cfg_msg_received_err_cor_UNCONNECTED,
      cfg_msg_received_err_fatal => NLW_inst_cfg_msg_received_err_fatal_UNCONNECTED,
      cfg_msg_received_err_non_fatal => NLW_inst_cfg_msg_received_err_non_fatal_UNCONNECTED,
      cfg_msg_received_pm_as_nak => NLW_inst_cfg_msg_received_pm_as_nak_UNCONNECTED,
      cfg_msg_received_pm_pme => NLW_inst_cfg_msg_received_pm_pme_UNCONNECTED,
      cfg_msg_received_pme_to_ack => NLW_inst_cfg_msg_received_pme_to_ack_UNCONNECTED,
      cfg_msg_received_setslotpowerlimit => NLW_inst_cfg_msg_received_setslotpowerlimit_UNCONNECTED,
      cfg_pcie_link_state(2 downto 0) => NLW_inst_cfg_pcie_link_state_UNCONNECTED(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => B"00000",
      cfg_pm_force_state(1 downto 0) => B"00",
      cfg_pm_force_state_en => '0',
      cfg_pm_halt_aspm_l0s => '0',
      cfg_pm_halt_aspm_l1 => '0',
      cfg_pm_send_pme_to => '0',
      cfg_pm_wake => '0',
      cfg_pmcsr_pme_en => NLW_inst_cfg_pmcsr_pme_en_UNCONNECTED,
      cfg_pmcsr_pme_status => NLW_inst_cfg_pmcsr_pme_status_UNCONNECTED,
      cfg_pmcsr_powerstate(1 downto 0) => NLW_inst_cfg_pmcsr_powerstate_UNCONNECTED(1 downto 0),
      cfg_received_func_lvl_rst => NLW_inst_cfg_received_func_lvl_rst_UNCONNECTED,
      cfg_root_control_pme_int_en => NLW_inst_cfg_root_control_pme_int_en_UNCONNECTED,
      cfg_root_control_syserr_corr_err_en => NLW_inst_cfg_root_control_syserr_corr_err_en_UNCONNECTED,
      cfg_root_control_syserr_fatal_err_en => NLW_inst_cfg_root_control_syserr_fatal_err_en_UNCONNECTED,
      cfg_root_control_syserr_non_fatal_err_en => NLW_inst_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED,
      cfg_slot_control_electromech_il_ctl_pulse => NLW_inst_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED,
      cfg_status(15 downto 0) => NLW_inst_cfg_status_UNCONNECTED(15 downto 0),
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => '0',
      cfg_turnoff_ok => '0',
      cfg_vc_tcvc_map(6 downto 0) => NLW_inst_cfg_vc_tcvc_map_UNCONNECTED(6 downto 0),
      common_commands_in(11 downto 0) => B"000000000000",
      common_commands_out(11 downto 0) => NLW_inst_common_commands_out_UNCONNECTED(11 downto 0),
      ext_ch_gt_drpaddr(17 downto 0) => B"000000000000000000",
      ext_ch_gt_drpclk => NLW_inst_ext_ch_gt_drpclk_UNCONNECTED,
      ext_ch_gt_drpdi(31 downto 0) => B"00000000000000000000000000000000",
      ext_ch_gt_drpdo(31 downto 0) => NLW_inst_ext_ch_gt_drpdo_UNCONNECTED(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => B"00",
      ext_ch_gt_drprdy(1 downto 0) => NLW_inst_ext_ch_gt_drprdy_UNCONNECTED(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => B"00",
      fc_cpld(11 downto 0) => NLW_inst_fc_cpld_UNCONNECTED(11 downto 0),
      fc_cplh(7 downto 0) => NLW_inst_fc_cplh_UNCONNECTED(7 downto 0),
      fc_npd(11 downto 0) => NLW_inst_fc_npd_UNCONNECTED(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => NLW_inst_fc_pd_UNCONNECTED(11 downto 0),
      fc_ph(7 downto 0) => NLW_inst_fc_ph_UNCONNECTED(7 downto 0),
      fc_sel(2 downto 1) => B"10",
      fc_sel(0) => fc_sel(0),
      gt_ch_drp_rdy(1 downto 0) => NLW_inst_gt_ch_drp_rdy_UNCONNECTED(1 downto 0),
      icap_clk => '0',
      icap_csib => '0',
      icap_i(31 downto 0) => B"00000000000000000000000000000000",
      icap_o(31 downto 0) => NLW_inst_icap_o_UNCONNECTED(31 downto 0),
      icap_rdwrb => '0',
      int_dclk_out => NLW_inst_int_dclk_out_UNCONNECTED,
      int_mmcm_lock_out => NLW_inst_int_mmcm_lock_out_UNCONNECTED,
      int_oobclk_out => NLW_inst_int_oobclk_out_UNCONNECTED,
      int_pclk_out_slave => NLW_inst_int_pclk_out_slave_UNCONNECTED,
      int_pclk_sel_slave(1 downto 0) => B"00",
      int_pipe_rxusrclk_out => NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED,
      int_qplllock_out(1 downto 0) => NLW_inst_int_qplllock_out_UNCONNECTED(1 downto 0),
      int_qplloutclk_out(1 downto 0) => NLW_inst_int_qplloutclk_out_UNCONNECTED(1 downto 0),
      int_qplloutrefclk_out(1 downto 0) => NLW_inst_int_qplloutrefclk_out_UNCONNECTED(1 downto 0),
      int_rxoutclk_out(1 downto 0) => NLW_inst_int_rxoutclk_out_UNCONNECTED(1 downto 0),
      int_userclk1_out => NLW_inst_int_userclk1_out_UNCONNECTED,
      int_userclk2_out => NLW_inst_int_userclk2_out_UNCONNECTED,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 4) => \^m_axis_rx_tkeep\(7 downto 4),
      m_axis_rx_tkeep(3 downto 0) => NLW_inst_m_axis_rx_tkeep_UNCONNECTED(3 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21) => \^m_axis_rx_tuser\(21),
      m_axis_rx_tuser(20) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(20),
      m_axis_rx_tuser(19 downto 17) => \^m_axis_rx_tuser\(19 downto 17),
      m_axis_rx_tuser(16 downto 15) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(16 downto 15),
      m_axis_rx_tuser(14) => \^m_axis_rx_tuser\(14),
      m_axis_rx_tuser(13 downto 9) => NLW_inst_m_axis_rx_tuser_UNCONNECTED(13 downto 9),
      m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser\(8 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pcie_drp_addr(8 downto 0) => B"000000000",
      pcie_drp_clk => '1',
      pcie_drp_di(15 downto 0) => B"0000000000000000",
      pcie_drp_do(15 downto 0) => NLW_inst_pcie_drp_do_UNCONNECTED(15 downto 0),
      pcie_drp_en => '0',
      pcie_drp_rdy => NLW_inst_pcie_drp_rdy_UNCONNECTED,
      pcie_drp_we => '0',
      pipe_cpll_lock(1 downto 0) => NLW_inst_pipe_cpll_lock_UNCONNECTED(1 downto 0),
      pipe_dclk_in => '0',
      pipe_debug(31 downto 0) => NLW_inst_pipe_debug_UNCONNECTED(31 downto 0),
      pipe_debug_0(1 downto 0) => NLW_inst_pipe_debug_0_UNCONNECTED(1 downto 0),
      pipe_debug_1(1 downto 0) => NLW_inst_pipe_debug_1_UNCONNECTED(1 downto 0),
      pipe_debug_2(1 downto 0) => NLW_inst_pipe_debug_2_UNCONNECTED(1 downto 0),
      pipe_debug_3(1 downto 0) => NLW_inst_pipe_debug_3_UNCONNECTED(1 downto 0),
      pipe_debug_4(1 downto 0) => NLW_inst_pipe_debug_4_UNCONNECTED(1 downto 0),
      pipe_debug_5(1 downto 0) => NLW_inst_pipe_debug_5_UNCONNECTED(1 downto 0),
      pipe_debug_6(1 downto 0) => NLW_inst_pipe_debug_6_UNCONNECTED(1 downto 0),
      pipe_debug_7(1 downto 0) => NLW_inst_pipe_debug_7_UNCONNECTED(1 downto 0),
      pipe_debug_8(1 downto 0) => NLW_inst_pipe_debug_8_UNCONNECTED(1 downto 0),
      pipe_debug_9(1 downto 0) => NLW_inst_pipe_debug_9_UNCONNECTED(1 downto 0),
      pipe_dmonitorout(29 downto 0) => NLW_inst_pipe_dmonitorout_UNCONNECTED(29 downto 0),
      pipe_drp_fsm(13 downto 0) => NLW_inst_pipe_drp_fsm_UNCONNECTED(13 downto 0),
      pipe_eyescandataerror(1 downto 0) => NLW_inst_pipe_eyescandataerror_UNCONNECTED(1 downto 0),
      pipe_gen3_out => NLW_inst_pipe_gen3_out_UNCONNECTED,
      pipe_loopback(2 downto 0) => B"000",
      pipe_mmcm_lock_in => '1',
      pipe_mmcm_rst_n => '1',
      pipe_oobclk_in => '0',
      pipe_pclk_in => '0',
      pipe_pclk_sel_out(1 downto 0) => NLW_inst_pipe_pclk_sel_out_UNCONNECTED(1 downto 0),
      pipe_qpll_lock(0) => NLW_inst_pipe_qpll_lock_UNCONNECTED(0),
      pipe_qrst_fsm(11 downto 0) => NLW_inst_pipe_qrst_fsm_UNCONNECTED(11 downto 0),
      pipe_qrst_idle => NLW_inst_pipe_qrst_idle_UNCONNECTED,
      pipe_rate_fsm(9 downto 0) => NLW_inst_pipe_rate_fsm_UNCONNECTED(9 downto 0),
      pipe_rate_idle => NLW_inst_pipe_rate_idle_UNCONNECTED,
      pipe_rst_fsm(4 downto 0) => NLW_inst_pipe_rst_fsm_UNCONNECTED(4 downto 0),
      pipe_rst_idle => NLW_inst_pipe_rst_idle_UNCONNECTED,
      pipe_rx_0_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_1_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_2_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_3_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_4_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_5_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_6_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_7_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rxbufstatus(5 downto 0) => NLW_inst_pipe_rxbufstatus_UNCONNECTED(5 downto 0),
      pipe_rxcommadet(1 downto 0) => NLW_inst_pipe_rxcommadet_UNCONNECTED(1 downto 0),
      pipe_rxdisperr(15 downto 0) => NLW_inst_pipe_rxdisperr_UNCONNECTED(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => NLW_inst_pipe_rxdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_rxnotintable(15 downto 0) => NLW_inst_pipe_rxnotintable_UNCONNECTED(15 downto 0),
      pipe_rxoutclk_in(1 downto 0) => B"00",
      pipe_rxoutclk_out(1 downto 0) => NLW_inst_pipe_rxoutclk_out_UNCONNECTED(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => NLW_inst_pipe_rxphaligndone_UNCONNECTED(1 downto 0),
      pipe_rxpmaresetdone(1 downto 0) => NLW_inst_pipe_rxpmaresetdone_UNCONNECTED(1 downto 0),
      pipe_rxprbscntreset => '0',
      pipe_rxprbserr(1 downto 0) => NLW_inst_pipe_rxprbserr_UNCONNECTED(1 downto 0),
      pipe_rxprbssel(2 downto 0) => B"000",
      pipe_rxstatus(5 downto 0) => NLW_inst_pipe_rxstatus_UNCONNECTED(5 downto 0),
      pipe_rxsyncdone(1 downto 0) => NLW_inst_pipe_rxsyncdone_UNCONNECTED(1 downto 0),
      pipe_rxusrclk_in => '0',
      pipe_sync_fsm_rx(13 downto 0) => NLW_inst_pipe_sync_fsm_rx_UNCONNECTED(13 downto 0),
      pipe_sync_fsm_tx(11 downto 0) => NLW_inst_pipe_sync_fsm_tx_UNCONNECTED(11 downto 0),
      pipe_tx_0_sigs(24 downto 0) => NLW_inst_pipe_tx_0_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_1_sigs(24 downto 0) => NLW_inst_pipe_tx_1_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_2_sigs(24 downto 0) => NLW_inst_pipe_tx_2_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_3_sigs(24 downto 0) => NLW_inst_pipe_tx_3_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_4_sigs(24 downto 0) => NLW_inst_pipe_tx_4_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_5_sigs(24 downto 0) => NLW_inst_pipe_tx_5_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_6_sigs(24 downto 0) => NLW_inst_pipe_tx_6_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_7_sigs(24 downto 0) => NLW_inst_pipe_tx_7_sigs_UNCONNECTED(24 downto 0),
      pipe_txdlysresetdone(1 downto 0) => NLW_inst_pipe_txdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_txinhibit(1 downto 0) => B"00",
      pipe_txoutclk_out => NLW_inst_pipe_txoutclk_out_UNCONNECTED,
      pipe_txphaligndone(1 downto 0) => NLW_inst_pipe_txphaligndone_UNCONNECTED(1 downto 0),
      pipe_txphinitdone(1 downto 0) => NLW_inst_pipe_txphinitdone_UNCONNECTED(1 downto 0),
      pipe_txprbsforceerr => '0',
      pipe_txprbssel(2 downto 0) => B"000",
      pipe_userclk1_in => '1',
      pipe_userclk2_in => '0',
      pl_directed_change_done => NLW_inst_pl_directed_change_done_UNCONNECTED,
      pl_directed_link_auton => '0',
      pl_directed_link_change(1 downto 0) => B"00",
      pl_directed_link_speed => '0',
      pl_directed_link_width(1 downto 0) => B"00",
      pl_downstream_deemph_source => '0',
      pl_initial_link_width(2 downto 0) => NLW_inst_pl_initial_link_width_UNCONNECTED(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => NLW_inst_pl_lane_reversal_mode_UNCONNECTED(1 downto 0),
      pl_link_gen2_cap => NLW_inst_pl_link_gen2_cap_UNCONNECTED,
      pl_link_partner_gen2_supported => NLW_inst_pl_link_partner_gen2_supported_UNCONNECTED,
      pl_link_upcfg_cap => NLW_inst_pl_link_upcfg_cap_UNCONNECTED,
      pl_ltssm_state(5 downto 0) => NLW_inst_pl_ltssm_state_UNCONNECTED(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => NLW_inst_pl_received_hot_rst_UNCONNECTED,
      pl_rx_pm_state(1 downto 0) => NLW_inst_pl_rx_pm_state_UNCONNECTED(1 downto 0),
      pl_sel_lnk_rate => NLW_inst_pl_sel_lnk_rate_UNCONNECTED,
      pl_sel_lnk_width(1 downto 0) => NLW_inst_pl_sel_lnk_width_UNCONNECTED(1 downto 0),
      pl_transmit_hot_rst => '0',
      pl_tx_pm_state(2 downto 0) => NLW_inst_pl_tx_pm_state_UNCONNECTED(2 downto 0),
      pl_upstream_prefer_deemph => '0',
      qpll_drp_clk => NLW_inst_qpll_drp_clk_UNCONNECTED,
      qpll_drp_crscode(11 downto 0) => B"000000000000",
      qpll_drp_done(1 downto 0) => B"00",
      qpll_drp_fsm(17 downto 0) => B"000000000000000000",
      qpll_drp_gen3 => NLW_inst_qpll_drp_gen3_UNCONNECTED,
      qpll_drp_ovrd => NLW_inst_qpll_drp_ovrd_UNCONNECTED,
      qpll_drp_reset(1 downto 0) => B"00",
      qpll_drp_rst_n => NLW_inst_qpll_drp_rst_n_UNCONNECTED,
      qpll_drp_start => NLW_inst_qpll_drp_start_UNCONNECTED,
      qpll_qplld => NLW_inst_qpll_qplld_UNCONNECTED,
      qpll_qplllock(1 downto 0) => B"00",
      qpll_qplloutclk(1 downto 0) => B"00",
      qpll_qplloutrefclk(1 downto 0) => B"00",
      qpll_qpllreset(1 downto 0) => NLW_inst_qpll_qpllreset_UNCONNECTED(1 downto 0),
      rx_np_ok => '0',
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(7) => s_axis_tx_tkeep(7),
      s_axis_tx_tkeep(6 downto 0) => B"0000000",
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => B"0000",
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      startup_cfgclk => NLW_inst_startup_cfgclk_UNCONNECTED,
      startup_cfgmclk => NLW_inst_startup_cfgmclk_UNCONNECTED,
      startup_clk => '0',
      startup_eos => NLW_inst_startup_eos_UNCONNECTED,
      startup_eos_in => '0',
      startup_gsr => '0',
      startup_gts => '0',
      startup_keyclearb => '1',
      startup_pack => '0',
      startup_preq => NLW_inst_startup_preq_UNCONNECTED,
      startup_usrcclko => '1',
      startup_usrcclkts => '0',
      startup_usrdoneo => '0',
      startup_usrdonets => '1',
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      tx_buf_av(5 downto 0) => NLW_inst_tx_buf_av_UNCONNECTED(5 downto 0),
      tx_cfg_gnt => '1',
      tx_cfg_req => NLW_inst_tx_cfg_req_UNCONNECTED,
      tx_err_drop => NLW_inst_tx_err_drop_UNCONNECTED,
      user_app_rdy => NLW_inst_user_app_rdy_UNCONNECTED,
      user_clk_out => user_clk_out,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_pcie2_fifo_generator_dma_cpl is
  port (
    s_aclk : in STD_LOGIC;
    s_aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tlast : in STD_LOGIC;
    s_axis_tuser : in STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_tlast : out STD_LOGIC;
    m_axis_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    axis_prog_full : out STD_LOGIC
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0_pcie2_fifo_generator_dma_cpl : entity is "pcie2_fifo_generator_dma_cpl,fifo_generator_v13_1_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0_pcie2_fifo_generator_dma_cpl : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_pcie2_fifo_generator_dma_cpl : entity is "pcie2_fifo_generator_dma_cpl";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0_pcie2_fifo_generator_dma_cpl : entity is "fifo_generator_v13_1_4,Vivado 2020.2";
end xdma_0_pcie2_fifo_generator_dma_cpl;

architecture STRUCTURE of xdma_0_pcie2_fifo_generator_dma_cpl is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_dout_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute C_ADD_NGC_CONSTRAINT : integer;
  attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
  attribute C_APPLICATION_TYPE_AXIS : integer;
  attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
  attribute C_APPLICATION_TYPE_RACH : integer;
  attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_RDCH : integer;
  attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WACH : integer;
  attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WDCH : integer;
  attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
  attribute C_APPLICATION_TYPE_WRCH : integer;
  attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
  attribute C_AXIS_TDATA_WIDTH : integer;
  attribute C_AXIS_TDATA_WIDTH of U0 : label is 64;
  attribute C_AXIS_TDEST_WIDTH : integer;
  attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
  attribute C_AXIS_TID_WIDTH : integer;
  attribute C_AXIS_TID_WIDTH of U0 : label is 1;
  attribute C_AXIS_TKEEP_WIDTH : integer;
  attribute C_AXIS_TKEEP_WIDTH of U0 : label is 8;
  attribute C_AXIS_TSTRB_WIDTH : integer;
  attribute C_AXIS_TSTRB_WIDTH of U0 : label is 8;
  attribute C_AXIS_TUSER_WIDTH : integer;
  attribute C_AXIS_TUSER_WIDTH of U0 : label is 22;
  attribute C_AXIS_TYPE : integer;
  attribute C_AXIS_TYPE of U0 : label is 0;
  attribute C_AXI_ADDR_WIDTH : integer;
  attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
  attribute C_AXI_ARUSER_WIDTH : integer;
  attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_AWUSER_WIDTH : integer;
  attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_BUSER_WIDTH : integer;
  attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_DATA_WIDTH : integer;
  attribute C_AXI_DATA_WIDTH of U0 : label is 64;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 1;
  attribute C_AXI_LEN_WIDTH : integer;
  attribute C_AXI_LEN_WIDTH of U0 : label is 8;
  attribute C_AXI_LOCK_WIDTH : integer;
  attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
  attribute C_AXI_RUSER_WIDTH : integer;
  attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_AXI_WUSER_WIDTH : integer;
  attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
  attribute C_COMMON_CLOCK : integer;
  attribute C_COMMON_CLOCK of U0 : label is 1;
  attribute C_COUNT_TYPE : integer;
  attribute C_COUNT_TYPE of U0 : label is 0;
  attribute C_DATA_COUNT_WIDTH : integer;
  attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_DEFAULT_VALUE : string;
  attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
  attribute C_DIN_WIDTH : integer;
  attribute C_DIN_WIDTH of U0 : label is 18;
  attribute C_DIN_WIDTH_AXIS : integer;
  attribute C_DIN_WIDTH_AXIS of U0 : label is 95;
  attribute C_DIN_WIDTH_RACH : integer;
  attribute C_DIN_WIDTH_RACH of U0 : label is 32;
  attribute C_DIN_WIDTH_RDCH : integer;
  attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
  attribute C_DIN_WIDTH_WACH : integer;
  attribute C_DIN_WIDTH_WACH of U0 : label is 32;
  attribute C_DIN_WIDTH_WDCH : integer;
  attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
  attribute C_DIN_WIDTH_WRCH : integer;
  attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
  attribute C_DOUT_RST_VAL : string;
  attribute C_DOUT_RST_VAL of U0 : label is "0";
  attribute C_DOUT_WIDTH : integer;
  attribute C_DOUT_WIDTH of U0 : label is 18;
  attribute C_ENABLE_RLOCS : integer;
  attribute C_ENABLE_RLOCS of U0 : label is 0;
  attribute C_ENABLE_RST_SYNC : integer;
  attribute C_ENABLE_RST_SYNC of U0 : label is 1;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE : integer;
  attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
  attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_RACH : integer;
  attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
  attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WACH : integer;
  attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
  attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
  attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
  attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_FULL_FLAGS_RST_VAL : integer;
  attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
  attribute C_HAS_ALMOST_EMPTY : integer;
  attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
  attribute C_HAS_ALMOST_FULL : integer;
  attribute C_HAS_ALMOST_FULL of U0 : label is 0;
  attribute C_HAS_AXIS_TDATA : integer;
  attribute C_HAS_AXIS_TDATA of U0 : label is 1;
  attribute C_HAS_AXIS_TDEST : integer;
  attribute C_HAS_AXIS_TDEST of U0 : label is 0;
  attribute C_HAS_AXIS_TID : integer;
  attribute C_HAS_AXIS_TID of U0 : label is 0;
  attribute C_HAS_AXIS_TKEEP : integer;
  attribute C_HAS_AXIS_TKEEP of U0 : label is 1;
  attribute C_HAS_AXIS_TLAST : integer;
  attribute C_HAS_AXIS_TLAST of U0 : label is 1;
  attribute C_HAS_AXIS_TREADY : integer;
  attribute C_HAS_AXIS_TREADY of U0 : label is 1;
  attribute C_HAS_AXIS_TSTRB : integer;
  attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
  attribute C_HAS_AXIS_TUSER : integer;
  attribute C_HAS_AXIS_TUSER of U0 : label is 1;
  attribute C_HAS_AXI_ARUSER : integer;
  attribute C_HAS_AXI_ARUSER of U0 : label is 0;
  attribute C_HAS_AXI_AWUSER : integer;
  attribute C_HAS_AXI_AWUSER of U0 : label is 0;
  attribute C_HAS_AXI_BUSER : integer;
  attribute C_HAS_AXI_BUSER of U0 : label is 0;
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_AXI_RD_CHANNEL : integer;
  attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
  attribute C_HAS_AXI_RUSER : integer;
  attribute C_HAS_AXI_RUSER of U0 : label is 0;
  attribute C_HAS_AXI_WR_CHANNEL : integer;
  attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
  attribute C_HAS_AXI_WUSER : integer;
  attribute C_HAS_AXI_WUSER of U0 : label is 0;
  attribute C_HAS_BACKUP : integer;
  attribute C_HAS_BACKUP of U0 : label is 0;
  attribute C_HAS_DATA_COUNT : integer;
  attribute C_HAS_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_AXIS : integer;
  attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_RACH : integer;
  attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_RDCH : integer;
  attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WACH : integer;
  attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WDCH : integer;
  attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
  attribute C_HAS_DATA_COUNTS_WRCH : integer;
  attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
  attribute C_HAS_INT_CLK : integer;
  attribute C_HAS_INT_CLK of U0 : label is 0;
  attribute C_HAS_MASTER_CE : integer;
  attribute C_HAS_MASTER_CE of U0 : label is 0;
  attribute C_HAS_MEMINIT_FILE : integer;
  attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
  attribute C_HAS_OVERFLOW : integer;
  attribute C_HAS_OVERFLOW of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_AXIS : integer;
  attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_RACH : integer;
  attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_RDCH : integer;
  attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WACH : integer;
  attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WDCH : integer;
  attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
  attribute C_HAS_PROG_FLAGS_WRCH : integer;
  attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
  attribute C_HAS_RD_DATA_COUNT : integer;
  attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_RD_RST : integer;
  attribute C_HAS_RD_RST of U0 : label is 0;
  attribute C_HAS_RST : integer;
  attribute C_HAS_RST of U0 : label is 1;
  attribute C_HAS_SLAVE_CE : integer;
  attribute C_HAS_SLAVE_CE of U0 : label is 0;
  attribute C_HAS_SRST : integer;
  attribute C_HAS_SRST of U0 : label is 0;
  attribute C_HAS_UNDERFLOW : integer;
  attribute C_HAS_UNDERFLOW of U0 : label is 0;
  attribute C_HAS_VALID : integer;
  attribute C_HAS_VALID of U0 : label is 0;
  attribute C_HAS_WR_ACK : integer;
  attribute C_HAS_WR_ACK of U0 : label is 0;
  attribute C_HAS_WR_DATA_COUNT : integer;
  attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
  attribute C_HAS_WR_RST : integer;
  attribute C_HAS_WR_RST of U0 : label is 0;
  attribute C_IMPLEMENTATION_TYPE : integer;
  attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
  attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
  attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
  attribute C_IMPLEMENTATION_TYPE_RACH : integer;
  attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 2;
  attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
  attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
  attribute C_IMPLEMENTATION_TYPE_WACH : integer;
  attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 2;
  attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
  attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
  attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
  attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 2;
  attribute C_INIT_WR_PNTR_VAL : integer;
  attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 1;
  attribute C_MEMORY_TYPE : integer;
  attribute C_MEMORY_TYPE of U0 : label is 1;
  attribute C_MIF_FILE_NAME : string;
  attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
  attribute C_MSGON_VAL : integer;
  attribute C_MSGON_VAL of U0 : label is 1;
  attribute C_OPTIMIZATION_MODE : integer;
  attribute C_OPTIMIZATION_MODE of U0 : label is 0;
  attribute C_OVERFLOW_LOW : integer;
  attribute C_OVERFLOW_LOW of U0 : label is 0;
  attribute C_POWER_SAVING_MODE : integer;
  attribute C_POWER_SAVING_MODE of U0 : label is 0;
  attribute C_PRELOAD_LATENCY : integer;
  attribute C_PRELOAD_LATENCY of U0 : label is 1;
  attribute C_PRELOAD_REGS : integer;
  attribute C_PRELOAD_REGS of U0 : label is 0;
  attribute C_PRIM_FIFO_TYPE : string;
  attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx4";
  attribute C_PRIM_FIFO_TYPE_AXIS : string;
  attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "512x72";
  attribute C_PRIM_FIFO_TYPE_RACH : string;
  attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
  attribute C_PRIM_FIFO_TYPE_RDCH : string;
  attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
  attribute C_PRIM_FIFO_TYPE_WACH : string;
  attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
  attribute C_PRIM_FIFO_TYPE_WDCH : string;
  attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
  attribute C_PRIM_FIFO_TYPE_WRCH : string;
  attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 62;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
  attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 14;
  attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
  attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
  attribute C_PROG_EMPTY_TYPE : integer;
  attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_AXIS : integer;
  attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_RACH : integer;
  attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_RDCH : integer;
  attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WACH : integer;
  attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WDCH : integer;
  attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
  attribute C_PROG_EMPTY_TYPE_WRCH : integer;
  attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 45;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
  attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 15;
  attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
  attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
  attribute C_PROG_FULL_TYPE : integer;
  attribute C_PROG_FULL_TYPE of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_AXIS : integer;
  attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 1;
  attribute C_PROG_FULL_TYPE_RACH : integer;
  attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_RDCH : integer;
  attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WACH : integer;
  attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WDCH : integer;
  attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
  attribute C_PROG_FULL_TYPE_WRCH : integer;
  attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
  attribute C_RACH_TYPE : integer;
  attribute C_RACH_TYPE of U0 : label is 0;
  attribute C_RDCH_TYPE : integer;
  attribute C_RDCH_TYPE of U0 : label is 0;
  attribute C_RD_DATA_COUNT_WIDTH : integer;
  attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_RD_DEPTH : integer;
  attribute C_RD_DEPTH of U0 : label is 1024;
  attribute C_RD_FREQ : integer;
  attribute C_RD_FREQ of U0 : label is 1;
  attribute C_RD_PNTR_WIDTH : integer;
  attribute C_RD_PNTR_WIDTH of U0 : label is 10;
  attribute C_REG_SLICE_MODE_AXIS : integer;
  attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
  attribute C_REG_SLICE_MODE_RACH : integer;
  attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_RDCH : integer;
  attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WACH : integer;
  attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WDCH : integer;
  attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
  attribute C_REG_SLICE_MODE_WRCH : integer;
  attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
  attribute C_SELECT_XPM : integer;
  attribute C_SELECT_XPM of U0 : label is 0;
  attribute C_SYNCHRONIZER_STAGE : integer;
  attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
  attribute C_UNDERFLOW_LOW : integer;
  attribute C_UNDERFLOW_LOW of U0 : label is 0;
  attribute C_USE_COMMON_OVERFLOW : integer;
  attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
  attribute C_USE_COMMON_UNDERFLOW : integer;
  attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
  attribute C_USE_DEFAULT_SETTINGS : integer;
  attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
  attribute C_USE_DOUT_RST : integer;
  attribute C_USE_DOUT_RST of U0 : label is 1;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_ECC_AXIS : integer;
  attribute C_USE_ECC_AXIS of U0 : label is 0;
  attribute C_USE_ECC_RACH : integer;
  attribute C_USE_ECC_RACH of U0 : label is 0;
  attribute C_USE_ECC_RDCH : integer;
  attribute C_USE_ECC_RDCH of U0 : label is 0;
  attribute C_USE_ECC_WACH : integer;
  attribute C_USE_ECC_WACH of U0 : label is 0;
  attribute C_USE_ECC_WDCH : integer;
  attribute C_USE_ECC_WDCH of U0 : label is 0;
  attribute C_USE_ECC_WRCH : integer;
  attribute C_USE_ECC_WRCH of U0 : label is 0;
  attribute C_USE_EMBEDDED_REG : integer;
  attribute C_USE_EMBEDDED_REG of U0 : label is 0;
  attribute C_USE_FIFO16_FLAGS : integer;
  attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
  attribute C_USE_FWFT_DATA_COUNT : integer;
  attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
  attribute C_USE_PIPELINE_REG : integer;
  attribute C_USE_PIPELINE_REG of U0 : label is 0;
  attribute C_VALID_LOW : integer;
  attribute C_VALID_LOW of U0 : label is 0;
  attribute C_WACH_TYPE : integer;
  attribute C_WACH_TYPE of U0 : label is 0;
  attribute C_WDCH_TYPE : integer;
  attribute C_WDCH_TYPE of U0 : label is 0;
  attribute C_WRCH_TYPE : integer;
  attribute C_WRCH_TYPE of U0 : label is 0;
  attribute C_WR_ACK_LOW : integer;
  attribute C_WR_ACK_LOW of U0 : label is 0;
  attribute C_WR_DATA_COUNT_WIDTH : integer;
  attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
  attribute C_WR_DEPTH : integer;
  attribute C_WR_DEPTH of U0 : label is 1024;
  attribute C_WR_DEPTH_AXIS : integer;
  attribute C_WR_DEPTH_AXIS of U0 : label is 64;
  attribute C_WR_DEPTH_RACH : integer;
  attribute C_WR_DEPTH_RACH of U0 : label is 16;
  attribute C_WR_DEPTH_RDCH : integer;
  attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
  attribute C_WR_DEPTH_WACH : integer;
  attribute C_WR_DEPTH_WACH of U0 : label is 16;
  attribute C_WR_DEPTH_WDCH : integer;
  attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
  attribute C_WR_DEPTH_WRCH : integer;
  attribute C_WR_DEPTH_WRCH of U0 : label is 16;
  attribute C_WR_FREQ : integer;
  attribute C_WR_FREQ of U0 : label is 1;
  attribute C_WR_PNTR_WIDTH : integer;
  attribute C_WR_PNTR_WIDTH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_AXIS : integer;
  attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 6;
  attribute C_WR_PNTR_WIDTH_RACH : integer;
  attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
  attribute C_WR_PNTR_WIDTH_RDCH : integer;
  attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_WACH : integer;
  attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
  attribute C_WR_PNTR_WIDTH_WDCH : integer;
  attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
  attribute C_WR_PNTR_WIDTH_WRCH : integer;
  attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
  attribute C_WR_RESPONSE_LATENCY : integer;
  attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of m_axis_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
  attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
  attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of m_axis_tvalid : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_aclk : signal is "xilinx.com:signal:clock:1.0 slave_aclk CLK";
  attribute X_INTERFACE_PARAMETER of s_aclk : signal is "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_aresetn : signal is "xilinx.com:signal:reset:1.0 slave_aresetn RST";
  attribute X_INTERFACE_PARAMETER of s_aresetn : signal is "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of s_axis_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
  attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
  attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
  attribute X_INTERFACE_PARAMETER of s_axis_tvalid : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
  attribute X_INTERFACE_INFO of m_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
  attribute X_INTERFACE_INFO of m_axis_tuser : signal is "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
  attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
  attribute X_INTERFACE_INFO of s_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
  attribute X_INTERFACE_INFO of s_axis_tuser : signal is "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
begin
  axis_prog_full <= \<const0>\;
  m_axis_tkeep(7) <= \<const0>\;
  m_axis_tkeep(6) <= \<const0>\;
  m_axis_tkeep(5) <= \<const0>\;
  m_axis_tkeep(4) <= \<const0>\;
  m_axis_tkeep(3) <= \<const0>\;
  m_axis_tkeep(2) <= \<const0>\;
  m_axis_tkeep(1) <= \<const0>\;
  m_axis_tkeep(0) <= \<const0>\;
  m_axis_tuser(21) <= \<const0>\;
  m_axis_tuser(20) <= \<const0>\;
  m_axis_tuser(19) <= \<const0>\;
  m_axis_tuser(18) <= \<const0>\;
  m_axis_tuser(17) <= \<const0>\;
  m_axis_tuser(16) <= \<const0>\;
  m_axis_tuser(15) <= \<const0>\;
  m_axis_tuser(14) <= \<const0>\;
  m_axis_tuser(13) <= \<const0>\;
  m_axis_tuser(12) <= \<const0>\;
  m_axis_tuser(11) <= \<const0>\;
  m_axis_tuser(10) <= \<const0>\;
  m_axis_tuser(9) <= \<const0>\;
  m_axis_tuser(8) <= \<const0>\;
  m_axis_tuser(7) <= \<const0>\;
  m_axis_tuser(6) <= \<const0>\;
  m_axis_tuser(5) <= \<const0>\;
  m_axis_tuser(4) <= \<const0>\;
  m_axis_tuser(3) <= \<const0>\;
  m_axis_tuser(2) <= \<const0>\;
  m_axis_tuser(1) <= \<const0>\;
  m_axis_tuser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.xdma_0_fifo_generator_v13_1_4
     port map (
      almost_empty => NLW_U0_almost_empty_UNCONNECTED,
      almost_full => NLW_U0_almost_full_UNCONNECTED,
      axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
      axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
      axi_ar_injectdbiterr => '0',
      axi_ar_injectsbiterr => '0',
      axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
      axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
      axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
      axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
      axi_ar_prog_full_thresh(3 downto 0) => B"0000",
      axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
      axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
      axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
      axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
      axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
      axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
      axi_aw_injectdbiterr => '0',
      axi_aw_injectsbiterr => '0',
      axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
      axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
      axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
      axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
      axi_aw_prog_full_thresh(3 downto 0) => B"0000",
      axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
      axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
      axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
      axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
      axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
      axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
      axi_b_injectdbiterr => '0',
      axi_b_injectsbiterr => '0',
      axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
      axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
      axi_b_prog_empty_thresh(3 downto 0) => B"0000",
      axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
      axi_b_prog_full_thresh(3 downto 0) => B"0000",
      axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
      axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
      axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
      axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
      axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
      axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
      axi_r_injectdbiterr => '0',
      axi_r_injectsbiterr => '0',
      axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
      axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
      axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
      axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
      axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
      axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
      axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
      axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
      axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
      axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
      axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
      axi_w_injectdbiterr => '0',
      axi_w_injectsbiterr => '0',
      axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
      axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
      axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
      axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
      axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
      axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
      axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
      axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
      axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
      axis_data_count(6 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(6 downto 0),
      axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
      axis_injectdbiterr => '0',
      axis_injectsbiterr => '0',
      axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
      axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
      axis_prog_empty_thresh(5 downto 0) => B"000000",
      axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
      axis_prog_full_thresh(5 downto 0) => B"000000",
      axis_rd_data_count(6 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(6 downto 0),
      axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
      axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
      axis_wr_data_count(6 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(6 downto 0),
      backup => '0',
      backup_marker => '0',
      clk => '0',
      data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      din(17 downto 0) => B"000000000000000000",
      dout(17 downto 0) => NLW_U0_dout_UNCONNECTED(17 downto 0),
      empty => NLW_U0_empty_UNCONNECTED,
      full => NLW_U0_full_UNCONNECTED,
      injectdbiterr => '0',
      injectsbiterr => '0',
      int_clk => '0',
      m_aclk => '0',
      m_aclk_en => '0',
      m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
      m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
      m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
      m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
      m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
      m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
      m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
      m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
      m_axi_arready => '0',
      m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
      m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
      m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
      m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
      m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
      m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
      m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
      m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
      m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
      m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
      m_axi_awready => '0',
      m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
      m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
      m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
      m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
      m_axi_bid(0) => '0',
      m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
      m_axi_bresp(1 downto 0) => B"00",
      m_axi_buser(0) => '0',
      m_axi_bvalid => '0',
      m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      m_axi_rid(0) => '0',
      m_axi_rlast => '0',
      m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
      m_axi_rresp(1 downto 0) => B"00",
      m_axi_ruser(0) => '0',
      m_axi_rvalid => '0',
      m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
      m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
      m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
      m_axi_wready => '0',
      m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
      m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
      m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
      m_axis_tdata(63 downto 0) => m_axis_tdata(63 downto 0),
      m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
      m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
      m_axis_tkeep(7 downto 0) => NLW_U0_m_axis_tkeep_UNCONNECTED(7 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tready => m_axis_tready,
      m_axis_tstrb(7 downto 0) => NLW_U0_m_axis_tstrb_UNCONNECTED(7 downto 0),
      m_axis_tuser(21 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(21 downto 0),
      m_axis_tvalid => m_axis_tvalid,
      overflow => NLW_U0_overflow_UNCONNECTED,
      prog_empty => NLW_U0_prog_empty_UNCONNECTED,
      prog_empty_thresh(9 downto 0) => B"0000000000",
      prog_empty_thresh_assert(9 downto 0) => B"0000000000",
      prog_empty_thresh_negate(9 downto 0) => B"0000000000",
      prog_full => NLW_U0_prog_full_UNCONNECTED,
      prog_full_thresh(9 downto 0) => B"0000000000",
      prog_full_thresh_assert(9 downto 0) => B"0000000000",
      prog_full_thresh_negate(9 downto 0) => B"0000000000",
      rd_clk => '0',
      rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
      rd_en => '0',
      rd_rst => '0',
      rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
      rst => '0',
      s_aclk => s_aclk,
      s_aclk_en => '0',
      s_aresetn => s_aresetn,
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arcache(3 downto 0) => B"0000",
      s_axi_arid(0) => '0',
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arlock(0) => '0',
      s_axi_arprot(2 downto 0) => B"000",
      s_axi_arqos(3 downto 0) => B"0000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arregion(3 downto 0) => B"0000",
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_aruser(0) => '0',
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(0) => '0',
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awregion(3 downto 0) => B"0000",
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(0) => '0',
      s_axi_awvalid => '0',
      s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wid(0) => '0',
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wuser(0) => '0',
      s_axi_wvalid => '0',
      s_axis_tdata(63 downto 0) => s_axis_tdata(63 downto 0),
      s_axis_tdest(0) => '0',
      s_axis_tid(0) => '0',
      s_axis_tkeep(7 downto 4) => s_axis_tkeep(7 downto 4),
      s_axis_tkeep(3 downto 0) => B"1111",
      s_axis_tlast => s_axis_tlast,
      s_axis_tready => s_axis_tready,
      s_axis_tstrb(7 downto 0) => B"00000000",
      s_axis_tuser(21) => s_axis_tuser(21),
      s_axis_tuser(20) => '0',
      s_axis_tuser(19 downto 17) => s_axis_tuser(19 downto 17),
      s_axis_tuser(16 downto 15) => B"00",
      s_axis_tuser(14) => s_axis_tuser(14),
      s_axis_tuser(13 downto 9) => B"00000",
      s_axis_tuser(8 downto 0) => s_axis_tuser(8 downto 0),
      s_axis_tvalid => s_axis_tvalid,
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      sleep => '0',
      srst => '0',
      underflow => NLW_U0_underflow_UNCONNECTED,
      valid => NLW_U0_valid_UNCONNECTED,
      wr_ack => NLW_U0_wr_ack_UNCONNECTED,
      wr_clk => '0',
      wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
      wr_en => '0',
      wr_rst => '0',
      wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_rx_demux is
  port (
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    empty_fwft_i_reg : out STD_LOGIC;
    \goreg_dm.dout_i_reg[94]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_tlast : out STD_LOGIC;
    m_axis_rx_tready : out STD_LOGIC;
    in_packet_q_reg : out STD_LOGIC_VECTOR ( 15 downto 0 );
    in_packet_q_reg_0 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    in_packet_q_reg_1 : out STD_LOGIC_VECTOR ( 9 downto 0 );
    in_packet_q_reg_2 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    in_packet_q_reg_3 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    in_packet_q_reg_4 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    user_reset_out_reg : out STD_LOGIC;
    \goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \goreg_dm.dout_i_reg[59]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    req_VDM : out STD_LOGIC;
    req_OBFF : out STD_LOGIC;
    req_LTR : out STD_LOGIC;
    \goreg_dm.dout_i_reg[59]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    req_ATS : out STD_LOGIC;
    \sop__0\ : out STD_LOGIC;
    user_clk_out : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_tready : in STD_LOGIC;
    m_axis_rx_tkeep_o : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axis_rx_tlast : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_rc\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    in_packet_q : in STD_LOGIC;
    \tx_64.req_bar_id_reg[0]\ : in STD_LOGIC;
    in_packet_q_0 : in STD_LOGIC;
    state : in STD_LOGIC_VECTOR ( 0 to 0 );
    req_mesg : in STD_LOGIC;
    m_axis_rx_tuser_o : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_rx_demux : entity is "xdma_0_rx_demux";
end xdma_0_xdma_0_rx_demux;

architecture STRUCTURE of xdma_0_xdma_0_rx_demux is
  signal active_intfc : STD_LOGIC;
  signal \active_intfc1__0\ : STD_LOGIC;
  signal active_intfc_i_1_n_0 : STD_LOGIC;
  signal cplfifo_s_axis_tdata : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[0]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[10]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[11]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[12]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[13]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[14]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[15]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[16]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[17]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[18]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[19]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[1]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[20]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[21]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[22]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[23]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[24]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[25]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[26]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[27]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[28]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[29]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[2]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[30]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[32]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[33]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[34]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[35]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[36]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[37]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[38]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[39]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[3]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[40]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[41]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[42]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[43]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[44]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[45]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[46]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[47]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[48]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[49]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[4]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[50]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[51]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[52]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[53]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[54]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[55]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[56]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[57]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[58]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[59]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[5]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[60]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[61]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[62]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[63]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[6]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[7]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[8]\ : STD_LOGIC;
  signal \cplfifo_s_axis_tdata_reg_n_0_[9]\ : STD_LOGIC;
  signal cplfifo_s_axis_tkeep : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal cplfifo_s_axis_tlast_reg_n_0 : STD_LOGIC;
  signal cplfifo_s_axis_tready : STD_LOGIC;
  signal cplfifo_s_axis_tuser : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal cplfifo_s_axis_tvalid_i_1_n_0 : STD_LOGIC;
  signal cplfifo_s_axis_tvalid_i_2_n_0 : STD_LOGIC;
  signal cplfifo_s_axis_tvalid_i_3_n_0 : STD_LOGIC;
  signal cplfifo_s_axis_tvalid_reg_n_0 : STD_LOGIC;
  signal \^empty_fwft_i_reg\ : STD_LOGIC;
  signal \^goreg_dm.dout_i_reg[94]\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal in_pkt : STD_LOGIC;
  signal in_pkt_i_1_n_0 : STD_LOGIC;
  signal m_axis_rx_cpl_tlast : STD_LOGIC;
  signal m_axis_rx_cpl_tready : STD_LOGIC;
  signal m_axis_rx_tgt_tuser : STD_LOGIC_VECTOR ( 6 downto 2 );
  signal \^m_axis_tdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \^m_axis_tvalid\ : STD_LOGIC;
  signal tgtfifo_s_axis_tdata : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[0]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[10]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[11]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[12]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[13]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[14]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[15]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[16]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[17]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[18]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[19]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[1]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[20]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[21]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[22]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[23]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[24]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[25]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[26]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[27]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[28]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[29]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[2]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[30]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[31]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[32]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[33]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[34]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[35]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[36]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[37]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[38]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[39]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[3]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[40]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[41]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[42]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[43]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[44]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[45]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[46]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[47]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[48]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[49]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[4]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[50]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[51]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[52]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[53]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[54]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[55]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[56]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[57]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[58]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[59]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[5]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[60]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[61]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[62]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[63]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[6]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[7]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[8]\ : STD_LOGIC;
  signal \tgtfifo_s_axis_tdata_reg_n_0_[9]\ : STD_LOGIC;
  signal tgtfifo_s_axis_tkeep : STD_LOGIC_VECTOR ( 7 to 7 );
  signal tgtfifo_s_axis_tlast_reg_n_0 : STD_LOGIC;
  signal tgtfifo_s_axis_tready : STD_LOGIC;
  signal tgtfifo_s_axis_tuser : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal tgtfifo_s_axis_tvalid_i_1_n_0 : STD_LOGIC;
  signal tgtfifo_s_axis_tvalid_i_2_n_0 : STD_LOGIC;
  signal tgtfifo_s_axis_tvalid_i_3_n_0 : STD_LOGIC;
  signal tgtfifo_s_axis_tvalid_reg_n_0 : STD_LOGIC;
  signal \tx_64.req_ATS_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.req_OBFF_i_2_n_0\ : STD_LOGIC;
  signal \tx_64.req_VDM_i_2_n_0\ : STD_LOGIC;
  signal NLW_dma_cpl_fifo_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_dma_cpl_fifo_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_dma_cpl_fifo_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal NLW_tgt_brdg_fifo_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
  signal NLW_tgt_brdg_fifo_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_64.state[0]_i_2__0\ : label is "soft_lutpair2046";
  attribute SOFT_HLUTNM of active_intfc_i_2 : label is "soft_lutpair2039";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of dma_cpl_fifo_inst : label is "pcie2_fifo_generator_dma_cpl,fifo_generator_v13_1_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of dma_cpl_fifo_inst : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of dma_cpl_fifo_inst : label is "fifo_generator_v13_1_4,Vivado 2020.2";
  attribute SOFT_HLUTNM of dma_cpl_fifo_inst_i_2 : label is "soft_lutpair2041";
  attribute SOFT_HLUTNM of \in_packet_q_i_1__1\ : label is "soft_lutpair2041";
  attribute SOFT_HLUTNM of pcie2_ip_i_i_1 : label is "soft_lutpair2039";
  attribute SOFT_HLUTNM of \rc_64.wr_attr[0]_i_1\ : label is "soft_lutpair2066";
  attribute SOFT_HLUTNM of \rc_64.wr_attr[1]_i_1\ : label is "soft_lutpair2066";
  attribute SOFT_HLUTNM of \rc_64.wr_attr[2]_i_1\ : label is "soft_lutpair2067";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[0]_i_1\ : label is "soft_lutpair2055";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[10]_i_1\ : label is "soft_lutpair2060";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[11]_i_1\ : label is "soft_lutpair2060";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[1]_i_1\ : label is "soft_lutpair2055";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[2]_i_1\ : label is "soft_lutpair2056";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[3]_i_1\ : label is "soft_lutpair2056";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[4]_i_1\ : label is "soft_lutpair2057";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[5]_i_1\ : label is "soft_lutpair2057";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[6]_i_1\ : label is "soft_lutpair2058";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[7]_i_1\ : label is "soft_lutpair2058";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[8]_i_1\ : label is "soft_lutpair2059";
  attribute SOFT_HLUTNM of \rc_64.wr_byte[9]_i_1\ : label is "soft_lutpair2059";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[0]_i_1\ : label is "soft_lutpair2047";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[10]_i_1\ : label is "soft_lutpair2052";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[11]_i_1\ : label is "soft_lutpair2052";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[12]_i_1\ : label is "soft_lutpair2053";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[13]_i_1\ : label is "soft_lutpair2053";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[14]_i_1\ : label is "soft_lutpair2054";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[15]_i_1\ : label is "soft_lutpair2054";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[1]_i_1\ : label is "soft_lutpair2047";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[2]_i_1\ : label is "soft_lutpair2048";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[3]_i_1\ : label is "soft_lutpair2048";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[4]_i_1\ : label is "soft_lutpair2049";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[5]_i_1\ : label is "soft_lutpair2049";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[6]_i_1\ : label is "soft_lutpair2050";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[7]_i_1\ : label is "soft_lutpair2050";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[8]_i_1\ : label is "soft_lutpair2051";
  attribute SOFT_HLUTNM of \rc_64.wr_cid[9]_i_1\ : label is "soft_lutpair2051";
  attribute SOFT_HLUTNM of \rc_64.wr_compl_status[0]_i_1\ : label is "soft_lutpair2069";
  attribute SOFT_HLUTNM of \rc_64.wr_compl_status[1]_i_1\ : label is "soft_lutpair2069";
  attribute SOFT_HLUTNM of \rc_64.wr_len[0]_i_1\ : label is "soft_lutpair2061";
  attribute SOFT_HLUTNM of \rc_64.wr_len[1]_i_1\ : label is "soft_lutpair2061";
  attribute SOFT_HLUTNM of \rc_64.wr_len[2]_i_1\ : label is "soft_lutpair2062";
  attribute SOFT_HLUTNM of \rc_64.wr_len[3]_i_1\ : label is "soft_lutpair2062";
  attribute SOFT_HLUTNM of \rc_64.wr_len[4]_i_1\ : label is "soft_lutpair2063";
  attribute SOFT_HLUTNM of \rc_64.wr_len[5]_i_1\ : label is "soft_lutpair2063";
  attribute SOFT_HLUTNM of \rc_64.wr_len[6]_i_1\ : label is "soft_lutpair2064";
  attribute SOFT_HLUTNM of \rc_64.wr_len[7]_i_1\ : label is "soft_lutpair2064";
  attribute SOFT_HLUTNM of \rc_64.wr_len[8]_i_1\ : label is "soft_lutpair2065";
  attribute SOFT_HLUTNM of \rc_64.wr_len[9]_i_2\ : label is "soft_lutpair2065";
  attribute SOFT_HLUTNM of \rc_64.wr_tc[0]_i_1\ : label is "soft_lutpair2067";
  attribute SOFT_HLUTNM of \rc_64.wr_tc[1]_i_1\ : label is "soft_lutpair2068";
  attribute SOFT_HLUTNM of \rc_64.wr_tc[2]_i_1\ : label is "soft_lutpair2068";
  attribute CHECK_LICENSE_TYPE of tgt_brdg_fifo_inst : label is "pcie2_fifo_generator_tgt_brdg,fifo_generator_v13_1_4,{}";
  attribute DowngradeIPIdentifiedWarnings of tgt_brdg_fifo_inst : label is "yes";
  attribute x_core_info of tgt_brdg_fifo_inst : label is "fifo_generator_v13_1_4,Vivado 2020.2";
  attribute SOFT_HLUTNM of \tx_64.req_bar_id[1]_i_1\ : label is "soft_lutpair2040";
  attribute SOFT_HLUTNM of \tx_64.req_bar_id[2]_i_1\ : label is "soft_lutpair2040";
  attribute SOFT_HLUTNM of \tx_64.req_fbe[0]_i_1\ : label is "soft_lutpair2042";
  attribute SOFT_HLUTNM of \tx_64.req_fbe[1]_i_1\ : label is "soft_lutpair2043";
  attribute SOFT_HLUTNM of \tx_64.req_fbe[2]_i_1\ : label is "soft_lutpair2044";
  attribute SOFT_HLUTNM of \tx_64.req_fbe[3]_i_1\ : label is "soft_lutpair2045";
  attribute SOFT_HLUTNM of \tx_64.req_msg_code[0]_i_1\ : label is "soft_lutpair2042";
  attribute SOFT_HLUTNM of \tx_64.req_msg_code[1]_i_1\ : label is "soft_lutpair2043";
  attribute SOFT_HLUTNM of \tx_64.req_msg_code[2]_i_1\ : label is "soft_lutpair2044";
  attribute SOFT_HLUTNM of \tx_64.req_msg_code[3]_i_1\ : label is "soft_lutpair2045";
  attribute SOFT_HLUTNM of \tx_64.req_msg_code[4]_i_1\ : label is "soft_lutpair2046";
begin
  empty_fwft_i_reg <= \^empty_fwft_i_reg\;
  \goreg_dm.dout_i_reg[94]\(63 downto 0) <= \^goreg_dm.dout_i_reg[94]\(63 downto 0);
  m_axis_tdata(63 downto 0) <= \^m_axis_tdata\(63 downto 0);
  m_axis_tvalid <= \^m_axis_tvalid\;
\FSM_sequential_tx_64.state[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^empty_fwft_i_reg\,
      I1 => in_packet_q_0,
      O => \sop__0\
    );
active_intfc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8A8A8A8ABA8A"
    )
        port map (
      I0 => active_intfc,
      I1 => in_pkt,
      I2 => \active_intfc1__0\,
      I3 => D(27),
      I4 => D(26),
      I5 => D(28),
      O => active_intfc_i_1_n_0
    );
active_intfc_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2A00000"
    )
        port map (
      I0 => tgtfifo_s_axis_tready,
      I1 => active_intfc,
      I2 => cplfifo_s_axis_tready,
      I3 => in_pkt,
      I4 => m_axis_rx_tvalid,
      O => \active_intfc1__0\
    );
active_intfc_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => active_intfc_i_1_n_0,
      Q => active_intfc,
      R => SR(0)
    );
\cplfifo_s_axis_tdata[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => cplfifo_s_axis_tready,
      I1 => SR(0),
      O => cplfifo_s_axis_tdata
    );
\cplfifo_s_axis_tdata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(0),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[0]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(10),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[10]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(11),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[11]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(12),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[12]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(13),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[13]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(14),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[14]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(15),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[15]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(16),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[16]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(17),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[17]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(18),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[18]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(19),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[19]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(1),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[1]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(20),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[20]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(21),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[21]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(22),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[22]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(23),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[23]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(24),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[24]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(25),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[25]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(26),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[26]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(27),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[27]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(28),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[28]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(29),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[29]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(2),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[2]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(30),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[30]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(31),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[31]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(32),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[32]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(33),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[33]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(34),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[34]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(35),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[35]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(36),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[36]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(37),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[37]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(38),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[38]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(39),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[39]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(3),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[3]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(40),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[40]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(41),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[41]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(42),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[42]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(43),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[43]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(44),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[44]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(45),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[45]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(46),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[46]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(47),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[47]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(48),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[48]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(49),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[49]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(4),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[4]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(50),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[50]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(51),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[51]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(52),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[52]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(53),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[53]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(54),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[54]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(55),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[55]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(56),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[56]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(57),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[57]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(58),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[58]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(59),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[59]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(5),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[5]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(60),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[60]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(61),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[61]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(62),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[62]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(63),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[63]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(6),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[6]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(7),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[7]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(8),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[8]\,
      R => '0'
    );
\cplfifo_s_axis_tdata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => D(9),
      Q => \cplfifo_s_axis_tdata_reg_n_0_[9]\,
      R => '0'
    );
\cplfifo_s_axis_tkeep_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tkeep_o(0),
      Q => cplfifo_s_axis_tkeep(4),
      R => '0'
    );
\cplfifo_s_axis_tkeep_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tkeep_o(1),
      Q => cplfifo_s_axis_tkeep(5),
      R => '0'
    );
\cplfifo_s_axis_tkeep_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tkeep_o(2),
      Q => cplfifo_s_axis_tkeep(6),
      R => '0'
    );
\cplfifo_s_axis_tkeep_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tkeep_o(3),
      Q => cplfifo_s_axis_tkeep(7),
      R => '0'
    );
cplfifo_s_axis_tlast_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tlast,
      Q => cplfifo_s_axis_tlast_reg_n_0,
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(0),
      Q => cplfifo_s_axis_tuser(0),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(9),
      Q => cplfifo_s_axis_tuser(14),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(10),
      Q => cplfifo_s_axis_tuser(17),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(11),
      Q => cplfifo_s_axis_tuser(18),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(12),
      Q => cplfifo_s_axis_tuser(19),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(1),
      Q => cplfifo_s_axis_tuser(1),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(13),
      Q => cplfifo_s_axis_tuser(21),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(2),
      Q => cplfifo_s_axis_tuser(2),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(3),
      Q => cplfifo_s_axis_tuser(3),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(4),
      Q => cplfifo_s_axis_tuser(4),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(5),
      Q => cplfifo_s_axis_tuser(5),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(6),
      Q => cplfifo_s_axis_tuser(6),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(7),
      Q => cplfifo_s_axis_tuser(7),
      R => '0'
    );
\cplfifo_s_axis_tuser_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => cplfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(8),
      Q => cplfifo_s_axis_tuser(8),
      R => '0'
    );
cplfifo_s_axis_tvalid_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABBAABFAABBAAB0"
    )
        port map (
      I0 => cplfifo_s_axis_tvalid_i_2_n_0,
      I1 => cplfifo_s_axis_tvalid_i_3_n_0,
      I2 => cplfifo_s_axis_tready,
      I3 => SR(0),
      I4 => \active_intfc1__0\,
      I5 => cplfifo_s_axis_tvalid_reg_n_0,
      O => cplfifo_s_axis_tvalid_i_1_n_0
    );
cplfifo_s_axis_tvalid_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => SR(0),
      I1 => m_axis_rx_tvalid,
      I2 => in_pkt,
      I3 => cplfifo_s_axis_tready,
      I4 => active_intfc,
      O => cplfifo_s_axis_tvalid_i_2_n_0
    );
cplfifo_s_axis_tvalid_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
        port map (
      I0 => D(27),
      I1 => D(26),
      I2 => D(28),
      I3 => \active_intfc1__0\,
      I4 => in_pkt,
      O => cplfifo_s_axis_tvalid_i_3_n_0
    );
cplfifo_s_axis_tvalid_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => cplfifo_s_axis_tvalid_i_1_n_0,
      Q => cplfifo_s_axis_tvalid_reg_n_0,
      R => '0'
    );
dma_cpl_fifo_inst: entity work.xdma_0_pcie2_fifo_generator_dma_cpl
     port map (
      axis_prog_full => NLW_dma_cpl_fifo_inst_axis_prog_full_UNCONNECTED,
      m_axis_tdata(63 downto 0) => \^m_axis_tdata\(63 downto 0),
      m_axis_tkeep(7 downto 0) => NLW_dma_cpl_fifo_inst_m_axis_tkeep_UNCONNECTED(7 downto 0),
      m_axis_tlast => m_axis_rx_cpl_tlast,
      m_axis_tready => m_axis_rx_cpl_tready,
      m_axis_tuser(21 downto 0) => NLW_dma_cpl_fifo_inst_m_axis_tuser_UNCONNECTED(21 downto 0),
      m_axis_tvalid => \^m_axis_tvalid\,
      s_aclk => user_clk_out,
      s_aresetn => E(0),
      s_axis_tdata(63) => \cplfifo_s_axis_tdata_reg_n_0_[63]\,
      s_axis_tdata(62) => \cplfifo_s_axis_tdata_reg_n_0_[62]\,
      s_axis_tdata(61) => \cplfifo_s_axis_tdata_reg_n_0_[61]\,
      s_axis_tdata(60) => \cplfifo_s_axis_tdata_reg_n_0_[60]\,
      s_axis_tdata(59) => \cplfifo_s_axis_tdata_reg_n_0_[59]\,
      s_axis_tdata(58) => \cplfifo_s_axis_tdata_reg_n_0_[58]\,
      s_axis_tdata(57) => \cplfifo_s_axis_tdata_reg_n_0_[57]\,
      s_axis_tdata(56) => \cplfifo_s_axis_tdata_reg_n_0_[56]\,
      s_axis_tdata(55) => \cplfifo_s_axis_tdata_reg_n_0_[55]\,
      s_axis_tdata(54) => \cplfifo_s_axis_tdata_reg_n_0_[54]\,
      s_axis_tdata(53) => \cplfifo_s_axis_tdata_reg_n_0_[53]\,
      s_axis_tdata(52) => \cplfifo_s_axis_tdata_reg_n_0_[52]\,
      s_axis_tdata(51) => \cplfifo_s_axis_tdata_reg_n_0_[51]\,
      s_axis_tdata(50) => \cplfifo_s_axis_tdata_reg_n_0_[50]\,
      s_axis_tdata(49) => \cplfifo_s_axis_tdata_reg_n_0_[49]\,
      s_axis_tdata(48) => \cplfifo_s_axis_tdata_reg_n_0_[48]\,
      s_axis_tdata(47) => \cplfifo_s_axis_tdata_reg_n_0_[47]\,
      s_axis_tdata(46) => \cplfifo_s_axis_tdata_reg_n_0_[46]\,
      s_axis_tdata(45) => \cplfifo_s_axis_tdata_reg_n_0_[45]\,
      s_axis_tdata(44) => \cplfifo_s_axis_tdata_reg_n_0_[44]\,
      s_axis_tdata(43) => \cplfifo_s_axis_tdata_reg_n_0_[43]\,
      s_axis_tdata(42) => \cplfifo_s_axis_tdata_reg_n_0_[42]\,
      s_axis_tdata(41) => \cplfifo_s_axis_tdata_reg_n_0_[41]\,
      s_axis_tdata(40) => \cplfifo_s_axis_tdata_reg_n_0_[40]\,
      s_axis_tdata(39) => \cplfifo_s_axis_tdata_reg_n_0_[39]\,
      s_axis_tdata(38) => \cplfifo_s_axis_tdata_reg_n_0_[38]\,
      s_axis_tdata(37) => \cplfifo_s_axis_tdata_reg_n_0_[37]\,
      s_axis_tdata(36) => \cplfifo_s_axis_tdata_reg_n_0_[36]\,
      s_axis_tdata(35) => \cplfifo_s_axis_tdata_reg_n_0_[35]\,
      s_axis_tdata(34) => \cplfifo_s_axis_tdata_reg_n_0_[34]\,
      s_axis_tdata(33) => \cplfifo_s_axis_tdata_reg_n_0_[33]\,
      s_axis_tdata(32) => \cplfifo_s_axis_tdata_reg_n_0_[32]\,
      s_axis_tdata(31) => \cplfifo_s_axis_tdata_reg_n_0_[31]\,
      s_axis_tdata(30) => \cplfifo_s_axis_tdata_reg_n_0_[30]\,
      s_axis_tdata(29) => \cplfifo_s_axis_tdata_reg_n_0_[29]\,
      s_axis_tdata(28) => \cplfifo_s_axis_tdata_reg_n_0_[28]\,
      s_axis_tdata(27) => \cplfifo_s_axis_tdata_reg_n_0_[27]\,
      s_axis_tdata(26) => \cplfifo_s_axis_tdata_reg_n_0_[26]\,
      s_axis_tdata(25) => \cplfifo_s_axis_tdata_reg_n_0_[25]\,
      s_axis_tdata(24) => \cplfifo_s_axis_tdata_reg_n_0_[24]\,
      s_axis_tdata(23) => \cplfifo_s_axis_tdata_reg_n_0_[23]\,
      s_axis_tdata(22) => \cplfifo_s_axis_tdata_reg_n_0_[22]\,
      s_axis_tdata(21) => \cplfifo_s_axis_tdata_reg_n_0_[21]\,
      s_axis_tdata(20) => \cplfifo_s_axis_tdata_reg_n_0_[20]\,
      s_axis_tdata(19) => \cplfifo_s_axis_tdata_reg_n_0_[19]\,
      s_axis_tdata(18) => \cplfifo_s_axis_tdata_reg_n_0_[18]\,
      s_axis_tdata(17) => \cplfifo_s_axis_tdata_reg_n_0_[17]\,
      s_axis_tdata(16) => \cplfifo_s_axis_tdata_reg_n_0_[16]\,
      s_axis_tdata(15) => \cplfifo_s_axis_tdata_reg_n_0_[15]\,
      s_axis_tdata(14) => \cplfifo_s_axis_tdata_reg_n_0_[14]\,
      s_axis_tdata(13) => \cplfifo_s_axis_tdata_reg_n_0_[13]\,
      s_axis_tdata(12) => \cplfifo_s_axis_tdata_reg_n_0_[12]\,
      s_axis_tdata(11) => \cplfifo_s_axis_tdata_reg_n_0_[11]\,
      s_axis_tdata(10) => \cplfifo_s_axis_tdata_reg_n_0_[10]\,
      s_axis_tdata(9) => \cplfifo_s_axis_tdata_reg_n_0_[9]\,
      s_axis_tdata(8) => \cplfifo_s_axis_tdata_reg_n_0_[8]\,
      s_axis_tdata(7) => \cplfifo_s_axis_tdata_reg_n_0_[7]\,
      s_axis_tdata(6) => \cplfifo_s_axis_tdata_reg_n_0_[6]\,
      s_axis_tdata(5) => \cplfifo_s_axis_tdata_reg_n_0_[5]\,
      s_axis_tdata(4) => \cplfifo_s_axis_tdata_reg_n_0_[4]\,
      s_axis_tdata(3) => \cplfifo_s_axis_tdata_reg_n_0_[3]\,
      s_axis_tdata(2) => \cplfifo_s_axis_tdata_reg_n_0_[2]\,
      s_axis_tdata(1) => \cplfifo_s_axis_tdata_reg_n_0_[1]\,
      s_axis_tdata(0) => \cplfifo_s_axis_tdata_reg_n_0_[0]\,
      s_axis_tkeep(7 downto 4) => cplfifo_s_axis_tkeep(7 downto 4),
      s_axis_tkeep(3 downto 0) => B"1111",
      s_axis_tlast => cplfifo_s_axis_tlast_reg_n_0,
      s_axis_tready => cplfifo_s_axis_tready,
      s_axis_tuser(21) => cplfifo_s_axis_tuser(21),
      s_axis_tuser(20) => '0',
      s_axis_tuser(19 downto 17) => cplfifo_s_axis_tuser(19 downto 17),
      s_axis_tuser(16 downto 15) => B"00",
      s_axis_tuser(14) => cplfifo_s_axis_tuser(14),
      s_axis_tuser(13 downto 9) => B"00000",
      s_axis_tuser(8 downto 0) => cplfifo_s_axis_tuser(8 downto 0),
      s_axis_tvalid => cplfifo_s_axis_tvalid_reg_n_0
    );
dma_cpl_fifo_inst_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \s_axis_rc\\.tready\(0),
      I1 => SR(0),
      O => m_axis_rx_cpl_tready
    );
\in_packet_q_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04544444"
    )
        port map (
      I0 => SR(0),
      I1 => in_packet_q,
      I2 => \s_axis_rc\\.tready\(0),
      I3 => m_axis_rx_cpl_tlast,
      I4 => \^m_axis_tvalid\,
      O => user_reset_out_reg
    );
in_pkt_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"57F74400FFFF0000"
    )
        port map (
      I0 => m_axis_rx_tlast,
      I1 => tgtfifo_s_axis_tready,
      I2 => active_intfc,
      I3 => cplfifo_s_axis_tready,
      I4 => in_pkt,
      I5 => m_axis_rx_tvalid,
      O => in_pkt_i_1_n_0
    );
in_pkt_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => in_pkt_i_1_n_0,
      Q => in_pkt,
      R => SR(0)
    );
pcie2_ip_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CE80"
    )
        port map (
      I0 => in_pkt,
      I1 => cplfifo_s_axis_tready,
      I2 => active_intfc,
      I3 => tgtfifo_s_axis_tready,
      O => m_axis_rx_tready
    );
\rc_64.wr_attr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(12),
      O => in_packet_q_reg_2(0)
    );
\rc_64.wr_attr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(13),
      O => in_packet_q_reg_2(1)
    );
\rc_64.wr_attr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(18),
      O => in_packet_q_reg_2(2)
    );
\rc_64.wr_byte[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(32),
      O => in_packet_q_reg_0(0)
    );
\rc_64.wr_byte[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(42),
      O => in_packet_q_reg_0(10)
    );
\rc_64.wr_byte[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(43),
      O => in_packet_q_reg_0(11)
    );
\rc_64.wr_byte[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(33),
      O => in_packet_q_reg_0(1)
    );
\rc_64.wr_byte[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(34),
      O => in_packet_q_reg_0(2)
    );
\rc_64.wr_byte[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(35),
      O => in_packet_q_reg_0(3)
    );
\rc_64.wr_byte[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(36),
      O => in_packet_q_reg_0(4)
    );
\rc_64.wr_byte[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(37),
      O => in_packet_q_reg_0(5)
    );
\rc_64.wr_byte[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(38),
      O => in_packet_q_reg_0(6)
    );
\rc_64.wr_byte[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(39),
      O => in_packet_q_reg_0(7)
    );
\rc_64.wr_byte[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(40),
      O => in_packet_q_reg_0(8)
    );
\rc_64.wr_byte[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(41),
      O => in_packet_q_reg_0(9)
    );
\rc_64.wr_cid[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(48),
      O => in_packet_q_reg(0)
    );
\rc_64.wr_cid[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(58),
      O => in_packet_q_reg(10)
    );
\rc_64.wr_cid[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(59),
      O => in_packet_q_reg(11)
    );
\rc_64.wr_cid[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(60),
      O => in_packet_q_reg(12)
    );
\rc_64.wr_cid[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(61),
      O => in_packet_q_reg(13)
    );
\rc_64.wr_cid[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(62),
      O => in_packet_q_reg(14)
    );
\rc_64.wr_cid[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(63),
      O => in_packet_q_reg(15)
    );
\rc_64.wr_cid[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(49),
      O => in_packet_q_reg(1)
    );
\rc_64.wr_cid[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(50),
      O => in_packet_q_reg(2)
    );
\rc_64.wr_cid[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(51),
      O => in_packet_q_reg(3)
    );
\rc_64.wr_cid[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(52),
      O => in_packet_q_reg(4)
    );
\rc_64.wr_cid[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(53),
      O => in_packet_q_reg(5)
    );
\rc_64.wr_cid[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(54),
      O => in_packet_q_reg(6)
    );
\rc_64.wr_cid[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(55),
      O => in_packet_q_reg(7)
    );
\rc_64.wr_cid[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(56),
      O => in_packet_q_reg(8)
    );
\rc_64.wr_cid[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(57),
      O => in_packet_q_reg(9)
    );
\rc_64.wr_compl_status[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(45),
      O => in_packet_q_reg_4(0)
    );
\rc_64.wr_compl_status[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(46),
      O => in_packet_q_reg_4(1)
    );
\rc_64.wr_compl_status[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(47),
      O => in_packet_q_reg_4(2)
    );
\rc_64.wr_len[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(0),
      O => in_packet_q_reg_1(0)
    );
\rc_64.wr_len[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(1),
      O => in_packet_q_reg_1(1)
    );
\rc_64.wr_len[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(2),
      O => in_packet_q_reg_1(2)
    );
\rc_64.wr_len[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(3),
      O => in_packet_q_reg_1(3)
    );
\rc_64.wr_len[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(4),
      O => in_packet_q_reg_1(4)
    );
\rc_64.wr_len[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(5),
      O => in_packet_q_reg_1(5)
    );
\rc_64.wr_len[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(6),
      O => in_packet_q_reg_1(6)
    );
\rc_64.wr_len[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(7),
      O => in_packet_q_reg_1(7)
    );
\rc_64.wr_len[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(8),
      O => in_packet_q_reg_1(8)
    );
\rc_64.wr_len[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(9),
      O => in_packet_q_reg_1(9)
    );
\rc_64.wr_tc[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(20),
      O => in_packet_q_reg_3(0)
    );
\rc_64.wr_tc[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(21),
      O => in_packet_q_reg_3(1)
    );
\rc_64.wr_tc[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => in_packet_q,
      I1 => \^m_axis_tvalid\,
      I2 => \^m_axis_tdata\(22),
      O => in_packet_q_reg_3(2)
    );
tgt_brdg_fifo_inst: entity work.xdma_0_pcie2_fifo_generator_tgt_brdg
     port map (
      axis_prog_full => NLW_tgt_brdg_fifo_inst_axis_prog_full_UNCONNECTED,
      m_axis_tdata(63 downto 0) => \^goreg_dm.dout_i_reg[94]\(63 downto 0),
      m_axis_tkeep(7 downto 0) => NLW_tgt_brdg_fifo_inst_m_axis_tkeep_UNCONNECTED(7 downto 0),
      m_axis_tlast => m_axis_tlast,
      m_axis_tready => m_axis_tready,
      m_axis_tuser(21 downto 7) => NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED(21 downto 7),
      m_axis_tuser(6 downto 2) => m_axis_rx_tgt_tuser(6 downto 2),
      m_axis_tuser(1 downto 0) => NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED(1 downto 0),
      m_axis_tvalid => \^empty_fwft_i_reg\,
      s_aclk => user_clk_out,
      s_aresetn => E(0),
      s_axis_tdata(63) => \tgtfifo_s_axis_tdata_reg_n_0_[63]\,
      s_axis_tdata(62) => \tgtfifo_s_axis_tdata_reg_n_0_[62]\,
      s_axis_tdata(61) => \tgtfifo_s_axis_tdata_reg_n_0_[61]\,
      s_axis_tdata(60) => \tgtfifo_s_axis_tdata_reg_n_0_[60]\,
      s_axis_tdata(59) => \tgtfifo_s_axis_tdata_reg_n_0_[59]\,
      s_axis_tdata(58) => \tgtfifo_s_axis_tdata_reg_n_0_[58]\,
      s_axis_tdata(57) => \tgtfifo_s_axis_tdata_reg_n_0_[57]\,
      s_axis_tdata(56) => \tgtfifo_s_axis_tdata_reg_n_0_[56]\,
      s_axis_tdata(55) => \tgtfifo_s_axis_tdata_reg_n_0_[55]\,
      s_axis_tdata(54) => \tgtfifo_s_axis_tdata_reg_n_0_[54]\,
      s_axis_tdata(53) => \tgtfifo_s_axis_tdata_reg_n_0_[53]\,
      s_axis_tdata(52) => \tgtfifo_s_axis_tdata_reg_n_0_[52]\,
      s_axis_tdata(51) => \tgtfifo_s_axis_tdata_reg_n_0_[51]\,
      s_axis_tdata(50) => \tgtfifo_s_axis_tdata_reg_n_0_[50]\,
      s_axis_tdata(49) => \tgtfifo_s_axis_tdata_reg_n_0_[49]\,
      s_axis_tdata(48) => \tgtfifo_s_axis_tdata_reg_n_0_[48]\,
      s_axis_tdata(47) => \tgtfifo_s_axis_tdata_reg_n_0_[47]\,
      s_axis_tdata(46) => \tgtfifo_s_axis_tdata_reg_n_0_[46]\,
      s_axis_tdata(45) => \tgtfifo_s_axis_tdata_reg_n_0_[45]\,
      s_axis_tdata(44) => \tgtfifo_s_axis_tdata_reg_n_0_[44]\,
      s_axis_tdata(43) => \tgtfifo_s_axis_tdata_reg_n_0_[43]\,
      s_axis_tdata(42) => \tgtfifo_s_axis_tdata_reg_n_0_[42]\,
      s_axis_tdata(41) => \tgtfifo_s_axis_tdata_reg_n_0_[41]\,
      s_axis_tdata(40) => \tgtfifo_s_axis_tdata_reg_n_0_[40]\,
      s_axis_tdata(39) => \tgtfifo_s_axis_tdata_reg_n_0_[39]\,
      s_axis_tdata(38) => \tgtfifo_s_axis_tdata_reg_n_0_[38]\,
      s_axis_tdata(37) => \tgtfifo_s_axis_tdata_reg_n_0_[37]\,
      s_axis_tdata(36) => \tgtfifo_s_axis_tdata_reg_n_0_[36]\,
      s_axis_tdata(35) => \tgtfifo_s_axis_tdata_reg_n_0_[35]\,
      s_axis_tdata(34) => \tgtfifo_s_axis_tdata_reg_n_0_[34]\,
      s_axis_tdata(33) => \tgtfifo_s_axis_tdata_reg_n_0_[33]\,
      s_axis_tdata(32) => \tgtfifo_s_axis_tdata_reg_n_0_[32]\,
      s_axis_tdata(31) => \tgtfifo_s_axis_tdata_reg_n_0_[31]\,
      s_axis_tdata(30) => \tgtfifo_s_axis_tdata_reg_n_0_[30]\,
      s_axis_tdata(29) => \tgtfifo_s_axis_tdata_reg_n_0_[29]\,
      s_axis_tdata(28) => \tgtfifo_s_axis_tdata_reg_n_0_[28]\,
      s_axis_tdata(27) => \tgtfifo_s_axis_tdata_reg_n_0_[27]\,
      s_axis_tdata(26) => \tgtfifo_s_axis_tdata_reg_n_0_[26]\,
      s_axis_tdata(25) => \tgtfifo_s_axis_tdata_reg_n_0_[25]\,
      s_axis_tdata(24) => \tgtfifo_s_axis_tdata_reg_n_0_[24]\,
      s_axis_tdata(23) => \tgtfifo_s_axis_tdata_reg_n_0_[23]\,
      s_axis_tdata(22) => \tgtfifo_s_axis_tdata_reg_n_0_[22]\,
      s_axis_tdata(21) => \tgtfifo_s_axis_tdata_reg_n_0_[21]\,
      s_axis_tdata(20) => \tgtfifo_s_axis_tdata_reg_n_0_[20]\,
      s_axis_tdata(19) => \tgtfifo_s_axis_tdata_reg_n_0_[19]\,
      s_axis_tdata(18) => \tgtfifo_s_axis_tdata_reg_n_0_[18]\,
      s_axis_tdata(17) => \tgtfifo_s_axis_tdata_reg_n_0_[17]\,
      s_axis_tdata(16) => \tgtfifo_s_axis_tdata_reg_n_0_[16]\,
      s_axis_tdata(15) => \tgtfifo_s_axis_tdata_reg_n_0_[15]\,
      s_axis_tdata(14) => \tgtfifo_s_axis_tdata_reg_n_0_[14]\,
      s_axis_tdata(13) => \tgtfifo_s_axis_tdata_reg_n_0_[13]\,
      s_axis_tdata(12) => \tgtfifo_s_axis_tdata_reg_n_0_[12]\,
      s_axis_tdata(11) => \tgtfifo_s_axis_tdata_reg_n_0_[11]\,
      s_axis_tdata(10) => \tgtfifo_s_axis_tdata_reg_n_0_[10]\,
      s_axis_tdata(9) => \tgtfifo_s_axis_tdata_reg_n_0_[9]\,
      s_axis_tdata(8) => \tgtfifo_s_axis_tdata_reg_n_0_[8]\,
      s_axis_tdata(7) => \tgtfifo_s_axis_tdata_reg_n_0_[7]\,
      s_axis_tdata(6) => \tgtfifo_s_axis_tdata_reg_n_0_[6]\,
      s_axis_tdata(5) => \tgtfifo_s_axis_tdata_reg_n_0_[5]\,
      s_axis_tdata(4) => \tgtfifo_s_axis_tdata_reg_n_0_[4]\,
      s_axis_tdata(3) => \tgtfifo_s_axis_tdata_reg_n_0_[3]\,
      s_axis_tdata(2) => \tgtfifo_s_axis_tdata_reg_n_0_[2]\,
      s_axis_tdata(1) => \tgtfifo_s_axis_tdata_reg_n_0_[1]\,
      s_axis_tdata(0) => \tgtfifo_s_axis_tdata_reg_n_0_[0]\,
      s_axis_tkeep(7) => tgtfifo_s_axis_tkeep(7),
      s_axis_tkeep(6 downto 0) => B"0000000",
      s_axis_tlast => tgtfifo_s_axis_tlast_reg_n_0,
      s_axis_tready => tgtfifo_s_axis_tready,
      s_axis_tuser(21 downto 9) => B"0000000000000",
      s_axis_tuser(8 downto 0) => tgtfifo_s_axis_tuser(8 downto 0),
      s_axis_tvalid => tgtfifo_s_axis_tvalid_reg_n_0
    );
\tgtfifo_s_axis_tdata[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => tgtfifo_s_axis_tready,
      I1 => SR(0),
      O => tgtfifo_s_axis_tdata
    );
\tgtfifo_s_axis_tdata_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(0),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[0]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(10),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[10]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(11),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[11]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(12),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[12]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(13),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[13]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(14),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[14]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(15),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[15]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(16),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[16]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(17),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[17]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(18),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[18]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(19),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[19]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(1),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[1]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(20),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[20]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(21),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[21]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(22),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[22]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(23),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[23]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(24),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[24]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(25),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[25]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(26),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[26]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(27),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[27]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(28),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[28]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(29),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[29]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(2),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[2]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(30),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[30]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(31),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[31]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(32),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[32]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(33),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[33]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(34),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[34]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(35),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[35]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(36),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[36]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(37),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[37]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(38),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[38]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(39),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[39]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(3),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[3]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(40),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[40]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(41),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[41]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(42),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[42]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(43),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[43]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(44),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[44]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(45),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[45]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(46),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[46]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(47),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[47]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(48),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[48]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(49),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[49]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(4),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[4]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(50),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[50]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(51),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[51]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(52),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[52]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(53),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[53]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(54),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[54]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(55),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[55]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(56),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[56]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(57),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[57]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(58),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[58]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(59),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[59]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(5),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[5]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(60),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[60]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(61),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[61]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(62),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[62]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(63),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[63]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(6),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[6]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(7),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[7]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(8),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[8]\,
      R => '0'
    );
\tgtfifo_s_axis_tdata_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => D(9),
      Q => \tgtfifo_s_axis_tdata_reg_n_0_[9]\,
      R => '0'
    );
\tgtfifo_s_axis_tkeep_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tkeep_o(3),
      Q => tgtfifo_s_axis_tkeep(7),
      R => '0'
    );
tgtfifo_s_axis_tlast_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tlast,
      Q => tgtfifo_s_axis_tlast_reg_n_0,
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(0),
      Q => tgtfifo_s_axis_tuser(0),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(1),
      Q => tgtfifo_s_axis_tuser(1),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(2),
      Q => tgtfifo_s_axis_tuser(2),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(3),
      Q => tgtfifo_s_axis_tuser(3),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(4),
      Q => tgtfifo_s_axis_tuser(4),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(5),
      Q => tgtfifo_s_axis_tuser(5),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(6),
      Q => tgtfifo_s_axis_tuser(6),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(7),
      Q => tgtfifo_s_axis_tuser(7),
      R => '0'
    );
\tgtfifo_s_axis_tuser_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => tgtfifo_s_axis_tdata,
      D => m_axis_rx_tuser_o(8),
      Q => tgtfifo_s_axis_tuser(8),
      R => '0'
    );
tgtfifo_s_axis_tvalid_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444044444444"
    )
        port map (
      I0 => SR(0),
      I1 => tgtfifo_s_axis_tvalid_i_2_n_0,
      I2 => tgtfifo_s_axis_tvalid_i_3_n_0,
      I3 => D(28),
      I4 => D(26),
      I5 => D(27),
      O => tgtfifo_s_axis_tvalid_i_1_n_0
    );
tgtfifo_s_axis_tvalid_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"20A87FFF20A80000"
    )
        port map (
      I0 => m_axis_rx_tvalid,
      I1 => in_pkt,
      I2 => cplfifo_s_axis_tready,
      I3 => active_intfc,
      I4 => tgtfifo_s_axis_tready,
      I5 => tgtfifo_s_axis_tvalid_reg_n_0,
      O => tgtfifo_s_axis_tvalid_i_2_n_0
    );
tgtfifo_s_axis_tvalid_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => m_axis_rx_tvalid,
      I1 => in_pkt,
      I2 => cplfifo_s_axis_tready,
      I3 => tgtfifo_s_axis_tready,
      O => tgtfifo_s_axis_tvalid_i_3_n_0
    );
tgtfifo_s_axis_tvalid_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk_out,
      CE => '1',
      D => tgtfifo_s_axis_tvalid_i_1_n_0,
      Q => tgtfifo_s_axis_tvalid_reg_n_0,
      R => '0'
    );
\tx_64.req_ATS_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1E00000000000000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(34),
      I1 => \^goreg_dm.dout_i_reg[94]\(32),
      I2 => \^goreg_dm.dout_i_reg[94]\(33),
      I3 => \tx_64.req_ATS_i_2_n_0\,
      I4 => \^goreg_dm.dout_i_reg[94]\(28),
      I5 => \tx_64.req_bar_id_reg[0]\,
      O => req_ATS
    );
\tx_64.req_ATS_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(35),
      I1 => \^goreg_dm.dout_i_reg[94]\(36),
      I2 => \^goreg_dm.dout_i_reg[94]\(37),
      I3 => \^goreg_dm.dout_i_reg[94]\(39),
      I4 => \^goreg_dm.dout_i_reg[94]\(38),
      O => \tx_64.req_ATS_i_2_n_0\
    );
\tx_64.req_LTR_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(37),
      I1 => \^goreg_dm.dout_i_reg[94]\(35),
      I2 => \^goreg_dm.dout_i_reg[94]\(33),
      I3 => \tx_64.req_OBFF_i_2_n_0\,
      I4 => \^goreg_dm.dout_i_reg[94]\(36),
      I5 => req_mesg,
      O => req_LTR
    );
\tx_64.req_OBFF_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(37),
      I1 => \^goreg_dm.dout_i_reg[94]\(35),
      I2 => \^goreg_dm.dout_i_reg[94]\(33),
      I3 => \tx_64.req_OBFF_i_2_n_0\,
      I4 => \^goreg_dm.dout_i_reg[94]\(36),
      I5 => req_mesg,
      O => req_OBFF
    );
\tx_64.req_OBFF_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(39),
      I1 => \^goreg_dm.dout_i_reg[94]\(38),
      I2 => \^goreg_dm.dout_i_reg[94]\(34),
      I3 => \^goreg_dm.dout_i_reg[94]\(32),
      O => \tx_64.req_OBFF_i_2_n_0\
    );
\tx_64.req_VDM_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080888000000000"
    )
        port map (
      I0 => \tx_64.req_VDM_i_2_n_0\,
      I1 => \^goreg_dm.dout_i_reg[94]\(36),
      I2 => state(0),
      I3 => \^empty_fwft_i_reg\,
      I4 => in_packet_q_0,
      I5 => \^goreg_dm.dout_i_reg[94]\(28),
      O => req_VDM
    );
\tx_64.req_VDM_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(35),
      I1 => \^goreg_dm.dout_i_reg[94]\(37),
      I2 => \^goreg_dm.dout_i_reg[94]\(33),
      I3 => \^goreg_dm.dout_i_reg[94]\(34),
      I4 => \^goreg_dm.dout_i_reg[94]\(39),
      I5 => \^goreg_dm.dout_i_reg[94]\(38),
      O => \tx_64.req_VDM_i_2_n_0\
    );
\tx_64.req_bar_id[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF0D0000"
    )
        port map (
      I0 => m_axis_rx_tgt_tuser(6),
      I1 => m_axis_rx_tgt_tuser(5),
      I2 => m_axis_rx_tgt_tuser(4),
      I3 => m_axis_rx_tgt_tuser(3),
      I4 => \tx_64.req_bar_id_reg[0]\,
      I5 => m_axis_rx_tgt_tuser(2),
      O => \goreg_dm.dout_i_reg[4]\(0)
    );
\tx_64.req_bar_id[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00540000"
    )
        port map (
      I0 => m_axis_rx_tgt_tuser(3),
      I1 => m_axis_rx_tgt_tuser(4),
      I2 => m_axis_rx_tgt_tuser(5),
      I3 => m_axis_rx_tgt_tuser(2),
      I4 => \tx_64.req_bar_id_reg[0]\,
      O => \goreg_dm.dout_i_reg[4]\(1)
    );
\tx_64.req_bar_id[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => m_axis_rx_tgt_tuser(3),
      I1 => m_axis_rx_tgt_tuser(4),
      I2 => m_axis_rx_tgt_tuser(5),
      I3 => m_axis_rx_tgt_tuser(2),
      I4 => \tx_64.req_bar_id_reg[0]\,
      O => \goreg_dm.dout_i_reg[4]\(2)
    );
\tx_64.req_fbe[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(32),
      O => \goreg_dm.dout_i_reg[59]\(0)
    );
\tx_64.req_fbe[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(33),
      O => \goreg_dm.dout_i_reg[59]\(1)
    );
\tx_64.req_fbe[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(34),
      O => \goreg_dm.dout_i_reg[59]\(2)
    );
\tx_64.req_fbe[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(35),
      O => \goreg_dm.dout_i_reg[59]\(3)
    );
\tx_64.req_msg_code[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(32),
      O => \goreg_dm.dout_i_reg[59]_0\(0)
    );
\tx_64.req_msg_code[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(33),
      O => \goreg_dm.dout_i_reg[59]_0\(1)
    );
\tx_64.req_msg_code[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(34),
      O => \goreg_dm.dout_i_reg[59]_0\(2)
    );
\tx_64.req_msg_code[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(35),
      O => \goreg_dm.dout_i_reg[59]_0\(3)
    );
\tx_64.req_msg_code[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(36),
      O => \goreg_dm.dout_i_reg[59]_0\(4)
    );
\tx_64.req_msg_code[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(37),
      O => \goreg_dm.dout_i_reg[59]_0\(5)
    );
\tx_64.req_msg_code[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(38),
      O => \goreg_dm.dout_i_reg[59]_0\(6)
    );
\tx_64.req_msg_code[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA200000"
    )
        port map (
      I0 => \^goreg_dm.dout_i_reg[94]\(28),
      I1 => in_packet_q_0,
      I2 => \^empty_fwft_i_reg\,
      I3 => state(0),
      I4 => \^goreg_dm.dout_i_reg[94]\(39),
      O => \goreg_dm.dout_i_reg[59]_0\(7)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_axi_stream_intf is
  port (
    s_axis_tx_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tlast : out STD_LOGIC;
    s_axis_tx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : out STD_LOGIC;
    \pcie_dma_in\\.pcie_rq_seq_num0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pcie_dma_in\\.pcie_rq_seq_num_vld0\ : out STD_LOGIC;
    \m_axis_cc\\.tready\ : out STD_LOGIC;
    \m_axis_rq\\.tready\ : out STD_LOGIC;
    \s_axis_rc\\.tuser\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \s_axis_rc\\.tkeep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \s_axis_rc\\.tlast\ : out STD_LOGIC;
    \s_axis_rc\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \FSM_sequential_tx_64.state_reg[0]\ : out STD_LOGIC;
    \s_axis_cq\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_cq\\.tuser\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \s_axis_cq\\.tvalid\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk_out : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tkeep_o : in STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tlast : in STD_LOGIC;
    \m_axis_cc\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tvalid : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tready : in STD_LOGIC;
    \m_axis_rq\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_function_number_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_device_number_o : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_bus_number_o : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \m_axis_cc\\.tlast\ : in STD_LOGIC;
    \m_axis_cc\\.tvalid\ : in STD_LOGIC;
    \m_axis_rq\\.tvalid\ : in STD_LOGIC;
    \m_axis_rq\\.tlast\ : in STD_LOGIC;
    \s_axis_rc\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \s_axis_cq\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tuser_o : in STD_LOGIC_VECTOR ( 13 downto 0 );
    \m_axis_rq\\.tuser\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_axi_stream_intf : entity is "xdma_0_axi_stream_intf";
end xdma_0_xdma_0_axi_stream_intf;

architecture STRUCTURE of xdma_0_xdma_0_axi_stream_intf is
  signal in_packet_q : STD_LOGIC;
  signal in_packet_q_2 : STD_LOGIC;
  signal m_axis_rx_cpl_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal m_axis_rx_cpl_tvalid : STD_LOGIC;
  signal m_axis_rx_tgt_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal m_axis_rx_tgt_tlast : STD_LOGIC;
  signal m_axis_rx_tgt_tready : STD_LOGIC;
  signal m_axis_rx_tgt_tvalid : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 63 downto 2 );
  signal req_ATS : STD_LOGIC;
  signal req_LTR : STD_LOGIC;
  signal req_OBFF : STD_LOGIC;
  signal req_VDM : STD_LOGIC;
  signal req_bar_id : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal req_fbe : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal req_mesg : STD_LOGIC;
  signal req_msg_code : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal s_axis_tx_req_tlast : STD_LOGIC;
  signal s_axis_tx_req_tready : STD_LOGIC;
  signal s_axis_tx_req_tvalid : STD_LOGIC;
  signal s_axis_tx_tdata0_in : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal s_axis_tx_tgt_tdata : STD_LOGIC_VECTOR ( 13 to 13 );
  signal seq_num : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \sop__0\ : STD_LOGIC;
  signal state : STD_LOGIC_VECTOR ( 2 to 2 );
  signal state_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal state_1 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal transfer_SM : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal wr_attr : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_byte : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal wr_cid : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal wr_compl_status : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wr_len : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal wreq_data_le : STD_LOGIC_VECTOR ( 63 downto 7 );
  signal xdma_0_dma_req_i_n_1 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_100 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_101 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_102 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_103 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_104 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_105 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_106 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_107 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_108 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_109 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_110 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_111 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_112 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_113 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_114 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_115 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_116 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_117 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_118 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_119 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_120 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_124 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_125 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_126 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_127 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_2 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_72 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_83 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_84 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_85 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_86 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_87 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_88 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_89 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_90 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_91 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_92 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_93 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_94 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_95 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_96 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_97 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_98 : STD_LOGIC;
  signal xdma_0_dma_req_i_n_99 : STD_LOGIC;
  signal xdma_0_rx_demux_i_n_173 : STD_LOGIC;
  signal xdma_0_rx_demux_i_n_174 : STD_LOGIC;
  signal xdma_0_rx_demux_i_n_175 : STD_LOGIC;
  signal xdma_0_rx_demux_i_n_179 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_18 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_19 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_20 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_21 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_22 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_23 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_24 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_25 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_26 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_27 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_28 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_29 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_30 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_31 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_32 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_33 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_34 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_35 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_36 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_37 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_38 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_39 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_40 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_41 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_42 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_43 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_44 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_45 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_46 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_47 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_48 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_49 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_50 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_51 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_52 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_53 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_54 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_55 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_56 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_57 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_58 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_59 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_60 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_61 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_62 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_63 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_64 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_65 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_66 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_67 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_68 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_69 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_70 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_71 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_72 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_73 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_74 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_75 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_76 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_77 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_78 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_79 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_81 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_82 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_83 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_84 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_85 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_86 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_87 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_88 : STD_LOGIC;
  signal xdma_0_tgt_cpl_i_n_89 : STD_LOGIC;
  signal xdma_0_tgt_req_i_n_5 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_12 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_14 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_15 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_16 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_3 : STD_LOGIC;
  signal xdma_0_tx_mux_i_n_4 : STD_LOGIC;
begin
xdma_0_dma_cpl_i: entity work.xdma_0_xdma_0_dma_cpl
     port map (
      D(9 downto 0) => wr_len(9 downto 0),
      SR(0) => SR(0),
      in_packet_q => in_packet_q,
      in_packet_q_reg_0 => xdma_0_rx_demux_i_n_179,
      m_axis_tdata(63 downto 0) => m_axis_rx_cpl_tdata(63 downto 0),
      m_axis_tvalid => m_axis_rx_cpl_tvalid,
      \rc_64.wr_attr_reg[2]_0\(2 downto 0) => wr_attr(2 downto 0),
      \rc_64.wr_byte_reg[11]_0\(11 downto 0) => wr_byte(11 downto 0),
      \rc_64.wr_cid_reg[15]_0\(15 downto 0) => wr_cid(15 downto 0),
      \rc_64.wr_compl_status_reg[2]_0\(2 downto 0) => wr_compl_status(2 downto 0),
      \rc_64.wr_tc_reg[2]_0\(2) => xdma_0_rx_demux_i_n_173,
      \rc_64.wr_tc_reg[2]_0\(1) => xdma_0_rx_demux_i_n_174,
      \rc_64.wr_tc_reg[2]_0\(0) => xdma_0_rx_demux_i_n_175,
      \s_axis_rc\\.tdata\(63 downto 0) => \s_axis_rc\\.tdata\(63 downto 0),
      \s_axis_rc\\.tkeep\(1 downto 0) => \s_axis_rc\\.tkeep\(1 downto 0),
      \s_axis_rc\\.tlast\ => \s_axis_rc\\.tlast\,
      \s_axis_rc\\.tready\(0) => \s_axis_rc\\.tready\(0),
      \s_axis_rc\\.tuser\(3 downto 0) => \s_axis_rc\\.tuser\(3 downto 0),
      user_clk_out => user_clk_out
    );
xdma_0_dma_req_i: entity work.xdma_0_xdma_0_dma_req
     port map (
      D(46 downto 28) => s_axis_tx_tdata0_in(63 downto 45),
      D(27 downto 15) => s_axis_tx_tdata0_in(43 downto 31),
      D(14 downto 8) => s_axis_tx_tdata0_in(29 downto 23),
      D(7) => s_axis_tx_tdata0_in(19),
      D(6 downto 4) => s_axis_tx_tdata0_in(17 downto 15),
      D(3) => s_axis_tx_tdata0_in(13),
      D(2) => s_axis_tx_tdata0_in(7),
      D(1 downto 0) => s_axis_tx_tdata0_in(1 downto 0),
      \FSM_sequential_tx_64.state_reg[0]_0\ => xdma_0_dma_req_i_n_1,
      \FSM_sequential_tx_64.state_reg[2]_0\(0) => state(2),
      \FSM_sequential_tx_64.state_reg[2]_1\ => xdma_0_dma_req_i_n_89,
      \FSM_sequential_tx_64.state_reg[2]_2\ => xdma_0_dma_req_i_n_126,
      \FSM_sequential_tx_64.state_reg[2]_3\ => xdma_0_dma_req_i_n_127,
      \Head_reg[2]\ => xdma_0_dma_req_i_n_2,
      \Head_reg[36]\ => xdma_0_dma_req_i_n_86,
      \Head_reg[56]\ => xdma_0_dma_req_i_n_105,
      \Head_reg[56]_0\ => xdma_0_dma_req_i_n_106,
      \Head_reg[56]_1\ => xdma_0_dma_req_i_n_107,
      \Head_reg[56]_10\ => xdma_0_dma_req_i_n_116,
      \Head_reg[56]_11\ => xdma_0_dma_req_i_n_117,
      \Head_reg[56]_12\ => xdma_0_dma_req_i_n_118,
      \Head_reg[56]_13\ => xdma_0_dma_req_i_n_119,
      \Head_reg[56]_14\ => xdma_0_dma_req_i_n_120,
      \Head_reg[56]_2\ => xdma_0_dma_req_i_n_108,
      \Head_reg[56]_3\ => xdma_0_dma_req_i_n_109,
      \Head_reg[56]_4\ => xdma_0_dma_req_i_n_110,
      \Head_reg[56]_5\ => xdma_0_dma_req_i_n_111,
      \Head_reg[56]_6\ => xdma_0_dma_req_i_n_112,
      \Head_reg[56]_7\ => xdma_0_dma_req_i_n_113,
      \Head_reg[56]_8\ => xdma_0_dma_req_i_n_114,
      \Head_reg[56]_9\ => xdma_0_dma_req_i_n_115,
      Q(21) => p_0_in(2),
      Q(20 downto 13) => p_0_in(63 downto 56),
      Q(12 downto 10) => p_0_in(47 downto 45),
      Q(9 downto 0) => p_0_in(43 downto 34),
      SR(0) => SR(0),
      cfg_bus_number_o(7 downto 0) => cfg_bus_number_o(7 downto 0),
      cfg_device_number_o(4 downto 0) => cfg_device_number_o(4 downto 0),
      cfg_function_number_o(2 downto 0) => cfg_function_number_o(2 downto 0),
      \m_axis_cc\\.tdata\(14 downto 4) => \m_axis_cc\\.tdata\(63 downto 53),
      \m_axis_cc\\.tdata\(3 downto 0) => \m_axis_cc\\.tdata\(51 downto 48),
      \m_axis_rq\\.tdata\(63 downto 0) => \m_axis_rq\\.tdata\(63 downto 0),
      \m_axis_rq\\.tlast\ => \m_axis_rq\\.tlast\,
      \m_axis_rq\\.tready\ => \m_axis_rq\\.tready\,
      \m_axis_rq\\.tuser\(11 downto 0) => \m_axis_rq\\.tuser\(11 downto 0),
      \m_axis_rq\\.tvalid\ => \m_axis_rq\\.tvalid\,
      s_axis_tx_req_tlast => s_axis_tx_req_tlast,
      s_axis_tx_req_tready => s_axis_tx_req_tready,
      s_axis_tx_req_tvalid => s_axis_tx_req_tvalid,
      \s_axis_tx_tdata[30]_i_2_0\ => xdma_0_tx_mux_i_n_15,
      \s_axis_tx_tdata_reg[0]\ => xdma_0_tgt_cpl_i_n_84,
      \s_axis_tx_tdata_reg[15]\ => xdma_0_tgt_cpl_i_n_62,
      \s_axis_tx_tdata_reg[16]\ => xdma_0_tgt_cpl_i_n_63,
      \s_axis_tx_tdata_reg[17]\ => xdma_0_tgt_cpl_i_n_64,
      \s_axis_tx_tdata_reg[19]\ => xdma_0_tgt_cpl_i_n_65,
      \s_axis_tx_tdata_reg[1]\ => xdma_0_tgt_cpl_i_n_85,
      \s_axis_tx_tdata_reg[23]\ => xdma_0_tgt_cpl_i_n_66,
      \s_axis_tx_tdata_reg[24]\ => xdma_0_tgt_cpl_i_n_67,
      \s_axis_tx_tdata_reg[25]\ => xdma_0_tgt_cpl_i_n_42,
      \s_axis_tx_tdata_reg[25]_0\ => xdma_0_tgt_cpl_i_n_82,
      \s_axis_tx_tdata_reg[26]\ => xdma_0_tgt_cpl_i_n_68,
      \s_axis_tx_tdata_reg[27]\ => xdma_0_tgt_cpl_i_n_44,
      \s_axis_tx_tdata_reg[27]_0\ => xdma_0_tgt_cpl_i_n_83,
      \s_axis_tx_tdata_reg[28]\ => xdma_0_tgt_cpl_i_n_69,
      \s_axis_tx_tdata_reg[29]\ => xdma_0_tgt_cpl_i_n_18,
      \s_axis_tx_tdata_reg[29]_0\ => xdma_0_tgt_cpl_i_n_89,
      \s_axis_tx_tdata_reg[2]\ => xdma_0_tx_mux_i_n_16,
      \s_axis_tx_tdata_reg[2]_0\ => xdma_0_tgt_cpl_i_n_20,
      \s_axis_tx_tdata_reg[31]\ => xdma_0_tgt_cpl_i_n_70,
      \s_axis_tx_tdata_reg[32]\ => xdma_0_tgt_cpl_i_n_86,
      \s_axis_tx_tdata_reg[33]\ => xdma_0_tgt_cpl_i_n_87,
      \s_axis_tx_tdata_reg[34]\ => xdma_0_tgt_cpl_i_n_19,
      \s_axis_tx_tdata_reg[34]_0\ => xdma_0_tgt_cpl_i_n_21,
      \s_axis_tx_tdata_reg[35]\ => xdma_0_tgt_cpl_i_n_22,
      \s_axis_tx_tdata_reg[36]\ => xdma_0_tgt_cpl_i_n_23,
      \s_axis_tx_tdata_reg[37]\ => xdma_0_tgt_cpl_i_n_24,
      \s_axis_tx_tdata_reg[38]\ => xdma_0_tgt_cpl_i_n_25,
      \s_axis_tx_tdata_reg[39]\ => xdma_0_tgt_cpl_i_n_26,
      \s_axis_tx_tdata_reg[40]\ => xdma_0_tgt_cpl_i_n_27,
      \s_axis_tx_tdata_reg[41]\ => xdma_0_tgt_cpl_i_n_28,
      \s_axis_tx_tdata_reg[42]\ => xdma_0_tgt_cpl_i_n_29,
      \s_axis_tx_tdata_reg[43]\ => xdma_0_tgt_cpl_i_n_30,
      \s_axis_tx_tdata_reg[45]\ => xdma_0_tgt_cpl_i_n_31,
      \s_axis_tx_tdata_reg[46]\ => xdma_0_tgt_cpl_i_n_32,
      \s_axis_tx_tdata_reg[47]\ => xdma_0_tgt_cpl_i_n_33,
      \s_axis_tx_tdata_reg[48]\ => xdma_0_tgt_cpl_i_n_71,
      \s_axis_tx_tdata_reg[48]_0\ => xdma_0_tgt_cpl_i_n_45,
      \s_axis_tx_tdata_reg[49]\ => xdma_0_tgt_cpl_i_n_72,
      \s_axis_tx_tdata_reg[49]_0\ => xdma_0_tgt_cpl_i_n_46,
      \s_axis_tx_tdata_reg[50]\ => xdma_0_tgt_cpl_i_n_73,
      \s_axis_tx_tdata_reg[50]_0\ => xdma_0_tgt_cpl_i_n_47,
      \s_axis_tx_tdata_reg[51]\ => xdma_0_tgt_cpl_i_n_74,
      \s_axis_tx_tdata_reg[51]_0\ => xdma_0_tgt_cpl_i_n_48,
      \s_axis_tx_tdata_reg[52]\ => xdma_0_tgt_cpl_i_n_75,
      \s_axis_tx_tdata_reg[52]_0\ => xdma_0_tgt_cpl_i_n_49,
      \s_axis_tx_tdata_reg[53]\ => xdma_0_tgt_cpl_i_n_76,
      \s_axis_tx_tdata_reg[53]_0\ => xdma_0_tgt_cpl_i_n_50,
      \s_axis_tx_tdata_reg[54]\ => xdma_0_tgt_cpl_i_n_77,
      \s_axis_tx_tdata_reg[54]_0\ => xdma_0_tgt_cpl_i_n_51,
      \s_axis_tx_tdata_reg[55]\ => xdma_0_tgt_cpl_i_n_78,
      \s_axis_tx_tdata_reg[55]_0\ => xdma_0_tgt_cpl_i_n_52,
      \s_axis_tx_tdata_reg[56]\ => xdma_0_tgt_cpl_i_n_34,
      \s_axis_tx_tdata_reg[56]_0\ => xdma_0_tgt_cpl_i_n_53,
      \s_axis_tx_tdata_reg[57]\ => xdma_0_tgt_cpl_i_n_35,
      \s_axis_tx_tdata_reg[57]_0\ => xdma_0_tgt_cpl_i_n_54,
      \s_axis_tx_tdata_reg[58]\ => xdma_0_tgt_cpl_i_n_36,
      \s_axis_tx_tdata_reg[58]_0\ => xdma_0_tgt_cpl_i_n_55,
      \s_axis_tx_tdata_reg[59]\ => xdma_0_tgt_cpl_i_n_37,
      \s_axis_tx_tdata_reg[59]_0\ => xdma_0_tgt_cpl_i_n_56,
      \s_axis_tx_tdata_reg[60]\ => xdma_0_tgt_cpl_i_n_38,
      \s_axis_tx_tdata_reg[60]_0\ => xdma_0_tgt_cpl_i_n_57,
      \s_axis_tx_tdata_reg[61]\ => xdma_0_tgt_cpl_i_n_39,
      \s_axis_tx_tdata_reg[61]_0\ => xdma_0_tgt_cpl_i_n_58,
      \s_axis_tx_tdata_reg[62]\ => xdma_0_tgt_cpl_i_n_40,
      \s_axis_tx_tdata_reg[62]_0\ => xdma_0_tgt_cpl_i_n_59,
      \s_axis_tx_tdata_reg[63]\ => xdma_0_tgt_cpl_i_n_41,
      \s_axis_tx_tdata_reg[63]_0\ => xdma_0_tgt_cpl_i_n_60,
      \s_axis_tx_tdata_reg[7]\ => xdma_0_tgt_cpl_i_n_61,
      s_axis_tx_tgt_tdata(0) => s_axis_tx_tgt_tdata(13),
      \s_axis_tx_tkeep_reg[7]\ => xdma_0_tx_mux_i_n_14,
      \s_axis_tx_tkeep_reg[7]_0\ => xdma_0_tgt_cpl_i_n_88,
      \s_axis_tx_tkeep_reg[7]_1\ => xdma_0_tx_mux_i_n_4,
      s_axis_tx_tready => s_axis_tx_tready,
      transfer_SM(1 downto 0) => transfer_SM(1 downto 0),
      \tx_64.req_4dw_reg_0\ => xdma_0_dma_req_i_n_72,
      \tx_64.req_4dw_reg_1\ => xdma_0_dma_req_i_n_83,
      \tx_64.req_4dw_reg_2\ => xdma_0_dma_req_i_n_84,
      \tx_64.req_4dw_reg_3\ => xdma_0_dma_req_i_n_85,
      \tx_64.req_addr_reg[35]_0\ => xdma_0_dma_req_i_n_90,
      \tx_64.req_addr_reg[36]_0\ => xdma_0_dma_req_i_n_91,
      \tx_64.req_addr_reg[37]_0\ => xdma_0_dma_req_i_n_92,
      \tx_64.req_addr_reg[38]_0\ => xdma_0_dma_req_i_n_93,
      \tx_64.req_addr_reg[40]_0\ => xdma_0_dma_req_i_n_94,
      \tx_64.req_addr_reg[41]_0\ => xdma_0_dma_req_i_n_95,
      \tx_64.req_addr_reg[42]_0\ => xdma_0_dma_req_i_n_96,
      \tx_64.req_addr_reg[43]_0\ => xdma_0_dma_req_i_n_97,
      \tx_64.req_addr_reg[44]_0\ => xdma_0_dma_req_i_n_98,
      \tx_64.req_addr_reg[46]_0\ => xdma_0_dma_req_i_n_99,
      \tx_64.req_addr_reg[50]_0\ => xdma_0_dma_req_i_n_100,
      \tx_64.req_addr_reg[52]_0\ => xdma_0_dma_req_i_n_101,
      \tx_64.req_addr_reg[53]_0\ => xdma_0_dma_req_i_n_102,
      \tx_64.req_addr_reg[54]_0\ => xdma_0_dma_req_i_n_103,
      \tx_64.req_addr_reg[57]_0\ => xdma_0_dma_req_i_n_124,
      \tx_64.req_addr_reg[59]_0\ => xdma_0_dma_req_i_n_125,
      \tx_64.req_addr_reg[62]_0\ => xdma_0_dma_req_i_n_104,
      \tx_64.seq_num_reg[3]_0\(3 downto 0) => seq_num(3 downto 0),
      \tx_64.wr_data_reg[52]_0\ => xdma_0_dma_req_i_n_88,
      \tx_64.wr_data_reg[55]_0\(9) => wreq_data_le(47),
      \tx_64.wr_data_reg[55]_0\(8) => wreq_data_le(55),
      \tx_64.wr_data_reg[55]_0\(7) => wreq_data_le(51),
      \tx_64.wr_data_reg[55]_0\(6 downto 5) => wreq_data_le(49 downto 48),
      \tx_64.wr_data_reg[55]_0\(4) => wreq_data_le(63),
      \tx_64.wr_data_reg[55]_0\(3) => wreq_data_le(60),
      \tx_64.wr_data_reg[55]_0\(2) => wreq_data_le(58),
      \tx_64.wr_data_reg[55]_0\(1) => wreq_data_le(56),
      \tx_64.wr_data_reg[55]_0\(0) => wreq_data_le(7),
      \tx_64.wr_data_reg[58]_0\ => xdma_0_dma_req_i_n_87,
      user_clk_out => user_clk_out
    );
xdma_0_rx_demux_i: entity work.xdma_0_xdma_0_rx_demux
     port map (
      D(63 downto 0) => D(63 downto 0),
      E(0) => E(0),
      SR(0) => SR(0),
      empty_fwft_i_reg => m_axis_rx_tgt_tvalid,
      \goreg_dm.dout_i_reg[4]\(2 downto 0) => req_bar_id(2 downto 0),
      \goreg_dm.dout_i_reg[59]\(3 downto 0) => req_fbe(3 downto 0),
      \goreg_dm.dout_i_reg[59]_0\(7 downto 0) => req_msg_code(7 downto 0),
      \goreg_dm.dout_i_reg[94]\(63 downto 0) => m_axis_rx_tgt_tdata(63 downto 0),
      in_packet_q => in_packet_q,
      in_packet_q_0 => in_packet_q_2,
      in_packet_q_reg(15 downto 0) => wr_cid(15 downto 0),
      in_packet_q_reg_0(11 downto 0) => wr_byte(11 downto 0),
      in_packet_q_reg_1(9 downto 0) => wr_len(9 downto 0),
      in_packet_q_reg_2(2 downto 0) => wr_attr(2 downto 0),
      in_packet_q_reg_3(2) => xdma_0_rx_demux_i_n_173,
      in_packet_q_reg_3(1) => xdma_0_rx_demux_i_n_174,
      in_packet_q_reg_3(0) => xdma_0_rx_demux_i_n_175,
      in_packet_q_reg_4(2 downto 0) => wr_compl_status(2 downto 0),
      m_axis_rx_tkeep_o(3 downto 0) => m_axis_rx_tkeep_o(3 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser_o(13 downto 0) => m_axis_rx_tuser_o(13 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      m_axis_tdata(63 downto 0) => m_axis_rx_cpl_tdata(63 downto 0),
      m_axis_tlast => m_axis_rx_tgt_tlast,
      m_axis_tready => m_axis_rx_tgt_tready,
      m_axis_tvalid => m_axis_rx_cpl_tvalid,
      req_ATS => req_ATS,
      req_LTR => req_LTR,
      req_OBFF => req_OBFF,
      req_VDM => req_VDM,
      req_mesg => req_mesg,
      \s_axis_rc\\.tready\(0) => \s_axis_rc\\.tready\(0),
      \sop__0\ => \sop__0\,
      state(0) => state_1(1),
      \tx_64.req_bar_id_reg[0]\ => xdma_0_tgt_req_i_n_5,
      user_clk_out => user_clk_out,
      user_reset_out_reg => xdma_0_rx_demux_i_n_179
    );
xdma_0_tgt_cpl_i: entity work.xdma_0_xdma_0_tgt_cpl
     port map (
      D(16) => s_axis_tx_tdata0_in(44),
      D(15) => s_axis_tx_tdata0_in(30),
      D(14 downto 12) => s_axis_tx_tdata0_in(22 downto 20),
      D(11) => s_axis_tx_tdata0_in(18),
      D(10) => s_axis_tx_tdata0_in(14),
      D(9 downto 5) => s_axis_tx_tdata0_in(12 downto 8),
      D(4 downto 0) => s_axis_tx_tdata0_in(6 downto 2),
      \FSM_sequential_tx_64.state_reg[0]_0\ => xdma_0_tgt_cpl_i_n_62,
      \FSM_sequential_tx_64.state_reg[0]_1\ => xdma_0_tgt_cpl_i_n_63,
      \FSM_sequential_tx_64.state_reg[0]_10\ => xdma_0_tgt_cpl_i_n_89,
      \FSM_sequential_tx_64.state_reg[0]_11\ => xdma_0_tx_mux_i_n_12,
      \FSM_sequential_tx_64.state_reg[0]_2\ => xdma_0_tgt_cpl_i_n_64,
      \FSM_sequential_tx_64.state_reg[0]_3\ => xdma_0_tgt_cpl_i_n_65,
      \FSM_sequential_tx_64.state_reg[0]_4\ => xdma_0_tgt_cpl_i_n_66,
      \FSM_sequential_tx_64.state_reg[0]_5\ => xdma_0_tgt_cpl_i_n_67,
      \FSM_sequential_tx_64.state_reg[0]_6\ => xdma_0_tgt_cpl_i_n_68,
      \FSM_sequential_tx_64.state_reg[0]_7\ => xdma_0_tgt_cpl_i_n_69,
      \FSM_sequential_tx_64.state_reg[0]_8\ => xdma_0_tgt_cpl_i_n_70,
      \FSM_sequential_tx_64.state_reg[0]_9\ => xdma_0_tgt_cpl_i_n_81,
      \FSM_sequential_tx_64.state_reg[1]_0\ => xdma_0_tgt_cpl_i_n_19,
      \FSM_sequential_tx_64.state_reg[1]_1\ => xdma_0_tgt_cpl_i_n_42,
      \FSM_sequential_tx_64.state_reg[1]_2\ => xdma_0_tgt_cpl_i_n_43,
      \FSM_sequential_tx_64.state_reg[1]_3\ => xdma_0_tgt_cpl_i_n_44,
      \Head_reg[10]\ => xdma_0_tgt_cpl_i_n_73,
      \Head_reg[11]\ => xdma_0_tgt_cpl_i_n_74,
      \Head_reg[12]\ => xdma_0_tgt_cpl_i_n_75,
      \Head_reg[13]\ => xdma_0_tgt_cpl_i_n_76,
      \Head_reg[14]\ => xdma_0_tgt_cpl_i_n_77,
      \Head_reg[15]\ => xdma_0_tgt_cpl_i_n_78,
      \Head_reg[8]\ => xdma_0_tgt_cpl_i_n_71,
      \Head_reg[9]\ => xdma_0_tgt_cpl_i_n_72,
      Q(21) => p_0_in(2),
      Q(20 downto 13) => p_0_in(63 downto 56),
      Q(12 downto 10) => p_0_in(47 downto 45),
      Q(9 downto 0) => p_0_in(43 downto 34),
      SR(0) => SR(0),
      \aa256_tdata_ff_reg[0]\ => xdma_0_tgt_cpl_i_n_34,
      \aa256_tdata_ff_reg[1]\ => xdma_0_tgt_cpl_i_n_35,
      \aa256_tdata_ff_reg[24]\ => xdma_0_tgt_cpl_i_n_53,
      \aa256_tdata_ff_reg[24]_0\ => xdma_0_tgt_cpl_i_n_54,
      \aa256_tdata_ff_reg[24]_1\ => xdma_0_tgt_cpl_i_n_55,
      \aa256_tdata_ff_reg[24]_2\ => xdma_0_tgt_cpl_i_n_56,
      \aa256_tdata_ff_reg[24]_3\ => xdma_0_tgt_cpl_i_n_57,
      \aa256_tdata_ff_reg[24]_4\ => xdma_0_tgt_cpl_i_n_58,
      \aa256_tdata_ff_reg[24]_5\ => xdma_0_tgt_cpl_i_n_59,
      \aa256_tdata_ff_reg[24]_6\ => xdma_0_tgt_cpl_i_n_60,
      \aa256_tdata_ff_reg[24]_7\ => xdma_0_tgt_cpl_i_n_86,
      \aa256_tdata_ff_reg[25]\ => xdma_0_tgt_cpl_i_n_87,
      \aa256_tdata_ff_reg[2]\ => xdma_0_tgt_cpl_i_n_36,
      \aa256_tdata_ff_reg[3]\ => xdma_0_tgt_cpl_i_n_37,
      \aa256_tdata_ff_reg[4]\ => xdma_0_tgt_cpl_i_n_38,
      \aa256_tdata_ff_reg[5]\ => xdma_0_tgt_cpl_i_n_39,
      \aa256_tdata_ff_reg[6]\ => xdma_0_tgt_cpl_i_n_40,
      \aa256_tdata_ff_reg[7]\ => xdma_0_tgt_cpl_i_n_41,
      cfg_bus_number_o(7 downto 0) => cfg_bus_number_o(7 downto 0),
      \cfg_device_number_d_reg[0]\ => xdma_0_tgt_cpl_i_n_48,
      \cfg_device_number_d_reg[1]\ => xdma_0_tgt_cpl_i_n_49,
      \cfg_device_number_d_reg[2]\ => xdma_0_tgt_cpl_i_n_50,
      \cfg_device_number_d_reg[3]\ => xdma_0_tgt_cpl_i_n_51,
      \cfg_device_number_d_reg[4]\ => xdma_0_tgt_cpl_i_n_52,
      cfg_device_number_o(4 downto 0) => cfg_device_number_o(4 downto 0),
      \cfg_function_number_d_reg[0]\ => xdma_0_tgt_cpl_i_n_45,
      \cfg_function_number_d_reg[1]\ => xdma_0_tgt_cpl_i_n_46,
      \cfg_function_number_d_reg[2]\ => xdma_0_tgt_cpl_i_n_47,
      cfg_function_number_o(2 downto 0) => cfg_function_number_o(2 downto 0),
      \m_axis_cc\\.tdata\(63 downto 0) => \m_axis_cc\\.tdata\(63 downto 0),
      \m_axis_cc\\.tlast\ => \m_axis_cc\\.tlast\,
      \m_axis_cc\\.tready\ => \m_axis_cc\\.tready\,
      \m_axis_cc\\.tvalid\ => \m_axis_cc\\.tvalid\,
      \m_axis_rq\\.tdata\(7 downto 0) => \m_axis_rq\\.tdata\(15 downto 8),
      s_axis_tx_req_tvalid => s_axis_tx_req_tvalid,
      \s_axis_tx_tdata_reg[10]\ => xdma_0_dma_req_i_n_96,
      \s_axis_tx_tdata_reg[11]\ => xdma_0_dma_req_i_n_97,
      \s_axis_tx_tdata_reg[12]\ => xdma_0_dma_req_i_n_98,
      \s_axis_tx_tdata_reg[14]\ => xdma_0_dma_req_i_n_99,
      \s_axis_tx_tdata_reg[15]\(9) => wreq_data_le(47),
      \s_axis_tx_tdata_reg[15]\(8) => wreq_data_le(55),
      \s_axis_tx_tdata_reg[15]\(7) => wreq_data_le(51),
      \s_axis_tx_tdata_reg[15]\(6 downto 5) => wreq_data_le(49 downto 48),
      \s_axis_tx_tdata_reg[15]\(4) => wreq_data_le(63),
      \s_axis_tx_tdata_reg[15]\(3) => wreq_data_le(60),
      \s_axis_tx_tdata_reg[15]\(2) => wreq_data_le(58),
      \s_axis_tx_tdata_reg[15]\(1) => wreq_data_le(56),
      \s_axis_tx_tdata_reg[15]\(0) => wreq_data_le(7),
      \s_axis_tx_tdata_reg[15]_0\ => xdma_0_dma_req_i_n_89,
      \s_axis_tx_tdata_reg[18]\ => xdma_0_dma_req_i_n_100,
      \s_axis_tx_tdata_reg[20]\ => xdma_0_dma_req_i_n_101,
      \s_axis_tx_tdata_reg[21]\ => xdma_0_dma_req_i_n_102,
      \s_axis_tx_tdata_reg[22]\ => xdma_0_dma_req_i_n_103,
      \s_axis_tx_tdata_reg[25]\ => xdma_0_dma_req_i_n_124,
      \s_axis_tx_tdata_reg[25]_0\ => xdma_0_dma_req_i_n_126,
      \s_axis_tx_tdata_reg[27]\ => xdma_0_dma_req_i_n_125,
      \s_axis_tx_tdata_reg[29]\ => xdma_0_dma_req_i_n_83,
      \s_axis_tx_tdata_reg[2]\ => xdma_0_dma_req_i_n_87,
      \s_axis_tx_tdata_reg[2]_0\ => xdma_0_tx_mux_i_n_3,
      \s_axis_tx_tdata_reg[2]_1\ => xdma_0_dma_req_i_n_2,
      \s_axis_tx_tdata_reg[30]\ => xdma_0_tx_mux_i_n_4,
      \s_axis_tx_tdata_reg[30]_0\ => xdma_0_dma_req_i_n_104,
      \s_axis_tx_tdata_reg[34]\ => xdma_0_dma_req_i_n_72,
      \s_axis_tx_tdata_reg[3]\ => xdma_0_dma_req_i_n_90,
      \s_axis_tx_tdata_reg[44]\ => xdma_0_dma_req_i_n_86,
      \s_axis_tx_tdata_reg[44]_0\ => xdma_0_dma_req_i_n_88,
      \s_axis_tx_tdata_reg[48]\ => xdma_0_dma_req_i_n_105,
      \s_axis_tx_tdata_reg[48]_0\ => xdma_0_tx_mux_i_n_16,
      \s_axis_tx_tdata_reg[49]\ => xdma_0_dma_req_i_n_106,
      \s_axis_tx_tdata_reg[4]\ => xdma_0_dma_req_i_n_91,
      \s_axis_tx_tdata_reg[50]\ => xdma_0_dma_req_i_n_107,
      \s_axis_tx_tdata_reg[51]\ => xdma_0_dma_req_i_n_108,
      \s_axis_tx_tdata_reg[52]\ => xdma_0_dma_req_i_n_109,
      \s_axis_tx_tdata_reg[53]\ => xdma_0_dma_req_i_n_110,
      \s_axis_tx_tdata_reg[54]\ => xdma_0_dma_req_i_n_111,
      \s_axis_tx_tdata_reg[55]\ => xdma_0_dma_req_i_n_112,
      \s_axis_tx_tdata_reg[56]\ => xdma_0_dma_req_i_n_84,
      \s_axis_tx_tdata_reg[56]_0\ => xdma_0_dma_req_i_n_113,
      \s_axis_tx_tdata_reg[57]\ => xdma_0_dma_req_i_n_114,
      \s_axis_tx_tdata_reg[58]\ => xdma_0_dma_req_i_n_115,
      \s_axis_tx_tdata_reg[59]\ => xdma_0_dma_req_i_n_116,
      \s_axis_tx_tdata_reg[5]\ => xdma_0_dma_req_i_n_92,
      \s_axis_tx_tdata_reg[60]\ => xdma_0_dma_req_i_n_117,
      \s_axis_tx_tdata_reg[61]\ => xdma_0_dma_req_i_n_118,
      \s_axis_tx_tdata_reg[62]\ => xdma_0_dma_req_i_n_119,
      \s_axis_tx_tdata_reg[63]\ => xdma_0_dma_req_i_n_120,
      \s_axis_tx_tdata_reg[6]\ => xdma_0_dma_req_i_n_93,
      \s_axis_tx_tdata_reg[7]\ => xdma_0_dma_req_i_n_85,
      \s_axis_tx_tdata_reg[8]\ => xdma_0_dma_req_i_n_94,
      \s_axis_tx_tdata_reg[9]\ => xdma_0_dma_req_i_n_95,
      s_axis_tx_tgt_tdata(0) => s_axis_tx_tgt_tdata(13),
      s_axis_tx_tready => s_axis_tx_tready,
      state(0) => state_0(0),
      transfer_SM(1 downto 0) => transfer_SM(1 downto 0),
      tready_thrtl_reg => xdma_0_tgt_cpl_i_n_79,
      \tx_64.compl_addr_reg[2]_0\ => xdma_0_tgt_cpl_i_n_82,
      \tx_64.compl_addr_reg[2]_1\ => xdma_0_tgt_cpl_i_n_83,
      \tx_64.compl_byte_reg[10]_0\ => xdma_0_tgt_cpl_i_n_29,
      \tx_64.compl_byte_reg[11]_0\ => xdma_0_tgt_cpl_i_n_30,
      \tx_64.compl_byte_reg[2]_0\ => xdma_0_tgt_cpl_i_n_21,
      \tx_64.compl_byte_reg[3]_0\ => xdma_0_tgt_cpl_i_n_22,
      \tx_64.compl_byte_reg[4]_0\ => xdma_0_tgt_cpl_i_n_23,
      \tx_64.compl_byte_reg[5]_0\ => xdma_0_tgt_cpl_i_n_24,
      \tx_64.compl_byte_reg[6]_0\ => xdma_0_tgt_cpl_i_n_25,
      \tx_64.compl_byte_reg[7]_0\ => xdma_0_tgt_cpl_i_n_26,
      \tx_64.compl_byte_reg[8]_0\ => xdma_0_tgt_cpl_i_n_27,
      \tx_64.compl_byte_reg[9]_0\ => xdma_0_tgt_cpl_i_n_28,
      \tx_64.compl_data_reg[37]_0\ => xdma_0_tgt_cpl_i_n_18,
      \tx_64.compl_len_reg[0]_0\ => xdma_0_tgt_cpl_i_n_84,
      \tx_64.compl_len_reg[1]_0\ => xdma_0_tgt_cpl_i_n_85,
      \tx_64.compl_len_reg[2]_0\ => xdma_0_tgt_cpl_i_n_20,
      \tx_64.compl_len_reg[7]_0\ => xdma_0_tgt_cpl_i_n_61,
      \tx_64.compl_status_reg[0]_0\ => xdma_0_tgt_cpl_i_n_31,
      \tx_64.compl_status_reg[0]_1\ => xdma_0_tgt_cpl_i_n_88,
      \tx_64.compl_status_reg[1]_0\ => xdma_0_tgt_cpl_i_n_32,
      \tx_64.compl_status_reg[2]_0\ => xdma_0_tgt_cpl_i_n_33,
      user_clk_out => user_clk_out
    );
xdma_0_tgt_req_i: entity work.xdma_0_xdma_0_tgt_req
     port map (
      D(3 downto 0) => req_fbe(3 downto 0),
      \FSM_sequential_tx_64.state_reg[0]_0\ => \FSM_sequential_tx_64.state_reg[0]\,
      \FSM_sequential_tx_64.state_reg[1]_0\(0) => state_1(1),
      SR(0) => SR(0),
      in_packet_q => in_packet_q_2,
      in_packet_q_reg_0 => xdma_0_tgt_req_i_n_5,
      m_axis_tlast => m_axis_rx_tgt_tlast,
      m_axis_tready => m_axis_rx_tgt_tready,
      req_ATS => req_ATS,
      req_LTR => req_LTR,
      req_OBFF => req_OBFF,
      req_VDM => req_VDM,
      req_mesg => req_mesg,
      \s_axis_cq\\.tdata\(63 downto 0) => \s_axis_cq\\.tdata\(63 downto 0),
      \s_axis_cq\\.tready\(0) => \s_axis_cq\\.tready\(0),
      \s_axis_cq\\.tuser\(4 downto 0) => \s_axis_cq\\.tuser\(4 downto 0),
      \s_axis_cq\\.tvalid\ => \s_axis_cq\\.tvalid\,
      \sop__0\ => \sop__0\,
      \tx_64.req_bar_id_reg[2]_0\(2 downto 0) => req_bar_id(2 downto 0),
      \tx_64.req_msg_code_reg[7]_0\(7 downto 0) => req_msg_code(7 downto 0),
      \tx_64.req_rid_reg[15]_0\(63 downto 0) => m_axis_rx_tgt_tdata(63 downto 0),
      \tx_64.req_tag_reg[0]_0\ => m_axis_rx_tgt_tvalid,
      user_clk_out => user_clk_out
    );
xdma_0_tx_mux_i: entity work.xdma_0_xdma_0_tx_mux
     port map (
      D(63 downto 0) => s_axis_tx_tdata0_in(63 downto 0),
      \FSM_sequential_transfer_SM_reg[1]_0\ => xdma_0_tx_mux_i_n_3,
      \FSM_sequential_transfer_SM_reg[1]_1\ => xdma_0_tx_mux_i_n_4,
      \FSM_sequential_transfer_SM_reg[1]_2\ => xdma_0_tgt_cpl_i_n_81,
      \FSM_sequential_transfer_SM_reg[1]_3\ => xdma_0_dma_req_i_n_127,
      \FSM_sequential_transfer_SM_reg[1]_4\ => xdma_0_tgt_cpl_i_n_79,
      \Head_reg[11]\ => xdma_0_tx_mux_i_n_15,
      Q(63 downto 0) => Q(63 downto 0),
      SR(0) => SR(0),
      \m_axis_cc\\.tlast\ => \m_axis_cc\\.tlast\,
      \m_axis_rq\\.tdata\(3 downto 0) => \m_axis_rq\\.tdata\(14 downto 11),
      \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0) => \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0),
      \pcie_dma_in\\.pcie_rq_seq_num_vld0\ => \pcie_dma_in\\.pcie_rq_seq_num_vld0\,
      \pcie_rq_seq_ret_wr_ff_reg[8]\(3 downto 0) => seq_num(3 downto 0),
      s_axis_tx_req_tlast => s_axis_tx_req_tlast,
      s_axis_tx_req_tready => s_axis_tx_req_tready,
      s_axis_tx_req_tvalid => s_axis_tx_req_tvalid,
      \s_axis_tx_tdata[33]_i_3\(0) => state(2),
      s_axis_tx_tgt_tdata(0) => s_axis_tx_tgt_tdata(13),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      \s_axis_tx_tkeep_reg[7]_0\ => xdma_0_dma_req_i_n_1,
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tlast_reg_0 => xdma_0_tgt_cpl_i_n_43,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      state(0) => state_0(0),
      transfer_SM(1 downto 0) => transfer_SM(1 downto 0),
      tready_thrtl_reg => xdma_0_tx_mux_i_n_12,
      user_clk_out => user_clk_out,
      user_reset_out_reg => xdma_0_tx_mux_i_n_14,
      user_reset_out_reg_0 => xdma_0_tx_mux_i_n_16
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_pcie2_to_pcie3_wrapper is
  port (
    user_clk_out : out STD_LOGIC;
    in0 : out STD_LOGIC;
    m_axis_rx_tkeep_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Integrated_bloc_reset_o : out STD_LOGIC;
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_lnk_up : out STD_LOGIC;
    s_axis_tx_tready_o : out STD_LOGIC;
    m_axis_rx_tdata_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tlast_o : out STD_LOGIC;
    m_axis_rx_tvalid_o : out STD_LOGIC;
    m_axis_rx_tuser_o : out STD_LOGIC_VECTOR ( 13 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_dcommand : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_to_turnoff_o : out STD_LOGIC;
    cfg_bus_number_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pcie_dma_in\\.cfg_phy_link_down\ : out STD_LOGIC;
    \pcie_dma_in\\.pcie_rq_seq_num0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \pcie_dma_in\\.pcie_rq_seq_num_vld0\ : out STD_LOGIC;
    \m_axis_cc\\.tready\ : out STD_LOGIC;
    \m_axis_rq\\.tready\ : out STD_LOGIC;
    \s_axis_rc\\.tuser\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \s_axis_rc\\.tkeep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \s_axis_rc\\.tlast\ : out STD_LOGIC;
    \s_axis_rc\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_cq\\.tlast\ : out STD_LOGIC;
    \s_axis_cq\\.tdata\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \s_axis_cq\\.tuser\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \s_axis_cq\\.tvalid\ : out STD_LOGIC;
    \pcie_dma_in\\.cfg_interrupt_sent\ : out STD_LOGIC;
    \pcie_dma_in\\.cfg_interrupt_msi_sent\ : out STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rdy_reg1_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pcie_dma_out\\.pcie_cq_np_req\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pcie_dma_out\\.cfg_fc_sel\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    clk_msien_reg : in STD_LOGIC_VECTOR ( 31 downto 0 );
    clk_msien_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    clk_msien_reg_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
    clk_msien_reg_2 : in STD_LOGIC;
    clk_msien_reg_3 : in STD_LOGIC;
    clk_msien_reg_4 : in STD_LOGIC;
    rdy_reg1_reg_0 : in STD_LOGIC;
    reset_n_reg2_reg : in STD_LOGIC;
    \m_axis_cc\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \pcie_dma_out\\.cfg_interrupt_int\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_axis_rq\\.tdata\ : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \m_axis_rq\\.tuser\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
    \m_axis_cc\\.tlast\ : in STD_LOGIC;
    \m_axis_cc\\.tvalid\ : in STD_LOGIC;
    \m_axis_rq\\.tvalid\ : in STD_LOGIC;
    \m_axis_rq\\.tlast\ : in STD_LOGIC;
    \s_axis_rc\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \s_axis_cq\\.tready\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pcie_dma_out\\.cfg_interrupt_msi_int\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_pcie2_to_pcie3_wrapper : entity is "xdma_0_pcie2_to_pcie3_wrapper";
end xdma_0_xdma_0_pcie2_to_pcie3_wrapper;

architecture STRUCTURE of xdma_0_xdma_0_pcie2_to_pcie3_wrapper is
  signal \^integrated_bloc_reset_o\ : STD_LOGIC;
  signal \^cfg_bus_number_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^cfg_device_number_o\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^cfg_function_number_o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cfg_interrupt_mmenable\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cfg_interrupt_msienable\ : STD_LOGIC;
  signal g2ip_cfg_interrupt : STD_LOGIC;
  signal g2ip_cfg_interrupt_assert : STD_LOGIC;
  signal g2ip_cfg_interrupt_di : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal g2ip_cfg_interrupt_rdy : STD_LOGIC;
  signal \^in0\ : STD_LOGIC;
  signal \^m_axis_rx_tdata_o\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \^m_axis_rx_tkeep_o\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^m_axis_rx_tlast_o\ : STD_LOGIC;
  signal m_axis_rx_tready : STD_LOGIC;
  signal \^m_axis_rx_tuser_o\ : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal \^m_axis_rx_tvalid_o\ : STD_LOGIC;
  signal pcie2_ip_i_n_235 : STD_LOGIC;
  signal pcie2_ip_i_n_414 : STD_LOGIC;
  signal s_axis_tx_tdata : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal s_axis_tx_tkeep : STD_LOGIC_VECTOR ( 7 to 7 );
  signal s_axis_tx_tlast : STD_LOGIC;
  signal \^s_axis_tx_tready_o\ : STD_LOGIC;
  signal s_axis_tx_tvalid : STD_LOGIC;
  signal \^user_clk_out\ : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_ecrc_check_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_ecrc_gen_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_bridge_serr_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_err_aer_headerlog_set_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_err_cpl_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_interrupt_msixenable_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_interrupt_msixfm_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_assert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_assert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_assert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_assert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_deassert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_deassert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_deassert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_deassert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_err_cor_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_err_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_err_non_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_pm_as_nak_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_pm_pme_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_pme_to_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_msg_received_setslotpowerlimit_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_pmcsr_pme_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_pmcsr_pme_status_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_received_func_lvl_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_root_control_pme_int_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_root_control_syserr_corr_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_root_control_syserr_fatal_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_directed_change_done_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_link_gen2_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_link_partner_gen2_supported_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_link_upcfg_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_received_hot_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_pl_sel_lnk_rate_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_tx_cfg_req_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_tx_err_drop_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_user_app_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_pcie2_ip_i_cfg_command_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_dcommand2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_dstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_interrupt_do_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_pcie2_ip_i_cfg_lcommand_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_lstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_msg_data_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_pcie_link_state_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_pcie2_ip_i_cfg_pmcsr_powerstate_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_pcie2_ip_i_cfg_status_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_pcie2_ip_i_cfg_vc_tcvc_map_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_pcie2_ip_i_fc_cpld_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_pcie2_ip_i_fc_cplh_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_pcie2_ip_i_fc_npd_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_pcie2_ip_i_fc_pd_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_pcie2_ip_i_fc_ph_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_pcie2_ip_i_m_axis_rx_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 9 );
  signal NLW_pcie2_ip_i_pl_initial_link_width_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_pcie2_ip_i_pl_lane_reversal_mode_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_pcie2_ip_i_pl_ltssm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_pcie2_ip_i_pl_rx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_pcie2_ip_i_pl_sel_lnk_width_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_pcie2_ip_i_pl_tx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_pcie2_ip_i_tx_buf_av_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pcie2_ip_i : label is "xdma_0_pcie2_ip,xdma_0_pcie2_ip_pcie2_top,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of pcie2_ip_i : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of pcie2_ip_i : label is "xdma_0_pcie2_ip_pcie2_top,Vivado 2020.2";
begin
  Integrated_bloc_reset_o <= \^integrated_bloc_reset_o\;
  cfg_bus_number_o(7 downto 0) <= \^cfg_bus_number_o\(7 downto 0);
  cfg_device_number_o(4 downto 0) <= \^cfg_device_number_o\(4 downto 0);
  cfg_function_number_o(2 downto 0) <= \^cfg_function_number_o\(2 downto 0);
  cfg_interrupt_mmenable(2 downto 0) <= \^cfg_interrupt_mmenable\(2 downto 0);
  cfg_interrupt_msienable <= \^cfg_interrupt_msienable\;
  in0 <= \^in0\;
  m_axis_rx_tdata_o(63 downto 0) <= \^m_axis_rx_tdata_o\(63 downto 0);
  m_axis_rx_tkeep_o(3 downto 0) <= \^m_axis_rx_tkeep_o\(3 downto 0);
  m_axis_rx_tlast_o <= \^m_axis_rx_tlast_o\;
  m_axis_rx_tuser_o(13 downto 0) <= \^m_axis_rx_tuser_o\(13 downto 0);
  m_axis_rx_tvalid_o <= \^m_axis_rx_tvalid_o\;
  s_axis_tx_tready_o <= \^s_axis_tx_tready_o\;
  user_clk_out <= \^user_clk_out\;
pcie2_ip_i: entity work.xdma_0_xdma_0_pcie2_ip
     port map (
      cfg_aer_ecrc_check_en => NLW_pcie2_ip_i_cfg_aer_ecrc_check_en_UNCONNECTED,
      cfg_aer_ecrc_gen_en => NLW_pcie2_ip_i_cfg_aer_ecrc_gen_en_UNCONNECTED,
      cfg_aer_interrupt_msgnum(4 downto 0) => B"00000",
      cfg_aer_rooterr_corr_err_received => NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_received_UNCONNECTED,
      cfg_aer_rooterr_corr_err_reporting_en => NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED,
      cfg_aer_rooterr_fatal_err_received => NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_received_UNCONNECTED,
      cfg_aer_rooterr_fatal_err_reporting_en => NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED,
      cfg_aer_rooterr_non_fatal_err_received => NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED,
      cfg_aer_rooterr_non_fatal_err_reporting_en => NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED,
      cfg_bridge_serr_en => NLW_pcie2_ip_i_cfg_bridge_serr_en_UNCONNECTED,
      cfg_bus_number(7 downto 0) => \^cfg_bus_number_o\(7 downto 0),
      cfg_command(15 downto 3) => NLW_pcie2_ip_i_cfg_command_UNCONNECTED(15 downto 3),
      cfg_command(2) => pcie2_ip_i_n_235,
      cfg_command(1 downto 0) => NLW_pcie2_ip_i_cfg_command_UNCONNECTED(1 downto 0),
      cfg_dcommand(15) => NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED(15),
      cfg_dcommand(14 downto 12) => cfg_dcommand(5 downto 3),
      cfg_dcommand(11 downto 8) => NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED(11 downto 8),
      cfg_dcommand(7 downto 5) => cfg_dcommand(2 downto 0),
      cfg_dcommand(4 downto 0) => NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED(4 downto 0),
      cfg_dcommand2(15 downto 0) => NLW_pcie2_ip_i_cfg_dcommand2_UNCONNECTED(15 downto 0),
      cfg_device_number(4 downto 0) => \^cfg_device_number_o\(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => B"00000000",
      cfg_ds_device_number(4 downto 0) => B"00000",
      cfg_ds_function_number(2 downto 0) => B"000",
      cfg_dsn(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      cfg_dstatus(15 downto 0) => NLW_pcie2_ip_i_cfg_dstatus_UNCONNECTED(15 downto 0),
      cfg_err_acs => '0',
      cfg_err_aer_headerlog(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      cfg_err_aer_headerlog_set => NLW_pcie2_ip_i_cfg_err_aer_headerlog_set_UNCONNECTED,
      cfg_err_atomic_egress_blocked => '0',
      cfg_err_cor => '0',
      cfg_err_cpl_abort => '0',
      cfg_err_cpl_rdy => NLW_pcie2_ip_i_cfg_err_cpl_rdy_UNCONNECTED,
      cfg_err_cpl_timeout => '0',
      cfg_err_cpl_unexpect => '0',
      cfg_err_ecrc => '0',
      cfg_err_internal_cor => '0',
      cfg_err_internal_uncor => '0',
      cfg_err_locked => '0',
      cfg_err_malformed => '0',
      cfg_err_mc_blocked => '0',
      cfg_err_norecovery => '0',
      cfg_err_poisoned => '0',
      cfg_err_posted => '0',
      cfg_err_tlp_cpl_header(47 downto 0) => B"000000000000000000000000000000000000000000000000",
      cfg_err_ur => '0',
      cfg_function_number(2 downto 0) => \^cfg_function_number_o\(2 downto 0),
      cfg_interrupt => g2ip_cfg_interrupt,
      cfg_interrupt_assert => g2ip_cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 5) => B"000",
      cfg_interrupt_di(4 downto 0) => g2ip_cfg_interrupt_di(4 downto 0),
      cfg_interrupt_do(7 downto 0) => NLW_pcie2_ip_i_cfg_interrupt_do_UNCONNECTED(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => \^cfg_interrupt_mmenable\(2 downto 0),
      cfg_interrupt_msienable => \^cfg_interrupt_msienable\,
      cfg_interrupt_msixenable => NLW_pcie2_ip_i_cfg_interrupt_msixenable_UNCONNECTED,
      cfg_interrupt_msixfm => NLW_pcie2_ip_i_cfg_interrupt_msixfm_UNCONNECTED,
      cfg_interrupt_rdy => g2ip_cfg_interrupt_rdy,
      cfg_interrupt_stat => '0',
      cfg_lcommand(15 downto 0) => NLW_pcie2_ip_i_cfg_lcommand_UNCONNECTED(15 downto 0),
      cfg_lstatus(15 downto 0) => NLW_pcie2_ip_i_cfg_lstatus_UNCONNECTED(15 downto 0),
      cfg_mgmt_byte_en(3 downto 0) => clk_msien_reg_0(3 downto 0),
      cfg_mgmt_di(31 downto 0) => clk_msien_reg(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => clk_msien_reg_1(9 downto 0),
      cfg_mgmt_rd_en => clk_msien_reg_3,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => clk_msien_reg_2,
      cfg_mgmt_wr_readonly => clk_msien_reg_4,
      cfg_mgmt_wr_rw1c_as_rw => '0',
      cfg_msg_data(15 downto 0) => NLW_pcie2_ip_i_cfg_msg_data_UNCONNECTED(15 downto 0),
      cfg_msg_received => NLW_pcie2_ip_i_cfg_msg_received_UNCONNECTED,
      cfg_msg_received_assert_int_a => NLW_pcie2_ip_i_cfg_msg_received_assert_int_a_UNCONNECTED,
      cfg_msg_received_assert_int_b => NLW_pcie2_ip_i_cfg_msg_received_assert_int_b_UNCONNECTED,
      cfg_msg_received_assert_int_c => NLW_pcie2_ip_i_cfg_msg_received_assert_int_c_UNCONNECTED,
      cfg_msg_received_assert_int_d => NLW_pcie2_ip_i_cfg_msg_received_assert_int_d_UNCONNECTED,
      cfg_msg_received_deassert_int_a => NLW_pcie2_ip_i_cfg_msg_received_deassert_int_a_UNCONNECTED,
      cfg_msg_received_deassert_int_b => NLW_pcie2_ip_i_cfg_msg_received_deassert_int_b_UNCONNECTED,
      cfg_msg_received_deassert_int_c => NLW_pcie2_ip_i_cfg_msg_received_deassert_int_c_UNCONNECTED,
      cfg_msg_received_deassert_int_d => NLW_pcie2_ip_i_cfg_msg_received_deassert_int_d_UNCONNECTED,
      cfg_msg_received_err_cor => NLW_pcie2_ip_i_cfg_msg_received_err_cor_UNCONNECTED,
      cfg_msg_received_err_fatal => NLW_pcie2_ip_i_cfg_msg_received_err_fatal_UNCONNECTED,
      cfg_msg_received_err_non_fatal => NLW_pcie2_ip_i_cfg_msg_received_err_non_fatal_UNCONNECTED,
      cfg_msg_received_pm_as_nak => NLW_pcie2_ip_i_cfg_msg_received_pm_as_nak_UNCONNECTED,
      cfg_msg_received_pm_pme => NLW_pcie2_ip_i_cfg_msg_received_pm_pme_UNCONNECTED,
      cfg_msg_received_pme_to_ack => NLW_pcie2_ip_i_cfg_msg_received_pme_to_ack_UNCONNECTED,
      cfg_msg_received_setslotpowerlimit => NLW_pcie2_ip_i_cfg_msg_received_setslotpowerlimit_UNCONNECTED,
      cfg_pcie_link_state(2 downto 0) => NLW_pcie2_ip_i_cfg_pcie_link_state_UNCONNECTED(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => B"00000",
      cfg_pm_force_state(1 downto 0) => B"00",
      cfg_pm_force_state_en => '0',
      cfg_pm_halt_aspm_l0s => '0',
      cfg_pm_halt_aspm_l1 => '0',
      cfg_pm_send_pme_to => '0',
      cfg_pm_wake => '0',
      cfg_pmcsr_pme_en => NLW_pcie2_ip_i_cfg_pmcsr_pme_en_UNCONNECTED,
      cfg_pmcsr_pme_status => NLW_pcie2_ip_i_cfg_pmcsr_pme_status_UNCONNECTED,
      cfg_pmcsr_powerstate(1 downto 0) => NLW_pcie2_ip_i_cfg_pmcsr_powerstate_UNCONNECTED(1 downto 0),
      cfg_received_func_lvl_rst => NLW_pcie2_ip_i_cfg_received_func_lvl_rst_UNCONNECTED,
      cfg_root_control_pme_int_en => NLW_pcie2_ip_i_cfg_root_control_pme_int_en_UNCONNECTED,
      cfg_root_control_syserr_corr_err_en => NLW_pcie2_ip_i_cfg_root_control_syserr_corr_err_en_UNCONNECTED,
      cfg_root_control_syserr_fatal_err_en => NLW_pcie2_ip_i_cfg_root_control_syserr_fatal_err_en_UNCONNECTED,
      cfg_root_control_syserr_non_fatal_err_en => NLW_pcie2_ip_i_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED,
      cfg_slot_control_electromech_il_ctl_pulse => NLW_pcie2_ip_i_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED,
      cfg_status(15 downto 0) => NLW_pcie2_ip_i_cfg_status_UNCONNECTED(15 downto 0),
      cfg_to_turnoff => cfg_to_turnoff_o,
      cfg_trn_pending => '0',
      cfg_turnoff_ok => '0',
      cfg_vc_tcvc_map(6 downto 0) => NLW_pcie2_ip_i_cfg_vc_tcvc_map_UNCONNECTED(6 downto 0),
      fc_cpld(11 downto 0) => NLW_pcie2_ip_i_fc_cpld_UNCONNECTED(11 downto 0),
      fc_cplh(7 downto 0) => NLW_pcie2_ip_i_fc_cplh_UNCONNECTED(7 downto 0),
      fc_npd(11 downto 0) => NLW_pcie2_ip_i_fc_npd_UNCONNECTED(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => NLW_pcie2_ip_i_fc_pd_UNCONNECTED(11 downto 0),
      fc_ph(7 downto 0) => NLW_pcie2_ip_i_fc_ph_UNCONNECTED(7 downto 0),
      fc_sel(2 downto 1) => B"10",
      fc_sel(0) => \pcie_dma_out\\.cfg_fc_sel\(0),
      m_axis_rx_tdata(63 downto 0) => \^m_axis_rx_tdata_o\(63 downto 0),
      m_axis_rx_tkeep(7 downto 4) => \^m_axis_rx_tkeep_o\(3 downto 0),
      m_axis_rx_tkeep(3 downto 0) => NLW_pcie2_ip_i_m_axis_rx_tkeep_UNCONNECTED(3 downto 0),
      m_axis_rx_tlast => \^m_axis_rx_tlast_o\,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21) => \^m_axis_rx_tuser_o\(13),
      m_axis_rx_tuser(20) => NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED(20),
      m_axis_rx_tuser(19 downto 17) => \^m_axis_rx_tuser_o\(12 downto 10),
      m_axis_rx_tuser(16 downto 15) => NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED(16 downto 15),
      m_axis_rx_tuser(14) => \^m_axis_rx_tuser_o\(9),
      m_axis_rx_tuser(13 downto 9) => NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED(13 downto 9),
      m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser_o\(8 downto 0),
      m_axis_rx_tvalid => \^m_axis_rx_tvalid_o\,
      pci_exp_rxn(1 downto 0) => rdy_reg1_reg(1 downto 0),
      pci_exp_rxp(1 downto 0) => \out\(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pl_directed_change_done => NLW_pcie2_ip_i_pl_directed_change_done_UNCONNECTED,
      pl_directed_link_auton => '0',
      pl_directed_link_change(1 downto 0) => B"00",
      pl_directed_link_speed => '0',
      pl_directed_link_width(1 downto 0) => B"00",
      pl_downstream_deemph_source => '0',
      pl_initial_link_width(2 downto 0) => NLW_pcie2_ip_i_pl_initial_link_width_UNCONNECTED(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => NLW_pcie2_ip_i_pl_lane_reversal_mode_UNCONNECTED(1 downto 0),
      pl_link_gen2_cap => NLW_pcie2_ip_i_pl_link_gen2_cap_UNCONNECTED,
      pl_link_partner_gen2_supported => NLW_pcie2_ip_i_pl_link_partner_gen2_supported_UNCONNECTED,
      pl_link_upcfg_cap => NLW_pcie2_ip_i_pl_link_upcfg_cap_UNCONNECTED,
      pl_ltssm_state(5 downto 0) => NLW_pcie2_ip_i_pl_ltssm_state_UNCONNECTED(5 downto 0),
      pl_phy_lnk_up => pcie2_ip_i_n_414,
      pl_received_hot_rst => NLW_pcie2_ip_i_pl_received_hot_rst_UNCONNECTED,
      pl_rx_pm_state(1 downto 0) => NLW_pcie2_ip_i_pl_rx_pm_state_UNCONNECTED(1 downto 0),
      pl_sel_lnk_rate => NLW_pcie2_ip_i_pl_sel_lnk_rate_UNCONNECTED,
      pl_sel_lnk_width(1 downto 0) => NLW_pcie2_ip_i_pl_sel_lnk_width_UNCONNECTED(1 downto 0),
      pl_transmit_hot_rst => '0',
      pl_tx_pm_state(2 downto 0) => NLW_pcie2_ip_i_pl_tx_pm_state_UNCONNECTED(2 downto 0),
      pl_upstream_prefer_deemph => '0',
      rx_np_ok => '0',
      rx_np_req => \pcie_dma_out\\.pcie_cq_np_req\(0),
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(7) => s_axis_tx_tkeep(7),
      s_axis_tx_tkeep(6 downto 0) => B"0000000",
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => \^s_axis_tx_tready_o\,
      s_axis_tx_tuser(3 downto 0) => B"0000",
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_clk => rdy_reg1_reg_0,
      sys_rst_n => reset_n_reg2_reg,
      tx_buf_av(5 downto 0) => NLW_pcie2_ip_i_tx_buf_av_UNCONNECTED(5 downto 0),
      tx_cfg_gnt => '1',
      tx_cfg_req => NLW_pcie2_ip_i_tx_cfg_req_UNCONNECTED,
      tx_err_drop => NLW_pcie2_ip_i_tx_err_drop_UNCONNECTED,
      user_app_rdy => NLW_pcie2_ip_i_user_app_rdy_UNCONNECTED,
      user_clk_out => \^user_clk_out\,
      user_lnk_up => user_lnk_up,
      user_reset_out => \^integrated_bloc_reset_o\
    );
udma_wrapper_i_147: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pcie2_ip_i_n_414,
      O => \pcie_dma_in\\.cfg_phy_link_down\
    );
xdma_0_axi_stream_intf_i: entity work.xdma_0_xdma_0_axi_stream_intf
     port map (
      D(63 downto 0) => \^m_axis_rx_tdata_o\(63 downto 0),
      E(0) => \^in0\,
      \FSM_sequential_tx_64.state_reg[0]\ => \s_axis_cq\\.tlast\,
      Q(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      SR(0) => \^integrated_bloc_reset_o\,
      cfg_bus_number_o(7 downto 0) => \^cfg_bus_number_o\(7 downto 0),
      cfg_device_number_o(4 downto 0) => \^cfg_device_number_o\(4 downto 0),
      cfg_function_number_o(2 downto 0) => \^cfg_function_number_o\(2 downto 0),
      \m_axis_cc\\.tdata\(63 downto 0) => \m_axis_cc\\.tdata\(63 downto 0),
      \m_axis_cc\\.tlast\ => \m_axis_cc\\.tlast\,
      \m_axis_cc\\.tready\ => \m_axis_cc\\.tready\,
      \m_axis_cc\\.tvalid\ => \m_axis_cc\\.tvalid\,
      \m_axis_rq\\.tdata\(63 downto 0) => \m_axis_rq\\.tdata\(63 downto 0),
      \m_axis_rq\\.tlast\ => \m_axis_rq\\.tlast\,
      \m_axis_rq\\.tready\ => \m_axis_rq\\.tready\,
      \m_axis_rq\\.tuser\(11 downto 0) => \m_axis_rq\\.tuser\(11 downto 0),
      \m_axis_rq\\.tvalid\ => \m_axis_rq\\.tvalid\,
      m_axis_rx_tkeep_o(3 downto 0) => \^m_axis_rx_tkeep_o\(3 downto 0),
      m_axis_rx_tlast => \^m_axis_rx_tlast_o\,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser_o(13 downto 0) => \^m_axis_rx_tuser_o\(13 downto 0),
      m_axis_rx_tvalid => \^m_axis_rx_tvalid_o\,
      \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0) => \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0),
      \pcie_dma_in\\.pcie_rq_seq_num_vld0\ => \pcie_dma_in\\.pcie_rq_seq_num_vld0\,
      \s_axis_cq\\.tdata\(63 downto 0) => \s_axis_cq\\.tdata\(63 downto 0),
      \s_axis_cq\\.tready\(0) => \s_axis_cq\\.tready\(0),
      \s_axis_cq\\.tuser\(4 downto 0) => \s_axis_cq\\.tuser\(4 downto 0),
      \s_axis_cq\\.tvalid\ => \s_axis_cq\\.tvalid\,
      \s_axis_rc\\.tdata\(63 downto 0) => \s_axis_rc\\.tdata\(63 downto 0),
      \s_axis_rc\\.tkeep\(1 downto 0) => \s_axis_rc\\.tkeep\(1 downto 0),
      \s_axis_rc\\.tlast\ => \s_axis_rc\\.tlast\,
      \s_axis_rc\\.tready\(0) => \s_axis_rc\\.tready\(0),
      \s_axis_rc\\.tuser\(3 downto 0) => \s_axis_rc\\.tuser\(3 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(7),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => \^s_axis_tx_tready_o\,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      user_clk_out => \^user_clk_out\
    );
xdma_0_cfg_sideband_i: entity work.xdma_0_xdma_0_cfg_sideband
     port map (
      E(0) => \^in0\,
      Q(4 downto 0) => g2ip_cfg_interrupt_di(4 downto 0),
      cfg_command(0) => pcie2_ip_i_n_235,
      cfg_interrupt => g2ip_cfg_interrupt,
      cfg_interrupt_assert => g2ip_cfg_interrupt_assert,
      cfg_interrupt_mmenable(2 downto 0) => \^cfg_interrupt_mmenable\(2 downto 0),
      cfg_interrupt_msienable => \^cfg_interrupt_msienable\,
      cfg_interrupt_rdy => g2ip_cfg_interrupt_rdy,
      \pcie_dma_in\\.cfg_interrupt_msi_sent\ => \pcie_dma_in\\.cfg_interrupt_msi_sent\,
      \pcie_dma_in\\.cfg_interrupt_sent\ => \pcie_dma_in\\.cfg_interrupt_sent\,
      \pcie_dma_out\\.cfg_interrupt_int\(0) => \pcie_dma_out\\.cfg_interrupt_int\(0),
      \pcie_dma_out\\.cfg_interrupt_msi_int\(31 downto 0) => \pcie_dma_out\\.cfg_interrupt_msi_int\(31 downto 0),
      user_clk_out => \^user_clk_out\,
      user_reset_out => \^integrated_bloc_reset_o\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0_xdma_0_core_top is
  port (
    sys_clk : in STD_LOGIC;
    sys_clk_ce_out : out STD_LOGIC;
    sys_clk_gt : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    dma_bridge_resetn : in STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    cfg_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    free_run_clock : in STD_LOGIC;
    gt_drp_clk : out STD_LOGIC;
    axi_aclk : out STD_LOGIC;
    axi_aresetn : out STD_LOGIC;
    axi_ctl_aclk : in STD_LOGIC;
    axi_ctl_aresetn : out STD_LOGIC;
    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
    usr_irq_function_number : in STD_LOGIC_VECTOR ( 1 downto 0 );
    msi_enable : out STD_LOGIC;
    msix_enable : out STD_LOGIC;
    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_awready : in STD_LOGIC;
    m_axi_awlock : out STD_LOGIC;
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_wuser : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_wready : in STD_LOGIC;
    m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bvalid : in STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_arready : in STD_LOGIC;
    m_axi_arlock : out STD_LOGIC;
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_ruser : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rlast : in STD_LOGIC;
    m_axi_rvalid : in STD_LOGIC;
    m_axi_rready : out STD_LOGIC;
    m_axib_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_awuser : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awvalid : out STD_LOGIC;
    m_axib_awready : in STD_LOGIC;
    m_axib_awlock : out STD_LOGIC;
    m_axib_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_wuser : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_wlast : out STD_LOGIC;
    m_axib_wvalid : out STD_LOGIC;
    m_axib_wready : in STD_LOGIC;
    m_axib_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_bvalid : in STD_LOGIC;
    m_axib_bready : out STD_LOGIC;
    m_axib_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_aruser : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arvalid : out STD_LOGIC;
    m_axib_arready : in STD_LOGIC;
    m_axib_arlock : out STD_LOGIC;
    m_axib_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_ruser : in STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_rlast : in STD_LOGIC;
    m_axib_rvalid : in STD_LOGIC;
    m_axib_rready : out STD_LOGIC;
    s_axib_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axib_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axib_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axib_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axib_awvalid : in STD_LOGIC;
    s_axib_awready : out STD_LOGIC;
    s_axib_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axib_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axib_wlast : in STD_LOGIC;
    s_axib_wvalid : in STD_LOGIC;
    s_axib_wready : out STD_LOGIC;
    s_axib_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axib_bvalid : out STD_LOGIC;
    s_axib_bready : in STD_LOGIC;
    s_axib_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axib_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axib_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axib_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axib_arvalid : in STD_LOGIC;
    s_axib_arready : out STD_LOGIC;
    s_axib_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axib_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axib_rlast : out STD_LOGIC;
    s_axib_rvalid : out STD_LOGIC;
    s_axib_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axib_wuser : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axib_ruser : out STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axib_rready : in STD_LOGIC;
    interrupt_out : out STD_LOGIC;
    interrupt_out_msi_vec0to31 : out STD_LOGIC;
    interrupt_out_msi_vec32to63 : out STD_LOGIC;
    interrupt_out_msix_0 : out STD_LOGIC;
    interrupt_out_msix_1 : out STD_LOGIC;
    interrupt_out_msix_2 : out STD_LOGIC;
    interrupt_out_msix_3 : out STD_LOGIC;
    s_axis_c2h_tdata_0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_c2h_tlast_0 : in STD_LOGIC;
    s_axis_c2h_tuser_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tkeep_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tvalid_0 : in STD_LOGIC;
    s_axis_c2h_tready_0 : out STD_LOGIC;
    m_axis_h2c_tdata_0 : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_h2c_tlast_0 : out STD_LOGIC;
    m_axis_h2c_tuser_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tkeep_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tvalid_0 : out STD_LOGIC;
    m_axis_h2c_tready_0 : in STD_LOGIC;
    s_axis_c2h_tdata_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_c2h_tlast_1 : in STD_LOGIC;
    s_axis_c2h_tuser_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tkeep_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tvalid_1 : in STD_LOGIC;
    s_axis_c2h_tready_1 : out STD_LOGIC;
    m_axis_h2c_tdata_1 : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_h2c_tlast_1 : out STD_LOGIC;
    m_axis_h2c_tuser_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tkeep_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tvalid_1 : out STD_LOGIC;
    m_axis_h2c_tready_1 : in STD_LOGIC;
    s_axis_c2h_tdata_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_c2h_tlast_2 : in STD_LOGIC;
    s_axis_c2h_tuser_2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tkeep_2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tvalid_2 : in STD_LOGIC;
    s_axis_c2h_tready_2 : out STD_LOGIC;
    m_axis_h2c_tdata_2 : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_h2c_tlast_2 : out STD_LOGIC;
    m_axis_h2c_tuser_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tkeep_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tvalid_2 : out STD_LOGIC;
    m_axis_h2c_tready_2 : in STD_LOGIC;
    s_axis_c2h_tdata_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_c2h_tlast_3 : in STD_LOGIC;
    s_axis_c2h_tuser_3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tkeep_3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_c2h_tvalid_3 : in STD_LOGIC;
    s_axis_c2h_tready_3 : out STD_LOGIC;
    m_axis_h2c_tdata_3 : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_h2c_tlast_3 : out STD_LOGIC;
    m_axis_h2c_tuser_3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tkeep_3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_h2c_tvalid_3 : out STD_LOGIC;
    m_axis_h2c_tready_3 : in STD_LOGIC;
    m_axil_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axil_awuser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axil_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axil_awvalid : out STD_LOGIC;
    m_axil_awready : in STD_LOGIC;
    m_axil_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axil_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axil_wvalid : out STD_LOGIC;
    m_axil_wready : in STD_LOGIC;
    m_axil_bvalid : in STD_LOGIC;
    m_axil_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axil_bready : out STD_LOGIC;
    m_axil_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axil_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 );
    m_axil_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axil_arvalid : out STD_LOGIC;
    m_axil_arready : in STD_LOGIC;
    m_axil_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axil_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axil_rvalid : in STD_LOGIC;
    m_axil_rready : out STD_LOGIC;
    s_axil_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axil_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axil_awvalid : in STD_LOGIC;
    s_axil_awready : out STD_LOGIC;
    s_axil_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axil_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axil_wvalid : in STD_LOGIC;
    s_axil_wready : out STD_LOGIC;
    s_axil_bvalid : out STD_LOGIC;
    s_axil_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axil_bready : in STD_LOGIC;
    s_axil_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axil_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axil_arvalid : in STD_LOGIC;
    s_axil_arready : out STD_LOGIC;
    s_axil_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axil_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axil_rvalid : out STD_LOGIC;
    s_axil_rready : in STD_LOGIC;
    c2h_dsc_byp_ready_0 : out STD_LOGIC;
    c2h_dsc_byp_src_addr_0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_dst_addr_0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_len_0 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    c2h_dsc_byp_ctl_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    c2h_dsc_byp_load_0 : in STD_LOGIC;
    c2h_dsc_byp_ready_1 : out STD_LOGIC;
    c2h_dsc_byp_src_addr_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_dst_addr_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_len_1 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    c2h_dsc_byp_ctl_1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    c2h_dsc_byp_load_1 : in STD_LOGIC;
    c2h_dsc_byp_ready_2 : out STD_LOGIC;
    c2h_dsc_byp_src_addr_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_dst_addr_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_len_2 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    c2h_dsc_byp_ctl_2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    c2h_dsc_byp_load_2 : in STD_LOGIC;
    c2h_dsc_byp_ready_3 : out STD_LOGIC;
    c2h_dsc_byp_src_addr_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_dst_addr_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    c2h_dsc_byp_len_3 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    c2h_dsc_byp_ctl_3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    c2h_dsc_byp_load_3 : in STD_LOGIC;
    h2c_dsc_byp_ready_0 : out STD_LOGIC;
    h2c_dsc_byp_src_addr_0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_dst_addr_0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_len_0 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    h2c_dsc_byp_ctl_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    h2c_dsc_byp_load_0 : in STD_LOGIC;
    h2c_dsc_byp_ready_1 : out STD_LOGIC;
    h2c_dsc_byp_src_addr_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_dst_addr_1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_len_1 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    h2c_dsc_byp_ctl_1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    h2c_dsc_byp_load_1 : in STD_LOGIC;
    h2c_dsc_byp_ready_2 : out STD_LOGIC;
    h2c_dsc_byp_src_addr_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_dst_addr_2 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_len_2 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    h2c_dsc_byp_ctl_2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    h2c_dsc_byp_load_2 : in STD_LOGIC;
    h2c_dsc_byp_ready_3 : out STD_LOGIC;
    h2c_dsc_byp_src_addr_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_dst_addr_3 : in STD_LOGIC_VECTOR ( 63 downto 0 );
    h2c_dsc_byp_len_3 : in STD_LOGIC_VECTOR ( 27 downto 0 );
    h2c_dsc_byp_ctl_3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    h2c_dsc_byp_load_3 : in STD_LOGIC;
    c2h_sts_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    h2c_sts_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    c2h_sts_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    h2c_sts_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    c2h_sts_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    h2c_sts_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    c2h_sts_3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    h2c_sts_3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_ctl_in_tx0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_debug_ctl_in_tx1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_debug_ctl_in_rx0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_debug_ctl_in_rx1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_debug_ltssm_rec_spd_1 : in STD_LOGIC;
    pipe_debug_ltssm_pol_act : in STD_LOGIC;
    pipe_debug_ctl_vec4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_debug_mux_ctl : in STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_debug_debug_out_128_0 : out STD_LOGIC_VECTOR ( 127 downto 0 );
    pipe_debug_debug_out_ext_16_0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_debug_debug_out_128_1 : out STD_LOGIC_VECTOR ( 127 downto 0 );
    pipe_debug_debug_out_ext_16_1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_debug_debug_out_128_2 : out STD_LOGIC_VECTOR ( 127 downto 0 );
    pipe_debug_debug_out_ext_16_2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_debug_debug_out_128_3 : out STD_LOGIC_VECTOR ( 127 downto 0 );
    pipe_debug_debug_out_ext_16_3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_debug_inject_tx_status : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_inject_rx_status : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_subsys_vend_id : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dev_id_pf0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_rev_id_pf0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_subsys_id_pf0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dev_id_pf1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_rev_id_pf1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_subsys_id_pf1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dev_id_pf2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_rev_id_pf2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_subsys_id_pf2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dev_id_pf3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_rev_id_pf3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_subsys_id_pf3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    common_commands_in : in STD_LOGIC_VECTOR ( 25 downto 0 );
    pipe_rx_0_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_1_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_2_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_3_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_4_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_5_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_6_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_7_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_8_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_9_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_10_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_11_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_12_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_13_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_14_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_rx_15_sigs : in STD_LOGIC_VECTOR ( 83 downto 0 );
    common_commands_out : out STD_LOGIC_VECTOR ( 25 downto 0 );
    pipe_tx_0_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_1_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_2_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_3_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_4_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_5_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_6_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_7_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_8_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_9_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_10_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_11_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_12_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_13_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_14_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    pipe_tx_15_sigs : out STD_LOGIC_VECTOR ( 83 downto 0 );
    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
    cfg_mgmt_write : in STD_LOGIC;
    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_read : in STD_LOGIC;
    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_read_write_done : out STD_LOGIC;
    cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC;
    pipe_txprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_txprbsforceerr : in STD_LOGIC;
    pipe_rxprbscntreset : in STD_LOGIC;
    pipe_loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    pipe_sync_fsm_tx : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_drp_fsm : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_rst_idle : out STD_LOGIC;
    pipe_qrst_idle : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 29 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qpll_lock : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxpmaresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxsyncdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt_pcieuserratedone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_loopback : in STD_LOGIC_VECTOR ( 5 downto 0 );
    gt_txprbsforceerr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txprbssel : in STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rxprbssel : in STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rxprbscntreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_dmonitorclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_dmonfiforeset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txelecidle : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxpmaresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxsyncdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_dmonitorout : out STD_LOGIC_VECTOR ( 33 downto 0 );
    gt_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_phystatus : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxcdrlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_pcierateidle : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_pcieuserratestart : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_gtpowergood : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_cplllock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxoutclk : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxrecclkout : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_qpll1lock : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    gt_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    gt_bufgtdiv : out STD_LOGIC_VECTOR ( 8 downto 0 );
    phy_txeq_ctrl : out STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_txeq_preset : out STD_LOGIC_VECTOR ( 7 downto 0 );
    phy_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    phy_txeq_fsm : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_rxeq_fsm : out STD_LOGIC_VECTOR ( 5 downto 0 );
    phy_rst_idle : out STD_LOGIC;
    phy_rrst_n : out STD_LOGIC;
    phy_prst_n : out STD_LOGIC;
    ext_ch_gt_drpclk : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    mcap_design_switch : out STD_LOGIC;
    cap_req : out STD_LOGIC;
    cap_gnt : in STD_LOGIC;
    cap_rel : in STD_LOGIC;
    mcap_eos_in : in STD_LOGIC;
    startup_cfgclk : out STD_LOGIC;
    startup_cfgmclk : out STD_LOGIC;
    startup_di : out STD_LOGIC_VECTOR ( 3 downto 0 );
    startup_eos : out STD_LOGIC;
    startup_preq : out STD_LOGIC;
    startup_do : in STD_LOGIC_VECTOR ( 3 downto 0 );
    startup_dts : in STD_LOGIC_VECTOR ( 3 downto 0 );
    startup_fcsbo : in STD_LOGIC;
    startup_fcsbts : in STD_LOGIC;
    startup_gsr : in STD_LOGIC;
    startup_gts : in STD_LOGIC;
    startup_keyclearb : in STD_LOGIC;
    startup_pack : in STD_LOGIC;
    startup_usrcclko : in STD_LOGIC;
    startup_usrcclkts : in STD_LOGIC;
    startup_usrdoneo : in STD_LOGIC;
    startup_usrdonets : in STD_LOGIC;
    drp_rdy : out STD_LOGIC;
    drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drp_clk : in STD_LOGIC;
    drp_en : in STD_LOGIC;
    drp_we : in STD_LOGIC;
    drp_addr : in STD_LOGIC_VECTOR ( 10 downto 0 );
    drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_ext_read_received : out STD_LOGIC;
    cfg_ext_write_received : out STD_LOGIC;
    cfg_ext_register_number : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_ext_function_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ext_write_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_ext_write_byte_enable : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_ext_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_ext_read_data_valid : in STD_LOGIC;
    int_pclk_out_slave : out STD_LOGIC;
    int_pipe_rxusrclk_out : out STD_LOGIC;
    int_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_dclk_out : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    int_userclk2_out : out STD_LOGIC;
    int_oobclk_out : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_in : in STD_LOGIC;
    pipe_rxusrclk_in : in STD_LOGIC;
    pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_dclk_in : in STD_LOGIC;
    pipe_userclk1_in : in STD_LOGIC;
    pipe_userclk2_in : in STD_LOGIC;
    pipe_oobclk_in : in STD_LOGIC;
    pipe_mmcm_rst_n : in STD_LOGIC;
    pipe_mmcm_lock_in : in STD_LOGIC;
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_gen3_out : out STD_LOGIC;
    qpll_drp_crscode : in STD_LOGIC_VECTOR ( 11 downto 0 );
    qpll_drp_fsm : in STD_LOGIC_VECTOR ( 17 downto 0 );
    qpll_drp_done : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_reset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplllock : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutrefclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplld : out STD_LOGIC;
    qpll_qpllreset : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_clk : out STD_LOGIC;
    qpll_drp_rst_n : out STD_LOGIC;
    qpll_drp_ovrd : out STD_LOGIC;
    qpll_drp_gen3 : out STD_LOGIC;
    qpll_drp_start : out STD_LOGIC;
    int_qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1refclk : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1pd : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1rate : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ext_qpll1reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rq_tdata_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rq_tlast_out : out STD_LOGIC;
    m_axis_rq_tuser_out : out STD_LOGIC_VECTOR ( 59 downto 0 );
    m_axis_rq_tkeep_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_rq_tready_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axis_rq_tvalid_out : out STD_LOGIC;
    s_axis_rc_tdata_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_rc_tuser_out : out STD_LOGIC_VECTOR ( 74 downto 0 );
    s_axis_rc_tlast_out : out STD_LOGIC;
    s_axis_rc_tkeep_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_rc_tvalid_out : out STD_LOGIC;
    s_axis_rc_tready_out : out STD_LOGIC;
    s_axis_cq_tdata_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_cq_tuser_out : out STD_LOGIC_VECTOR ( 84 downto 0 );
    s_axis_cq_tlast_out : out STD_LOGIC;
    s_axis_cq_tkeep_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_cq_tvalid_out : out STD_LOGIC;
    s_axis_cq_tready_out : out STD_LOGIC;
    m_axis_cc_tdata_out : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_cc_tuser_out : out STD_LOGIC_VECTOR ( 32 downto 0 );
    m_axis_cc_tlast_out : out STD_LOGIC;
    m_axis_cc_tkeep_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_cc_tvalid_out : out STD_LOGIC;
    m_axis_cc_tready_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt_qpll0lock : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_gen34_eios_det : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txoutclk : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txoutclkfabric : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxoutclkfabric : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txoutclkpcs : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxoutclkpcs : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txpmareset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxpmareset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txpcsreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxpcsreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxbufreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxcdrreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxdfelpmreset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txprogdivresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txpmaresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_txsyncdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxprbslocked : out STD_LOGIC_VECTOR ( 1 downto 0 );
    bufgtce_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    bufgtcemask_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    bufgtdiv_us_out : in STD_LOGIC_VECTOR ( 17 downto 0 );
    bufgtreset_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    bufgtrstmask_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cplllock_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonitorout_us_out : in STD_LOGIC_VECTOR ( 33 downto 0 );
    drpdo_us_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    drprdy_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    eyescandataerror_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gthtxn_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gthtxp_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gtpowergood_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierategen3_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierateidle_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierateqpllpd_us_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pcierateqpllreset_us_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pciesynctxsyncdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieusergen3rdy_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserphystatusrst_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserratestart_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcsrsvdout_us_out : in STD_LOGIC_VECTOR ( 23 downto 0 );
    phystatus_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbufstatus_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rxbyteisaligned_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbyterealign_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrlock_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxclkcorcnt_us_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rxcommadet_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxctrl0_us_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rxctrl1_us_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rxctrl2_us_out : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rxctrl3_us_out : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rxdata_us_out : in STD_LOGIC_VECTOR ( 255 downto 0 );
    rxdlysresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxelecidle_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoutclk_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxphaligndone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpmaresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbserr_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbslocked_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprgdivresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxratedone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxstatus_us_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rxsyncdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxvalid_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlysresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txoutclk_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txphaligndone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txphinitdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txpmaresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txprgdivresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txresetdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncout_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncdone_us_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cpllpd_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfeagchold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfecfokhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfelfhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfekhhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap2hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap3hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap4hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap5hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap6hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap7hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap8hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap9hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap10hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap11hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap12hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap13hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap14hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap15hold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfeuthold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfevphold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoshold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmgchold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmhfhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmlfhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmoshold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cpllreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonfiforeset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonitorclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpaddr_us_in : out STD_LOGIC_VECTOR ( 17 downto 0 );
    drpdi_us_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    drpen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpwe_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    eyescanreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthrxn_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthrxp_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtrefclk0_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtrxreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gttxreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtwiz_reset_rx_done_us_in : out STD_LOGIC;
    gtwiz_reset_tx_done_us_in : out STD_LOGIC;
    gtwiz_userclk_rx_active_us_in : out STD_LOGIC;
    gtwiz_userclk_tx_active_us_in : out STD_LOGIC;
    gtwiz_userclk_tx_reset_us_in : out STD_LOGIC;
    loopback_us_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pcieeqrxeqadaptdone_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierstidle_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pciersttxsyncstart_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserratedone_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcsrsvdin_us_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    rx8b10ben_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbufreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcommadeten_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxmcommaalignen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpcommaalignen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpd_us_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rxpolarity_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbscntreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbssel_us_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rxprogdivreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxrate_us_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    rxratemode_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxslide_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxuserrdy_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxusrclk2_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxusrclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    tx8b10ben_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txctrl0_us_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    txctrl1_us_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    txctrl2_us_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
    txdata_us_in : out STD_LOGIC_VECTOR ( 255 downto 0 );
    txdeemph_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdetectrx_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdiffctrl_us_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
    txdlybypass_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyhold_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyovrden_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlysreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyupdown_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txelecidle_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txinhibit_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txmaincursor_us_in : out STD_LOGIC_VECTOR ( 13 downto 0 );
    txmargin_us_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txoutclksel_us_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txpd_us_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    txphalign_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphalignen_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlypd_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlyreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlytstclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphinit_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphovrden_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txpostcursor_us_in : out STD_LOGIC_VECTOR ( 9 downto 0 );
    txprbsforceerr_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txprbssel_us_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
    txprecursor_us_in : out STD_LOGIC_VECTOR ( 9 downto 0 );
    txprogdivreset_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txrate_us_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txswing_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncallin_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncin_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncmode_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txuserrdy_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txusrclk2_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txusrclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll0clk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll0refclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll1clk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll1refclk_us_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtrefclk01_us_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1pd_us_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1reset_us_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpllrsvd2_us_in : out STD_LOGIC_VECTOR ( 4 downto 0 );
    qpllrsvd3_us_in : out STD_LOGIC_VECTOR ( 4 downto 0 );
    qpll1lock_us_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1outclk_us_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1outrefclk_us_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_bus_number_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_to_turnoff_o : out STD_LOGIC;
    m_axis_rx_tdata_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast_o : out STD_LOGIC;
    m_axis_rx_tuser_o : out STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_rx_tvalid_o : out STD_LOGIC;
    s_axis_tx_tready_o : out STD_LOGIC;
    Integrated_bloc_reset_o : out STD_LOGIC;
    gtrefclk01_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    gtrefclk00_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    pcierateqpll0_usp_in : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pcierateqpll1_usp_in : out STD_LOGIC_VECTOR ( 2 downto 0 );
    qpll0pd_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll0reset_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1pd_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1reset_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpll0lock_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll0outclk_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll0outrefclk_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1lock_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1outclk_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll1outrefclk_usp_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpll0freqlock_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll1freqlock_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierateqpllpd_usp_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pcierateqpllreset_usp_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rcalenb_usp_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    txpisopd_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    bufgtce_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    bufgtcemask_usp_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    bufgtdiv_usp_out : in STD_LOGIC_VECTOR ( 17 downto 0 );
    bufgtreset_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    bufgtrstmask_usp_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cpllfreqlock_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cplllock_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cpllpd_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cpllreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonfiforeset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonitorclk_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    dmonitorout_usp_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    eyescanreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtpowergood_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gtrefclk0_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtrxreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gttxreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gtwiz_reset_rx_done_usp_in : out STD_LOGIC;
    gtwiz_reset_tx_done_usp_in : out STD_LOGIC;
    gtwiz_userclk_rx_active_usp_in : out STD_LOGIC;
    gtwiz_userclk_tx_active_usp_in : out STD_LOGIC;
    loopback_usp_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pcieeqrxeqadaptdone_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierategen3_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierateidle_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcierstidle_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pciersttxsyncstart_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pciesynctxsyncdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieusergen3rdy_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserphystatusrst_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserratedone_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcieuserratestart_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    phystatus_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    resetovrd_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx8b10ben_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbufreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbufstatus_usp_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rxbyteisaligned_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxbyterealign_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrfreqreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrlock_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcdrreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxclkcorcnt_usp_out : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rxcommadet_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxcommadeten_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxctrl0_usp_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rxctrl1_usp_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rxctrl2_usp_out : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rxctrl3_usp_out : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rxdata_usp_out : in STD_LOGIC_VECTOR ( 255 downto 0 );
    rxdfeagchold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfecfokhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfekhhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfelfhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfelpmreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap10hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap11hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap12hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap13hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap14hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap15hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap2hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap3hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap4hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap5hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap6hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap7hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap8hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfetap9hold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfeuthold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdfevphold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxdlysresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxelecidle_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmgchold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmhfhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmlfhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxlpmoshold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxmcommaalignen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoshold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoutclk_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoutclkfabric_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxoutclkpcs_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpcommaalignen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpcsreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpd_usp_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rxphaligndone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpmareset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpmaresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxpolarity_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbscntreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbserr_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbslocked_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxprbssel_usp_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rxprogdivreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxrate_usp_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    rxratedone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxrecclkout_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxslide_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxstatus_usp_out : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rxsyncdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxtermination_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxuserrdy_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxusrclk2_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxusrclk_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxvalid_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    tx8b10ben_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txctrl0_usp_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    txctrl1_usp_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    txctrl2_usp_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
    txdata_usp_in : out STD_LOGIC_VECTOR ( 255 downto 0 );
    txdeemph_usp_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    txdetectrx_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdiffctrl_usp_in : out STD_LOGIC_VECTOR ( 9 downto 0 );
    txdlybypass_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyhold_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyovrden_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlysreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlysresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txdlyupdown_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txelecidle_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txmaincursor_usp_in : out STD_LOGIC_VECTOR ( 13 downto 0 );
    txmargin_usp_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txoutclk_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txoutclkfabric_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txoutclkpcs_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txoutclksel_usp_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txpcsreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txpd_usp_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
    txphalign_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphaligndone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txphalignen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlypd_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlyreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphdlytstclk_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphinit_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txphinitdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txphovrden_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rxratemode_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txpmareset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txpmaresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txpostcursor_usp_in : out STD_LOGIC_VECTOR ( 9 downto 0 );
    txprbsforceerr_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txprbssel_usp_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
    txprecursor_usp_in : out STD_LOGIC_VECTOR ( 9 downto 0 );
    txprgdivresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txprogdivreset_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txpdelecidlemode_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txrate_usp_in : out STD_LOGIC_VECTOR ( 5 downto 0 );
    txresetdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txswing_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncallin_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncdone_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncin_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncmode_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txsyncout_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txuserrdy_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txusrclk2_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txusrclk_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpclk_usp_in : out STD_LOGIC;
    drpaddr_usp_in : out STD_LOGIC_VECTOR ( 19 downto 0 );
    drpen_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drprst_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpwe_usp_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
    drpdi_usp_in : out STD_LOGIC_VECTOR ( 31 downto 0 );
    drprdy_usp_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    drpdo_usp_out : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_phy_clk_pclk2_gt : in STD_LOGIC;
    ext_phy_clk_int_clock : in STD_LOGIC;
    ext_phy_clk_pclk : in STD_LOGIC;
    ext_phy_clk_phy_pclk2 : in STD_LOGIC;
    ext_phy_clk_phy_coreclk : in STD_LOGIC;
    ext_phy_clk_phy_userclk : in STD_LOGIC;
    ext_phy_clk_phy_mcapclk : in STD_LOGIC;
    ext_phy_clk_bufg_gt_ce : out STD_LOGIC;
    ext_phy_clk_bufg_gt_reset : out STD_LOGIC;
    ext_phy_clk_rst_idle : out STD_LOGIC;
    ext_phy_clk_txoutclk : out STD_LOGIC;
    ext_phy_clk_bufgtcemask : out STD_LOGIC;
    ext_phy_clk_gt_bufgtrstmask : out STD_LOGIC;
    ext_phy_clk_bufgtdiv : out STD_LOGIC_VECTOR ( 8 downto 0 );
    int_usp_qpll0lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_usp_qpll0outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_usp_qpll0outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_usp_qpll1lock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_usp_qpll1outrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_usp_qpll1outclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpllxrefclk : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpllxrate : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ext_usp_qpllxrcalenb : out STD_LOGIC;
    ext_usp_qpll0pd : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll0reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll0lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll0outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll0outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll1pd : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll1reset : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll1lock_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll1outclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_usp_qpll1outrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_negotiated_width_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_current_speed_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_ltssm_state_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_err_cor_o : out STD_LOGIC;
    cfg_err_fatal_o : out STD_LOGIC;
    cfg_err_nonfatal_o : out STD_LOGIC;
    cfg_local_error_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_local_error_valid_o : out STD_LOGIC;
    pipe_tx0_rcvr_det : out STD_LOGIC;
    pipe_clk : out STD_LOGIC;
    sys_clk_bufg : out STD_LOGIC;
    pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_function_status : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_max_read_req : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_max_payload : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_flr_done : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_flr_in_process : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_vf_flr_in_process : out STD_LOGIC_VECTOR ( 251 downto 0 );
    cfg_vf_flr_func_num : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_vf_flr_done : in STD_LOGIC;
    cfg_interrupt_msi_enable : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msix_enable : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_msix_mask : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_msix_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_msix_address : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt_msix_int : in STD_LOGIC;
    cfg_interrupt_msi_sent : out STD_LOGIC;
    cfg_interrupt_msi_fail : out STD_LOGIC;
    cfg_interrupt_msix_sent : out STD_LOGIC;
    cfg_interrupt_msix_fail : out STD_LOGIC;
    phy_rdy_out_sd : in STD_LOGIC;
    cfg_err_cor_in_sd : out STD_LOGIC;
    cfg_link_training_enable_sd : out STD_LOGIC;
    cfg_ltssm_state_sd : in STD_LOGIC_VECTOR ( 5 downto 0 );
    user_lnk_up_sd : in STD_LOGIC;
    s_axis_rq_tdata_sd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_rq_tlast_sd : out STD_LOGIC;
    s_axis_rq_tuser_sd : out STD_LOGIC_VECTOR ( 59 downto 0 );
    s_axis_rq_tkeep_sd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_rq_tvalid_sd : out STD_LOGIC;
    s_axis_rq_tready_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axis_rc_tdata_sd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rc_tuser_sd : in STD_LOGIC_VECTOR ( 74 downto 0 );
    m_axis_rc_tlast_sd : in STD_LOGIC;
    m_axis_rc_tkeep_sd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_rc_tvalid_sd : in STD_LOGIC;
    m_axis_rc_tready_sd : out STD_LOGIC;
    m_axis_cq_tdata_sd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_cq_tuser_sd : in STD_LOGIC_VECTOR ( 84 downto 0 );
    m_axis_cq_tlast_sd : in STD_LOGIC;
    m_axis_cq_tkeep_sd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_cq_tvalid_sd : in STD_LOGIC;
    m_axis_cq_tready_sd : out STD_LOGIC;
    s_axis_cc_tdata_sd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_cc_tuser_sd : out STD_LOGIC_VECTOR ( 32 downto 0 );
    s_axis_cc_tlast_sd : out STD_LOGIC;
    s_axis_cc_tkeep_sd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_cc_tvalid_sd : out STD_LOGIC;
    s_axis_cc_tready_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    rbar_bar_size_sd : in STD_LOGIC_VECTOR ( 5 downto 0 );
    rbar_function_number_sd : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rbar_write_enable_bar0_sd : in STD_LOGIC;
    rbar_write_enable_bar1_sd : in STD_LOGIC;
    rbar_write_enable_bar2_sd : in STD_LOGIC;
    rbar_write_enable_bar3_sd : in STD_LOGIC;
    rbar_write_enable_bar4_sd : in STD_LOGIC;
    rbar_write_enable_bar5_sd : in STD_LOGIC;
    user_clk_sd : in STD_LOGIC;
    user_reset_sd : in STD_LOGIC;
    pcie_cq_np_req_sd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcie_cq_np_req_count_sd : in STD_LOGIC_VECTOR ( 5 downto 0 );
    pcie_tfc_nph_av_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pcie_tfc_npd_av_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pcie_rq_seq_num_vld0_sd : in STD_LOGIC;
    pcie_rq_seq_num0_sd : in STD_LOGIC_VECTOR ( 5 downto 0 );
    pcie_rq_seq_num_vld1_sd : in STD_LOGIC;
    pcie_rq_seq_num1_sd : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_fc_nph_sd : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_fc_sel_sd : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_phy_link_down_sd : in STD_LOGIC;
    cfg_phy_link_status_sd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_negotiated_width_sd : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_current_speed_sd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pl_status_change_sd : in STD_LOGIC;
    cfg_hot_reset_out_sd : in STD_LOGIC;
    cfg_ds_port_number_sd : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_bus_number_sd : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number_sd : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number_sd : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_dsn_sd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_function_status_sd : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_max_read_req_sd : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_max_payload_sd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_err_uncor_in_sd : out STD_LOGIC;
    cfg_flr_done_sd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_flr_in_process_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_vf_flr_in_process_sd : in STD_LOGIC_VECTOR ( 251 downto 0 );
    usr_flr_fnc : out STD_LOGIC_VECTOR ( 7 downto 0 );
    usr_flr_set : out STD_LOGIC;
    usr_flr_clr : out STD_LOGIC;
    usr_flr_done_fnc : in STD_LOGIC_VECTOR ( 7 downto 0 );
    usr_flr_done_vld : in STD_LOGIC;
    cfg_err_cor_out_sd : in STD_LOGIC;
    cfg_err_nonfatal_out_sd : in STD_LOGIC;
    cfg_err_fatal_out_sd : in STD_LOGIC;
    cfg_local_error_out_sd : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_msg_received_sd : in STD_LOGIC;
    cfg_msg_received_data_sd : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_msg_received_type_sd : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_msg_transmit_sd : out STD_LOGIC;
    cfg_msg_transmit_type_sd : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_msg_transmit_data_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_msg_transmit_done_sd : in STD_LOGIC;
    cfg_mgmt_addr_sd : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_write_sd : out STD_LOGIC;
    cfg_mgmt_write_data_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_enable_sd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_read_sd : out STD_LOGIC;
    cfg_mgmt_type1_cfg_reg_access_sd : out STD_LOGIC;
    cfg_mgmt_read_data_sd : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_read_write_done_sd : in STD_LOGIC;
    cfg_mgmt_function_number_sd : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_int_sd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_sent_sd : in STD_LOGIC;
    cfg_interrupt_pending_sd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msi_enable_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msi_mask_update_sd : in STD_LOGIC;
    cfg_interrupt_msi_data_sd : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_msi_int_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_msi_pending_status_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_msi_pending_status_data_enable_sd : out STD_LOGIC;
    cfg_interrupt_msi_pending_status_function_num_sd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msi_attr_sd : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msi_tph_present_sd : out STD_LOGIC;
    cfg_interrupt_msi_tph_type_sd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_msi_tph_st_tag_sd : out STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_interrupt_msi_function_number_sd : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_msi_sent_sd : in STD_LOGIC;
    cfg_interrupt_msi_fail_sd : in STD_LOGIC;
    cfg_interrupt_msix_enable_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msix_mask_sd : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msix_data_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_interrupt_msix_address_sd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt_msix_int_sd : out STD_LOGIC;
    cfg_interrupt_msix_vf_enable_sd : in STD_LOGIC_VECTOR ( 251 downto 0 );
    cfg_interrupt_msix_vf_mask_sd : in STD_LOGIC_VECTOR ( 251 downto 0 );
    cfg_interrupt_msix_vec_pending_sd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_msix_vec_pending_status_sd : in STD_LOGIC;
    rd_interrupt : out STD_LOGIC;
    wr_interrupt : out STD_LOGIC;
    ats_pri_en : out STD_LOGIC;
    cfg_fc_vc_sel : in STD_LOGIC;
    core_clk : out STD_LOGIC;
    cxs0_active_req_tx : in STD_LOGIC;
    cxs0_active_ack_tx : out STD_LOGIC;
    cxs0_deact_hint_tx : out STD_LOGIC;
    cxs0_valid_tx : in STD_LOGIC;
    cxs0_crdgnt_tx : out STD_LOGIC;
    cxs0_crdrtn_tx : in STD_LOGIC;
    cxs0_cntl_tx : in STD_LOGIC_VECTOR ( 13 downto 0 );
    cxs0_data_tx : in STD_LOGIC_VECTOR ( 255 downto 0 );
    cxs0_valid_chk_tx : in STD_LOGIC;
    cxs0_crdgnt_chk_tx : out STD_LOGIC;
    cxs0_crdrtn_chk_tx : in STD_LOGIC;
    cxs0_cntl_chk_tx : in STD_LOGIC;
    cxs0_data_chk_tx : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cxs0_active_req_rx : out STD_LOGIC;
    cxs0_active_ack_rx : in STD_LOGIC;
    cxs0_deact_hint_rx : in STD_LOGIC;
    cxs0_valid_rx : out STD_LOGIC;
    cxs0_crdgnt_rx : in STD_LOGIC;
    cxs0_crdrtn_rx : out STD_LOGIC;
    cxs0_cntl_rx : out STD_LOGIC_VECTOR ( 13 downto 0 );
    cxs0_data_rx : out STD_LOGIC_VECTOR ( 255 downto 0 );
    cxs0_valid_chk_rx : out STD_LOGIC;
    cxs0_crdgnt_chk_rx : in STD_LOGIC;
    cxs0_crdrtn_chk_rx : out STD_LOGIC;
    cxs0_cntl_chk_rx : out STD_LOGIC;
    cxs0_data_chk_rx : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pcie4_cxs0_active_req_tx_sd : out STD_LOGIC;
    pcie4_cxs0_active_ack_tx_sd : in STD_LOGIC;
    pcie4_cxs0_deact_hint_tx_sd : in STD_LOGIC;
    pcie4_cxs0_valid_tx_sd : out STD_LOGIC;
    pcie4_cxs0_crdgnt_tx_sd : in STD_LOGIC;
    pcie4_cxs0_crdrtn_tx_sd : out STD_LOGIC;
    pcie4_cxs0_cntl_tx_sd : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pcie4_cxs0_data_tx_sd : out STD_LOGIC_VECTOR ( 255 downto 0 );
    pcie4_cxs0_valid_chk_tx_sd : out STD_LOGIC;
    pcie4_cxs0_crdgnt_chk_tx_sd : in STD_LOGIC;
    pcie4_cxs0_crdrtn_chk_tx_sd : out STD_LOGIC;
    pcie4_cxs0_cntl_chk_tx_sd : out STD_LOGIC;
    pcie4_cxs0_data_chk_tx_sd : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pcie4_cxs0_active_req_rx_sd : in STD_LOGIC;
    pcie4_cxs0_active_ack_rx_sd : out STD_LOGIC;
    pcie4_cxs0_deact_hint_rx_sd : out STD_LOGIC;
    pcie4_cxs0_valid_rx_sd : in STD_LOGIC;
    pcie4_cxs0_crdgnt_rx_sd : out STD_LOGIC;
    pcie4_cxs0_crdrtn_rx_sd : in STD_LOGIC;
    pcie4_cxs0_cntl_rx_sd : in STD_LOGIC_VECTOR ( 13 downto 0 );
    pcie4_cxs0_data_rx_sd : in STD_LOGIC_VECTOR ( 255 downto 0 );
    pcie4_cxs0_valid_chk_rx_sd : in STD_LOGIC;
    pcie4_cxs0_crdgnt_chk_rx_sd : out STD_LOGIC;
    pcie4_cxs0_crdrtn_chk_rx_sd : in STD_LOGIC;
    pcie4_cxs0_cntl_chk_rx_sd : in STD_LOGIC;
    pcie4_cxs0_data_chk_rx_sd : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ccix_optimized_tlp_tx_and_rx_enable_in : in STD_LOGIC;
    sc0_ats_s_axis_rq_tvalid : in STD_LOGIC;
    sc0_ats_s_axis_rq_tready : out STD_LOGIC;
    sc0_ats_s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    sc0_ats_s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    sc0_ats_s_axis_rq_tlast : in STD_LOGIC;
    sc0_ats_s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 );
    sc0_ats_m_axis_rc_tvalid : out STD_LOGIC;
    sc0_ats_m_axis_rc_tready : in STD_LOGIC;
    sc0_ats_m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    sc0_ats_m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sc0_ats_m_axis_rc_tlast : out STD_LOGIC;
    sc0_ats_m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 );
    sc0_ats_s_axis_cc_tvalid : in STD_LOGIC;
    sc0_ats_s_axis_cc_tready : out STD_LOGIC;
    sc0_ats_s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    sc0_ats_s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    sc0_ats_s_axis_cc_tlast : in STD_LOGIC;
    sc0_ats_s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 );
    sc0_ats_m_axis_cq_tvalid : out STD_LOGIC;
    sc0_ats_m_axis_cq_tready : in STD_LOGIC;
    sc0_ats_m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    sc0_ats_m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sc0_ats_m_axis_cq_tlast : out STD_LOGIC;
    sc0_ats_m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 );
    sc1_ats_s_axis_rq_tvalid : in STD_LOGIC;
    sc1_ats_s_axis_rq_tready : out STD_LOGIC;
    sc1_ats_s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    sc1_ats_s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    sc1_ats_s_axis_rq_tlast : in STD_LOGIC;
    sc1_ats_s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 );
    sc1_ats_m_axis_rc_tvalid : out STD_LOGIC;
    sc1_ats_m_axis_rc_tready : in STD_LOGIC;
    sc1_ats_m_axis_rc_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    sc1_ats_m_axis_rc_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sc1_ats_m_axis_rc_tlast : out STD_LOGIC;
    sc1_ats_m_axis_rc_tuser : out STD_LOGIC_VECTOR ( 74 downto 0 );
    sc1_ats_s_axis_cc_tvalid : in STD_LOGIC;
    sc1_ats_s_axis_cc_tready : out STD_LOGIC;
    sc1_ats_s_axis_cc_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    sc1_ats_s_axis_cc_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    sc1_ats_s_axis_cc_tlast : in STD_LOGIC;
    sc1_ats_s_axis_cc_tuser : in STD_LOGIC_VECTOR ( 32 downto 0 );
    sc1_ats_m_axis_cq_tvalid : out STD_LOGIC;
    sc1_ats_m_axis_cq_tready : in STD_LOGIC;
    sc1_ats_m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    sc1_ats_m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sc1_ats_m_axis_cq_tlast : out STD_LOGIC;
    sc1_ats_m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 );
    s_aclk : in STD_LOGIC;
    s_aresetn : in STD_LOGIC;
    s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_arready : out STD_LOGIC;
    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_aruser : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_arvalid : in STD_LOGIC;
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_awready : out STD_LOGIC;
    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    s_axi_awuser : in STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_awvalid : in STD_LOGIC;
    s_axi_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_bready : in STD_LOGIC;
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_bvalid : out STD_LOGIC;
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    s_axi_rlast : out STD_LOGIC;
    s_axi_rready : in STD_LOGIC;
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axi_rvalid : out STD_LOGIC;
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    s_axi_wlast : in STD_LOGIC;
    s_axi_wready : out STD_LOGIC;
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axi_wvalid : in STD_LOGIC;
    atspri_m_axis_cq_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    atspri_m_axis_cq_tuser : out STD_LOGIC_VECTOR ( 84 downto 0 );
    atspri_m_axis_cq_tlast : out STD_LOGIC;
    atspri_m_axis_cq_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    atspri_m_axis_cq_tvalid : out STD_LOGIC;
    atspri_m_axis_cq_tready : in STD_LOGIC;
    atspri_s_axis_rq_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    atspri_s_axis_rq_tuser : in STD_LOGIC_VECTOR ( 59 downto 0 );
    atspri_s_axis_rq_tlast : in STD_LOGIC;
    atspri_s_axis_rq_tkeep : in STD_LOGIC_VECTOR ( 1 downto 0 );
    atspri_s_axis_rq_tvalid : in STD_LOGIC;
    atspri_s_axis_rq_tready : out STD_LOGIC;
    cfg_status_ats_stu : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_status_ats_en : out STD_LOGIC;
    cfg_status_pr_en : out STD_LOGIC;
    cfg_status_pr_rst : out STD_LOGIC;
    cfg_status_pr_uprgi : out STD_LOGIC;
    cfg_status_set_uprgi : in STD_LOGIC;
    cfg_status_pr_rf : out STD_LOGIC;
    cfg_status_set_rf : in STD_LOGIC;
    cfg_status_set_s : in STD_LOGIC;
    cfg_status_clr_s : in STD_LOGIC;
    cfg_status_ost_pr_alloc : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ACS_EXT_CAP_ENABLE : string;
  attribute ACS_EXT_CAP_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute AXI4MM_ULTRA : integer;
  attribute AXI4MM_ULTRA of xdma_0_xdma_0_core_top : entity is 0;
  attribute AXILITE_MASTER_APERTURE_SIZE : string;
  attribute AXILITE_MASTER_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001101";
  attribute AXILITE_MASTER_CONTROL : string;
  attribute AXILITE_MASTER_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute AXISTEN_IF_ENABLE_MSG_ROUTE : string;
  attribute AXISTEN_IF_ENABLE_MSG_ROUTE of xdma_0_xdma_0_core_top : entity is "18'b000000000000000000";
  attribute AXIST_BYPASS_APERTURE_SIZE : string;
  attribute AXIST_BYPASS_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001101";
  attribute AXIST_BYPASS_CONTROL : string;
  attribute AXIST_BYPASS_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b100";
  attribute AXIS_CCIX_RX_TDATA_WIDTH : integer;
  attribute AXIS_CCIX_RX_TDATA_WIDTH of xdma_0_xdma_0_core_top : entity is 256;
  attribute AXIS_CCIX_RX_TUSER_WIDTH : integer;
  attribute AXIS_CCIX_RX_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 47;
  attribute AXIS_CCIX_TX_TDATA_WIDTH : integer;
  attribute AXIS_CCIX_TX_TDATA_WIDTH of xdma_0_xdma_0_core_top : entity is 256;
  attribute AXIS_CCIX_TX_TUSER_WIDTH : integer;
  attribute AXIS_CCIX_TX_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 47;
  attribute AXIS_PIPE_LINE_STAGE : integer;
  attribute AXIS_PIPE_LINE_STAGE of xdma_0_xdma_0_core_top : entity is 0;
  attribute AXI_ACLK_LOOPBACK : string;
  attribute AXI_ACLK_LOOPBACK of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute AXI_ADDR_WIDTH : integer;
  attribute AXI_ADDR_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute AXI_DATA_WIDTH : integer;
  attribute AXI_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute AXI_VIP_IN_EXDES : string;
  attribute AXI_VIP_IN_EXDES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute AXSIZE_BYTE_ACCESS_EN : string;
  attribute AXSIZE_BYTE_ACCESS_EN of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute BACKPRESSURE : integer;
  attribute BACKPRESSURE of xdma_0_xdma_0_core_top : entity is 0;
  attribute BARLITE0 : integer;
  attribute BARLITE0 of xdma_0_xdma_0_core_top : entity is 7;
  attribute BARLITE1 : integer;
  attribute BARLITE1 of xdma_0_xdma_0_core_top : entity is 0;
  attribute BARLITE2 : integer;
  attribute BARLITE2 of xdma_0_xdma_0_core_top : entity is 7;
  attribute BARLITE_EXT_PF0 : string;
  attribute BARLITE_EXT_PF0 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_EXT_PF1 : string;
  attribute BARLITE_EXT_PF1 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_EXT_PF2 : string;
  attribute BARLITE_EXT_PF2 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_EXT_PF3 : string;
  attribute BARLITE_EXT_PF3 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_INT_PF0 : string;
  attribute BARLITE_INT_PF0 of xdma_0_xdma_0_core_top : entity is "6'b000001";
  attribute BARLITE_INT_PF1 : string;
  attribute BARLITE_INT_PF1 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_INT_PF2 : string;
  attribute BARLITE_INT_PF2 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute BARLITE_INT_PF3 : string;
  attribute BARLITE_INT_PF3 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute C2H_XDMA_CHNL : string;
  attribute C2H_XDMA_CHNL of xdma_0_xdma_0_core_top : entity is "8'b00001111";
  attribute CCIX_DVSEC : string;
  attribute CCIX_DVSEC of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute CCIX_ENABLE : string;
  attribute CCIX_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute CDC_WB_EN : integer;
  attribute CDC_WB_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute CFG_EXT_IF : string;
  attribute CFG_EXT_IF of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute COMPONENT_NAME : string;
  attribute COMPONENT_NAME of xdma_0_xdma_0_core_top : entity is "xdma_0";
  attribute CORE_CLK_FREQ : integer;
  attribute CORE_CLK_FREQ of xdma_0_xdma_0_core_top : entity is 2;
  attribute C_ADDR_ALGN : integer;
  attribute C_ADDR_ALGN of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_ADDR_BITS : integer;
  attribute C_ADDR_BITS of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_ATS_CAP_NEXTPTR : string;
  attribute C_ATS_CAP_NEXTPTR of xdma_0_xdma_0_core_top : entity is "12'b000000000000";
  attribute C_ATS_CC_TUSER_WIDTH : integer;
  attribute C_ATS_CC_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 33;
  attribute C_ATS_CQ_TUSER_WIDTH : integer;
  attribute C_ATS_CQ_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 85;
  attribute C_ATS_DATA_WIDTH : integer;
  attribute C_ATS_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_ATS_ENABLE : string;
  attribute C_ATS_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute C_ATS_OFFSET : string;
  attribute C_ATS_OFFSET of xdma_0_xdma_0_core_top : entity is "30'b000000000000000000000100100000";
  attribute C_ATS_RC_TUSER_WIDTH : integer;
  attribute C_ATS_RC_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 75;
  attribute C_ATS_RQ_TUSER_WIDTH : integer;
  attribute C_ATS_RQ_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 60;
  attribute C_ATS_SWITCH_UNIQUE_BDF : integer;
  attribute C_ATS_SWITCH_UNIQUE_BDF of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR2PCIEATTR_0 : string;
  attribute C_AXIBAR2PCIEATTR_0 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEATTR_1 : string;
  attribute C_AXIBAR2PCIEATTR_1 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEATTR_2 : string;
  attribute C_AXIBAR2PCIEATTR_2 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEATTR_3 : string;
  attribute C_AXIBAR2PCIEATTR_3 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEATTR_4 : string;
  attribute C_AXIBAR2PCIEATTR_4 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEATTR_5 : string;
  attribute C_AXIBAR2PCIEATTR_5 of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute C_AXIBAR2PCIEBAR_0 : string;
  attribute C_AXIBAR2PCIEBAR_0 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_1 : string;
  attribute C_AXIBAR2PCIEBAR_1 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_2 : string;
  attribute C_AXIBAR2PCIEBAR_2 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_3 : string;
  attribute C_AXIBAR2PCIEBAR_3 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_4 : string;
  attribute C_AXIBAR2PCIEBAR_4 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_5 : string;
  attribute C_AXIBAR2PCIEBAR_5 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_0 : string;
  attribute C_AXIBAR_0 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_1 : string;
  attribute C_AXIBAR_1 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_2 : string;
  attribute C_AXIBAR_2 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_3 : string;
  attribute C_AXIBAR_3 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_4 : string;
  attribute C_AXIBAR_4 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_5 : string;
  attribute C_AXIBAR_5 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_AS_0 : integer;
  attribute C_AXIBAR_AS_0 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_AS_1 : integer;
  attribute C_AXIBAR_AS_1 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_AS_2 : integer;
  attribute C_AXIBAR_AS_2 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_AS_3 : integer;
  attribute C_AXIBAR_AS_3 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_AS_4 : integer;
  attribute C_AXIBAR_AS_4 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_AS_5 : integer;
  attribute C_AXIBAR_AS_5 of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_HIGHADDR_0 : string;
  attribute C_AXIBAR_HIGHADDR_0 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_1 : string;
  attribute C_AXIBAR_HIGHADDR_1 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_2 : string;
  attribute C_AXIBAR_HIGHADDR_2 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_3 : string;
  attribute C_AXIBAR_HIGHADDR_3 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_4 : string;
  attribute C_AXIBAR_HIGHADDR_4 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_5 : string;
  attribute C_AXIBAR_HIGHADDR_5 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_NOXLATE : integer;
  attribute C_AXIBAR_NOXLATE of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_AXIBAR_NUM : integer;
  attribute C_AXIBAR_NUM of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_AXIBAR_REGIONEN : integer;
  attribute C_AXIBAR_REGIONEN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_BASEADDR : integer;
  attribute C_BASEADDR of xdma_0_xdma_0_core_top : entity is 4096;
  attribute C_C2H_NUM_CHNL : integer;
  attribute C_C2H_NUM_CHNL of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_C2H_NUM_RIDS : integer;
  attribute C_C2H_NUM_RIDS of xdma_0_xdma_0_core_top : entity is 16;
  attribute C_C2H_TUSER_WIDTH : integer;
  attribute C_C2H_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_COMP_TIMEOUT : integer;
  attribute C_COMP_TIMEOUT of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_DEVICE_NUMBER : integer;
  attribute C_DEVICE_NUMBER of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_DSC_MAGIC_EN : integer;
  attribute C_DSC_MAGIC_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_ECC_ENABLE : integer;
  attribute C_ECC_ENABLE of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_ENABLE_RESOURCE_REDUCTION : string;
  attribute C_ENABLE_RESOURCE_REDUCTION of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute C_FAMILY : string;
  attribute C_FAMILY of xdma_0_xdma_0_core_top : entity is "artix7";
  attribute C_FF_ON_INT_IF : string;
  attribute C_FF_ON_INT_IF of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute C_GEN2_DEVICES : string;
  attribute C_GEN2_DEVICES of xdma_0_xdma_0_core_top : entity is "1'b1";
  attribute C_H2C_NUM_CHNL : integer;
  attribute C_H2C_NUM_CHNL of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_H2C_NUM_RIDS : integer;
  attribute C_H2C_NUM_RIDS of xdma_0_xdma_0_core_top : entity is 32;
  attribute C_H2C_TUSER_WIDTH : integer;
  attribute C_H2C_TUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 48;
  attribute C_HIGHADDR : integer;
  attribute C_HIGHADDR of xdma_0_xdma_0_core_top : entity is 8191;
  attribute C_IGNORE_SIZE_AXI_SLAVE : integer;
  attribute C_IGNORE_SIZE_AXI_SLAVE of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_INCLUDE_BAROFFSET_REG : integer;
  attribute C_INCLUDE_BAROFFSET_REG of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_INCLUDE_RC : integer;
  attribute C_INCLUDE_RC of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_INTX_RX_PIN_EN : integer;
  attribute C_INTX_RX_PIN_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_INV_QUEUE_DEPTH : string;
  attribute C_INV_QUEUE_DEPTH of xdma_0_xdma_0_core_top : entity is "5'b00000";
  attribute C_KEEP_WIDTH : integer;
  attribute C_KEEP_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_LAST_CORE_CAP_ADDR : string;
  attribute C_LAST_CORE_CAP_ADDR of xdma_0_xdma_0_core_top : entity is "12'b000100000000";
  attribute C_LEGACY_INT_EN : string;
  attribute C_LEGACY_INT_EN of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute C_METERING_ON : integer;
  attribute C_METERING_ON of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_MSIX_INT_TABLE_EN : integer;
  attribute C_MSIX_INT_TABLE_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_MSIX_RX_PIN_EN : integer;
  attribute C_MSIX_RX_PIN_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_MSI_ENABLED : string;
  attribute C_MSI_ENABLED of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute C_MSI_RX_PIN_EN : integer;
  attribute C_MSI_RX_PIN_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_M_AXIL_ARUSER_WIDTH : integer;
  attribute C_M_AXIL_ARUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 11;
  attribute C_M_AXIL_AWUSER_WIDTH : integer;
  attribute C_M_AXIL_AWUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 11;
  attribute C_M_AXIS_DATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_M_AXIS_RC_USER_WIDTH : integer;
  attribute C_M_AXIS_RC_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 75;
  attribute C_M_AXIS_RQ_USER_WIDTH : integer;
  attribute C_M_AXIS_RQ_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 60;
  attribute C_M_AXIS_USER_WIDTH : integer;
  attribute C_M_AXIS_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_M_AXI_ADDR_WIDTH : integer;
  attribute C_M_AXI_ADDR_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_M_AXI_ARUSER_WIDTH : integer;
  attribute C_M_AXI_ARUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_M_AXI_AWUSER_WIDTH : integer;
  attribute C_M_AXI_AWUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_M_AXI_BUSER_WIDTH : integer;
  attribute C_M_AXI_BUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_M_AXI_DATA_WIDTH : integer;
  attribute C_M_AXI_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_M_AXI_ID_WIDTH : integer;
  attribute C_M_AXI_ID_WIDTH of xdma_0_xdma_0_core_top : entity is 4;
  attribute C_M_AXI_NUM_READ : integer;
  attribute C_M_AXI_NUM_READ of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_M_AXI_NUM_READQ : integer;
  attribute C_M_AXI_NUM_READQ of xdma_0_xdma_0_core_top : entity is 2;
  attribute C_M_AXI_NUM_WRITE : integer;
  attribute C_M_AXI_NUM_WRITE of xdma_0_xdma_0_core_top : entity is 4;
  attribute C_M_AXI_NUM_WRITE_SCALE : integer;
  attribute C_M_AXI_NUM_WRITE_SCALE of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_M_AXI_RUSER_WIDTH : integer;
  attribute C_M_AXI_RUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_M_AXI_WUSER_WIDTH : integer;
  attribute C_M_AXI_WUSER_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_M_KEEP_WIDTH : integer;
  attribute C_M_KEEP_WIDTH of xdma_0_xdma_0_core_top : entity is 2;
  attribute C_NUMQ_PER_CHNL : integer;
  attribute C_NUMQ_PER_CHNL of xdma_0_xdma_0_core_top : entity is 256;
  attribute C_NUM_AXI_DSC_CPL_DID : integer;
  attribute C_NUM_AXI_DSC_CPL_DID of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_NUM_DSC_PCIE_RID : integer;
  attribute C_NUM_DSC_PCIE_RID of xdma_0_xdma_0_core_top : entity is 32;
  attribute C_NUM_MSIX_VECTORS : integer;
  attribute C_NUM_MSIX_VECTORS of xdma_0_xdma_0_core_top : entity is 32;
  attribute C_NUM_OF_SC : integer;
  attribute C_NUM_OF_SC of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_NUM_PCIE_DSC_CPL_DID : integer;
  attribute C_NUM_PCIE_DSC_CPL_DID of xdma_0_xdma_0_core_top : entity is 256;
  attribute C_NUM_USER_INTR : integer;
  attribute C_NUM_USER_INTR of xdma_0_xdma_0_core_top : entity is 9;
  attribute C_NUM_USER_NEW_INTR : integer;
  attribute C_NUM_USER_NEW_INTR of xdma_0_xdma_0_core_top : entity is 6;
  attribute C_NUM_USR_IRQ : integer;
  attribute C_NUM_USR_IRQ of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_OLD_BRIDGE_TIMEOUT : integer;
  attribute C_OLD_BRIDGE_TIMEOUT of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_OST_PR_CAP : integer;
  attribute C_OST_PR_CAP of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_PARITY_CHECK : integer;
  attribute C_PARITY_CHECK of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_PARITY_GEN : integer;
  attribute C_PARITY_GEN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_PARITY_PROP : integer;
  attribute C_PARITY_PROP of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_PCIEBAR2AXIBAR_0 : string;
  attribute C_PCIEBAR2AXIBAR_0 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_0_TMP : string;
  attribute C_PCIEBAR2AXIBAR_0_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_1 : string;
  attribute C_PCIEBAR2AXIBAR_1 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_1_TMP : string;
  attribute C_PCIEBAR2AXIBAR_1_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_2 : string;
  attribute C_PCIEBAR2AXIBAR_2 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_2_TMP : string;
  attribute C_PCIEBAR2AXIBAR_2_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_3 : string;
  attribute C_PCIEBAR2AXIBAR_3 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_3_TMP : string;
  attribute C_PCIEBAR2AXIBAR_3_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_4 : string;
  attribute C_PCIEBAR2AXIBAR_4 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_4_TMP : string;
  attribute C_PCIEBAR2AXIBAR_4_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_5 : string;
  attribute C_PCIEBAR2AXIBAR_5 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_5_TMP : string;
  attribute C_PCIEBAR2AXIBAR_5_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_6 : string;
  attribute C_PCIEBAR2AXIBAR_6 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_6_TMP : string;
  attribute C_PCIEBAR2AXIBAR_6_TMP of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR_AS : integer;
  attribute C_PCIEBAR_AS of xdma_0_xdma_0_core_top : entity is 1;
  attribute C_PCIEBAR_LEN_0 : integer;
  attribute C_PCIEBAR_LEN_0 of xdma_0_xdma_0_core_top : entity is 16;
  attribute C_PCIEBAR_LEN_1 : integer;
  attribute C_PCIEBAR_LEN_1 of xdma_0_xdma_0_core_top : entity is 20;
  attribute C_PCIEBAR_LEN_2 : integer;
  attribute C_PCIEBAR_LEN_2 of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_PCIEBAR_LEN_3 : integer;
  attribute C_PCIEBAR_LEN_3 of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_PCIEBAR_LEN_4 : integer;
  attribute C_PCIEBAR_LEN_4 of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_PCIEBAR_LEN_5 : integer;
  attribute C_PCIEBAR_LEN_5 of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_PCIEBAR_LEN_6 : integer;
  attribute C_PCIEBAR_LEN_6 of xdma_0_xdma_0_core_top : entity is 7;
  attribute C_PCIEBAR_NUM : integer;
  attribute C_PCIEBAR_NUM of xdma_0_xdma_0_core_top : entity is 6;
  attribute C_PCIE_PFS_SUPPORTED : integer;
  attribute C_PCIE_PFS_SUPPORTED of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_PRI_ENABLE : string;
  attribute C_PRI_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute C_PR_CAP_NEXTPTR : string;
  attribute C_PR_CAP_NEXTPTR of xdma_0_xdma_0_core_top : entity is "12'b000000000000";
  attribute C_PR_OFFSET : string;
  attribute C_PR_OFFSET of xdma_0_xdma_0_core_top : entity is "30'b000000000000000000000100100100";
  attribute C_RD_BUFFER_ADDR_SIZE : integer;
  attribute C_RD_BUFFER_ADDR_SIZE of xdma_0_xdma_0_core_top : entity is 9;
  attribute C_RD_BUFFER_SIZE_BITS : integer;
  attribute C_RD_BUFFER_SIZE_BITS of xdma_0_xdma_0_core_top : entity is 5;
  attribute C_SLAVE_READ_64OS_EN : integer;
  attribute C_SLAVE_READ_64OS_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_SMMU_EN : integer;
  attribute C_SMMU_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_SRIOV_EN : integer;
  attribute C_SRIOV_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_S_AXIS_CC_USER_WIDTH : integer;
  attribute C_S_AXIS_CC_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 33;
  attribute C_S_AXIS_CQP_USER_WIDTH : integer;
  attribute C_S_AXIS_CQP_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 85;
  attribute C_S_AXIS_CQ_USER_WIDTH : integer;
  attribute C_S_AXIS_CQ_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 85;
  attribute C_S_AXIS_DATA_WIDTH : integer;
  attribute C_S_AXIS_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_S_AXIS_USER_WIDTH : integer;
  attribute C_S_AXIS_USER_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute C_S_AXI_ID_WIDTH : integer;
  attribute C_S_AXI_ID_WIDTH of xdma_0_xdma_0_core_top : entity is 4;
  attribute C_S_AXI_NUM_READ : integer;
  attribute C_S_AXI_NUM_READ of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_S_AXI_NUM_WRITE : integer;
  attribute C_S_AXI_NUM_WRITE of xdma_0_xdma_0_core_top : entity is 8;
  attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
  attribute C_S_AXI_SUPPORTS_NARROW_BURST of xdma_0_xdma_0_core_top : entity is 0;
  attribute C_S_KEEP_WIDTH : integer;
  attribute C_S_KEEP_WIDTH of xdma_0_xdma_0_core_top : entity is 2;
  attribute C_TIMEOUT0_SEL : string;
  attribute C_TIMEOUT0_SEL of xdma_0_xdma_0_core_top : entity is "4'b1110";
  attribute C_TIMEOUT1_SEL : string;
  attribute C_TIMEOUT1_SEL of xdma_0_xdma_0_core_top : entity is "4'b1111";
  attribute C_TIMEOUT_MULT : string;
  attribute C_TIMEOUT_MULT of xdma_0_xdma_0_core_top : entity is "3'b011";
  attribute C_USER_PTR : string;
  attribute C_USER_PTR of xdma_0_xdma_0_core_top : entity is "16'b0000000011011000";
  attribute C_VSEC_CAP_ADDR : string;
  attribute C_VSEC_CAP_ADDR of xdma_0_xdma_0_core_top : entity is "12'b000100101000";
  attribute C_VSEC_CAP_LAST : string;
  attribute C_VSEC_CAP_LAST of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute C_VSEC_ID : string;
  attribute C_VSEC_ID of xdma_0_xdma_0_core_top : entity is "16'b0000000000000000";
  attribute DAT_WIDTH : integer;
  attribute DAT_WIDTH of xdma_0_xdma_0_core_top : entity is 64;
  attribute DEDICATE_PERST : string;
  attribute DEDICATE_PERST of xdma_0_xdma_0_core_top : entity is "true";
  attribute DEV_PORT_TYPE : integer;
  attribute DEV_PORT_TYPE of xdma_0_xdma_0_core_top : entity is 0;
  attribute DIFF_AXI_ADDR_WIDTH : integer;
  attribute DIFF_AXI_ADDR_WIDTH of xdma_0_xdma_0_core_top : entity is 0;
  attribute DISABLE_BRAM_PIPELINE : string;
  attribute DISABLE_BRAM_PIPELINE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute DISABLE_EQ_SYNCHRONIZER : string;
  attribute DISABLE_EQ_SYNCHRONIZER of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute DMA_2RP : string;
  attribute DMA_2RP of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute DMA_EN : integer;
  attribute DMA_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute DMA_MM : integer;
  attribute DMA_MM of xdma_0_xdma_0_core_top : entity is 1;
  attribute DMA_RESET_SOURCE_SEL : integer;
  attribute DMA_RESET_SOURCE_SEL of xdma_0_xdma_0_core_top : entity is 0;
  attribute DMA_SP : integer;
  attribute DMA_SP of xdma_0_xdma_0_core_top : entity is 0;
  attribute DMA_ST : integer;
  attribute DMA_ST of xdma_0_xdma_0_core_top : entity is 0;
  attribute DRP_CLK_SEL : integer;
  attribute DRP_CLK_SEL of xdma_0_xdma_0_core_top : entity is 0;
  attribute DSC_BYPASS_RD : integer;
  attribute DSC_BYPASS_RD of xdma_0_xdma_0_core_top : entity is 0;
  attribute DSC_BYPASS_WR : integer;
  attribute DSC_BYPASS_WR of xdma_0_xdma_0_core_top : entity is 0;
  attribute ENABLE_ATS_SWITCH : string;
  attribute ENABLE_ATS_SWITCH of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute ENABLE_IBERT : string;
  attribute ENABLE_IBERT of xdma_0_xdma_0_core_top : entity is "false";
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute ENABLE_LTSSM_DBG : string;
  attribute ENABLE_LTSSM_DBG of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute ENABLE_MORE : string;
  attribute ENABLE_MORE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_AXI_MASTER_IF : string;
  attribute EN_AXI_MASTER_IF of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute EN_AXI_SLAVE_IF : string;
  attribute EN_AXI_SLAVE_IF of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute EN_DEBUG_PORTS : string;
  attribute EN_DEBUG_PORTS of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_GT_SELECTION : string;
  attribute EN_GT_SELECTION of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_PCIE_DEBUG_PORTS : string;
  attribute EN_PCIE_DEBUG_PORTS of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_0 : string;
  attribute EN_RCHNL_0 of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute EN_RCHNL_1 : string;
  attribute EN_RCHNL_1 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_2 : string;
  attribute EN_RCHNL_2 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_3 : string;
  attribute EN_RCHNL_3 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_4 : string;
  attribute EN_RCHNL_4 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_5 : string;
  attribute EN_RCHNL_5 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_6 : string;
  attribute EN_RCHNL_6 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_RCHNL_7 : string;
  attribute EN_RCHNL_7 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_TRANSCEIVER_STATUS_PORTS : string;
  attribute EN_TRANSCEIVER_STATUS_PORTS of xdma_0_xdma_0_core_top : entity is "false";
  attribute EN_WCHNL_0 : string;
  attribute EN_WCHNL_0 of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute EN_WCHNL_1 : string;
  attribute EN_WCHNL_1 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_2 : string;
  attribute EN_WCHNL_2 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_3 : string;
  attribute EN_WCHNL_3 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_4 : string;
  attribute EN_WCHNL_4 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_5 : string;
  attribute EN_WCHNL_5 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_6 : string;
  attribute EN_WCHNL_6 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EN_WCHNL_7 : string;
  attribute EN_WCHNL_7 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of xdma_0_xdma_0_core_top : entity is "false";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of xdma_0_xdma_0_core_top : entity is "false";
  attribute EXT_SYS_CLK_BUFG : string;
  attribute EXT_SYS_CLK_BUFG of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute EXT_XVC_VSEC_ENABLE : string;
  attribute EXT_XVC_VSEC_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute FIRSTVF_OFFSET_PF0 : integer;
  attribute FIRSTVF_OFFSET_PF0 of xdma_0_xdma_0_core_top : entity is 0;
  attribute FIRSTVF_OFFSET_PF1 : integer;
  attribute FIRSTVF_OFFSET_PF1 of xdma_0_xdma_0_core_top : entity is 0;
  attribute FIRSTVF_OFFSET_PF2 : integer;
  attribute FIRSTVF_OFFSET_PF2 of xdma_0_xdma_0_core_top : entity is 0;
  attribute FIRSTVF_OFFSET_PF3 : integer;
  attribute FIRSTVF_OFFSET_PF3 of xdma_0_xdma_0_core_top : entity is 0;
  attribute FLR_ENABLE : string;
  attribute FLR_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute FREE_RUN_FREQ : integer;
  attribute FREE_RUN_FREQ of xdma_0_xdma_0_core_top : entity is 0;
  attribute FUNC_MODE : integer;
  attribute FUNC_MODE of xdma_0_xdma_0_core_top : entity is 1;
  attribute GEN4_EIEOS_0S7 : string;
  attribute GEN4_EIEOS_0S7 of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute GTCOM_IN_CORE : integer;
  attribute GTCOM_IN_CORE of xdma_0_xdma_0_core_top : entity is 2;
  attribute GTWIZ_IN_CORE : integer;
  attribute GTWIZ_IN_CORE of xdma_0_xdma_0_core_top : entity is 1;
  attribute H2C_XDMA_CHNL : string;
  attribute H2C_XDMA_CHNL of xdma_0_xdma_0_core_top : entity is "8'b00001111";
  attribute IMPL_TARGET : string;
  attribute IMPL_TARGET of xdma_0_xdma_0_core_top : entity is "SOFT";
  attribute INS_LOSS_PROFILE : string;
  attribute INS_LOSS_PROFILE of xdma_0_xdma_0_core_top : entity is "Add-in_Card";
  attribute INTERRUPT_OUT_WIDTH : integer;
  attribute INTERRUPT_OUT_WIDTH of xdma_0_xdma_0_core_top : entity is 1;
  attribute IS_BOARD_PROJECT : integer;
  attribute IS_BOARD_PROJECT of xdma_0_xdma_0_core_top : entity is 0;
  attribute LEGACY_CFG_EXT_IF : string;
  attribute LEGACY_CFG_EXT_IF of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute MCAP_ENABLEMENT : string;
  attribute MCAP_ENABLEMENT of xdma_0_xdma_0_core_top : entity is "NONE";
  attribute MCAP_FPGA_BITSTREAM_VERSION : integer;
  attribute MCAP_FPGA_BITSTREAM_VERSION of xdma_0_xdma_0_core_top : entity is 0;
  attribute MM_SLAVE_EN : integer;
  attribute MM_SLAVE_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute MSIX_ENABLED : string;
  attribute MSIX_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute MSIX_IMPL_EXT : string;
  attribute MSIX_IMPL_EXT of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute MSIX_PCIE_INTERNAL : integer;
  attribute MSIX_PCIE_INTERNAL of xdma_0_xdma_0_core_top : entity is 0;
  attribute MSIX_RX_DECODE_EN : string;
  attribute MSIX_RX_DECODE_EN of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute MSIX_VEC_NUM : integer;
  attribute MSIX_VEC_NUM of xdma_0_xdma_0_core_top : entity is 1024;
  attribute MSI_ENABLED : string;
  attribute MSI_ENABLED of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute MULTQ_CHNL : string;
  attribute MULTQ_CHNL of xdma_0_xdma_0_core_top : entity is "8'b00000000";
  attribute MULTQ_EN : integer;
  attribute MULTQ_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute MULT_PF_DES : string;
  attribute MULT_PF_DES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute MULT_PF_DESIGN : integer;
  attribute MULT_PF_DESIGN of xdma_0_xdma_0_core_top : entity is 0;
  attribute NUM_PFS : integer;
  attribute NUM_PFS of xdma_0_xdma_0_core_top : entity is 1;
  attribute NUM_VFS_PF0 : integer;
  attribute NUM_VFS_PF0 of xdma_0_xdma_0_core_top : entity is 0;
  attribute NUM_VFS_PF1 : integer;
  attribute NUM_VFS_PF1 of xdma_0_xdma_0_core_top : entity is 0;
  attribute NUM_VFS_PF2 : integer;
  attribute NUM_VFS_PF2 of xdma_0_xdma_0_core_top : entity is 0;
  attribute NUM_VFS_PF3 : integer;
  attribute NUM_VFS_PF3 of xdma_0_xdma_0_core_top : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of xdma_0_xdma_0_core_top : entity is "xdma_0_core_top";
  attribute PCIE3_DRP : string;
  attribute PCIE3_DRP of xdma_0_xdma_0_core_top : entity is "false";
  attribute PCIEBAR_NUM : integer;
  attribute PCIEBAR_NUM of xdma_0_xdma_0_core_top : entity is 6;
  attribute PCIE_BLK_LOCN : integer;
  attribute PCIE_BLK_LOCN of xdma_0_xdma_0_core_top : entity is 0;
  attribute PCIE_BLK_TYPE : integer;
  attribute PCIE_BLK_TYPE of xdma_0_xdma_0_core_top : entity is 0;
  attribute PCIE_ID_IF : string;
  attribute PCIE_ID_IF of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PF0_BAR0_APERTURE_SIZE : string;
  attribute PF0_BAR0_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF0_BAR0_CONTROL : string;
  attribute PF0_BAR0_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b100";
  attribute PF0_BAR1_APERTURE_SIZE : string;
  attribute PF0_BAR1_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00000101";
  attribute PF0_BAR1_CONTROL : string;
  attribute PF0_BAR1_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF0_BAR2_APERTURE_SIZE : string;
  attribute PF0_BAR2_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00000101";
  attribute PF0_BAR2_CONTROL : string;
  attribute PF0_BAR2_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF0_BAR3_APERTURE_SIZE : string;
  attribute PF0_BAR3_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00000101";
  attribute PF0_BAR3_CONTROL : string;
  attribute PF0_BAR3_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF0_BAR4_APERTURE_SIZE : string;
  attribute PF0_BAR4_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00000101";
  attribute PF0_BAR4_CONTROL : string;
  attribute PF0_BAR4_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF0_BAR5_APERTURE_SIZE : string;
  attribute PF0_BAR5_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00000101";
  attribute PF0_BAR5_CONTROL : string;
  attribute PF0_BAR5_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF0_CLASS_CODE : string;
  attribute PF0_CLASS_CODE of xdma_0_xdma_0_core_top : entity is "24'b000001110000000000000001";
  attribute PF0_DEVICE_ID : string;
  attribute PF0_DEVICE_ID of xdma_0_xdma_0_core_top : entity is "16'b0111000000100010";
  attribute PF0_EXPANSION_ROM_APERTURE_SIZE : string;
  attribute PF0_EXPANSION_ROM_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "5'b00000";
  attribute PF0_EXPANSION_ROM_ENABLE : string;
  attribute PF0_EXPANSION_ROM_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PF0_INTERRUPT_PIN : string;
  attribute PF0_INTERRUPT_PIN of xdma_0_xdma_0_core_top : entity is "3'b001";
  attribute PF0_MSIX_TAR_ID : string;
  attribute PF0_MSIX_TAR_ID of xdma_0_xdma_0_core_top : entity is "6'b001000";
  attribute PF0_MSI_CAP_MULTIMSGCAP : integer;
  attribute PF0_MSI_CAP_MULTIMSGCAP of xdma_0_xdma_0_core_top : entity is 0;
  attribute PF0_REVISION_ID : string;
  attribute PF0_REVISION_ID of xdma_0_xdma_0_core_top : entity is "8'b00000000";
  attribute PF0_SUBSYSTEM_ID : string;
  attribute PF0_SUBSYSTEM_ID of xdma_0_xdma_0_core_top : entity is "16'b0000000000000111";
  attribute PF0_SUBSYSTEM_VENDOR_ID : string;
  attribute PF0_SUBSYSTEM_VENDOR_ID of xdma_0_xdma_0_core_top : entity is "16'b0001000011101110";
  attribute PF0_VENDOR_ID : string;
  attribute PF0_VENDOR_ID of xdma_0_xdma_0_core_top : entity is "16'b0001000011101110";
  attribute PF1_BAR0_APERTURE_SIZE : string;
  attribute PF1_BAR0_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00010010";
  attribute PF1_BAR0_CONTROL : string;
  attribute PF1_BAR0_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b100";
  attribute PF1_BAR1_APERTURE_SIZE : string;
  attribute PF1_BAR1_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF1_BAR1_CONTROL : string;
  attribute PF1_BAR1_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF1_BAR2_APERTURE_SIZE : string;
  attribute PF1_BAR2_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF1_BAR2_CONTROL : string;
  attribute PF1_BAR2_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b110";
  attribute PF1_BAR3_APERTURE_SIZE : string;
  attribute PF1_BAR3_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF1_BAR3_CONTROL : string;
  attribute PF1_BAR3_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF1_BAR4_APERTURE_SIZE : string;
  attribute PF1_BAR4_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF1_BAR4_CONTROL : string;
  attribute PF1_BAR4_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b110";
  attribute PF1_BAR5_APERTURE_SIZE : string;
  attribute PF1_BAR5_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001010";
  attribute PF1_BAR5_CONTROL : string;
  attribute PF1_BAR5_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b000";
  attribute PF1_CLASS_CODE : string;
  attribute PF1_CLASS_CODE of xdma_0_xdma_0_core_top : entity is "24'b000001110000000000000001";
  attribute PF1_DEVICE_ID : string;
  attribute PF1_DEVICE_ID of xdma_0_xdma_0_core_top : entity is "16'b1001000100010001";
  attribute PF1_ENABLED : integer;
  attribute PF1_ENABLED of xdma_0_xdma_0_core_top : entity is 0;
  attribute PF1_EXPANSION_ROM_APERTURE_SIZE : string;
  attribute PF1_EXPANSION_ROM_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "5'b00000";
  attribute PF1_EXPANSION_ROM_ENABLE : string;
  attribute PF1_EXPANSION_ROM_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PF1_MSIX_TAR_ID : string;
  attribute PF1_MSIX_TAR_ID of xdma_0_xdma_0_core_top : entity is "6'b001001";
  attribute PF1_PCIEBAR2AXIBAR_0 : string;
  attribute PF1_PCIEBAR2AXIBAR_0 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_1 : string;
  attribute PF1_PCIEBAR2AXIBAR_1 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_2 : string;
  attribute PF1_PCIEBAR2AXIBAR_2 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_3 : string;
  attribute PF1_PCIEBAR2AXIBAR_3 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_4 : string;
  attribute PF1_PCIEBAR2AXIBAR_4 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_5 : string;
  attribute PF1_PCIEBAR2AXIBAR_5 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_6 : string;
  attribute PF1_PCIEBAR2AXIBAR_6 of xdma_0_xdma_0_core_top : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_REVISION_ID : string;
  attribute PF1_REVISION_ID of xdma_0_xdma_0_core_top : entity is "8'b00000000";
  attribute PF1_SUBSYSTEM_ID : string;
  attribute PF1_SUBSYSTEM_ID of xdma_0_xdma_0_core_top : entity is "16'b0000000000000111";
  attribute PF1_SUBSYSTEM_VENDOR_ID : string;
  attribute PF1_SUBSYSTEM_VENDOR_ID of xdma_0_xdma_0_core_top : entity is "16'b0001000011101110";
  attribute PF1_VENDOR_ID : string;
  attribute PF1_VENDOR_ID of xdma_0_xdma_0_core_top : entity is "16'b0001000011101110";
  attribute PF2_DEVICE_ID : string;
  attribute PF2_DEVICE_ID of xdma_0_xdma_0_core_top : entity is "16'b1001001000010001";
  attribute PF2_ENABLED : integer;
  attribute PF2_ENABLED of xdma_0_xdma_0_core_top : entity is 0;
  attribute PF2_REVISION_ID : string;
  attribute PF2_REVISION_ID of xdma_0_xdma_0_core_top : entity is "8'b00000000";
  attribute PF2_SUBSYSTEM_ID : string;
  attribute PF2_SUBSYSTEM_ID of xdma_0_xdma_0_core_top : entity is "16'b0000000000000111";
  attribute PF3_DEVICE_ID : string;
  attribute PF3_DEVICE_ID of xdma_0_xdma_0_core_top : entity is "16'b1001001100010001";
  attribute PF3_ENABLED : integer;
  attribute PF3_ENABLED of xdma_0_xdma_0_core_top : entity is 0;
  attribute PF3_REVISION_ID : string;
  attribute PF3_REVISION_ID of xdma_0_xdma_0_core_top : entity is "8'b00000000";
  attribute PF3_SUBSYSTEM_ID : string;
  attribute PF3_SUBSYSTEM_ID of xdma_0_xdma_0_core_top : entity is "16'b0000000000000111";
  attribute PF_SWAP : string;
  attribute PF_SWAP of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PIPE_DEBUG_EN : string;
  attribute PIPE_DEBUG_EN of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PIPE_LINE_STAGE : integer;
  attribute PIPE_LINE_STAGE of xdma_0_xdma_0_core_top : entity is 2;
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of xdma_0_xdma_0_core_top : entity is "false";
  attribute PLL_TYPE : integer;
  attribute PLL_TYPE of xdma_0_xdma_0_core_top : entity is 2;
  attribute PL_DISABLE_UPCONFIG_CAPABLE : string;
  attribute PL_DISABLE_UPCONFIG_CAPABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute PL_LINK_CAP_MAX_LINK_SPEED : integer;
  attribute PL_LINK_CAP_MAX_LINK_SPEED of xdma_0_xdma_0_core_top : entity is 2;
  attribute PL_LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute PL_LINK_CAP_MAX_LINK_WIDTH of xdma_0_xdma_0_core_top : entity is 2;
  attribute PL_UPSTREAM_FACING : string;
  attribute PL_UPSTREAM_FACING of xdma_0_xdma_0_core_top : entity is "true";
  attribute PMON_EN : integer;
  attribute PMON_EN of xdma_0_xdma_0_core_top : entity is 1;
  attribute PROG_USR_IRQ_VEC_MAP : integer;
  attribute PROG_USR_IRQ_VEC_MAP of xdma_0_xdma_0_core_top : entity is 0;
  attribute RBAR_ENABLE : string;
  attribute RBAR_ENABLE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute RD_CH0_ENABLED : string;
  attribute RD_CH0_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute RD_CH1_ENABLED : string;
  attribute RD_CH1_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute RD_CH2_ENABLED : string;
  attribute RD_CH2_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute RD_CH3_ENABLED : string;
  attribute RD_CH3_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute REF_CLK_FREQ : integer;
  attribute REF_CLK_FREQ of xdma_0_xdma_0_core_top : entity is 0;
  attribute RQ_SEQ_NUM_IGNORE : integer;
  attribute RQ_SEQ_NUM_IGNORE of xdma_0_xdma_0_core_top : entity is 0;
  attribute RUNBIT_FIX : string;
  attribute RUNBIT_FIX of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute RUN_BIT_FIX : integer;
  attribute RUN_BIT_FIX of xdma_0_xdma_0_core_top : entity is 0;
  attribute RX_DETECT : integer;
  attribute RX_DETECT of xdma_0_xdma_0_core_top : entity is 0;
  attribute SELECT_QUAD : string;
  attribute SELECT_QUAD of xdma_0_xdma_0_core_top : entity is "GTH_Quad_128";
  attribute SHARED_LOGIC : integer;
  attribute SHARED_LOGIC of xdma_0_xdma_0_core_top : entity is 0;
  attribute SHARED_LOGIC_BOTH : string;
  attribute SHARED_LOGIC_BOTH of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHARED_LOGIC_BOTH_7XG2 : string;
  attribute SHARED_LOGIC_BOTH_7XG2 of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHARED_LOGIC_CLK : string;
  attribute SHARED_LOGIC_CLK of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHARED_LOGIC_CLK_7XG2 : string;
  attribute SHARED_LOGIC_CLK_7XG2 of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHARED_LOGIC_GTC : string;
  attribute SHARED_LOGIC_GTC of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHARED_LOGIC_GTC_7XG2 : string;
  attribute SHARED_LOGIC_GTC_7XG2 of xdma_0_xdma_0_core_top : entity is "false";
  attribute SHELL_BRIDGE : integer;
  attribute SHELL_BRIDGE of xdma_0_xdma_0_core_top : entity is 0;
  attribute SILICON_REV : string;
  attribute SILICON_REV of xdma_0_xdma_0_core_top : entity is "Pre-Production";
  attribute SOFT_RESET_EN : string;
  attribute SOFT_RESET_EN of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute SPLIT_DMA : string;
  attribute SPLIT_DMA of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute SPLIT_DMA_SINGLE_PF : string;
  attribute SPLIT_DMA_SINGLE_PF of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute SRIOV_ACTIVE_VFS : integer;
  attribute SRIOV_ACTIVE_VFS of xdma_0_xdma_0_core_top : entity is 252;
  attribute SRIOV_EN : integer;
  attribute SRIOV_EN of xdma_0_xdma_0_core_top : entity is 0;
  attribute STS_WIDTH : integer;
  attribute STS_WIDTH of xdma_0_xdma_0_core_top : entity is 8;
  attribute SYS_RESET_POLARITY : integer;
  attribute SYS_RESET_POLARITY of xdma_0_xdma_0_core_top : entity is 0;
  attribute TCQ : integer;
  attribute TCQ of xdma_0_xdma_0_core_top : entity is 1;
  attribute TL_LEGACY_MODE_ENABLE : string;
  attribute TL_LEGACY_MODE_ENABLE of xdma_0_xdma_0_core_top : entity is "false";
  attribute TL_PF_ENABLE_REG : string;
  attribute TL_PF_ENABLE_REG of xdma_0_xdma_0_core_top : entity is "2'b00";
  attribute ULTRASCALE : string;
  attribute ULTRASCALE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute ULTRASCALE_PLUS : string;
  attribute ULTRASCALE_PLUS of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute USER_CLK_FREQ : integer;
  attribute USER_CLK_FREQ of xdma_0_xdma_0_core_top : entity is 1;
  attribute USE_ATTR : integer;
  attribute USE_ATTR of xdma_0_xdma_0_core_top : entity is 0;
  attribute USE_STANDARD_INTERFACES : string;
  attribute USE_STANDARD_INTERFACES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute USRINT_EXPN : string;
  attribute USRINT_EXPN of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute USR_INT_EXPN : integer;
  attribute USR_INT_EXPN of xdma_0_xdma_0_core_top : entity is 0;
  attribute USR_IRQ_EXDES : string;
  attribute USR_IRQ_EXDES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute USR_MPL_SIZE : integer;
  attribute USR_MPL_SIZE of xdma_0_xdma_0_core_top : entity is 4096;
  attribute USR_MRS_SIZE : integer;
  attribute USR_MRS_SIZE of xdma_0_xdma_0_core_top : entity is 4096;
  attribute V7_GEN3 : string;
  attribute V7_GEN3 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute VCU118_BOARD : string;
  attribute VCU118_BOARD of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute VCU1262 : string;
  attribute VCU1262 of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute VERSION : integer;
  attribute VERSION of xdma_0_xdma_0_core_top : entity is 6;
  attribute VF_BARLITE_EXT_PF0 : string;
  attribute VF_BARLITE_EXT_PF0 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute VF_BARLITE_EXT_PF1 : string;
  attribute VF_BARLITE_EXT_PF1 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute VF_BARLITE_EXT_PF2 : string;
  attribute VF_BARLITE_EXT_PF2 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute VF_BARLITE_EXT_PF3 : string;
  attribute VF_BARLITE_EXT_PF3 of xdma_0_xdma_0_core_top : entity is "6'b000000";
  attribute VF_BARLITE_INT_PF0 : string;
  attribute VF_BARLITE_INT_PF0 of xdma_0_xdma_0_core_top : entity is "6'b000001";
  attribute VF_BARLITE_INT_PF1 : string;
  attribute VF_BARLITE_INT_PF1 of xdma_0_xdma_0_core_top : entity is "6'b000001";
  attribute VF_BARLITE_INT_PF2 : string;
  attribute VF_BARLITE_INT_PF2 of xdma_0_xdma_0_core_top : entity is "6'b000001";
  attribute VF_BARLITE_INT_PF3 : string;
  attribute VF_BARLITE_INT_PF3 of xdma_0_xdma_0_core_top : entity is "6'b000001";
  attribute VU9P_BOARD : string;
  attribute VU9P_BOARD of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute VU9P_TUL_EX : string;
  attribute VU9P_TUL_EX of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute WR_CH0_ENABLED : string;
  attribute WR_CH0_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute WR_CH1_ENABLED : string;
  attribute WR_CH1_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute WR_CH2_ENABLED : string;
  attribute WR_CH2_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute WR_CH3_ENABLED : string;
  attribute WR_CH3_ENABLED of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_APERTURE_SIZE : string;
  attribute XDMA_APERTURE_SIZE of xdma_0_xdma_0_core_top : entity is "8'b00001001";
  attribute XDMA_AXILITE_MASTER : string;
  attribute XDMA_AXILITE_MASTER of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_AXILITE_SLAVE : string;
  attribute XDMA_AXILITE_SLAVE of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_AXIST_BYPASS : string;
  attribute XDMA_AXIST_BYPASS of xdma_0_xdma_0_core_top : entity is "TRUE";
  attribute XDMA_AXI_INTF_MM : integer;
  attribute XDMA_AXI_INTF_MM of xdma_0_xdma_0_core_top : entity is 1;
  attribute XDMA_CONTROL : string;
  attribute XDMA_CONTROL of xdma_0_xdma_0_core_top : entity is "3'b100";
  attribute XDMA_DSC_BYPASS : string;
  attribute XDMA_DSC_BYPASS of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_DSC_ENG : integer;
  attribute XDMA_DSC_ENG of xdma_0_xdma_0_core_top : entity is 1;
  attribute XDMA_NON_INCREMENTAL_EXDES : string;
  attribute XDMA_NON_INCREMENTAL_EXDES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_NUM_PCIE_TAG : integer;
  attribute XDMA_NUM_PCIE_TAG of xdma_0_xdma_0_core_top : entity is 64;
  attribute XDMA_NUM_USR_IRQ : integer;
  attribute XDMA_NUM_USR_IRQ of xdma_0_xdma_0_core_top : entity is 1;
  attribute XDMA_PCIE_64BIT_EN : string;
  attribute XDMA_PCIE_64BIT_EN of xdma_0_xdma_0_core_top : entity is "xdma_pcie_64bit_en";
  attribute XDMA_RNUM_CHNL : integer;
  attribute XDMA_RNUM_CHNL of xdma_0_xdma_0_core_top : entity is 1;
  attribute XDMA_RNUM_RIDS : integer;
  attribute XDMA_RNUM_RIDS of xdma_0_xdma_0_core_top : entity is 32;
  attribute XDMA_STS_PORTS : string;
  attribute XDMA_STS_PORTS of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_ST_INFINITE_DESC_EXDES : string;
  attribute XDMA_ST_INFINITE_DESC_EXDES of xdma_0_xdma_0_core_top : entity is "FALSE";
  attribute XDMA_WNUM_CHNL : integer;
  attribute XDMA_WNUM_CHNL of xdma_0_xdma_0_core_top : entity is 1;
  attribute XDMA_WNUM_RIDS : integer;
  attribute XDMA_WNUM_RIDS of xdma_0_xdma_0_core_top : entity is 16;
  attribute xlnx_ref_board : string;
  attribute xlnx_ref_board of xdma_0_xdma_0_core_top : entity is "None";
end xdma_0_xdma_0_core_top;

architecture STRUCTURE of xdma_0_xdma_0_core_top is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^integrated_bloc_reset_o\ : STD_LOGIC;
  signal \^axi_aclk\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of axi_aclk : signal is "true";
  signal \axis_rc\\.tready\ : STD_LOGIC;
  signal blk_cfg_ext_function_number : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute RTL_KEEP of blk_cfg_ext_function_number : signal is "true";
  signal blk_cfg_ext_read_data : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute RTL_KEEP of blk_cfg_ext_read_data : signal is "true";
  signal blk_cfg_ext_read_data_valid : STD_LOGIC;
  attribute RTL_KEEP of blk_cfg_ext_read_data_valid : signal is "true";
  signal blk_cfg_ext_read_received : STD_LOGIC;
  attribute RTL_KEEP of blk_cfg_ext_read_received : signal is "true";
  signal blk_cfg_ext_register_number : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute RTL_KEEP of blk_cfg_ext_register_number : signal is "true";
  signal blk_cfg_ext_write_byte_enable : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute RTL_KEEP of blk_cfg_ext_write_byte_enable : signal is "true";
  signal blk_cfg_ext_write_data : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute RTL_KEEP of blk_cfg_ext_write_data : signal is "true";
  signal blk_cfg_ext_write_received : STD_LOGIC;
  attribute RTL_KEEP of blk_cfg_ext_write_received : signal is "true";
  signal cfg_fc_sel : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cfg_interrupt_int : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cfg_interrupt_msi_int : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal m_axi_araddr_temp : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute RTL_KEEP of m_axi_araddr_temp : signal is "true";
  signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \^m_axi_arburst\ : signal is "true";
  signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axi_arsize\ : signal is "true";
  signal m_axi_awaddr_temp : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute RTL_KEEP of m_axi_awaddr_temp : signal is "true";
  signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP of \^m_axi_awburst\ : signal is "true";
  signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axi_awsize\ : signal is "true";
  signal m_axib_araddr_temp : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute RTL_KEEP of m_axib_araddr_temp : signal is "true";
  signal \^m_axib_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axib_arprot\ : signal is "true";
  signal \^m_axib_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axib_arsize\ : signal is "true";
  signal m_axib_awaddr_temp : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute RTL_KEEP of m_axib_awaddr_temp : signal is "true";
  signal \^m_axib_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axib_awprot\ : signal is "true";
  signal \^m_axib_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \^m_axib_awsize\ : signal is "true";
  signal \^m_axis_rx_tkeep_o\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \^m_axis_rx_tuser_o\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \mi_c2h0_dat\\.radr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_c2h0_dat\\.rdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_c2h0_dat\\.wadr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_c2h0_dat\\.wdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_c2h0_dat\\.wen\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mi_c2h_pcie_dsc_cpld\\.radr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_c2h_pcie_dsc_cpld\\.rdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_c2h_pcie_dsc_cpld\\.wadr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_c2h_pcie_dsc_cpld\\.wdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_c2h_pcie_dsc_cpld\\.wen\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mi_h2c0_dat\\.radr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c0_dat\\.rdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c0_dat\\.wadr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c0_dat\\.wdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c0_dat\\.wen\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mi_h2c0_dat\\.wpar\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \mi_h2c_rd_brg_dat\\.radr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c_rd_brg_dat\\.rdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c_rd_brg_dat\\.wadr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c_rd_brg_dat\\.wdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c_rd_brg_dat\\.wen\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \mi_h2c_wr_brg_dat\\.radr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c_wr_brg_dat\\.rdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c_wr_brg_dat\\.rpar\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \mi_h2c_wr_brg_dat\\.wadr\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \mi_h2c_wr_brg_dat\\.wdat\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \mi_h2c_wr_brg_dat\\.wen\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^msi_enable\ : STD_LOGIC;
  attribute RTL_KEEP of msi_enable : signal is "true";
  signal n_0_0 : STD_LOGIC;
  attribute RTL_KEEP of n_0_0 : signal is "true";
  signal n_0_1 : STD_LOGIC;
  attribute RTL_KEEP of n_0_1 : signal is "true";
  signal n_0_100 : STD_LOGIC;
  attribute RTL_KEEP of n_0_100 : signal is "true";
  signal n_0_101 : STD_LOGIC;
  attribute RTL_KEEP of n_0_101 : signal is "true";
  signal n_0_102 : STD_LOGIC;
  attribute RTL_KEEP of n_0_102 : signal is "true";
  signal n_0_103 : STD_LOGIC;
  attribute RTL_KEEP of n_0_103 : signal is "true";
  signal n_0_104 : STD_LOGIC;
  attribute RTL_KEEP of n_0_104 : signal is "true";
  signal n_0_105 : STD_LOGIC;
  attribute RTL_KEEP of n_0_105 : signal is "true";
  signal n_0_106 : STD_LOGIC;
  attribute RTL_KEEP of n_0_106 : signal is "true";
  signal n_0_107 : STD_LOGIC;
  attribute RTL_KEEP of n_0_107 : signal is "true";
  signal n_0_108 : STD_LOGIC;
  attribute RTL_KEEP of n_0_108 : signal is "true";
  signal n_0_109 : STD_LOGIC;
  attribute RTL_KEEP of n_0_109 : signal is "true";
  signal n_0_110 : STD_LOGIC;
  attribute RTL_KEEP of n_0_110 : signal is "true";
  signal n_0_111 : STD_LOGIC;
  attribute RTL_KEEP of n_0_111 : signal is "true";
  signal n_0_112 : STD_LOGIC;
  attribute RTL_KEEP of n_0_112 : signal is "true";
  signal n_0_113 : STD_LOGIC;
  attribute RTL_KEEP of n_0_113 : signal is "true";
  signal n_0_114 : STD_LOGIC;
  attribute RTL_KEEP of n_0_114 : signal is "true";
  signal n_0_115 : STD_LOGIC;
  attribute RTL_KEEP of n_0_115 : signal is "true";
  signal n_0_116 : STD_LOGIC;
  attribute RTL_KEEP of n_0_116 : signal is "true";
  signal n_0_117 : STD_LOGIC;
  attribute RTL_KEEP of n_0_117 : signal is "true";
  signal n_0_118 : STD_LOGIC;
  attribute RTL_KEEP of n_0_118 : signal is "true";
  signal n_0_119 : STD_LOGIC;
  attribute RTL_KEEP of n_0_119 : signal is "true";
  signal n_0_120 : STD_LOGIC;
  attribute RTL_KEEP of n_0_120 : signal is "true";
  signal n_0_121 : STD_LOGIC;
  attribute RTL_KEEP of n_0_121 : signal is "true";
  signal n_0_122 : STD_LOGIC;
  attribute RTL_KEEP of n_0_122 : signal is "true";
  signal n_0_123 : STD_LOGIC;
  attribute RTL_KEEP of n_0_123 : signal is "true";
  signal n_0_124 : STD_LOGIC;
  attribute RTL_KEEP of n_0_124 : signal is "true";
  signal n_0_125 : STD_LOGIC;
  attribute RTL_KEEP of n_0_125 : signal is "true";
  signal n_0_126 : STD_LOGIC;
  attribute RTL_KEEP of n_0_126 : signal is "true";
  signal n_0_127 : STD_LOGIC;
  attribute RTL_KEEP of n_0_127 : signal is "true";
  signal n_0_128 : STD_LOGIC;
  attribute RTL_KEEP of n_0_128 : signal is "true";
  signal n_0_129 : STD_LOGIC;
  attribute RTL_KEEP of n_0_129 : signal is "true";
  signal n_0_130 : STD_LOGIC;
  attribute RTL_KEEP of n_0_130 : signal is "true";
  signal n_0_131 : STD_LOGIC;
  attribute RTL_KEEP of n_0_131 : signal is "true";
  signal n_0_132 : STD_LOGIC;
  attribute RTL_KEEP of n_0_132 : signal is "true";
  signal n_0_133 : STD_LOGIC;
  attribute RTL_KEEP of n_0_133 : signal is "true";
  signal n_0_134 : STD_LOGIC;
  attribute RTL_KEEP of n_0_134 : signal is "true";
  signal n_0_135 : STD_LOGIC;
  attribute RTL_KEEP of n_0_135 : signal is "true";
  signal n_0_136 : STD_LOGIC;
  attribute RTL_KEEP of n_0_136 : signal is "true";
  signal n_0_137 : STD_LOGIC;
  attribute RTL_KEEP of n_0_137 : signal is "true";
  signal n_0_138 : STD_LOGIC;
  attribute RTL_KEEP of n_0_138 : signal is "true";
  signal n_0_16 : STD_LOGIC;
  attribute RTL_KEEP of n_0_16 : signal is "true";
  signal n_0_17 : STD_LOGIC;
  attribute RTL_KEEP of n_0_17 : signal is "true";
  signal n_0_172 : STD_LOGIC;
  attribute RTL_KEEP of n_0_172 : signal is "true";
  signal n_0_173 : STD_LOGIC;
  attribute RTL_KEEP of n_0_173 : signal is "true";
  signal n_0_174 : STD_LOGIC;
  attribute RTL_KEEP of n_0_174 : signal is "true";
  signal n_0_175 : STD_LOGIC;
  attribute RTL_KEEP of n_0_175 : signal is "true";
  signal n_0_176 : STD_LOGIC;
  attribute RTL_KEEP of n_0_176 : signal is "true";
  signal n_0_177 : STD_LOGIC;
  attribute RTL_KEEP of n_0_177 : signal is "true";
  signal n_0_178 : STD_LOGIC;
  attribute RTL_KEEP of n_0_178 : signal is "true";
  signal n_0_179 : STD_LOGIC;
  attribute RTL_KEEP of n_0_179 : signal is "true";
  signal n_0_18 : STD_LOGIC;
  attribute RTL_KEEP of n_0_18 : signal is "true";
  signal n_0_180 : STD_LOGIC;
  attribute RTL_KEEP of n_0_180 : signal is "true";
  signal n_0_181 : STD_LOGIC;
  attribute RTL_KEEP of n_0_181 : signal is "true";
  signal n_0_182 : STD_LOGIC;
  attribute RTL_KEEP of n_0_182 : signal is "true";
  signal n_0_183 : STD_LOGIC;
  attribute RTL_KEEP of n_0_183 : signal is "true";
  signal n_0_184 : STD_LOGIC;
  attribute RTL_KEEP of n_0_184 : signal is "true";
  signal n_0_185 : STD_LOGIC;
  attribute RTL_KEEP of n_0_185 : signal is "true";
  signal n_0_186 : STD_LOGIC;
  attribute RTL_KEEP of n_0_186 : signal is "true";
  signal n_0_187 : STD_LOGIC;
  attribute RTL_KEEP of n_0_187 : signal is "true";
  signal n_0_188 : STD_LOGIC;
  attribute RTL_KEEP of n_0_188 : signal is "true";
  signal n_0_189 : STD_LOGIC;
  attribute RTL_KEEP of n_0_189 : signal is "true";
  signal n_0_19 : STD_LOGIC;
  attribute RTL_KEEP of n_0_19 : signal is "true";
  signal n_0_190 : STD_LOGIC;
  attribute RTL_KEEP of n_0_190 : signal is "true";
  signal n_0_191 : STD_LOGIC;
  attribute RTL_KEEP of n_0_191 : signal is "true";
  signal n_0_192 : STD_LOGIC;
  attribute RTL_KEEP of n_0_192 : signal is "true";
  signal n_0_193 : STD_LOGIC;
  attribute RTL_KEEP of n_0_193 : signal is "true";
  signal n_0_194 : STD_LOGIC;
  attribute RTL_KEEP of n_0_194 : signal is "true";
  signal n_0_195 : STD_LOGIC;
  attribute RTL_KEEP of n_0_195 : signal is "true";
  signal n_0_196 : STD_LOGIC;
  attribute RTL_KEEP of n_0_196 : signal is "true";
  signal n_0_197 : STD_LOGIC;
  attribute RTL_KEEP of n_0_197 : signal is "true";
  signal n_0_198 : STD_LOGIC;
  attribute RTL_KEEP of n_0_198 : signal is "true";
  signal n_0_199 : STD_LOGIC;
  attribute RTL_KEEP of n_0_199 : signal is "true";
  signal n_0_20 : STD_LOGIC;
  attribute RTL_KEEP of n_0_20 : signal is "true";
  signal n_0_200 : STD_LOGIC;
  attribute RTL_KEEP of n_0_200 : signal is "true";
  signal n_0_201 : STD_LOGIC;
  attribute RTL_KEEP of n_0_201 : signal is "true";
  signal n_0_202 : STD_LOGIC;
  attribute RTL_KEEP of n_0_202 : signal is "true";
  signal n_0_203 : STD_LOGIC;
  attribute RTL_KEEP of n_0_203 : signal is "true";
  signal n_0_204 : STD_LOGIC;
  attribute RTL_KEEP of n_0_204 : signal is "true";
  signal n_0_205 : STD_LOGIC;
  attribute RTL_KEEP of n_0_205 : signal is "true";
  signal n_0_206 : STD_LOGIC;
  attribute RTL_KEEP of n_0_206 : signal is "true";
  signal n_0_207 : STD_LOGIC;
  attribute RTL_KEEP of n_0_207 : signal is "true";
  signal n_0_208 : STD_LOGIC;
  attribute RTL_KEEP of n_0_208 : signal is "true";
  signal n_0_209 : STD_LOGIC;
  attribute RTL_KEEP of n_0_209 : signal is "true";
  signal n_0_21 : STD_LOGIC;
  attribute RTL_KEEP of n_0_21 : signal is "true";
  signal n_0_210 : STD_LOGIC;
  attribute RTL_KEEP of n_0_210 : signal is "true";
  signal n_0_211 : STD_LOGIC;
  attribute RTL_KEEP of n_0_211 : signal is "true";
  signal n_0_212 : STD_LOGIC;
  attribute RTL_KEEP of n_0_212 : signal is "true";
  signal n_0_213 : STD_LOGIC;
  attribute RTL_KEEP of n_0_213 : signal is "true";
  signal n_0_214 : STD_LOGIC;
  attribute RTL_KEEP of n_0_214 : signal is "true";
  signal n_0_215 : STD_LOGIC;
  attribute RTL_KEEP of n_0_215 : signal is "true";
  signal n_0_216 : STD_LOGIC;
  attribute RTL_KEEP of n_0_216 : signal is "true";
  signal n_0_217 : STD_LOGIC;
  attribute RTL_KEEP of n_0_217 : signal is "true";
  signal n_0_218 : STD_LOGIC;
  attribute RTL_KEEP of n_0_218 : signal is "true";
  signal n_0_219 : STD_LOGIC;
  attribute RTL_KEEP of n_0_219 : signal is "true";
  signal n_0_22 : STD_LOGIC;
  attribute RTL_KEEP of n_0_22 : signal is "true";
  signal n_0_220 : STD_LOGIC;
  attribute RTL_KEEP of n_0_220 : signal is "true";
  signal n_0_221 : STD_LOGIC;
  attribute RTL_KEEP of n_0_221 : signal is "true";
  signal n_0_222 : STD_LOGIC;
  attribute RTL_KEEP of n_0_222 : signal is "true";
  signal n_0_223 : STD_LOGIC;
  attribute RTL_KEEP of n_0_223 : signal is "true";
  signal n_0_224 : STD_LOGIC;
  attribute RTL_KEEP of n_0_224 : signal is "true";
  signal n_0_225 : STD_LOGIC;
  attribute RTL_KEEP of n_0_225 : signal is "true";
  signal n_0_226 : STD_LOGIC;
  attribute RTL_KEEP of n_0_226 : signal is "true";
  signal n_0_227 : STD_LOGIC;
  attribute RTL_KEEP of n_0_227 : signal is "true";
  signal n_0_228 : STD_LOGIC;
  attribute RTL_KEEP of n_0_228 : signal is "true";
  signal n_0_229 : STD_LOGIC;
  attribute RTL_KEEP of n_0_229 : signal is "true";
  signal n_0_23 : STD_LOGIC;
  attribute RTL_KEEP of n_0_23 : signal is "true";
  signal n_0_230 : STD_LOGIC;
  attribute RTL_KEEP of n_0_230 : signal is "true";
  signal n_0_231 : STD_LOGIC;
  attribute RTL_KEEP of n_0_231 : signal is "true";
  signal n_0_232 : STD_LOGIC;
  attribute RTL_KEEP of n_0_232 : signal is "true";
  signal n_0_233 : STD_LOGIC;
  attribute RTL_KEEP of n_0_233 : signal is "true";
  signal n_0_234 : STD_LOGIC;
  attribute RTL_KEEP of n_0_234 : signal is "true";
  signal n_0_235 : STD_LOGIC;
  attribute RTL_KEEP of n_0_235 : signal is "true";
  signal n_0_236 : STD_LOGIC;
  attribute RTL_KEEP of n_0_236 : signal is "true";
  signal n_0_237 : STD_LOGIC;
  attribute RTL_KEEP of n_0_237 : signal is "true";
  signal n_0_238 : STD_LOGIC;
  attribute RTL_KEEP of n_0_238 : signal is "true";
  signal n_0_239 : STD_LOGIC;
  attribute RTL_KEEP of n_0_239 : signal is "true";
  signal n_0_240 : STD_LOGIC;
  attribute RTL_KEEP of n_0_240 : signal is "true";
  signal n_0_241 : STD_LOGIC;
  attribute RTL_KEEP of n_0_241 : signal is "true";
  signal n_0_242 : STD_LOGIC;
  attribute RTL_KEEP of n_0_242 : signal is "true";
  signal n_0_243 : STD_LOGIC;
  attribute RTL_KEEP of n_0_243 : signal is "true";
  signal n_0_244 : STD_LOGIC;
  attribute RTL_KEEP of n_0_244 : signal is "true";
  signal n_0_245 : STD_LOGIC;
  attribute RTL_KEEP of n_0_245 : signal is "true";
  signal n_0_246 : STD_LOGIC;
  attribute RTL_KEEP of n_0_246 : signal is "true";
  signal n_0_247 : STD_LOGIC;
  attribute RTL_KEEP of n_0_247 : signal is "true";
  signal n_0_248 : STD_LOGIC;
  attribute RTL_KEEP of n_0_248 : signal is "true";
  signal n_0_249 : STD_LOGIC;
  attribute RTL_KEEP of n_0_249 : signal is "true";
  signal n_0_250 : STD_LOGIC;
  attribute RTL_KEEP of n_0_250 : signal is "true";
  signal n_0_251 : STD_LOGIC;
  attribute RTL_KEEP of n_0_251 : signal is "true";
  signal n_0_252 : STD_LOGIC;
  attribute RTL_KEEP of n_0_252 : signal is "true";
  signal n_0_253 : STD_LOGIC;
  attribute RTL_KEEP of n_0_253 : signal is "true";
  signal n_0_254 : STD_LOGIC;
  attribute RTL_KEEP of n_0_254 : signal is "true";
  signal n_0_255 : STD_LOGIC;
  attribute RTL_KEEP of n_0_255 : signal is "true";
  signal n_0_256 : STD_LOGIC;
  attribute RTL_KEEP of n_0_256 : signal is "true";
  signal n_0_257 : STD_LOGIC;
  attribute RTL_KEEP of n_0_257 : signal is "true";
  signal n_0_258 : STD_LOGIC;
  attribute RTL_KEEP of n_0_258 : signal is "true";
  signal n_0_259 : STD_LOGIC;
  attribute RTL_KEEP of n_0_259 : signal is "true";
  signal n_0_260 : STD_LOGIC;
  attribute RTL_KEEP of n_0_260 : signal is "true";
  signal n_0_261 : STD_LOGIC;
  attribute RTL_KEEP of n_0_261 : signal is "true";
  signal n_0_262 : STD_LOGIC;
  attribute RTL_KEEP of n_0_262 : signal is "true";
  signal n_0_263 : STD_LOGIC;
  attribute RTL_KEEP of n_0_263 : signal is "true";
  signal n_0_264 : STD_LOGIC;
  attribute RTL_KEEP of n_0_264 : signal is "true";
  signal n_0_265 : STD_LOGIC;
  attribute RTL_KEEP of n_0_265 : signal is "true";
  signal n_0_266 : STD_LOGIC;
  attribute RTL_KEEP of n_0_266 : signal is "true";
  signal n_0_267 : STD_LOGIC;
  attribute RTL_KEEP of n_0_267 : signal is "true";
  signal n_0_268 : STD_LOGIC;
  attribute RTL_KEEP of n_0_268 : signal is "true";
  signal n_0_269 : STD_LOGIC;
  attribute RTL_KEEP of n_0_269 : signal is "true";
  signal n_0_270 : STD_LOGIC;
  attribute RTL_KEEP of n_0_270 : signal is "true";
  signal n_0_271 : STD_LOGIC;
  attribute RTL_KEEP of n_0_271 : signal is "true";
  signal n_0_272 : STD_LOGIC;
  attribute RTL_KEEP of n_0_272 : signal is "true";
  signal n_0_273 : STD_LOGIC;
  attribute RTL_KEEP of n_0_273 : signal is "true";
  signal n_0_274 : STD_LOGIC;
  attribute RTL_KEEP of n_0_274 : signal is "true";
  signal n_0_275 : STD_LOGIC;
  attribute RTL_KEEP of n_0_275 : signal is "true";
  signal n_0_276 : STD_LOGIC;
  attribute RTL_KEEP of n_0_276 : signal is "true";
  signal n_0_277 : STD_LOGIC;
  attribute RTL_KEEP of n_0_277 : signal is "true";
  signal n_0_278 : STD_LOGIC;
  attribute RTL_KEEP of n_0_278 : signal is "true";
  signal n_0_279 : STD_LOGIC;
  attribute RTL_KEEP of n_0_279 : signal is "true";
  signal n_0_280 : STD_LOGIC;
  attribute RTL_KEEP of n_0_280 : signal is "true";
  signal n_0_281 : STD_LOGIC;
  attribute RTL_KEEP of n_0_281 : signal is "true";
  signal n_0_282 : STD_LOGIC;
  attribute RTL_KEEP of n_0_282 : signal is "true";
  signal n_0_283 : STD_LOGIC;
  attribute RTL_KEEP of n_0_283 : signal is "true";
  signal n_0_284 : STD_LOGIC;
  attribute RTL_KEEP of n_0_284 : signal is "true";
  signal n_0_285 : STD_LOGIC;
  attribute RTL_KEEP of n_0_285 : signal is "true";
  signal n_0_286 : STD_LOGIC;
  attribute RTL_KEEP of n_0_286 : signal is "true";
  signal n_0_287 : STD_LOGIC;
  attribute RTL_KEEP of n_0_287 : signal is "true";
  signal n_0_288 : STD_LOGIC;
  attribute RTL_KEEP of n_0_288 : signal is "true";
  signal n_0_289 : STD_LOGIC;
  attribute RTL_KEEP of n_0_289 : signal is "true";
  signal n_0_290 : STD_LOGIC;
  attribute RTL_KEEP of n_0_290 : signal is "true";
  signal n_0_291 : STD_LOGIC;
  attribute RTL_KEEP of n_0_291 : signal is "true";
  signal n_0_292 : STD_LOGIC;
  attribute RTL_KEEP of n_0_292 : signal is "true";
  signal n_0_293 : STD_LOGIC;
  attribute RTL_KEEP of n_0_293 : signal is "true";
  signal n_0_294 : STD_LOGIC;
  attribute RTL_KEEP of n_0_294 : signal is "true";
  signal n_0_295 : STD_LOGIC;
  attribute RTL_KEEP of n_0_295 : signal is "true";
  signal n_0_296 : STD_LOGIC;
  attribute RTL_KEEP of n_0_296 : signal is "true";
  signal n_0_297 : STD_LOGIC;
  attribute RTL_KEEP of n_0_297 : signal is "true";
  signal n_0_298 : STD_LOGIC;
  attribute RTL_KEEP of n_0_298 : signal is "true";
  signal n_0_299 : STD_LOGIC;
  attribute RTL_KEEP of n_0_299 : signal is "true";
  signal n_0_300 : STD_LOGIC;
  attribute RTL_KEEP of n_0_300 : signal is "true";
  signal n_0_301 : STD_LOGIC;
  attribute RTL_KEEP of n_0_301 : signal is "true";
  signal n_0_302 : STD_LOGIC;
  attribute RTL_KEEP of n_0_302 : signal is "true";
  signal n_0_303 : STD_LOGIC;
  attribute RTL_KEEP of n_0_303 : signal is "true";
  signal n_0_304 : STD_LOGIC;
  attribute RTL_KEEP of n_0_304 : signal is "true";
  signal n_0_305 : STD_LOGIC;
  attribute RTL_KEEP of n_0_305 : signal is "true";
  signal n_0_306 : STD_LOGIC;
  attribute RTL_KEEP of n_0_306 : signal is "true";
  signal n_0_307 : STD_LOGIC;
  attribute RTL_KEEP of n_0_307 : signal is "true";
  signal n_0_308 : STD_LOGIC;
  attribute RTL_KEEP of n_0_308 : signal is "true";
  signal n_0_309 : STD_LOGIC;
  attribute RTL_KEEP of n_0_309 : signal is "true";
  signal n_0_310 : STD_LOGIC;
  attribute RTL_KEEP of n_0_310 : signal is "true";
  signal n_0_311 : STD_LOGIC;
  attribute RTL_KEEP of n_0_311 : signal is "true";
  signal n_0_312 : STD_LOGIC;
  attribute RTL_KEEP of n_0_312 : signal is "true";
  signal n_0_313 : STD_LOGIC;
  attribute RTL_KEEP of n_0_313 : signal is "true";
  signal n_0_314 : STD_LOGIC;
  attribute RTL_KEEP of n_0_314 : signal is "true";
  signal n_0_315 : STD_LOGIC;
  attribute RTL_KEEP of n_0_315 : signal is "true";
  signal n_0_316 : STD_LOGIC;
  attribute RTL_KEEP of n_0_316 : signal is "true";
  signal n_0_317 : STD_LOGIC;
  attribute RTL_KEEP of n_0_317 : signal is "true";
  signal n_0_318 : STD_LOGIC;
  attribute RTL_KEEP of n_0_318 : signal is "true";
  signal n_0_319 : STD_LOGIC;
  attribute RTL_KEEP of n_0_319 : signal is "true";
  signal n_0_320 : STD_LOGIC;
  attribute RTL_KEEP of n_0_320 : signal is "true";
  signal n_0_321 : STD_LOGIC;
  attribute RTL_KEEP of n_0_321 : signal is "true";
  signal n_0_322 : STD_LOGIC;
  attribute RTL_KEEP of n_0_322 : signal is "true";
  signal n_0_323 : STD_LOGIC;
  attribute RTL_KEEP of n_0_323 : signal is "true";
  signal n_0_324 : STD_LOGIC;
  attribute RTL_KEEP of n_0_324 : signal is "true";
  signal n_0_325 : STD_LOGIC;
  attribute RTL_KEEP of n_0_325 : signal is "true";
  signal n_0_326 : STD_LOGIC;
  attribute RTL_KEEP of n_0_326 : signal is "true";
  signal n_0_327 : STD_LOGIC;
  attribute RTL_KEEP of n_0_327 : signal is "true";
  signal n_0_328 : STD_LOGIC;
  attribute RTL_KEEP of n_0_328 : signal is "true";
  signal n_0_329 : STD_LOGIC;
  attribute RTL_KEEP of n_0_329 : signal is "true";
  signal n_0_330 : STD_LOGIC;
  attribute RTL_KEEP of n_0_330 : signal is "true";
  signal n_0_331 : STD_LOGIC;
  attribute RTL_KEEP of n_0_331 : signal is "true";
  signal n_0_332 : STD_LOGIC;
  attribute RTL_KEEP of n_0_332 : signal is "true";
  signal n_0_333 : STD_LOGIC;
  attribute RTL_KEEP of n_0_333 : signal is "true";
  signal n_0_334 : STD_LOGIC;
  attribute RTL_KEEP of n_0_334 : signal is "true";
  signal n_0_335 : STD_LOGIC;
  attribute RTL_KEEP of n_0_335 : signal is "true";
  signal n_0_392 : STD_LOGIC;
  attribute RTL_KEEP of n_0_392 : signal is "true";
  signal n_0_393 : STD_LOGIC;
  attribute RTL_KEEP of n_0_393 : signal is "true";
  signal n_0_394 : STD_LOGIC;
  attribute RTL_KEEP of n_0_394 : signal is "true";
  signal n_0_395 : STD_LOGIC;
  attribute RTL_KEEP of n_0_395 : signal is "true";
  signal n_0_396 : STD_LOGIC;
  attribute RTL_KEEP of n_0_396 : signal is "true";
  signal n_0_397 : STD_LOGIC;
  attribute RTL_KEEP of n_0_397 : signal is "true";
  signal n_0_398 : STD_LOGIC;
  attribute RTL_KEEP of n_0_398 : signal is "true";
  signal n_0_399 : STD_LOGIC;
  attribute RTL_KEEP of n_0_399 : signal is "true";
  signal n_0_400 : STD_LOGIC;
  attribute RTL_KEEP of n_0_400 : signal is "true";
  signal n_0_401 : STD_LOGIC;
  attribute RTL_KEEP of n_0_401 : signal is "true";
  signal n_0_402 : STD_LOGIC;
  attribute RTL_KEEP of n_0_402 : signal is "true";
  signal n_0_403 : STD_LOGIC;
  attribute RTL_KEEP of n_0_403 : signal is "true";
  signal n_0_404 : STD_LOGIC;
  attribute RTL_KEEP of n_0_404 : signal is "true";
  signal n_0_405 : STD_LOGIC;
  attribute RTL_KEEP of n_0_405 : signal is "true";
  signal n_0_406 : STD_LOGIC;
  attribute RTL_KEEP of n_0_406 : signal is "true";
  signal n_0_407 : STD_LOGIC;
  attribute RTL_KEEP of n_0_407 : signal is "true";
  signal n_0_408 : STD_LOGIC;
  attribute RTL_KEEP of n_0_408 : signal is "true";
  signal n_0_409 : STD_LOGIC;
  attribute RTL_KEEP of n_0_409 : signal is "true";
  signal n_0_410 : STD_LOGIC;
  attribute RTL_KEEP of n_0_410 : signal is "true";
  signal n_0_411 : STD_LOGIC;
  attribute RTL_KEEP of n_0_411 : signal is "true";
  signal n_0_412 : STD_LOGIC;
  attribute RTL_KEEP of n_0_412 : signal is "true";
  signal n_0_413 : STD_LOGIC;
  attribute RTL_KEEP of n_0_413 : signal is "true";
  signal n_0_414 : STD_LOGIC;
  attribute RTL_KEEP of n_0_414 : signal is "true";
  signal n_0_415 : STD_LOGIC;
  attribute RTL_KEEP of n_0_415 : signal is "true";
  signal n_0_416 : STD_LOGIC;
  attribute RTL_KEEP of n_0_416 : signal is "true";
  signal n_0_417 : STD_LOGIC;
  attribute RTL_KEEP of n_0_417 : signal is "true";
  signal n_0_418 : STD_LOGIC;
  attribute RTL_KEEP of n_0_418 : signal is "true";
  signal n_0_419 : STD_LOGIC;
  attribute RTL_KEEP of n_0_419 : signal is "true";
  signal n_0_42 : STD_LOGIC;
  attribute RTL_KEEP of n_0_42 : signal is "true";
  signal n_0_420 : STD_LOGIC;
  attribute RTL_KEEP of n_0_420 : signal is "true";
  signal n_0_421 : STD_LOGIC;
  attribute RTL_KEEP of n_0_421 : signal is "true";
  signal n_0_422 : STD_LOGIC;
  attribute RTL_KEEP of n_0_422 : signal is "true";
  signal n_0_423 : STD_LOGIC;
  attribute RTL_KEEP of n_0_423 : signal is "true";
  signal n_0_424 : STD_LOGIC;
  attribute RTL_KEEP of n_0_424 : signal is "true";
  signal n_0_425 : STD_LOGIC;
  attribute RTL_KEEP of n_0_425 : signal is "true";
  signal n_0_426 : STD_LOGIC;
  attribute RTL_KEEP of n_0_426 : signal is "true";
  signal n_0_427 : STD_LOGIC;
  attribute RTL_KEEP of n_0_427 : signal is "true";
  signal n_0_428 : STD_LOGIC;
  attribute RTL_KEEP of n_0_428 : signal is "true";
  signal n_0_429 : STD_LOGIC;
  attribute RTL_KEEP of n_0_429 : signal is "true";
  signal n_0_43 : STD_LOGIC;
  attribute RTL_KEEP of n_0_43 : signal is "true";
  signal n_0_430 : STD_LOGIC;
  attribute RTL_KEEP of n_0_430 : signal is "true";
  signal n_0_431 : STD_LOGIC;
  attribute RTL_KEEP of n_0_431 : signal is "true";
  signal n_0_432 : STD_LOGIC;
  attribute RTL_KEEP of n_0_432 : signal is "true";
  signal n_0_433 : STD_LOGIC;
  attribute RTL_KEEP of n_0_433 : signal is "true";
  signal n_0_434 : STD_LOGIC;
  attribute RTL_KEEP of n_0_434 : signal is "true";
  signal n_0_435 : STD_LOGIC;
  attribute RTL_KEEP of n_0_435 : signal is "true";
  signal n_0_436 : STD_LOGIC;
  attribute RTL_KEEP of n_0_436 : signal is "true";
  signal n_0_437 : STD_LOGIC;
  attribute RTL_KEEP of n_0_437 : signal is "true";
  signal n_0_438 : STD_LOGIC;
  attribute RTL_KEEP of n_0_438 : signal is "true";
  signal n_0_439 : STD_LOGIC;
  attribute RTL_KEEP of n_0_439 : signal is "true";
  signal n_0_44 : STD_LOGIC;
  attribute RTL_KEEP of n_0_44 : signal is "true";
  signal n_0_440 : STD_LOGIC;
  attribute RTL_KEEP of n_0_440 : signal is "true";
  signal n_0_441 : STD_LOGIC;
  attribute RTL_KEEP of n_0_441 : signal is "true";
  signal n_0_442 : STD_LOGIC;
  attribute RTL_KEEP of n_0_442 : signal is "true";
  signal n_0_443 : STD_LOGIC;
  attribute RTL_KEEP of n_0_443 : signal is "true";
  signal n_0_444 : STD_LOGIC;
  attribute RTL_KEEP of n_0_444 : signal is "true";
  signal n_0_445 : STD_LOGIC;
  attribute RTL_KEEP of n_0_445 : signal is "true";
  signal n_0_446 : STD_LOGIC;
  attribute RTL_KEEP of n_0_446 : signal is "true";
  signal n_0_447 : STD_LOGIC;
  attribute RTL_KEEP of n_0_447 : signal is "true";
  signal n_0_448 : STD_LOGIC;
  attribute RTL_KEEP of n_0_448 : signal is "true";
  signal n_0_449 : STD_LOGIC;
  attribute RTL_KEEP of n_0_449 : signal is "true";
  signal n_0_45 : STD_LOGIC;
  attribute RTL_KEEP of n_0_45 : signal is "true";
  signal n_0_450 : STD_LOGIC;
  attribute RTL_KEEP of n_0_450 : signal is "true";
  signal n_0_451 : STD_LOGIC;
  attribute RTL_KEEP of n_0_451 : signal is "true";
  signal n_0_452 : STD_LOGIC;
  attribute RTL_KEEP of n_0_452 : signal is "true";
  signal n_0_453 : STD_LOGIC;
  attribute RTL_KEEP of n_0_453 : signal is "true";
  signal n_0_454 : STD_LOGIC;
  attribute RTL_KEEP of n_0_454 : signal is "true";
  signal n_0_455 : STD_LOGIC;
  attribute RTL_KEEP of n_0_455 : signal is "true";
  signal n_0_456 : STD_LOGIC;
  attribute RTL_KEEP of n_0_456 : signal is "true";
  signal n_0_457 : STD_LOGIC;
  attribute RTL_KEEP of n_0_457 : signal is "true";
  signal n_0_458 : STD_LOGIC;
  attribute RTL_KEEP of n_0_458 : signal is "true";
  signal n_0_459 : STD_LOGIC;
  attribute RTL_KEEP of n_0_459 : signal is "true";
  signal n_0_46 : STD_LOGIC;
  attribute RTL_KEEP of n_0_46 : signal is "true";
  signal n_0_460 : STD_LOGIC;
  attribute RTL_KEEP of n_0_460 : signal is "true";
  signal n_0_461 : STD_LOGIC;
  attribute RTL_KEEP of n_0_461 : signal is "true";
  signal n_0_462 : STD_LOGIC;
  attribute RTL_KEEP of n_0_462 : signal is "true";
  signal n_0_463 : STD_LOGIC;
  attribute RTL_KEEP of n_0_463 : signal is "true";
  signal n_0_464 : STD_LOGIC;
  attribute RTL_KEEP of n_0_464 : signal is "true";
  signal n_0_465 : STD_LOGIC;
  attribute RTL_KEEP of n_0_465 : signal is "true";
  signal n_0_466 : STD_LOGIC;
  attribute RTL_KEEP of n_0_466 : signal is "true";
  signal n_0_467 : STD_LOGIC;
  attribute RTL_KEEP of n_0_467 : signal is "true";
  signal n_0_468 : STD_LOGIC;
  attribute RTL_KEEP of n_0_468 : signal is "true";
  signal n_0_469 : STD_LOGIC;
  attribute RTL_KEEP of n_0_469 : signal is "true";
  signal n_0_47 : STD_LOGIC;
  attribute RTL_KEEP of n_0_47 : signal is "true";
  signal n_0_470 : STD_LOGIC;
  attribute RTL_KEEP of n_0_470 : signal is "true";
  signal n_0_471 : STD_LOGIC;
  attribute RTL_KEEP of n_0_471 : signal is "true";
  signal n_0_472 : STD_LOGIC;
  attribute RTL_KEEP of n_0_472 : signal is "true";
  signal n_0_473 : STD_LOGIC;
  attribute RTL_KEEP of n_0_473 : signal is "true";
  signal n_0_474 : STD_LOGIC;
  attribute RTL_KEEP of n_0_474 : signal is "true";
  signal n_0_475 : STD_LOGIC;
  attribute RTL_KEEP of n_0_475 : signal is "true";
  signal n_0_476 : STD_LOGIC;
  attribute RTL_KEEP of n_0_476 : signal is "true";
  signal n_0_477 : STD_LOGIC;
  attribute RTL_KEEP of n_0_477 : signal is "true";
  signal n_0_48 : STD_LOGIC;
  attribute RTL_KEEP of n_0_48 : signal is "true";
  signal n_0_49 : STD_LOGIC;
  attribute RTL_KEEP of n_0_49 : signal is "true";
  signal n_0_62 : STD_LOGIC;
  attribute RTL_KEEP of n_0_62 : signal is "true";
  signal n_0_63 : STD_LOGIC;
  attribute RTL_KEEP of n_0_63 : signal is "true";
  signal n_0_64 : STD_LOGIC;
  attribute RTL_KEEP of n_0_64 : signal is "true";
  signal n_0_65 : STD_LOGIC;
  attribute RTL_KEEP of n_0_65 : signal is "true";
  signal n_0_66 : STD_LOGIC;
  attribute RTL_KEEP of n_0_66 : signal is "true";
  signal n_0_67 : STD_LOGIC;
  attribute RTL_KEEP of n_0_67 : signal is "true";
  signal n_0_68 : STD_LOGIC;
  attribute RTL_KEEP of n_0_68 : signal is "true";
  signal n_0_69 : STD_LOGIC;
  attribute RTL_KEEP of n_0_69 : signal is "true";
  signal n_0_78 : STD_LOGIC;
  attribute RTL_KEEP of n_0_78 : signal is "true";
  signal n_0_79 : STD_LOGIC;
  attribute RTL_KEEP of n_0_79 : signal is "true";
  signal n_0_80 : STD_LOGIC;
  attribute RTL_KEEP of n_0_80 : signal is "true";
  signal n_0_81 : STD_LOGIC;
  attribute RTL_KEEP of n_0_81 : signal is "true";
  signal n_0_82 : STD_LOGIC;
  attribute RTL_KEEP of n_0_82 : signal is "true";
  signal n_0_83 : STD_LOGIC;
  attribute RTL_KEEP of n_0_83 : signal is "true";
  signal n_0_84 : STD_LOGIC;
  attribute RTL_KEEP of n_0_84 : signal is "true";
  signal n_0_85 : STD_LOGIC;
  attribute RTL_KEEP of n_0_85 : signal is "true";
  signal n_0_86 : STD_LOGIC;
  attribute RTL_KEEP of n_0_86 : signal is "true";
  signal n_0_87 : STD_LOGIC;
  attribute RTL_KEEP of n_0_87 : signal is "true";
  signal n_0_88 : STD_LOGIC;
  attribute RTL_KEEP of n_0_88 : signal is "true";
  signal n_0_89 : STD_LOGIC;
  attribute RTL_KEEP of n_0_89 : signal is "true";
  signal n_0_90 : STD_LOGIC;
  attribute RTL_KEEP of n_0_90 : signal is "true";
  signal n_0_91 : STD_LOGIC;
  attribute RTL_KEEP of n_0_91 : signal is "true";
  signal n_0_92 : STD_LOGIC;
  attribute RTL_KEEP of n_0_92 : signal is "true";
  signal n_0_93 : STD_LOGIC;
  attribute RTL_KEEP of n_0_93 : signal is "true";
  signal n_0_94 : STD_LOGIC;
  attribute RTL_KEEP of n_0_94 : signal is "true";
  signal n_0_95 : STD_LOGIC;
  attribute RTL_KEEP of n_0_95 : signal is "true";
  signal n_0_96 : STD_LOGIC;
  attribute RTL_KEEP of n_0_96 : signal is "true";
  signal n_0_97 : STD_LOGIC;
  attribute RTL_KEEP of n_0_97 : signal is "true";
  signal n_0_98 : STD_LOGIC;
  attribute RTL_KEEP of n_0_98 : signal is "true";
  signal n_0_99 : STD_LOGIC;
  attribute RTL_KEEP of n_0_99 : signal is "true";
  signal pcie_cq_np_req : STD_LOGIC;
  signal \pcie_dma_in\\.cfg_fc_nph\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pcie_dma_in\\.cfg_interrupt_sent\ : STD_LOGIC;
  signal \pcie_dma_in\\.cfg_phy_link_down\ : STD_LOGIC;
  signal pcie_rq_seq_num0 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal pcie_rq_seq_num_vld0 : STD_LOGIC;
  signal sys_rst_n_reg : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of sys_rst_n_reg : signal is "true";
  signal sys_rst_n_reg2 : STD_LOGIC;
  attribute async_reg of sys_rst_n_reg2 : signal is "true";
  signal sys_rst_n_reg_i_1_n_0 : STD_LOGIC;
  signal udma_wrapper_n_10730 : STD_LOGIC;
  signal udma_wrapper_n_10731 : STD_LOGIC;
  signal udma_wrapper_n_10732 : STD_LOGIC;
  signal udma_wrapper_n_10733 : STD_LOGIC;
  signal udma_wrapper_n_10734 : STD_LOGIC;
  signal udma_wrapper_n_10735 : STD_LOGIC;
  signal udma_wrapper_n_10736 : STD_LOGIC;
  signal udma_wrapper_n_10737 : STD_LOGIC;
  signal udma_wrapper_n_10738 : STD_LOGIC;
  signal udma_wrapper_n_10739 : STD_LOGIC;
  signal udma_wrapper_n_10740 : STD_LOGIC;
  signal udma_wrapper_n_10741 : STD_LOGIC;
  signal udma_wrapper_n_10742 : STD_LOGIC;
  signal udma_wrapper_n_10743 : STD_LOGIC;
  signal udma_wrapper_n_10744 : STD_LOGIC;
  signal udma_wrapper_n_10745 : STD_LOGIC;
  signal udma_wrapper_n_10746 : STD_LOGIC;
  signal udma_wrapper_n_10747 : STD_LOGIC;
  signal udma_wrapper_n_10748 : STD_LOGIC;
  signal udma_wrapper_n_10749 : STD_LOGIC;
  signal udma_wrapper_n_10750 : STD_LOGIC;
  signal udma_wrapper_n_10751 : STD_LOGIC;
  signal udma_wrapper_n_10752 : STD_LOGIC;
  signal udma_wrapper_n_10753 : STD_LOGIC;
  signal udma_wrapper_n_10754 : STD_LOGIC;
  signal udma_wrapper_n_10755 : STD_LOGIC;
  signal udma_wrapper_n_10756 : STD_LOGIC;
  signal udma_wrapper_n_10757 : STD_LOGIC;
  signal udma_wrapper_n_10758 : STD_LOGIC;
  signal udma_wrapper_n_10759 : STD_LOGIC;
  signal udma_wrapper_n_10760 : STD_LOGIC;
  signal udma_wrapper_n_10761 : STD_LOGIC;
  signal udma_wrapper_n_10762 : STD_LOGIC;
  signal udma_wrapper_n_10763 : STD_LOGIC;
  signal udma_wrapper_n_10764 : STD_LOGIC;
  signal udma_wrapper_n_10765 : STD_LOGIC;
  signal udma_wrapper_n_10766 : STD_LOGIC;
  signal udma_wrapper_n_10767 : STD_LOGIC;
  signal udma_wrapper_n_10768 : STD_LOGIC;
  signal udma_wrapper_n_10769 : STD_LOGIC;
  signal udma_wrapper_n_10770 : STD_LOGIC;
  signal udma_wrapper_n_10771 : STD_LOGIC;
  signal udma_wrapper_n_10772 : STD_LOGIC;
  signal udma_wrapper_n_10773 : STD_LOGIC;
  signal udma_wrapper_n_10774 : STD_LOGIC;
  signal udma_wrapper_n_10775 : STD_LOGIC;
  signal udma_wrapper_n_10776 : STD_LOGIC;
  signal udma_wrapper_n_10777 : STD_LOGIC;
  signal udma_wrapper_n_10778 : STD_LOGIC;
  signal udma_wrapper_n_10779 : STD_LOGIC;
  signal udma_wrapper_n_10780 : STD_LOGIC;
  signal udma_wrapper_n_10781 : STD_LOGIC;
  signal udma_wrapper_n_10782 : STD_LOGIC;
  signal udma_wrapper_n_10783 : STD_LOGIC;
  signal udma_wrapper_n_10784 : STD_LOGIC;
  signal udma_wrapper_n_10785 : STD_LOGIC;
  signal udma_wrapper_n_10786 : STD_LOGIC;
  signal udma_wrapper_n_10787 : STD_LOGIC;
  signal udma_wrapper_n_10788 : STD_LOGIC;
  signal udma_wrapper_n_10789 : STD_LOGIC;
  signal udma_wrapper_n_10790 : STD_LOGIC;
  signal udma_wrapper_n_10791 : STD_LOGIC;
  signal udma_wrapper_n_10792 : STD_LOGIC;
  signal udma_wrapper_n_10793 : STD_LOGIC;
  signal udma_wrapper_n_10794 : STD_LOGIC;
  signal udma_wrapper_n_10827 : STD_LOGIC;
  signal udma_wrapper_n_10828 : STD_LOGIC;
  signal udma_wrapper_n_10829 : STD_LOGIC;
  signal udma_wrapper_n_10830 : STD_LOGIC;
  signal udma_wrapper_n_10847 : STD_LOGIC;
  signal udma_wrapper_n_10848 : STD_LOGIC;
  signal udma_wrapper_n_10849 : STD_LOGIC;
  signal udma_wrapper_n_10850 : STD_LOGIC;
  signal udma_wrapper_n_10851 : STD_LOGIC;
  signal udma_wrapper_n_10852 : STD_LOGIC;
  signal udma_wrapper_n_10853 : STD_LOGIC;
  signal udma_wrapper_n_10854 : STD_LOGIC;
  signal udma_wrapper_n_10857 : STD_LOGIC;
  signal udma_wrapper_n_10858 : STD_LOGIC;
  signal udma_wrapper_n_10859 : STD_LOGIC;
  signal udma_wrapper_n_10860 : STD_LOGIC;
  signal udma_wrapper_n_10861 : STD_LOGIC;
  signal udma_wrapper_n_10862 : STD_LOGIC;
  signal udma_wrapper_n_10863 : STD_LOGIC;
  signal udma_wrapper_n_10864 : STD_LOGIC;
  signal udma_wrapper_n_10865 : STD_LOGIC;
  signal udma_wrapper_n_10866 : STD_LOGIC;
  signal udma_wrapper_n_10867 : STD_LOGIC;
  signal udma_wrapper_n_10868 : STD_LOGIC;
  signal udma_wrapper_n_10869 : STD_LOGIC;
  signal udma_wrapper_n_10870 : STD_LOGIC;
  signal udma_wrapper_n_10871 : STD_LOGIC;
  signal udma_wrapper_n_10872 : STD_LOGIC;
  signal udma_wrapper_n_10873 : STD_LOGIC;
  signal udma_wrapper_n_10874 : STD_LOGIC;
  signal udma_wrapper_n_10875 : STD_LOGIC;
  signal udma_wrapper_n_10876 : STD_LOGIC;
  signal udma_wrapper_n_10877 : STD_LOGIC;
  signal udma_wrapper_n_10878 : STD_LOGIC;
  signal udma_wrapper_n_10879 : STD_LOGIC;
  signal udma_wrapper_n_10880 : STD_LOGIC;
  signal udma_wrapper_n_10881 : STD_LOGIC;
  signal udma_wrapper_n_10882 : STD_LOGIC;
  signal udma_wrapper_n_10883 : STD_LOGIC;
  signal udma_wrapper_n_10884 : STD_LOGIC;
  signal udma_wrapper_n_10885 : STD_LOGIC;
  signal udma_wrapper_n_10886 : STD_LOGIC;
  signal udma_wrapper_n_10887 : STD_LOGIC;
  signal udma_wrapper_n_10888 : STD_LOGIC;
  signal udma_wrapper_n_10889 : STD_LOGIC;
  signal udma_wrapper_n_10890 : STD_LOGIC;
  signal udma_wrapper_n_10891 : STD_LOGIC;
  signal udma_wrapper_n_10892 : STD_LOGIC;
  signal udma_wrapper_n_10893 : STD_LOGIC;
  signal udma_wrapper_n_10894 : STD_LOGIC;
  signal udma_wrapper_n_10895 : STD_LOGIC;
  signal udma_wrapper_n_10896 : STD_LOGIC;
  signal udma_wrapper_n_10897 : STD_LOGIC;
  signal udma_wrapper_n_10898 : STD_LOGIC;
  signal udma_wrapper_n_10899 : STD_LOGIC;
  signal udma_wrapper_n_10900 : STD_LOGIC;
  signal udma_wrapper_n_10901 : STD_LOGIC;
  signal udma_wrapper_n_10902 : STD_LOGIC;
  signal udma_wrapper_n_10903 : STD_LOGIC;
  signal udma_wrapper_n_10904 : STD_LOGIC;
  signal udma_wrapper_n_10905 : STD_LOGIC;
  signal udma_wrapper_n_10906 : STD_LOGIC;
  signal udma_wrapper_n_10907 : STD_LOGIC;
  signal udma_wrapper_n_10908 : STD_LOGIC;
  signal udma_wrapper_n_10909 : STD_LOGIC;
  signal udma_wrapper_n_10910 : STD_LOGIC;
  signal udma_wrapper_n_10911 : STD_LOGIC;
  signal udma_wrapper_n_10912 : STD_LOGIC;
  signal udma_wrapper_n_10913 : STD_LOGIC;
  signal udma_wrapper_n_10914 : STD_LOGIC;
  signal udma_wrapper_n_10915 : STD_LOGIC;
  signal udma_wrapper_n_10916 : STD_LOGIC;
  signal udma_wrapper_n_10917 : STD_LOGIC;
  signal udma_wrapper_n_10918 : STD_LOGIC;
  signal udma_wrapper_n_10919 : STD_LOGIC;
  signal udma_wrapper_n_10920 : STD_LOGIC;
  signal udma_wrapper_n_10921 : STD_LOGIC;
  signal udma_wrapper_n_10955 : STD_LOGIC;
  signal udma_wrapper_n_10958 : STD_LOGIC;
  signal udma_wrapper_n_11002 : STD_LOGIC;
  signal udma_wrapper_n_12224 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12224 : signal is "true";
  signal udma_wrapper_n_12225 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12225 : signal is "true";
  signal udma_wrapper_n_12226 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12226 : signal is "true";
  signal udma_wrapper_n_12227 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12227 : signal is "true";
  signal udma_wrapper_n_12228 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12228 : signal is "true";
  signal udma_wrapper_n_12229 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12229 : signal is "true";
  signal udma_wrapper_n_12230 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12230 : signal is "true";
  signal udma_wrapper_n_12231 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12231 : signal is "true";
  signal udma_wrapper_n_12591 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12591 : signal is "true";
  signal udma_wrapper_n_12592 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12592 : signal is "true";
  signal udma_wrapper_n_12593 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12593 : signal is "true";
  signal udma_wrapper_n_12594 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12594 : signal is "true";
  signal udma_wrapper_n_12595 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12595 : signal is "true";
  signal udma_wrapper_n_12596 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12596 : signal is "true";
  signal udma_wrapper_n_12597 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12597 : signal is "true";
  signal udma_wrapper_n_12598 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12598 : signal is "true";
  signal udma_wrapper_n_12599 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12599 : signal is "true";
  signal udma_wrapper_n_12600 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12600 : signal is "true";
  signal udma_wrapper_n_12601 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12601 : signal is "true";
  signal udma_wrapper_n_12602 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12602 : signal is "true";
  signal udma_wrapper_n_12603 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12603 : signal is "true";
  signal udma_wrapper_n_12604 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12604 : signal is "true";
  signal udma_wrapper_n_12605 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12605 : signal is "true";
  signal udma_wrapper_n_12606 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12606 : signal is "true";
  signal udma_wrapper_n_12607 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12607 : signal is "true";
  signal udma_wrapper_n_12608 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12608 : signal is "true";
  signal udma_wrapper_n_12609 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12609 : signal is "true";
  signal udma_wrapper_n_12610 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12610 : signal is "true";
  signal udma_wrapper_n_12611 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12611 : signal is "true";
  signal udma_wrapper_n_12612 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12612 : signal is "true";
  signal udma_wrapper_n_12613 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12613 : signal is "true";
  signal udma_wrapper_n_12614 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12614 : signal is "true";
  signal udma_wrapper_n_12615 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12615 : signal is "true";
  signal udma_wrapper_n_12616 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12616 : signal is "true";
  signal udma_wrapper_n_12617 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12617 : signal is "true";
  signal udma_wrapper_n_12618 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12618 : signal is "true";
  signal udma_wrapper_n_12619 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12619 : signal is "true";
  signal udma_wrapper_n_12620 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12620 : signal is "true";
  signal udma_wrapper_n_12621 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12621 : signal is "true";
  signal udma_wrapper_n_12622 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12622 : signal is "true";
  signal udma_wrapper_n_12634 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12634 : signal is "true";
  signal udma_wrapper_n_12635 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12635 : signal is "true";
  signal udma_wrapper_n_12636 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12636 : signal is "true";
  signal udma_wrapper_n_12637 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12637 : signal is "true";
  signal udma_wrapper_n_12638 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12638 : signal is "true";
  signal udma_wrapper_n_12639 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12639 : signal is "true";
  signal udma_wrapper_n_12640 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12640 : signal is "true";
  signal udma_wrapper_n_12641 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12641 : signal is "true";
  signal udma_wrapper_n_12642 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12642 : signal is "true";
  signal udma_wrapper_n_12643 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12643 : signal is "true";
  signal udma_wrapper_n_12644 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12644 : signal is "true";
  signal udma_wrapper_n_12645 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12645 : signal is "true";
  signal udma_wrapper_n_12646 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12646 : signal is "true";
  signal udma_wrapper_n_12647 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12647 : signal is "true";
  signal udma_wrapper_n_12648 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12648 : signal is "true";
  signal udma_wrapper_n_12649 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12649 : signal is "true";
  signal udma_wrapper_n_12650 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12650 : signal is "true";
  signal udma_wrapper_n_12651 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12651 : signal is "true";
  signal udma_wrapper_n_12652 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12652 : signal is "true";
  signal udma_wrapper_n_12653 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12653 : signal is "true";
  signal udma_wrapper_n_12654 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12654 : signal is "true";
  signal udma_wrapper_n_12655 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12655 : signal is "true";
  signal udma_wrapper_n_12656 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12656 : signal is "true";
  signal udma_wrapper_n_12657 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12657 : signal is "true";
  signal udma_wrapper_n_12658 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12658 : signal is "true";
  signal udma_wrapper_n_12659 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12659 : signal is "true";
  signal udma_wrapper_n_12660 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12660 : signal is "true";
  signal udma_wrapper_n_12661 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12661 : signal is "true";
  signal udma_wrapper_n_12662 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12662 : signal is "true";
  signal udma_wrapper_n_12663 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12663 : signal is "true";
  signal udma_wrapper_n_12664 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12664 : signal is "true";
  signal udma_wrapper_n_12665 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12665 : signal is "true";
  signal udma_wrapper_n_12666 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12666 : signal is "true";
  signal udma_wrapper_n_12667 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12667 : signal is "true";
  signal udma_wrapper_n_12668 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12668 : signal is "true";
  signal udma_wrapper_n_12669 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12669 : signal is "true";
  signal udma_wrapper_n_12670 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12670 : signal is "true";
  signal udma_wrapper_n_12671 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12671 : signal is "true";
  signal udma_wrapper_n_12672 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12672 : signal is "true";
  signal udma_wrapper_n_12673 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12673 : signal is "true";
  signal udma_wrapper_n_12674 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12674 : signal is "true";
  signal udma_wrapper_n_12675 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12675 : signal is "true";
  signal udma_wrapper_n_12676 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12676 : signal is "true";
  signal udma_wrapper_n_12677 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12677 : signal is "true";
  signal udma_wrapper_n_12678 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12678 : signal is "true";
  signal udma_wrapper_n_12679 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12679 : signal is "true";
  signal udma_wrapper_n_12680 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12680 : signal is "true";
  signal udma_wrapper_n_12681 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12681 : signal is "true";
  signal udma_wrapper_n_12682 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12682 : signal is "true";
  signal udma_wrapper_n_12683 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12683 : signal is "true";
  signal udma_wrapper_n_12684 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12684 : signal is "true";
  signal udma_wrapper_n_12685 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12685 : signal is "true";
  signal udma_wrapper_n_12686 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12686 : signal is "true";
  signal udma_wrapper_n_12687 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12687 : signal is "true";
  signal udma_wrapper_n_12688 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12688 : signal is "true";
  signal udma_wrapper_n_12689 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12689 : signal is "true";
  signal udma_wrapper_n_12690 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12690 : signal is "true";
  signal udma_wrapper_n_12691 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12691 : signal is "true";
  signal udma_wrapper_n_12692 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12692 : signal is "true";
  signal udma_wrapper_n_12693 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12693 : signal is "true";
  signal udma_wrapper_n_12694 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12694 : signal is "true";
  signal udma_wrapper_n_12695 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12695 : signal is "true";
  signal udma_wrapper_n_12696 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12696 : signal is "true";
  signal udma_wrapper_n_12697 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12697 : signal is "true";
  signal udma_wrapper_n_12698 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12698 : signal is "true";
  signal udma_wrapper_n_12699 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12699 : signal is "true";
  signal udma_wrapper_n_12700 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12700 : signal is "true";
  signal udma_wrapper_n_12701 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12701 : signal is "true";
  signal udma_wrapper_n_12702 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12702 : signal is "true";
  signal udma_wrapper_n_12703 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12703 : signal is "true";
  signal udma_wrapper_n_12704 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12704 : signal is "true";
  signal udma_wrapper_n_12716 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12716 : signal is "true";
  signal udma_wrapper_n_12717 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12717 : signal is "true";
  signal udma_wrapper_n_12718 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12718 : signal is "true";
  signal udma_wrapper_n_12719 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12719 : signal is "true";
  signal udma_wrapper_n_12720 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12720 : signal is "true";
  signal udma_wrapper_n_12723 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12723 : signal is "true";
  signal udma_wrapper_n_12724 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12724 : signal is "true";
  signal udma_wrapper_n_12725 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12725 : signal is "true";
  signal udma_wrapper_n_12726 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12726 : signal is "true";
  signal udma_wrapper_n_12727 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12727 : signal is "true";
  signal udma_wrapper_n_12728 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12728 : signal is "true";
  signal udma_wrapper_n_12729 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12729 : signal is "true";
  signal udma_wrapper_n_12730 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12730 : signal is "true";
  signal udma_wrapper_n_12731 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12731 : signal is "true";
  signal udma_wrapper_n_12732 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12732 : signal is "true";
  signal udma_wrapper_n_12733 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12733 : signal is "true";
  signal udma_wrapper_n_12734 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12734 : signal is "true";
  signal udma_wrapper_n_12735 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12735 : signal is "true";
  signal udma_wrapper_n_12736 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12736 : signal is "true";
  signal udma_wrapper_n_12737 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12737 : signal is "true";
  signal udma_wrapper_n_12738 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12738 : signal is "true";
  signal udma_wrapper_n_12739 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12739 : signal is "true";
  signal udma_wrapper_n_12740 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12740 : signal is "true";
  signal udma_wrapper_n_12741 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12741 : signal is "true";
  signal udma_wrapper_n_12742 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12742 : signal is "true";
  signal udma_wrapper_n_12743 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12743 : signal is "true";
  signal udma_wrapper_n_12744 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12744 : signal is "true";
  signal udma_wrapper_n_12745 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12745 : signal is "true";
  signal udma_wrapper_n_12746 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12746 : signal is "true";
  signal udma_wrapper_n_12747 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12747 : signal is "true";
  signal udma_wrapper_n_12748 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12748 : signal is "true";
  signal udma_wrapper_n_12749 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12749 : signal is "true";
  signal udma_wrapper_n_12750 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12750 : signal is "true";
  signal udma_wrapper_n_12751 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12751 : signal is "true";
  signal udma_wrapper_n_12752 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12752 : signal is "true";
  signal udma_wrapper_n_12753 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12753 : signal is "true";
  signal udma_wrapper_n_12754 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12754 : signal is "true";
  signal udma_wrapper_n_12755 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12755 : signal is "true";
  signal udma_wrapper_n_12758 : STD_LOGIC;
  attribute RTL_KEEP of udma_wrapper_n_12758 : signal is "true";
  signal \^user_lnk_up\ : STD_LOGIC;
  attribute RTL_KEEP of user_lnk_up : signal is "true";
  signal \xdma_0_axi_stream_intf_i/xdma_0_dma_cpl_i/p_0_in\ : STD_LOGIC;
  attribute RTL_KEEP of \xdma_0_axi_stream_intf_i/xdma_0_dma_cpl_i/p_0_in\ : signal is "true";
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_134 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_135 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_136 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_137 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_138 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_139 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_167 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_168 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_169 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_170 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_171 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_172 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_173 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_174 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_175 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_176 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_177 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_178 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_179 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_180 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_181 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_182 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_183 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_184 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_185 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_186 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_187 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_188 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_189 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_190 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_191 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_192 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_193 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_194 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_195 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_196 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_197 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_198 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_199 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_200 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_201 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_202 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_203 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_204 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_205 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_206 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_207 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_208 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_209 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_210 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_211 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_212 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_213 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_214 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_215 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_216 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_217 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_218 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_219 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_220 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_221 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_222 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_223 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_224 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_225 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_226 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_227 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_228 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_229 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_230 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_231 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_232 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_233 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_234 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_235 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_236 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_237 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_238 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_239 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_240 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_241 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_242 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_243 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_244 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_245 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_246 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_247 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_248 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_249 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_250 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_251 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_252 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_253 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_254 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_255 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_256 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_257 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_258 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_259 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_260 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_261 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_262 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_263 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_264 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_265 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_266 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_267 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_268 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_269 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_270 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_271 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_272 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_273 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_274 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_275 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_276 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_277 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_278 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_279 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_280 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_281 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_282 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_283 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_284 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_285 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_286 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_287 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_288 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_289 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_290 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_291 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_292 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_293 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_294 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_295 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_296 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_297 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_298 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_299 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_300 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_301 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_302 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_303 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_304 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_305 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_306 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_307 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_308 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_309 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_310 : STD_LOGIC;
  signal xdma_0_pcie2_to_pcie3_wrapper_i_n_312 : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h0_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h0_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h1_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h1_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h2_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h2_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h3_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h3_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_rd_brg_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_rd_brg_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_wr_brg_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h_wr_brg_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_dsc_crd_rcv\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_dsc_crd_rcv\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c0_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c0_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c1_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c1_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c2_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c2_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c3_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c3_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_rd_brg_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_rd_brg_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_wr_brg_dat\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_h2c_wr_brg_dat\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_hw_ctxt\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_hw_ctxt\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_sw_ctxt\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_sw_ctxt\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_wb_base_ctxt\\.rdbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_wb_base_ctxt\\.rsbe_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ram_top_mi_c2h0_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_ram_top_mi_c2h0_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h1_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h1_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h2_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h2_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h3_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h3_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ram_top_mi_c2h_rd_brg_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h_rd_brg_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_c2h_wr_brg_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_c2h_wr_brg_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_dsc_crd_rcv\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_ram_top_mi_dsc_crd_rcv\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ram_top_mi_h2c0_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_ram_top_mi_h2c0_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c1_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_h2c1_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c2_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_h2c2_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c3_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_h2c3_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ram_top_mi_h2c_rd_brg_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_ram_top_mi_h2c_rd_brg_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_ram_top_mi_h2c_wr_brg_dat\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_ram_top_mi_h2c_wr_brg_dat\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 );
  signal \NLW_ram_top_mi_hw_ctxt\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_ram_top_mi_hw_ctxt\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ram_top_mi_sw_ctxt\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \NLW_ram_top_mi_sw_ctxt\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ram_top_mi_wb_base_ctxt\\.rdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \NLW_ram_top_mi_wb_base_ctxt\\.rpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_axi_aresetn_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_blk_cfg_ext_read_data_valid_o_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_cfg_status_ats_en_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_cfg_status_pr_en_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_cfg_status_pr_rf_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_cfg_status_pr_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_cfg_status_pr_uprgi_UNCONNECTED : STD_LOGIC;
  signal \NLW_udma_wrapper_dsc_in\\.crd[vld]_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_dsc_out\\.dsc[dir]_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_dsc_out\\.dsc[wbi]_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_dsc_out\\.dsc[wbi_chk]_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_vld_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.flr_clr_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.flr_set_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_vld_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.usr_irq_fail_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_fabric_out\\.usr_irq_sent_UNCONNECTED\ : STD_LOGIC;
  signal NLW_udma_wrapper_h2c_desc_cmd_in_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_h2c_desc_cmd_out_vld_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axi_arlock_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axi_awlock_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axib_arlock_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axib_awlock_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axis_cq_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_m_axis_cq_tvalid_UNCONNECTED : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h0_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wen_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c0_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.wen_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.ren_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_config_space_enable_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_err_cor_in_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_err_uncor_in_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ext_read_data_valid_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_hot_reset_in_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_data_enable_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_present_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_int_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_link_training_enable_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_read_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_type1_cfg_reg_access_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_write_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_logic_request_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_output_request_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_vf_flr_done_UNCONNECTED\ : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_s_axis_rq_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_user_cfg_ext_read_received_o_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_user_cfg_ext_write_received_o_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_usr_flr_clr_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_usr_flr_set_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_usr_irq_fail_UNCONNECTED : STD_LOGIC;
  signal NLW_udma_wrapper_blk_cfg_ext_read_data_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_c2h_desc_avail_inc_num[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \NLW_udma_wrapper_c2h_desc_avail_inc_qid[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_udma_wrapper_c2h_desc_avail_inc_vld_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_udma_wrapper_c2h_dsc_byp_ready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_udma_wrapper_c2h_pktin_accept_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_udma_wrapper_c2h_pktin_drop[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_c2h_sts_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_cfg_status_ats_stu_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_udma_wrapper_cfg_status_ost_pr_alloc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_dsc_in\\.crd[num]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_dsc_in\\.crd[qid]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[chn]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[cidx]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[dsc]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[qid]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[qst]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[siz]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_udma_wrapper_dsc_out\\.dsc[vld]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_chn_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_num_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_qid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_state_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_sts[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_sts[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_sts[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.c2h_sts[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.flr_fnc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.h2c_sts[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.h2c_sts[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.h2c_sts[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.h2c_sts[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_chn_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_qid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.usr_irq_rfnc_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_fabric_out\\.usr_irq_rvec_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_udma_wrapper_h2c_desc_cmd_out_data_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_udma_wrapper_h2c_desc_cmd_out_qid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_udma_wrapper_h2c_dsc_byp_ready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_udma_wrapper_h2c_sts_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_udma_wrapper_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_udma_wrapper_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_udma_wrapper_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_udma_wrapper_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axi_wdataeccparity_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axib_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_m_axib_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axib_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axib_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axib_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axib_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axib_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_m_axib_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axib_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_m_axib_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axib_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 );
  signal NLW_udma_wrapper_m_axib_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axil_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_udma_wrapper_m_axil_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axil_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_udma_wrapper_m_axil_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_m_axis_cc\\.tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_m_axis_cc\\.tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal NLW_udma_wrapper_m_axis_cq_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_udma_wrapper_m_axis_cq_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_m_axis_cq_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 84 downto 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tparity_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_udma_wrapper_m_axis_h2c_tvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_udma_wrapper_m_axis_rq\\.tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_m_axis_rq\\.tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 59 downto 8 );
  signal \NLW_udma_wrapper_mi_c2h0_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_udma_wrapper_mi_c2h0_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_udma_wrapper_mi_c2h0_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h1_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h2_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h3_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 to 9 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 to 9 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c0_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_udma_wrapper_mi_h2c0_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_udma_wrapper_mi_h2c0_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 );
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c1_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c2_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c3_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 79 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 9 );
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 9 );
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 511 downto 64 );
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_mi_hw_ctxt\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_mi_sw_ctxt\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.radr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.wadr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.wdat_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.wen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_mi_wb_base_ctxt\\.wpar_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_gic\\.interrupt_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_bus_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_device_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_function_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_port_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_dsn_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_ext_read_data_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_fc_sel_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_flr_done_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_int_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_attr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_function_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_function_num_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_st_tag_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_type_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_address_UNCONNECTED\ : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_data_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_pending_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_addr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_byte_enable_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_function_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_write_data_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_data_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_type_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_func_status_control_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_number_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.cfg_vf_flr_func_num_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_udma_wrapper_pcie_dma_out\\.pcie_cq_np_req_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_udma_wrapper_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_udma_wrapper_s_axi_rdataeccparity_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_s_axil_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_s_axil_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_udma_wrapper_s_axis_c2h_tready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_udma_wrapper_s_axis_cq\\.tready_UNCONNECTED\ : STD_LOGIC_VECTOR ( 21 downto 1 );
  signal \NLW_udma_wrapper_s_axis_rc\\.tready_UNCONNECTED\ : STD_LOGIC_VECTOR ( 21 downto 1 );
  signal NLW_udma_wrapper_user_cfg_ext_function_number_o_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_udma_wrapper_user_cfg_ext_register_number_o_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_udma_wrapper_user_cfg_ext_write_byte_enable_o_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udma_wrapper_user_cfg_ext_write_data_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_udma_wrapper_usr_flr_fnc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute AXI4MM_ULTRA of ram_top : label is 0;
  attribute C_C2H_NUM_CHNL of ram_top : label is 1;
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of ram_top : label is 64;
  attribute C_H2C_NUM_CHNL of ram_top : label is 1;
  attribute C_M_NUM_CQ_AXI_WRITE_SCALE : integer;
  attribute C_M_NUM_CQ_AXI_WRITE_SCALE of ram_top : label is 1;
  attribute C_NUMQ_PER_CHNL of ram_top : label is 256;
  attribute C_NUM_AXI_DSC_CPL_DID of ram_top : label is 64;
  attribute C_NUM_C2H_PCIE_DSC_CPL_DID : integer;
  attribute C_NUM_C2H_PCIE_DSC_CPL_DID of ram_top : label is 1024;
  attribute C_NUM_PCIE_DSC_CPL_DID of ram_top : label is 256;
  attribute C_SLAVE_READ_64OS_EN of ram_top : label is 0;
  attribute DSC_AXI_CPL_DID_WIDTH : integer;
  attribute DSC_AXI_CPL_DID_WIDTH of ram_top : label is 6;
  attribute DSC_C2H_PCIE_CPL_DID_WIDTH : integer;
  attribute DSC_C2H_PCIE_CPL_DID_WIDTH of ram_top : label is 10;
  attribute DSC_PCIE_CPL_DID_WIDTH : integer;
  attribute DSC_PCIE_CPL_DID_WIDTH of ram_top : label is 8;
  attribute IMPL_TARGET of ram_top : label is "SOFT";
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of ram_top : label is "soft";
  attribute MM_SLAVE_EN of ram_top : label is 0;
  attribute NUM_TOTQ : integer;
  attribute NUM_TOTQ of ram_top : label is 512;
  attribute SHELL_BRIDGE of ram_top : label is 0;
  attribute TCQ of ram_top : label is 1;
  attribute TOTQ_WIDTH : integer;
  attribute TOTQ_WIDTH of ram_top : label is 9;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of ram_top : label is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of sys_rst_n_reg2_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of sys_rst_n_reg2_reg : label is "yes";
  attribute ASYNC_REG_boolean of sys_rst_n_reg_reg : label is std.standard.true;
  attribute KEEP of sys_rst_n_reg_reg : label is "yes";
  attribute AXI4MM_ULTRA of udma_wrapper : label is 0;
  attribute AXIL_ADR_WIDTH : integer;
  attribute AXIL_ADR_WIDTH of udma_wrapper : label is 32;
  attribute AXIL_DAT_WIDTH : integer;
  attribute AXIL_DAT_WIDTH of udma_wrapper : label is 32;
  attribute AXI_DSC_ENG_EN : integer;
  attribute AXI_DSC_ENG_EN of udma_wrapper : label is 0;
  attribute AXI_WBK_ENG_EN : integer;
  attribute AXI_WBK_ENG_EN of udma_wrapper : label is 0;
  attribute AXSIZE_BYTE_ACCESS_EN of udma_wrapper : label is "FALSE";
  attribute BACKPRESSURE of udma_wrapper : label is 0;
  attribute BAR0_APERTURE_SIZE : integer;
  attribute BAR0_APERTURE_SIZE of udma_wrapper : label is 32;
  attribute BAR1_APERTURE_SIZE : integer;
  attribute BAR1_APERTURE_SIZE of udma_wrapper : label is 16;
  attribute BAR2_APERTURE_SIZE : integer;
  attribute BAR2_APERTURE_SIZE of udma_wrapper : label is 64;
  attribute BARLITE0 of udma_wrapper : label is 7;
  attribute BARLITE1 of udma_wrapper : label is 0;
  attribute BARLITE2 of udma_wrapper : label is 7;
  attribute C2H_WB : integer;
  attribute C2H_WB of udma_wrapper : label is 1;
  attribute C2H_XDMA_CHNL of udma_wrapper : label is "8'b00001111";
  attribute C_ADDR_ALGN of udma_wrapper : label is 1;
  attribute C_ADDR_BITS of udma_wrapper : label is 64;
  attribute C_ATS_CAP_NEXTPTR of udma_wrapper : label is "12'b000000000000";
  attribute C_ATS_ENABLE of udma_wrapper : label is "FALSE";
  attribute C_ATS_OFFSET of udma_wrapper : label is "30'b000000000000000000000100100000";
  attribute C_AXIBAR2PCIEATTR_0 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_1 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_2 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_3 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_4 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_5 of udma_wrapper : label is "3'b000";
  attribute C_AXIBAR2PCIEBAR_0 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_1 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_2 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_3 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_4 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_5 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_0 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_1 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_2 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_3 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_4 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_5 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_AS_0 of udma_wrapper : label is 1;
  attribute C_AXIBAR_AS_1 of udma_wrapper : label is 1;
  attribute C_AXIBAR_AS_2 of udma_wrapper : label is 1;
  attribute C_AXIBAR_AS_3 of udma_wrapper : label is 1;
  attribute C_AXIBAR_AS_4 of udma_wrapper : label is 1;
  attribute C_AXIBAR_AS_5 of udma_wrapper : label is 1;
  attribute C_AXIBAR_HIGHADDR_0 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_1 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_2 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_3 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_4 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_5 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_NOXLATE of udma_wrapper : label is 0;
  attribute C_AXIBAR_NUM of udma_wrapper : label is 6;
  attribute C_AXIBAR_REGIONEN of udma_wrapper : label is 0;
  attribute C_AXI_BUSER_WIDTH : integer;
  attribute C_AXI_BUSER_WIDTH of udma_wrapper : label is 1;
  attribute C_AXI_RUSER_WIDTH : integer;
  attribute C_AXI_RUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_AXI_WUSER_WIDTH : integer;
  attribute C_AXI_WUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_BASEADDR of udma_wrapper : label is 4096;
  attribute C_C2H_NUM_CHNL of udma_wrapper : label is 1;
  attribute C_C2H_NUM_RIDS of udma_wrapper : label is 16;
  attribute C_C2H_RID_WIDTH : integer;
  attribute C_C2H_RID_WIDTH of udma_wrapper : label is 8;
  attribute C_C2H_TUSER_WIDTH of udma_wrapper : label is 64;
  attribute C_COMP_TIMEOUT of udma_wrapper : label is 1;
  attribute C_DATA_WIDTH of udma_wrapper : label is 64;
  attribute C_DAT_BRAM_DEPTH : integer;
  attribute C_DAT_BRAM_DEPTH of udma_wrapper : label is 512;
  attribute C_DEVICE_NUMBER of udma_wrapper : label is 0;
  attribute C_DSC_BRAM_DEPTH : integer;
  attribute C_DSC_BRAM_DEPTH of udma_wrapper : label is 512;
  attribute C_DSC_DEPTH : integer;
  attribute C_DSC_DEPTH of udma_wrapper : label is 512;
  attribute C_DSC_MAGIC_EN of udma_wrapper : label is 1;
  attribute C_ECC_ENABLE of udma_wrapper : label is 0;
  attribute C_ENABLE_RESOURCE_REDUCTION of udma_wrapper : label is "FALSE";
  attribute C_EP_LINK_PARTNER_RCB : integer;
  attribute C_EP_LINK_PARTNER_RCB of udma_wrapper : label is 0;
  attribute C_FAMILY of udma_wrapper : label is "artix7";
  attribute C_FF_ON_INT_IF of udma_wrapper : label is "FALSE";
  attribute C_H2C_NUM_CHNL of udma_wrapper : label is 1;
  attribute C_H2C_NUM_RIDS of udma_wrapper : label is 32;
  attribute C_H2C_RID_WIDTH : integer;
  attribute C_H2C_RID_WIDTH of udma_wrapper : label is 8;
  attribute C_H2C_TUSER_WIDTH of udma_wrapper : label is 48;
  attribute C_HIGHADDR of udma_wrapper : label is 8191;
  attribute C_IGNORE_SIZE_AXI_SLAVE of udma_wrapper : label is 1;
  attribute C_INCLUDE_BAROFFSET_REG of udma_wrapper : label is 1;
  attribute C_INCLUDE_RC of udma_wrapper : label is 0;
  attribute C_INTX_RX_PIN_EN of udma_wrapper : label is 1;
  attribute C_INV_QUEUE_DEPTH of udma_wrapper : label is "5'b00000";
  attribute C_LAST_CORE_CAP_ADDR of udma_wrapper : label is "12'b000100000000";
  attribute C_MAX_NUM_CHNL : integer;
  attribute C_MAX_NUM_CHNL of udma_wrapper : label is 1;
  attribute C_MSIX_INT_TABLE_EN of udma_wrapper : label is 0;
  attribute C_MSIX_RX_PIN_EN of udma_wrapper : label is 1;
  attribute C_MSI_ENABLED of udma_wrapper : label is "TRUE";
  attribute C_MSI_RX_PIN_EN of udma_wrapper : label is 0;
  attribute C_MULTQ_MAX_QID : integer;
  attribute C_MULTQ_MAX_QID of udma_wrapper : label is 32;
  attribute C_MULTQ_MAX_RING_DEPTH : integer;
  attribute C_MULTQ_MAX_RING_DEPTH of udma_wrapper : label is 8192;
  attribute C_M_AXIL_ARUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_M_AXIL_AWUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_M_AXIS_DATA_WIDTH of udma_wrapper : label is 64;
  attribute C_M_AXIS_RC_USER_WIDTH of udma_wrapper : label is 75;
  attribute C_M_AXIS_RQ_USER_WIDTH of udma_wrapper : label is 60;
  attribute C_M_AXI_ADDR_WIDTH of udma_wrapper : label is 64;
  attribute C_M_AXI_ARUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_M_AXI_AWUSER_WIDTH of udma_wrapper : label is 8;
  attribute C_M_AXI_AXCACHE_EN : integer;
  attribute C_M_AXI_AXCACHE_EN of udma_wrapper : label is 0;
  attribute C_M_AXI_DATA_WIDTH of udma_wrapper : label is 64;
  attribute C_M_AXI_ID_WIDTH of udma_wrapper : label is 4;
  attribute C_M_INT_W_ORDER_EN : integer;
  attribute C_M_INT_W_ORDER_EN of udma_wrapper : label is 0;
  attribute C_M_KEEP_WIDTH of udma_wrapper : label is 2;
  attribute C_M_NUM_AXI_READ : integer;
  attribute C_M_NUM_AXI_READ of udma_wrapper : label is 16;
  attribute C_M_NUM_AXI_WRITE : integer;
  attribute C_M_NUM_AXI_WRITE of udma_wrapper : label is 16;
  attribute C_M_NUM_CQ_AXI_READ : integer;
  attribute C_M_NUM_CQ_AXI_READ of udma_wrapper : label is 8;
  attribute C_M_NUM_CQ_AXI_READQ : integer;
  attribute C_M_NUM_CQ_AXI_READQ of udma_wrapper : label is 2;
  attribute C_M_NUM_CQ_AXI_WRITE : integer;
  attribute C_M_NUM_CQ_AXI_WRITE of udma_wrapper : label is 4;
  attribute C_M_NUM_CQ_AXI_WRITE_SCALE of udma_wrapper : label is 1;
  attribute C_NUMQ_PER_CHNL of udma_wrapper : label is 256;
  attribute C_NUM_AXI_DSC_CPL_DID of udma_wrapper : label is 64;
  attribute C_NUM_DSC_AXI_RID : integer;
  attribute C_NUM_DSC_AXI_RID of udma_wrapper : label is 32;
  attribute C_NUM_DSC_PCIE_RID of udma_wrapper : label is 32;
  attribute C_NUM_MSIX_VECTORS of udma_wrapper : label is 32;
  attribute C_NUM_PCIE_DSC_CPL_DID of udma_wrapper : label is 256;
  attribute C_NUM_PCIE_TAGS : integer;
  attribute C_NUM_PCIE_TAGS of udma_wrapper : label is 64;
  attribute C_NUM_USER_INTR of udma_wrapper : label is 9;
  attribute C_NUM_USER_NEW_INTR of udma_wrapper : label is 6;
  attribute C_NUM_USR_IRQ of udma_wrapper : label is 1;
  attribute C_OLD_BRIDGE_TIMEOUT of udma_wrapper : label is 0;
  attribute C_OST_PR_CAP of udma_wrapper : label is 0;
  attribute C_PAGE_SIZE : integer;
  attribute C_PAGE_SIZE of udma_wrapper : label is 4096;
  attribute C_PARITY_CHECK of udma_wrapper : label is 0;
  attribute C_PARITY_GEN of udma_wrapper : label is 0;
  attribute C_PARITY_PROP of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_0 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_0_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_0_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_1 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_1_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_1_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_2 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_2_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_2_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_3 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_3_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_3_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_4 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_4_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_4_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_5 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_5_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_5_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR2AXIBAR_6 of udma_wrapper : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_6_SEC : integer;
  attribute C_PCIEBAR2AXIBAR_6_SEC of udma_wrapper : label is 0;
  attribute C_PCIEBAR_AS of udma_wrapper : label is 1;
  attribute C_PCIEBAR_LEN_0 of udma_wrapper : label is 16;
  attribute C_PCIEBAR_LEN_1 of udma_wrapper : label is 20;
  attribute C_PCIEBAR_LEN_2 of udma_wrapper : label is 64;
  attribute C_PCIEBAR_LEN_3 of udma_wrapper : label is 64;
  attribute C_PCIEBAR_LEN_4 of udma_wrapper : label is 64;
  attribute C_PCIEBAR_LEN_5 of udma_wrapper : label is 64;
  attribute C_PCIEBAR_LEN_6 of udma_wrapper : label is 7;
  attribute C_PCIEBAR_NUM of udma_wrapper : label is 6;
  attribute C_PCIE_PFS_ENABLED : integer;
  attribute C_PCIE_PFS_ENABLED of udma_wrapper : label is 1;
  attribute C_PCIE_PFS_SUPPORTED of udma_wrapper : label is 1;
  attribute C_PCIE_TDATA_WIDTH : integer;
  attribute C_PCIE_TDATA_WIDTH of udma_wrapper : label is 256;
  attribute C_PCIE_VFS_ENABLED : integer;
  attribute C_PCIE_VFS_ENABLED of udma_wrapper : label is 0;
  attribute C_PCIE_VFS_SUPPORTED : integer;
  attribute C_PCIE_VFS_SUPPORTED of udma_wrapper : label is 0;
  attribute C_PRI_ENABLE of udma_wrapper : label is "FALSE";
  attribute C_PR_CAP_NEXTPTR of udma_wrapper : label is "12'b000000000000";
  attribute C_PR_OFFSET of udma_wrapper : label is "30'b000000000000000000000100100100";
  attribute C_RD_BUFFER_ADDR_SIZE of udma_wrapper : label is 9;
  attribute C_RD_BUFFER_SIZE_BITS of udma_wrapper : label is 5;
  attribute C_SDMA_C2H_DESC_BYTES : integer;
  attribute C_SDMA_C2H_DESC_BYTES of udma_wrapper : label is 16;
  attribute C_SDMA_C2H_PERQ_DESC_STORE : integer;
  attribute C_SDMA_C2H_PERQ_DESC_STORE of udma_wrapper : label is 256;
  attribute C_SDMA_H2C_DESC_BYTES : integer;
  attribute C_SDMA_H2C_DESC_BYTES of udma_wrapper : label is 16;
  attribute C_SDMA_H2C_DESC_CMD_WIDTH : integer;
  attribute C_SDMA_H2C_DESC_CMD_WIDTH of udma_wrapper : label is 128;
  attribute C_SDMA_H2C_PERQ_DESC_CMD_STORE : integer;
  attribute C_SDMA_H2C_PERQ_DESC_CMD_STORE of udma_wrapper : label is 128;
  attribute C_SDMA_MAX_BUF_SIZE : integer;
  attribute C_SDMA_MAX_BUF_SIZE of udma_wrapper : label is 4096;
  attribute C_SDMA_MIN_BUF_SIZE : integer;
  attribute C_SDMA_MIN_BUF_SIZE of udma_wrapper : label is 1024;
  attribute C_SLAVE_ERROR_POISON : string;
  attribute C_SLAVE_ERROR_POISON of udma_wrapper : label is "1'b1";
  attribute C_SLAVE_READ_64OS_EN of udma_wrapper : label is 0;
  attribute C_SMMU_EN of udma_wrapper : label is 0;
  attribute C_SRIOV_EN of udma_wrapper : label is 0;
  attribute C_S_AXIS_CC_USER_WIDTH of udma_wrapper : label is 33;
  attribute C_S_AXIS_CQ_USER_WIDTH of udma_wrapper : label is 85;
  attribute C_S_AXIS_DATA_WIDTH of udma_wrapper : label is 64;
  attribute C_S_AXI_ADDR_WIDTH of udma_wrapper : label is 64;
  attribute C_S_AXI_DATA_WIDTH of udma_wrapper : label is 64;
  attribute C_S_AXI_ID_WIDTH of udma_wrapper : label is 4;
  attribute C_S_AXI_REG_ENABLE : integer;
  attribute C_S_AXI_REG_ENABLE of udma_wrapper : label is 1;
  attribute C_S_AXI_SUPPORTS_NARROW_BURST of udma_wrapper : label is 0;
  attribute C_S_KEEP_WIDTH of udma_wrapper : label is 2;
  attribute C_S_NUM_AXI_READ : integer;
  attribute C_S_NUM_AXI_READ of udma_wrapper : label is 8;
  attribute C_S_NUM_AXI_WRITE : integer;
  attribute C_S_NUM_AXI_WRITE of udma_wrapper : label is 8;
  attribute C_TIMEOUT0_SEL of udma_wrapper : label is "4'b1110";
  attribute C_TIMEOUT1_SEL of udma_wrapper : label is "4'b1111";
  attribute C_TIMEOUT_MULT of udma_wrapper : label is "3'b011";
  attribute C_USER_PTR of udma_wrapper : label is "16'b0000000011011000";
  attribute C_VSEC_CAP_ADDR of udma_wrapper : label is "12'b000100101000";
  attribute C_VSEC_CAP_LAST of udma_wrapper : label is "FALSE";
  attribute C_VSEC_ID of udma_wrapper : label is "16'b0000000000000000";
  attribute DMA_2RP of udma_wrapper : label is "FALSE";
  attribute DMA_EN of udma_wrapper : label is 1;
  attribute DMA_MM of udma_wrapper : label is 1;
  attribute DMA_ST of udma_wrapper : label is 0;
  attribute DSC_BYPASS_RD of udma_wrapper : label is 0;
  attribute DSC_BYPASS_WR of udma_wrapper : label is 0;
  attribute FUNC_MODE of udma_wrapper : label is 1;
  attribute H2C_XDMA_CHNL of udma_wrapper : label is "8'b00001111";
  attribute IMPL_TARGET of udma_wrapper : label is "SOFT";
  attribute KEEP_HIERARCHY of udma_wrapper : label is "soft";
  attribute MM_SLAVE_EN of udma_wrapper : label is 0;
  attribute MPL_SIZE : integer;
  attribute MPL_SIZE of udma_wrapper : label is 4096;
  attribute MRS_SIZE : integer;
  attribute MRS_SIZE of udma_wrapper : label is 4096;
  attribute MSIX_PCIE_INTERNAL of udma_wrapper : label is 0;
  attribute MSIX_RX_DECODE_EN of udma_wrapper : label is "FALSE";
  attribute MSIX_VEC_NUM of udma_wrapper : label is 1024;
  attribute MULTQ_CHNL of udma_wrapper : label is "8'b00000000";
  attribute MULTQ_LL_CHNL : string;
  attribute MULTQ_LL_CHNL of udma_wrapper : label is "8'b00001111";
  attribute MULTQ_MAX_CHNL : string;
  attribute MULTQ_MAX_CHNL of udma_wrapper : label is "48'b100000100000100000100000100000100000100000100000";
  attribute MULT_PF_DESIGN of udma_wrapper : label is 0;
  attribute PCIE_DSC_ENG_EN : integer;
  attribute PCIE_DSC_ENG_EN of udma_wrapper : label is 1;
  attribute PCIE_WBK_ENG_EN : integer;
  attribute PCIE_WBK_ENG_EN of udma_wrapper : label is 1;
  attribute PF0_MSIX_TAR_ID of udma_wrapper : label is "6'b001000";
  attribute PF1_MSIX_TAR_ID of udma_wrapper : label is "6'b001001";
  attribute PF_SWAP of udma_wrapper : label is "FALSE";
  attribute PL_DISABLE_UPCONFIG_CAPABLE of udma_wrapper : label is "FALSE";
  attribute PL_LINK_CAP_MAX_LINK_SPEED of udma_wrapper : label is 2;
  attribute PMON_EN of udma_wrapper : label is 1;
  attribute PROG_USR_IRQ_VEC_MAP of udma_wrapper : label is 0;
  attribute RBAR_ENABLE of udma_wrapper : label is "FALSE";
  attribute RQ_SEQ_NUM_IGNORE of udma_wrapper : label is 0;
  attribute RUN_BIT_FIX of udma_wrapper : label is 0;
  attribute SHELL_BRIDGE of udma_wrapper : label is 0;
  attribute STS_WIDTH of udma_wrapper : label is 8;
  attribute TCQ of udma_wrapper : label is 1;
  attribute TWO_AXILITE_BAR : integer;
  attribute TWO_AXILITE_BAR of udma_wrapper : label is 0;
  attribute USE_ATTR of udma_wrapper : label is 0;
  attribute USR_INT_EXPN of udma_wrapper : label is 0;
  attribute USR_MPL_SIZE of udma_wrapper : label is 4096;
  attribute USR_MRS_SIZE of udma_wrapper : label is 4096;
  attribute VERSION of udma_wrapper : label is 6;
  attribute XDMA_DSC_ENG of udma_wrapper : label is 1;
  attribute is_du_within_envelope of udma_wrapper : label is "true";
  attribute keep of axi_aclk : signal is "true";
  attribute keep of axi_aresetn : signal is "true";
  attribute keep of axi_ctl_aclk : signal is "true";
  attribute keep of axi_ctl_aresetn : signal is "true";
  attribute keep of cfg_mgmt_read : signal is "true";
  attribute keep of cfg_mgmt_read_write_done : signal is "true";
  attribute keep of cfg_mgmt_type1_cfg_reg_access : signal is "true";
  attribute keep of cfg_mgmt_write : signal is "true";
  attribute keep of drp_clk : signal is "true";
  attribute keep of drp_en : signal is "true";
  attribute keep of drp_we : signal is "true";
  attribute keep of ext_ch_gt_drpclk : signal is "true";
  attribute keep of m_axi_arlock : signal is "true";
  attribute keep of m_axi_arready : signal is "true";
  attribute keep of m_axi_arvalid : signal is "true";
  attribute keep of m_axi_awlock : signal is "true";
  attribute keep of m_axi_awready : signal is "true";
  attribute keep of m_axi_awvalid : signal is "true";
  attribute keep of m_axi_bready : signal is "true";
  attribute keep of m_axi_bvalid : signal is "true";
  attribute keep of m_axi_rlast : signal is "true";
  attribute keep of m_axi_rready : signal is "true";
  attribute keep of m_axi_rvalid : signal is "true";
  attribute keep of m_axi_wlast : signal is "true";
  attribute keep of m_axi_wready : signal is "true";
  attribute keep of m_axi_wvalid : signal is "true";
  attribute keep of m_axib_arready : signal is "true";
  attribute keep of m_axib_arvalid : signal is "true";
  attribute keep of m_axib_awready : signal is "true";
  attribute keep of m_axib_awvalid : signal is "true";
  attribute keep of m_axib_bready : signal is "true";
  attribute keep of m_axib_bvalid : signal is "true";
  attribute keep of m_axib_rlast : signal is "true";
  attribute keep of m_axib_rready : signal is "true";
  attribute keep of m_axib_rvalid : signal is "true";
  attribute keep of m_axib_wlast : signal is "true";
  attribute keep of m_axib_wready : signal is "true";
  attribute keep of m_axib_wvalid : signal is "true";
  attribute keep of m_axil_arready : signal is "true";
  attribute keep of m_axil_arvalid : signal is "true";
  attribute keep of m_axil_awready : signal is "true";
  attribute keep of m_axil_awvalid : signal is "true";
  attribute keep of m_axil_bready : signal is "true";
  attribute keep of m_axil_bvalid : signal is "true";
  attribute keep of m_axil_rready : signal is "true";
  attribute keep of m_axil_rvalid : signal is "true";
  attribute keep of m_axil_wready : signal is "true";
  attribute keep of m_axil_wvalid : signal is "true";
  attribute keep of msi_enable : signal is "true";
  attribute keep of msix_enable : signal is "true";
  attribute keep of s_axil_arready : signal is "true";
  attribute keep of s_axil_arvalid : signal is "true";
  attribute keep of s_axil_awready : signal is "true";
  attribute keep of s_axil_awvalid : signal is "true";
  attribute keep of s_axil_bready : signal is "true";
  attribute keep of s_axil_bvalid : signal is "true";
  attribute keep of s_axil_rready : signal is "true";
  attribute keep of s_axil_rvalid : signal is "true";
  attribute keep of s_axil_wready : signal is "true";
  attribute keep of s_axil_wvalid : signal is "true";
  attribute keep of sys_clk : signal is "true";
  attribute keep of sys_clk_ce_out : signal is "true";
  attribute keep of sys_clk_gt : signal is "true";
  attribute keep of sys_rst_n : signal is "true";
  attribute keep of user_lnk_up : signal is "true";
  attribute keep of cfg_mgmt_addr : signal is "true";
  attribute keep of cfg_mgmt_byte_enable : signal is "true";
  attribute keep of cfg_mgmt_read_data : signal is "true";
  attribute keep of cfg_mgmt_write_data : signal is "true";
  attribute keep of drp_addr : signal is "true";
  attribute keep of drp_di : signal is "true";
  attribute keep of ext_ch_gt_drpaddr : signal is "true";
  attribute keep of ext_ch_gt_drpdi : signal is "true";
  attribute keep of ext_ch_gt_drpdo : signal is "true";
  attribute keep of ext_ch_gt_drpen : signal is "true";
  attribute keep of ext_ch_gt_drprdy : signal is "true";
  attribute keep of ext_ch_gt_drpwe : signal is "true";
  attribute keep of m_axi_araddr : signal is "true";
  attribute keep of m_axi_arburst : signal is "true";
  attribute keep of m_axi_arcache : signal is "true";
  attribute keep of m_axi_arid : signal is "true";
  attribute keep of m_axi_arlen : signal is "true";
  attribute keep of m_axi_arprot : signal is "true";
  attribute keep of m_axi_arsize : signal is "true";
  attribute keep of m_axi_awaddr : signal is "true";
  attribute keep of m_axi_awburst : signal is "true";
  attribute keep of m_axi_awcache : signal is "true";
  attribute keep of m_axi_awid : signal is "true";
  attribute keep of m_axi_awlen : signal is "true";
  attribute keep of m_axi_awprot : signal is "true";
  attribute keep of m_axi_awsize : signal is "true";
  attribute keep of m_axi_bid : signal is "true";
  attribute keep of m_axi_bresp : signal is "true";
  attribute keep of m_axi_rdata : signal is "true";
  attribute keep of m_axi_rid : signal is "true";
  attribute keep of m_axi_rresp : signal is "true";
  attribute keep of m_axi_ruser : signal is "true";
  attribute keep of m_axi_wdata : signal is "true";
  attribute keep of m_axi_wstrb : signal is "true";
  attribute keep of m_axi_wuser : signal is "true";
  attribute keep of m_axib_araddr : signal is "true";
  attribute keep of m_axib_arburst : signal is "true";
  attribute keep of m_axib_arcache : signal is "true";
  attribute keep of m_axib_arid : signal is "true";
  attribute keep of m_axib_arlen : signal is "true";
  attribute keep of m_axib_arprot : signal is "true";
  attribute keep of m_axib_arsize : signal is "true";
  attribute keep of m_axib_aruser : signal is "true";
  attribute keep of m_axib_awaddr : signal is "true";
  attribute keep of m_axib_awburst : signal is "true";
  attribute keep of m_axib_awcache : signal is "true";
  attribute keep of m_axib_awid : signal is "true";
  attribute keep of m_axib_awlen : signal is "true";
  attribute keep of m_axib_awprot : signal is "true";
  attribute keep of m_axib_awsize : signal is "true";
  attribute keep of m_axib_awuser : signal is "true";
  attribute keep of m_axib_bid : signal is "true";
  attribute keep of m_axib_bresp : signal is "true";
  attribute keep of m_axib_rdata : signal is "true";
  attribute keep of m_axib_rid : signal is "true";
  attribute keep of m_axib_rresp : signal is "true";
  attribute keep of m_axib_ruser : signal is "true";
  attribute keep of m_axib_wdata : signal is "true";
  attribute keep of m_axib_wstrb : signal is "true";
  attribute keep of m_axib_wuser : signal is "true";
  attribute keep of m_axil_araddr : signal is "true";
  attribute keep of m_axil_aruser : signal is "true";
  attribute keep of m_axil_awaddr : signal is "true";
  attribute keep of m_axil_awuser : signal is "true";
  attribute keep of m_axil_bresp : signal is "true";
  attribute keep of m_axil_rdata : signal is "true";
  attribute keep of m_axil_rresp : signal is "true";
  attribute keep of m_axil_wdata : signal is "true";
  attribute keep of m_axil_wstrb : signal is "true";
  attribute keep of msi_vector_width : signal is "true";
  attribute keep of pci_exp_rxn : signal is "true";
  attribute keep of pci_exp_rxp : signal is "true";
  attribute keep of pci_exp_txn : signal is "true";
  attribute keep of pci_exp_txp : signal is "true";
  attribute keep of s_axil_araddr : signal is "true";
  attribute keep of s_axil_awaddr : signal is "true";
  attribute keep of s_axil_bresp : signal is "true";
  attribute keep of s_axil_rdata : signal is "true";
  attribute keep of s_axil_rresp : signal is "true";
  attribute keep of s_axil_wdata : signal is "true";
  attribute keep of s_axil_wstrb : signal is "true";
  attribute keep of usr_irq_ack : signal is "true";
  attribute keep of usr_irq_function_number : signal is "true";
  attribute keep of usr_irq_req : signal is "true";
begin
  Integrated_bloc_reset_o <= \^integrated_bloc_reset_o\;
  ats_pri_en <= \<const0>\;
  atspri_m_axis_cq_tdata(63) <= \<const0>\;
  atspri_m_axis_cq_tdata(62) <= \<const0>\;
  atspri_m_axis_cq_tdata(61) <= \<const0>\;
  atspri_m_axis_cq_tdata(60) <= \<const0>\;
  atspri_m_axis_cq_tdata(59) <= \<const0>\;
  atspri_m_axis_cq_tdata(58) <= \<const0>\;
  atspri_m_axis_cq_tdata(57) <= \<const0>\;
  atspri_m_axis_cq_tdata(56) <= \<const0>\;
  atspri_m_axis_cq_tdata(55) <= \<const0>\;
  atspri_m_axis_cq_tdata(54) <= \<const0>\;
  atspri_m_axis_cq_tdata(53) <= \<const0>\;
  atspri_m_axis_cq_tdata(52) <= \<const0>\;
  atspri_m_axis_cq_tdata(51) <= \<const0>\;
  atspri_m_axis_cq_tdata(50) <= \<const0>\;
  atspri_m_axis_cq_tdata(49) <= \<const0>\;
  atspri_m_axis_cq_tdata(48) <= \<const0>\;
  atspri_m_axis_cq_tdata(47) <= \<const0>\;
  atspri_m_axis_cq_tdata(46) <= \<const0>\;
  atspri_m_axis_cq_tdata(45) <= \<const0>\;
  atspri_m_axis_cq_tdata(44) <= \<const0>\;
  atspri_m_axis_cq_tdata(43) <= \<const0>\;
  atspri_m_axis_cq_tdata(42) <= \<const0>\;
  atspri_m_axis_cq_tdata(41) <= \<const0>\;
  atspri_m_axis_cq_tdata(40) <= \<const0>\;
  atspri_m_axis_cq_tdata(39) <= \<const0>\;
  atspri_m_axis_cq_tdata(38) <= \<const0>\;
  atspri_m_axis_cq_tdata(37) <= \<const0>\;
  atspri_m_axis_cq_tdata(36) <= \<const0>\;
  atspri_m_axis_cq_tdata(35) <= \<const0>\;
  atspri_m_axis_cq_tdata(34) <= \<const0>\;
  atspri_m_axis_cq_tdata(33) <= \<const0>\;
  atspri_m_axis_cq_tdata(32) <= \<const0>\;
  atspri_m_axis_cq_tdata(31) <= \<const0>\;
  atspri_m_axis_cq_tdata(30) <= \<const0>\;
  atspri_m_axis_cq_tdata(29) <= \<const0>\;
  atspri_m_axis_cq_tdata(28) <= \<const0>\;
  atspri_m_axis_cq_tdata(27) <= \<const0>\;
  atspri_m_axis_cq_tdata(26) <= \<const0>\;
  atspri_m_axis_cq_tdata(25) <= \<const0>\;
  atspri_m_axis_cq_tdata(24) <= \<const0>\;
  atspri_m_axis_cq_tdata(23) <= \<const0>\;
  atspri_m_axis_cq_tdata(22) <= \<const0>\;
  atspri_m_axis_cq_tdata(21) <= \<const0>\;
  atspri_m_axis_cq_tdata(20) <= \<const0>\;
  atspri_m_axis_cq_tdata(19) <= \<const0>\;
  atspri_m_axis_cq_tdata(18) <= \<const0>\;
  atspri_m_axis_cq_tdata(17) <= \<const0>\;
  atspri_m_axis_cq_tdata(16) <= \<const0>\;
  atspri_m_axis_cq_tdata(15) <= \<const0>\;
  atspri_m_axis_cq_tdata(14) <= \<const0>\;
  atspri_m_axis_cq_tdata(13) <= \<const0>\;
  atspri_m_axis_cq_tdata(12) <= \<const0>\;
  atspri_m_axis_cq_tdata(11) <= \<const0>\;
  atspri_m_axis_cq_tdata(10) <= \<const0>\;
  atspri_m_axis_cq_tdata(9) <= \<const0>\;
  atspri_m_axis_cq_tdata(8) <= \<const0>\;
  atspri_m_axis_cq_tdata(7) <= \<const0>\;
  atspri_m_axis_cq_tdata(6) <= \<const0>\;
  atspri_m_axis_cq_tdata(5) <= \<const0>\;
  atspri_m_axis_cq_tdata(4) <= \<const0>\;
  atspri_m_axis_cq_tdata(3) <= \<const0>\;
  atspri_m_axis_cq_tdata(2) <= \<const0>\;
  atspri_m_axis_cq_tdata(1) <= \<const0>\;
  atspri_m_axis_cq_tdata(0) <= \<const0>\;
  atspri_m_axis_cq_tkeep(1) <= \<const0>\;
  atspri_m_axis_cq_tkeep(0) <= \<const0>\;
  atspri_m_axis_cq_tlast <= \<const0>\;
  atspri_m_axis_cq_tuser(84) <= \<const0>\;
  atspri_m_axis_cq_tuser(83) <= \<const0>\;
  atspri_m_axis_cq_tuser(82) <= \<const0>\;
  atspri_m_axis_cq_tuser(81) <= \<const0>\;
  atspri_m_axis_cq_tuser(80) <= \<const0>\;
  atspri_m_axis_cq_tuser(79) <= \<const0>\;
  atspri_m_axis_cq_tuser(78) <= \<const0>\;
  atspri_m_axis_cq_tuser(77) <= \<const0>\;
  atspri_m_axis_cq_tuser(76) <= \<const0>\;
  atspri_m_axis_cq_tuser(75) <= \<const0>\;
  atspri_m_axis_cq_tuser(74) <= \<const0>\;
  atspri_m_axis_cq_tuser(73) <= \<const0>\;
  atspri_m_axis_cq_tuser(72) <= \<const0>\;
  atspri_m_axis_cq_tuser(71) <= \<const0>\;
  atspri_m_axis_cq_tuser(70) <= \<const0>\;
  atspri_m_axis_cq_tuser(69) <= \<const0>\;
  atspri_m_axis_cq_tuser(68) <= \<const0>\;
  atspri_m_axis_cq_tuser(67) <= \<const0>\;
  atspri_m_axis_cq_tuser(66) <= \<const0>\;
  atspri_m_axis_cq_tuser(65) <= \<const0>\;
  atspri_m_axis_cq_tuser(64) <= \<const0>\;
  atspri_m_axis_cq_tuser(63) <= \<const0>\;
  atspri_m_axis_cq_tuser(62) <= \<const0>\;
  atspri_m_axis_cq_tuser(61) <= \<const0>\;
  atspri_m_axis_cq_tuser(60) <= \<const0>\;
  atspri_m_axis_cq_tuser(59) <= \<const0>\;
  atspri_m_axis_cq_tuser(58) <= \<const0>\;
  atspri_m_axis_cq_tuser(57) <= \<const0>\;
  atspri_m_axis_cq_tuser(56) <= \<const0>\;
  atspri_m_axis_cq_tuser(55) <= \<const0>\;
  atspri_m_axis_cq_tuser(54) <= \<const0>\;
  atspri_m_axis_cq_tuser(53) <= \<const0>\;
  atspri_m_axis_cq_tuser(52) <= \<const0>\;
  atspri_m_axis_cq_tuser(51) <= \<const0>\;
  atspri_m_axis_cq_tuser(50) <= \<const0>\;
  atspri_m_axis_cq_tuser(49) <= \<const0>\;
  atspri_m_axis_cq_tuser(48) <= \<const0>\;
  atspri_m_axis_cq_tuser(47) <= \<const0>\;
  atspri_m_axis_cq_tuser(46) <= \<const0>\;
  atspri_m_axis_cq_tuser(45) <= \<const0>\;
  atspri_m_axis_cq_tuser(44) <= \<const0>\;
  atspri_m_axis_cq_tuser(43) <= \<const0>\;
  atspri_m_axis_cq_tuser(42) <= \<const0>\;
  atspri_m_axis_cq_tuser(41) <= \<const0>\;
  atspri_m_axis_cq_tuser(40) <= \<const0>\;
  atspri_m_axis_cq_tuser(39) <= \<const0>\;
  atspri_m_axis_cq_tuser(38) <= \<const0>\;
  atspri_m_axis_cq_tuser(37) <= \<const0>\;
  atspri_m_axis_cq_tuser(36) <= \<const0>\;
  atspri_m_axis_cq_tuser(35) <= \<const0>\;
  atspri_m_axis_cq_tuser(34) <= \<const0>\;
  atspri_m_axis_cq_tuser(33) <= \<const0>\;
  atspri_m_axis_cq_tuser(32) <= \<const0>\;
  atspri_m_axis_cq_tuser(31) <= \<const0>\;
  atspri_m_axis_cq_tuser(30) <= \<const0>\;
  atspri_m_axis_cq_tuser(29) <= \<const0>\;
  atspri_m_axis_cq_tuser(28) <= \<const0>\;
  atspri_m_axis_cq_tuser(27) <= \<const0>\;
  atspri_m_axis_cq_tuser(26) <= \<const0>\;
  atspri_m_axis_cq_tuser(25) <= \<const0>\;
  atspri_m_axis_cq_tuser(24) <= \<const0>\;
  atspri_m_axis_cq_tuser(23) <= \<const0>\;
  atspri_m_axis_cq_tuser(22) <= \<const0>\;
  atspri_m_axis_cq_tuser(21) <= \<const0>\;
  atspri_m_axis_cq_tuser(20) <= \<const0>\;
  atspri_m_axis_cq_tuser(19) <= \<const0>\;
  atspri_m_axis_cq_tuser(18) <= \<const0>\;
  atspri_m_axis_cq_tuser(17) <= \<const0>\;
  atspri_m_axis_cq_tuser(16) <= \<const0>\;
  atspri_m_axis_cq_tuser(15) <= \<const0>\;
  atspri_m_axis_cq_tuser(14) <= \<const0>\;
  atspri_m_axis_cq_tuser(13) <= \<const0>\;
  atspri_m_axis_cq_tuser(12) <= \<const0>\;
  atspri_m_axis_cq_tuser(11) <= \<const0>\;
  atspri_m_axis_cq_tuser(10) <= \<const0>\;
  atspri_m_axis_cq_tuser(9) <= \<const0>\;
  atspri_m_axis_cq_tuser(8) <= \<const0>\;
  atspri_m_axis_cq_tuser(7) <= \<const0>\;
  atspri_m_axis_cq_tuser(6) <= \<const0>\;
  atspri_m_axis_cq_tuser(5) <= \<const0>\;
  atspri_m_axis_cq_tuser(4) <= \<const0>\;
  atspri_m_axis_cq_tuser(3) <= \<const0>\;
  atspri_m_axis_cq_tuser(2) <= \<const0>\;
  atspri_m_axis_cq_tuser(1) <= \<const0>\;
  atspri_m_axis_cq_tuser(0) <= \<const0>\;
  atspri_m_axis_cq_tvalid <= \<const0>\;
  atspri_s_axis_rq_tready <= \<const0>\;
  axi_aclk <= \^axi_aclk\;
  axi_aresetn <= \xdma_0_axi_stream_intf_i/xdma_0_dma_cpl_i/p_0_in\;
  axi_ctl_aresetn <= \<const0>\;
  c2h_dsc_byp_ready_0 <= \<const0>\;
  c2h_dsc_byp_ready_1 <= \<const0>\;
  c2h_dsc_byp_ready_2 <= \<const0>\;
  c2h_dsc_byp_ready_3 <= \<const0>\;
  c2h_sts_0(7) <= \<const0>\;
  c2h_sts_0(6) <= \<const0>\;
  c2h_sts_0(5) <= \<const0>\;
  c2h_sts_0(4) <= \<const0>\;
  c2h_sts_0(3) <= \<const0>\;
  c2h_sts_0(2) <= \<const0>\;
  c2h_sts_0(1) <= \<const0>\;
  c2h_sts_0(0) <= \<const0>\;
  c2h_sts_1(7) <= \<const0>\;
  c2h_sts_1(6) <= \<const0>\;
  c2h_sts_1(5) <= \<const0>\;
  c2h_sts_1(4) <= \<const0>\;
  c2h_sts_1(3) <= \<const0>\;
  c2h_sts_1(2) <= \<const0>\;
  c2h_sts_1(1) <= \<const0>\;
  c2h_sts_1(0) <= \<const0>\;
  c2h_sts_2(7) <= \<const0>\;
  c2h_sts_2(6) <= \<const0>\;
  c2h_sts_2(5) <= \<const0>\;
  c2h_sts_2(4) <= \<const0>\;
  c2h_sts_2(3) <= \<const0>\;
  c2h_sts_2(2) <= \<const0>\;
  c2h_sts_2(1) <= \<const0>\;
  c2h_sts_2(0) <= \<const0>\;
  c2h_sts_3(7) <= \<const0>\;
  c2h_sts_3(6) <= \<const0>\;
  c2h_sts_3(5) <= \<const0>\;
  c2h_sts_3(4) <= \<const0>\;
  c2h_sts_3(3) <= \<const0>\;
  c2h_sts_3(2) <= \<const0>\;
  c2h_sts_3(1) <= \<const0>\;
  c2h_sts_3(0) <= \<const0>\;
  cap_req <= \<const0>\;
  cfg_current_speed_o(2) <= \<const0>\;
  cfg_current_speed_o(1) <= \<const0>\;
  cfg_current_speed_o(0) <= \<const0>\;
  cfg_ds_bus_number_sd(7) <= \<const0>\;
  cfg_ds_bus_number_sd(6) <= \<const0>\;
  cfg_ds_bus_number_sd(5) <= \<const0>\;
  cfg_ds_bus_number_sd(4) <= \<const0>\;
  cfg_ds_bus_number_sd(3) <= \<const0>\;
  cfg_ds_bus_number_sd(2) <= \<const0>\;
  cfg_ds_bus_number_sd(1) <= \<const0>\;
  cfg_ds_bus_number_sd(0) <= \<const0>\;
  cfg_ds_device_number_sd(4) <= \<const0>\;
  cfg_ds_device_number_sd(3) <= \<const0>\;
  cfg_ds_device_number_sd(2) <= \<const0>\;
  cfg_ds_device_number_sd(1) <= \<const0>\;
  cfg_ds_device_number_sd(0) <= \<const0>\;
  cfg_ds_function_number_sd(2) <= \<const0>\;
  cfg_ds_function_number_sd(1) <= \<const0>\;
  cfg_ds_function_number_sd(0) <= \<const0>\;
  cfg_ds_port_number_sd(7) <= \<const0>\;
  cfg_ds_port_number_sd(6) <= \<const0>\;
  cfg_ds_port_number_sd(5) <= \<const0>\;
  cfg_ds_port_number_sd(4) <= \<const0>\;
  cfg_ds_port_number_sd(3) <= \<const0>\;
  cfg_ds_port_number_sd(2) <= \<const0>\;
  cfg_ds_port_number_sd(1) <= \<const0>\;
  cfg_ds_port_number_sd(0) <= \<const0>\;
  cfg_dsn_sd(63) <= \<const0>\;
  cfg_dsn_sd(62) <= \<const0>\;
  cfg_dsn_sd(61) <= \<const0>\;
  cfg_dsn_sd(60) <= \<const0>\;
  cfg_dsn_sd(59) <= \<const0>\;
  cfg_dsn_sd(58) <= \<const0>\;
  cfg_dsn_sd(57) <= \<const0>\;
  cfg_dsn_sd(56) <= \<const0>\;
  cfg_dsn_sd(55) <= \<const0>\;
  cfg_dsn_sd(54) <= \<const0>\;
  cfg_dsn_sd(53) <= \<const0>\;
  cfg_dsn_sd(52) <= \<const0>\;
  cfg_dsn_sd(51) <= \<const0>\;
  cfg_dsn_sd(50) <= \<const0>\;
  cfg_dsn_sd(49) <= \<const0>\;
  cfg_dsn_sd(48) <= \<const0>\;
  cfg_dsn_sd(47) <= \<const0>\;
  cfg_dsn_sd(46) <= \<const0>\;
  cfg_dsn_sd(45) <= \<const0>\;
  cfg_dsn_sd(44) <= \<const0>\;
  cfg_dsn_sd(43) <= \<const0>\;
  cfg_dsn_sd(42) <= \<const0>\;
  cfg_dsn_sd(41) <= \<const0>\;
  cfg_dsn_sd(40) <= \<const0>\;
  cfg_dsn_sd(39) <= \<const0>\;
  cfg_dsn_sd(38) <= \<const0>\;
  cfg_dsn_sd(37) <= \<const0>\;
  cfg_dsn_sd(36) <= \<const0>\;
  cfg_dsn_sd(35) <= \<const0>\;
  cfg_dsn_sd(34) <= \<const0>\;
  cfg_dsn_sd(33) <= \<const0>\;
  cfg_dsn_sd(32) <= \<const0>\;
  cfg_dsn_sd(31) <= \<const0>\;
  cfg_dsn_sd(30) <= \<const0>\;
  cfg_dsn_sd(29) <= \<const0>\;
  cfg_dsn_sd(28) <= \<const0>\;
  cfg_dsn_sd(27) <= \<const0>\;
  cfg_dsn_sd(26) <= \<const0>\;
  cfg_dsn_sd(25) <= \<const0>\;
  cfg_dsn_sd(24) <= \<const0>\;
  cfg_dsn_sd(23) <= \<const0>\;
  cfg_dsn_sd(22) <= \<const0>\;
  cfg_dsn_sd(21) <= \<const0>\;
  cfg_dsn_sd(20) <= \<const0>\;
  cfg_dsn_sd(19) <= \<const0>\;
  cfg_dsn_sd(18) <= \<const0>\;
  cfg_dsn_sd(17) <= \<const0>\;
  cfg_dsn_sd(16) <= \<const0>\;
  cfg_dsn_sd(15) <= \<const0>\;
  cfg_dsn_sd(14) <= \<const0>\;
  cfg_dsn_sd(13) <= \<const0>\;
  cfg_dsn_sd(12) <= \<const0>\;
  cfg_dsn_sd(11) <= \<const0>\;
  cfg_dsn_sd(10) <= \<const0>\;
  cfg_dsn_sd(9) <= \<const0>\;
  cfg_dsn_sd(8) <= \<const0>\;
  cfg_dsn_sd(7) <= \<const0>\;
  cfg_dsn_sd(6) <= \<const0>\;
  cfg_dsn_sd(5) <= \<const0>\;
  cfg_dsn_sd(4) <= \<const0>\;
  cfg_dsn_sd(3) <= \<const0>\;
  cfg_dsn_sd(2) <= \<const0>\;
  cfg_dsn_sd(1) <= \<const0>\;
  cfg_dsn_sd(0) <= \<const0>\;
  cfg_err_cor_in_sd <= \<const0>\;
  cfg_err_cor_o <= \<const0>\;
  cfg_err_fatal_o <= \<const0>\;
  cfg_err_nonfatal_o <= \<const0>\;
  cfg_err_uncor_in_sd <= \<const0>\;
  cfg_ext_function_number(7) <= \<const0>\;
  cfg_ext_function_number(6) <= \<const0>\;
  cfg_ext_function_number(5) <= \<const0>\;
  cfg_ext_function_number(4) <= \<const0>\;
  cfg_ext_function_number(3) <= \<const0>\;
  cfg_ext_function_number(2) <= \<const0>\;
  cfg_ext_function_number(1) <= \<const0>\;
  cfg_ext_function_number(0) <= \<const0>\;
  cfg_ext_read_received <= \<const0>\;
  cfg_ext_register_number(9) <= \<const0>\;
  cfg_ext_register_number(8) <= \<const0>\;
  cfg_ext_register_number(7) <= \<const0>\;
  cfg_ext_register_number(6) <= \<const0>\;
  cfg_ext_register_number(5) <= \<const0>\;
  cfg_ext_register_number(4) <= \<const0>\;
  cfg_ext_register_number(3) <= \<const0>\;
  cfg_ext_register_number(2) <= \<const0>\;
  cfg_ext_register_number(1) <= \<const0>\;
  cfg_ext_register_number(0) <= \<const0>\;
  cfg_ext_write_byte_enable(3) <= \<const0>\;
  cfg_ext_write_byte_enable(2) <= \<const0>\;
  cfg_ext_write_byte_enable(1) <= \<const0>\;
  cfg_ext_write_byte_enable(0) <= \<const0>\;
  cfg_ext_write_data(31) <= \<const0>\;
  cfg_ext_write_data(30) <= \<const0>\;
  cfg_ext_write_data(29) <= \<const0>\;
  cfg_ext_write_data(28) <= \<const0>\;
  cfg_ext_write_data(27) <= \<const0>\;
  cfg_ext_write_data(26) <= \<const0>\;
  cfg_ext_write_data(25) <= \<const0>\;
  cfg_ext_write_data(24) <= \<const0>\;
  cfg_ext_write_data(23) <= \<const0>\;
  cfg_ext_write_data(22) <= \<const0>\;
  cfg_ext_write_data(21) <= \<const0>\;
  cfg_ext_write_data(20) <= \<const0>\;
  cfg_ext_write_data(19) <= \<const0>\;
  cfg_ext_write_data(18) <= \<const0>\;
  cfg_ext_write_data(17) <= \<const0>\;
  cfg_ext_write_data(16) <= \<const0>\;
  cfg_ext_write_data(15) <= \<const0>\;
  cfg_ext_write_data(14) <= \<const0>\;
  cfg_ext_write_data(13) <= \<const0>\;
  cfg_ext_write_data(12) <= \<const0>\;
  cfg_ext_write_data(11) <= \<const0>\;
  cfg_ext_write_data(10) <= \<const0>\;
  cfg_ext_write_data(9) <= \<const0>\;
  cfg_ext_write_data(8) <= \<const0>\;
  cfg_ext_write_data(7) <= \<const0>\;
  cfg_ext_write_data(6) <= \<const0>\;
  cfg_ext_write_data(5) <= \<const0>\;
  cfg_ext_write_data(4) <= \<const0>\;
  cfg_ext_write_data(3) <= \<const0>\;
  cfg_ext_write_data(2) <= \<const0>\;
  cfg_ext_write_data(1) <= \<const0>\;
  cfg_ext_write_data(0) <= \<const0>\;
  cfg_ext_write_received <= \<const0>\;
  cfg_fc_sel_sd(2) <= \<const0>\;
  cfg_fc_sel_sd(1) <= \<const0>\;
  cfg_fc_sel_sd(0) <= \<const0>\;
  cfg_flr_done_sd(3) <= \<const0>\;
  cfg_flr_done_sd(2) <= \<const0>\;
  cfg_flr_done_sd(1) <= \<const0>\;
  cfg_flr_done_sd(0) <= \<const0>\;
  cfg_flr_in_process(3) <= \<const0>\;
  cfg_flr_in_process(2) <= \<const0>\;
  cfg_flr_in_process(1) <= \<const0>\;
  cfg_flr_in_process(0) <= \<const0>\;
  cfg_function_status(7) <= \<const0>\;
  cfg_function_status(6) <= \<const0>\;
  cfg_function_status(5) <= \<const0>\;
  cfg_function_status(4) <= \<const0>\;
  cfg_function_status(3) <= \<const0>\;
  cfg_function_status(2) <= \<const0>\;
  cfg_function_status(1) <= \<const0>\;
  cfg_function_status(0) <= \<const0>\;
  cfg_interrupt_int_sd(3) <= \<const0>\;
  cfg_interrupt_int_sd(2) <= \<const0>\;
  cfg_interrupt_int_sd(1) <= \<const0>\;
  cfg_interrupt_int_sd(0) <= \<const0>\;
  cfg_interrupt_msi_attr_sd(2) <= \<const0>\;
  cfg_interrupt_msi_attr_sd(1) <= \<const0>\;
  cfg_interrupt_msi_attr_sd(0) <= \<const0>\;
  cfg_interrupt_msi_enable(3) <= \<const0>\;
  cfg_interrupt_msi_enable(2) <= \<const0>\;
  cfg_interrupt_msi_enable(1) <= \<const0>\;
  cfg_interrupt_msi_enable(0) <= \<const0>\;
  cfg_interrupt_msi_fail <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(7) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(6) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(5) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(4) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(3) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(2) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(1) <= \<const0>\;
  cfg_interrupt_msi_function_number_sd(0) <= \<const0>\;
  cfg_interrupt_msi_int_sd(31) <= \<const0>\;
  cfg_interrupt_msi_int_sd(30) <= \<const0>\;
  cfg_interrupt_msi_int_sd(29) <= \<const0>\;
  cfg_interrupt_msi_int_sd(28) <= \<const0>\;
  cfg_interrupt_msi_int_sd(27) <= \<const0>\;
  cfg_interrupt_msi_int_sd(26) <= \<const0>\;
  cfg_interrupt_msi_int_sd(25) <= \<const0>\;
  cfg_interrupt_msi_int_sd(24) <= \<const0>\;
  cfg_interrupt_msi_int_sd(23) <= \<const0>\;
  cfg_interrupt_msi_int_sd(22) <= \<const0>\;
  cfg_interrupt_msi_int_sd(21) <= \<const0>\;
  cfg_interrupt_msi_int_sd(20) <= \<const0>\;
  cfg_interrupt_msi_int_sd(19) <= \<const0>\;
  cfg_interrupt_msi_int_sd(18) <= \<const0>\;
  cfg_interrupt_msi_int_sd(17) <= \<const0>\;
  cfg_interrupt_msi_int_sd(16) <= \<const0>\;
  cfg_interrupt_msi_int_sd(15) <= \<const0>\;
  cfg_interrupt_msi_int_sd(14) <= \<const0>\;
  cfg_interrupt_msi_int_sd(13) <= \<const0>\;
  cfg_interrupt_msi_int_sd(12) <= \<const0>\;
  cfg_interrupt_msi_int_sd(11) <= \<const0>\;
  cfg_interrupt_msi_int_sd(10) <= \<const0>\;
  cfg_interrupt_msi_int_sd(9) <= \<const0>\;
  cfg_interrupt_msi_int_sd(8) <= \<const0>\;
  cfg_interrupt_msi_int_sd(7) <= \<const0>\;
  cfg_interrupt_msi_int_sd(6) <= \<const0>\;
  cfg_interrupt_msi_int_sd(5) <= \<const0>\;
  cfg_interrupt_msi_int_sd(4) <= \<const0>\;
  cfg_interrupt_msi_int_sd(3) <= \<const0>\;
  cfg_interrupt_msi_int_sd(2) <= \<const0>\;
  cfg_interrupt_msi_int_sd(1) <= \<const0>\;
  cfg_interrupt_msi_int_sd(0) <= \<const0>\;
  cfg_interrupt_msi_pending_status_data_enable_sd <= \<const0>\;
  cfg_interrupt_msi_pending_status_function_num_sd(3) <= \<const0>\;
  cfg_interrupt_msi_pending_status_function_num_sd(2) <= \<const0>\;
  cfg_interrupt_msi_pending_status_function_num_sd(1) <= \<const0>\;
  cfg_interrupt_msi_pending_status_function_num_sd(0) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(31) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(30) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(29) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(28) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(27) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(26) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(25) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(24) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(23) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(22) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(21) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(20) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(19) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(18) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(17) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(16) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(15) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(14) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(13) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(12) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(11) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(10) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(9) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(8) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(7) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(6) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(5) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(4) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(3) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(2) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(1) <= \<const0>\;
  cfg_interrupt_msi_pending_status_sd(0) <= \<const0>\;
  cfg_interrupt_msi_sent <= \<const0>\;
  cfg_interrupt_msi_tph_present_sd <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(8) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(7) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(6) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(5) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(4) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(3) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(2) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(1) <= \<const0>\;
  cfg_interrupt_msi_tph_st_tag_sd(0) <= \<const0>\;
  cfg_interrupt_msi_tph_type_sd(1) <= \<const0>\;
  cfg_interrupt_msi_tph_type_sd(0) <= \<const0>\;
  cfg_interrupt_msix_address_sd(63) <= \<const0>\;
  cfg_interrupt_msix_address_sd(62) <= \<const0>\;
  cfg_interrupt_msix_address_sd(61) <= \<const0>\;
  cfg_interrupt_msix_address_sd(60) <= \<const0>\;
  cfg_interrupt_msix_address_sd(59) <= \<const0>\;
  cfg_interrupt_msix_address_sd(58) <= \<const0>\;
  cfg_interrupt_msix_address_sd(57) <= \<const0>\;
  cfg_interrupt_msix_address_sd(56) <= \<const0>\;
  cfg_interrupt_msix_address_sd(55) <= \<const0>\;
  cfg_interrupt_msix_address_sd(54) <= \<const0>\;
  cfg_interrupt_msix_address_sd(53) <= \<const0>\;
  cfg_interrupt_msix_address_sd(52) <= \<const0>\;
  cfg_interrupt_msix_address_sd(51) <= \<const0>\;
  cfg_interrupt_msix_address_sd(50) <= \<const0>\;
  cfg_interrupt_msix_address_sd(49) <= \<const0>\;
  cfg_interrupt_msix_address_sd(48) <= \<const0>\;
  cfg_interrupt_msix_address_sd(47) <= \<const0>\;
  cfg_interrupt_msix_address_sd(46) <= \<const0>\;
  cfg_interrupt_msix_address_sd(45) <= \<const0>\;
  cfg_interrupt_msix_address_sd(44) <= \<const0>\;
  cfg_interrupt_msix_address_sd(43) <= \<const0>\;
  cfg_interrupt_msix_address_sd(42) <= \<const0>\;
  cfg_interrupt_msix_address_sd(41) <= \<const0>\;
  cfg_interrupt_msix_address_sd(40) <= \<const0>\;
  cfg_interrupt_msix_address_sd(39) <= \<const0>\;
  cfg_interrupt_msix_address_sd(38) <= \<const0>\;
  cfg_interrupt_msix_address_sd(37) <= \<const0>\;
  cfg_interrupt_msix_address_sd(36) <= \<const0>\;
  cfg_interrupt_msix_address_sd(35) <= \<const0>\;
  cfg_interrupt_msix_address_sd(34) <= \<const0>\;
  cfg_interrupt_msix_address_sd(33) <= \<const0>\;
  cfg_interrupt_msix_address_sd(32) <= \<const0>\;
  cfg_interrupt_msix_address_sd(31) <= \<const0>\;
  cfg_interrupt_msix_address_sd(30) <= \<const0>\;
  cfg_interrupt_msix_address_sd(29) <= \<const0>\;
  cfg_interrupt_msix_address_sd(28) <= \<const0>\;
  cfg_interrupt_msix_address_sd(27) <= \<const0>\;
  cfg_interrupt_msix_address_sd(26) <= \<const0>\;
  cfg_interrupt_msix_address_sd(25) <= \<const0>\;
  cfg_interrupt_msix_address_sd(24) <= \<const0>\;
  cfg_interrupt_msix_address_sd(23) <= \<const0>\;
  cfg_interrupt_msix_address_sd(22) <= \<const0>\;
  cfg_interrupt_msix_address_sd(21) <= \<const0>\;
  cfg_interrupt_msix_address_sd(20) <= \<const0>\;
  cfg_interrupt_msix_address_sd(19) <= \<const0>\;
  cfg_interrupt_msix_address_sd(18) <= \<const0>\;
  cfg_interrupt_msix_address_sd(17) <= \<const0>\;
  cfg_interrupt_msix_address_sd(16) <= \<const0>\;
  cfg_interrupt_msix_address_sd(15) <= \<const0>\;
  cfg_interrupt_msix_address_sd(14) <= \<const0>\;
  cfg_interrupt_msix_address_sd(13) <= \<const0>\;
  cfg_interrupt_msix_address_sd(12) <= \<const0>\;
  cfg_interrupt_msix_address_sd(11) <= \<const0>\;
  cfg_interrupt_msix_address_sd(10) <= \<const0>\;
  cfg_interrupt_msix_address_sd(9) <= \<const0>\;
  cfg_interrupt_msix_address_sd(8) <= \<const0>\;
  cfg_interrupt_msix_address_sd(7) <= \<const0>\;
  cfg_interrupt_msix_address_sd(6) <= \<const0>\;
  cfg_interrupt_msix_address_sd(5) <= \<const0>\;
  cfg_interrupt_msix_address_sd(4) <= \<const0>\;
  cfg_interrupt_msix_address_sd(3) <= \<const0>\;
  cfg_interrupt_msix_address_sd(2) <= \<const0>\;
  cfg_interrupt_msix_address_sd(1) <= \<const0>\;
  cfg_interrupt_msix_address_sd(0) <= \<const0>\;
  cfg_interrupt_msix_data_sd(31) <= \<const0>\;
  cfg_interrupt_msix_data_sd(30) <= \<const0>\;
  cfg_interrupt_msix_data_sd(29) <= \<const0>\;
  cfg_interrupt_msix_data_sd(28) <= \<const0>\;
  cfg_interrupt_msix_data_sd(27) <= \<const0>\;
  cfg_interrupt_msix_data_sd(26) <= \<const0>\;
  cfg_interrupt_msix_data_sd(25) <= \<const0>\;
  cfg_interrupt_msix_data_sd(24) <= \<const0>\;
  cfg_interrupt_msix_data_sd(23) <= \<const0>\;
  cfg_interrupt_msix_data_sd(22) <= \<const0>\;
  cfg_interrupt_msix_data_sd(21) <= \<const0>\;
  cfg_interrupt_msix_data_sd(20) <= \<const0>\;
  cfg_interrupt_msix_data_sd(19) <= \<const0>\;
  cfg_interrupt_msix_data_sd(18) <= \<const0>\;
  cfg_interrupt_msix_data_sd(17) <= \<const0>\;
  cfg_interrupt_msix_data_sd(16) <= \<const0>\;
  cfg_interrupt_msix_data_sd(15) <= \<const0>\;
  cfg_interrupt_msix_data_sd(14) <= \<const0>\;
  cfg_interrupt_msix_data_sd(13) <= \<const0>\;
  cfg_interrupt_msix_data_sd(12) <= \<const0>\;
  cfg_interrupt_msix_data_sd(11) <= \<const0>\;
  cfg_interrupt_msix_data_sd(10) <= \<const0>\;
  cfg_interrupt_msix_data_sd(9) <= \<const0>\;
  cfg_interrupt_msix_data_sd(8) <= \<const0>\;
  cfg_interrupt_msix_data_sd(7) <= \<const0>\;
  cfg_interrupt_msix_data_sd(6) <= \<const0>\;
  cfg_interrupt_msix_data_sd(5) <= \<const0>\;
  cfg_interrupt_msix_data_sd(4) <= \<const0>\;
  cfg_interrupt_msix_data_sd(3) <= \<const0>\;
  cfg_interrupt_msix_data_sd(2) <= \<const0>\;
  cfg_interrupt_msix_data_sd(1) <= \<const0>\;
  cfg_interrupt_msix_data_sd(0) <= \<const0>\;
  cfg_interrupt_msix_enable(1) <= \<const0>\;
  cfg_interrupt_msix_enable(0) <= \<const0>\;
  cfg_interrupt_msix_fail <= \<const0>\;
  cfg_interrupt_msix_int_sd <= \<const0>\;
  cfg_interrupt_msix_mask(1) <= \<const0>\;
  cfg_interrupt_msix_mask(0) <= \<const0>\;
  cfg_interrupt_msix_sent <= \<const0>\;
  cfg_interrupt_msix_vec_pending_sd(1) <= \<const0>\;
  cfg_interrupt_msix_vec_pending_sd(0) <= \<const0>\;
  cfg_interrupt_pending_sd(3) <= \<const0>\;
  cfg_interrupt_pending_sd(2) <= \<const0>\;
  cfg_interrupt_pending_sd(1) <= \<const0>\;
  cfg_interrupt_pending_sd(0) <= \<const0>\;
  cfg_link_training_enable_sd <= \<const0>\;
  cfg_local_error_o(4) <= \<const0>\;
  cfg_local_error_o(3) <= \<const0>\;
  cfg_local_error_o(2) <= \<const0>\;
  cfg_local_error_o(1) <= \<const0>\;
  cfg_local_error_o(0) <= \<const0>\;
  cfg_local_error_valid_o <= \<const0>\;
  cfg_ltssm_state(5) <= \<const0>\;
  cfg_ltssm_state(4) <= \<const0>\;
  cfg_ltssm_state(3) <= \<const0>\;
  cfg_ltssm_state(2) <= \<const0>\;
  cfg_ltssm_state(1) <= \<const0>\;
  cfg_ltssm_state(0) <= \<const0>\;
  cfg_ltssm_state_o(5) <= \<const0>\;
  cfg_ltssm_state_o(4) <= \<const0>\;
  cfg_ltssm_state_o(3) <= \<const0>\;
  cfg_ltssm_state_o(2) <= \<const0>\;
  cfg_ltssm_state_o(1) <= \<const0>\;
  cfg_ltssm_state_o(0) <= \<const0>\;
  cfg_max_payload(2) <= \<const0>\;
  cfg_max_payload(1) <= \<const0>\;
  cfg_max_payload(0) <= \<const0>\;
  cfg_max_read_req(2) <= \<const0>\;
  cfg_max_read_req(1) <= \<const0>\;
  cfg_max_read_req(0) <= \<const0>\;
  cfg_mgmt_addr_sd(9) <= \<const0>\;
  cfg_mgmt_addr_sd(8) <= \<const0>\;
  cfg_mgmt_addr_sd(7) <= \<const0>\;
  cfg_mgmt_addr_sd(6) <= \<const0>\;
  cfg_mgmt_addr_sd(5) <= \<const0>\;
  cfg_mgmt_addr_sd(4) <= \<const0>\;
  cfg_mgmt_addr_sd(3) <= \<const0>\;
  cfg_mgmt_addr_sd(2) <= \<const0>\;
  cfg_mgmt_addr_sd(1) <= \<const0>\;
  cfg_mgmt_addr_sd(0) <= \<const0>\;
  cfg_mgmt_byte_enable_sd(3) <= \<const0>\;
  cfg_mgmt_byte_enable_sd(2) <= \<const0>\;
  cfg_mgmt_byte_enable_sd(1) <= \<const0>\;
  cfg_mgmt_byte_enable_sd(0) <= \<const0>\;
  cfg_mgmt_function_number_sd(7) <= \<const0>\;
  cfg_mgmt_function_number_sd(6) <= \<const0>\;
  cfg_mgmt_function_number_sd(5) <= \<const0>\;
  cfg_mgmt_function_number_sd(4) <= \<const0>\;
  cfg_mgmt_function_number_sd(3) <= \<const0>\;
  cfg_mgmt_function_number_sd(2) <= \<const0>\;
  cfg_mgmt_function_number_sd(1) <= \<const0>\;
  cfg_mgmt_function_number_sd(0) <= \<const0>\;
  cfg_mgmt_read_sd <= \<const0>\;
  cfg_mgmt_type1_cfg_reg_access_sd <= \<const0>\;
  cfg_mgmt_write_data_sd(31) <= \<const0>\;
  cfg_mgmt_write_data_sd(30) <= \<const0>\;
  cfg_mgmt_write_data_sd(29) <= \<const0>\;
  cfg_mgmt_write_data_sd(28) <= \<const0>\;
  cfg_mgmt_write_data_sd(27) <= \<const0>\;
  cfg_mgmt_write_data_sd(26) <= \<const0>\;
  cfg_mgmt_write_data_sd(25) <= \<const0>\;
  cfg_mgmt_write_data_sd(24) <= \<const0>\;
  cfg_mgmt_write_data_sd(23) <= \<const0>\;
  cfg_mgmt_write_data_sd(22) <= \<const0>\;
  cfg_mgmt_write_data_sd(21) <= \<const0>\;
  cfg_mgmt_write_data_sd(20) <= \<const0>\;
  cfg_mgmt_write_data_sd(19) <= \<const0>\;
  cfg_mgmt_write_data_sd(18) <= \<const0>\;
  cfg_mgmt_write_data_sd(17) <= \<const0>\;
  cfg_mgmt_write_data_sd(16) <= \<const0>\;
  cfg_mgmt_write_data_sd(15) <= \<const0>\;
  cfg_mgmt_write_data_sd(14) <= \<const0>\;
  cfg_mgmt_write_data_sd(13) <= \<const0>\;
  cfg_mgmt_write_data_sd(12) <= \<const0>\;
  cfg_mgmt_write_data_sd(11) <= \<const0>\;
  cfg_mgmt_write_data_sd(10) <= \<const0>\;
  cfg_mgmt_write_data_sd(9) <= \<const0>\;
  cfg_mgmt_write_data_sd(8) <= \<const0>\;
  cfg_mgmt_write_data_sd(7) <= \<const0>\;
  cfg_mgmt_write_data_sd(6) <= \<const0>\;
  cfg_mgmt_write_data_sd(5) <= \<const0>\;
  cfg_mgmt_write_data_sd(4) <= \<const0>\;
  cfg_mgmt_write_data_sd(3) <= \<const0>\;
  cfg_mgmt_write_data_sd(2) <= \<const0>\;
  cfg_mgmt_write_data_sd(1) <= \<const0>\;
  cfg_mgmt_write_data_sd(0) <= \<const0>\;
  cfg_mgmt_write_sd <= \<const0>\;
  cfg_msg_transmit_data_sd(31) <= \<const0>\;
  cfg_msg_transmit_data_sd(30) <= \<const0>\;
  cfg_msg_transmit_data_sd(29) <= \<const0>\;
  cfg_msg_transmit_data_sd(28) <= \<const0>\;
  cfg_msg_transmit_data_sd(27) <= \<const0>\;
  cfg_msg_transmit_data_sd(26) <= \<const0>\;
  cfg_msg_transmit_data_sd(25) <= \<const0>\;
  cfg_msg_transmit_data_sd(24) <= \<const0>\;
  cfg_msg_transmit_data_sd(23) <= \<const0>\;
  cfg_msg_transmit_data_sd(22) <= \<const0>\;
  cfg_msg_transmit_data_sd(21) <= \<const0>\;
  cfg_msg_transmit_data_sd(20) <= \<const0>\;
  cfg_msg_transmit_data_sd(19) <= \<const0>\;
  cfg_msg_transmit_data_sd(18) <= \<const0>\;
  cfg_msg_transmit_data_sd(17) <= \<const0>\;
  cfg_msg_transmit_data_sd(16) <= \<const0>\;
  cfg_msg_transmit_data_sd(15) <= \<const0>\;
  cfg_msg_transmit_data_sd(14) <= \<const0>\;
  cfg_msg_transmit_data_sd(13) <= \<const0>\;
  cfg_msg_transmit_data_sd(12) <= \<const0>\;
  cfg_msg_transmit_data_sd(11) <= \<const0>\;
  cfg_msg_transmit_data_sd(10) <= \<const0>\;
  cfg_msg_transmit_data_sd(9) <= \<const0>\;
  cfg_msg_transmit_data_sd(8) <= \<const0>\;
  cfg_msg_transmit_data_sd(7) <= \<const0>\;
  cfg_msg_transmit_data_sd(6) <= \<const0>\;
  cfg_msg_transmit_data_sd(5) <= \<const0>\;
  cfg_msg_transmit_data_sd(4) <= \<const0>\;
  cfg_msg_transmit_data_sd(3) <= \<const0>\;
  cfg_msg_transmit_data_sd(2) <= \<const0>\;
  cfg_msg_transmit_data_sd(1) <= \<const0>\;
  cfg_msg_transmit_data_sd(0) <= \<const0>\;
  cfg_msg_transmit_sd <= \<const0>\;
  cfg_msg_transmit_type_sd(2) <= \<const0>\;
  cfg_msg_transmit_type_sd(1) <= \<const0>\;
  cfg_msg_transmit_type_sd(0) <= \<const0>\;
  cfg_negotiated_width_o(3) <= \<const0>\;
  cfg_negotiated_width_o(2) <= \<const0>\;
  cfg_negotiated_width_o(1) <= \<const0>\;
  cfg_negotiated_width_o(0) <= \<const0>\;
  cfg_status_ats_en <= \<const0>\;
  cfg_status_ats_stu(4) <= \<const0>\;
  cfg_status_ats_stu(3) <= \<const0>\;
  cfg_status_ats_stu(2) <= \<const0>\;
  cfg_status_ats_stu(1) <= \<const0>\;
  cfg_status_ats_stu(0) <= \<const0>\;
  cfg_status_ost_pr_alloc(31) <= \<const0>\;
  cfg_status_ost_pr_alloc(30) <= \<const0>\;
  cfg_status_ost_pr_alloc(29) <= \<const0>\;
  cfg_status_ost_pr_alloc(28) <= \<const0>\;
  cfg_status_ost_pr_alloc(27) <= \<const0>\;
  cfg_status_ost_pr_alloc(26) <= \<const0>\;
  cfg_status_ost_pr_alloc(25) <= \<const0>\;
  cfg_status_ost_pr_alloc(24) <= \<const0>\;
  cfg_status_ost_pr_alloc(23) <= \<const0>\;
  cfg_status_ost_pr_alloc(22) <= \<const0>\;
  cfg_status_ost_pr_alloc(21) <= \<const0>\;
  cfg_status_ost_pr_alloc(20) <= \<const0>\;
  cfg_status_ost_pr_alloc(19) <= \<const0>\;
  cfg_status_ost_pr_alloc(18) <= \<const0>\;
  cfg_status_ost_pr_alloc(17) <= \<const0>\;
  cfg_status_ost_pr_alloc(16) <= \<const0>\;
  cfg_status_ost_pr_alloc(15) <= \<const0>\;
  cfg_status_ost_pr_alloc(14) <= \<const0>\;
  cfg_status_ost_pr_alloc(13) <= \<const0>\;
  cfg_status_ost_pr_alloc(12) <= \<const0>\;
  cfg_status_ost_pr_alloc(11) <= \<const0>\;
  cfg_status_ost_pr_alloc(10) <= \<const0>\;
  cfg_status_ost_pr_alloc(9) <= \<const0>\;
  cfg_status_ost_pr_alloc(8) <= \<const0>\;
  cfg_status_ost_pr_alloc(7) <= \<const0>\;
  cfg_status_ost_pr_alloc(6) <= \<const0>\;
  cfg_status_ost_pr_alloc(5) <= \<const0>\;
  cfg_status_ost_pr_alloc(4) <= \<const0>\;
  cfg_status_ost_pr_alloc(3) <= \<const0>\;
  cfg_status_ost_pr_alloc(2) <= \<const0>\;
  cfg_status_ost_pr_alloc(1) <= \<const0>\;
  cfg_status_ost_pr_alloc(0) <= \<const0>\;
  cfg_status_pr_en <= \<const0>\;
  cfg_status_pr_rf <= \<const0>\;
  cfg_status_pr_rst <= \<const0>\;
  cfg_status_pr_uprgi <= \<const0>\;
  cfg_vf_flr_in_process(251) <= \<const0>\;
  cfg_vf_flr_in_process(250) <= \<const0>\;
  cfg_vf_flr_in_process(249) <= \<const0>\;
  cfg_vf_flr_in_process(248) <= \<const0>\;
  cfg_vf_flr_in_process(247) <= \<const0>\;
  cfg_vf_flr_in_process(246) <= \<const0>\;
  cfg_vf_flr_in_process(245) <= \<const0>\;
  cfg_vf_flr_in_process(244) <= \<const0>\;
  cfg_vf_flr_in_process(243) <= \<const0>\;
  cfg_vf_flr_in_process(242) <= \<const0>\;
  cfg_vf_flr_in_process(241) <= \<const0>\;
  cfg_vf_flr_in_process(240) <= \<const0>\;
  cfg_vf_flr_in_process(239) <= \<const0>\;
  cfg_vf_flr_in_process(238) <= \<const0>\;
  cfg_vf_flr_in_process(237) <= \<const0>\;
  cfg_vf_flr_in_process(236) <= \<const0>\;
  cfg_vf_flr_in_process(235) <= \<const0>\;
  cfg_vf_flr_in_process(234) <= \<const0>\;
  cfg_vf_flr_in_process(233) <= \<const0>\;
  cfg_vf_flr_in_process(232) <= \<const0>\;
  cfg_vf_flr_in_process(231) <= \<const0>\;
  cfg_vf_flr_in_process(230) <= \<const0>\;
  cfg_vf_flr_in_process(229) <= \<const0>\;
  cfg_vf_flr_in_process(228) <= \<const0>\;
  cfg_vf_flr_in_process(227) <= \<const0>\;
  cfg_vf_flr_in_process(226) <= \<const0>\;
  cfg_vf_flr_in_process(225) <= \<const0>\;
  cfg_vf_flr_in_process(224) <= \<const0>\;
  cfg_vf_flr_in_process(223) <= \<const0>\;
  cfg_vf_flr_in_process(222) <= \<const0>\;
  cfg_vf_flr_in_process(221) <= \<const0>\;
  cfg_vf_flr_in_process(220) <= \<const0>\;
  cfg_vf_flr_in_process(219) <= \<const0>\;
  cfg_vf_flr_in_process(218) <= \<const0>\;
  cfg_vf_flr_in_process(217) <= \<const0>\;
  cfg_vf_flr_in_process(216) <= \<const0>\;
  cfg_vf_flr_in_process(215) <= \<const0>\;
  cfg_vf_flr_in_process(214) <= \<const0>\;
  cfg_vf_flr_in_process(213) <= \<const0>\;
  cfg_vf_flr_in_process(212) <= \<const0>\;
  cfg_vf_flr_in_process(211) <= \<const0>\;
  cfg_vf_flr_in_process(210) <= \<const0>\;
  cfg_vf_flr_in_process(209) <= \<const0>\;
  cfg_vf_flr_in_process(208) <= \<const0>\;
  cfg_vf_flr_in_process(207) <= \<const0>\;
  cfg_vf_flr_in_process(206) <= \<const0>\;
  cfg_vf_flr_in_process(205) <= \<const0>\;
  cfg_vf_flr_in_process(204) <= \<const0>\;
  cfg_vf_flr_in_process(203) <= \<const0>\;
  cfg_vf_flr_in_process(202) <= \<const0>\;
  cfg_vf_flr_in_process(201) <= \<const0>\;
  cfg_vf_flr_in_process(200) <= \<const0>\;
  cfg_vf_flr_in_process(199) <= \<const0>\;
  cfg_vf_flr_in_process(198) <= \<const0>\;
  cfg_vf_flr_in_process(197) <= \<const0>\;
  cfg_vf_flr_in_process(196) <= \<const0>\;
  cfg_vf_flr_in_process(195) <= \<const0>\;
  cfg_vf_flr_in_process(194) <= \<const0>\;
  cfg_vf_flr_in_process(193) <= \<const0>\;
  cfg_vf_flr_in_process(192) <= \<const0>\;
  cfg_vf_flr_in_process(191) <= \<const0>\;
  cfg_vf_flr_in_process(190) <= \<const0>\;
  cfg_vf_flr_in_process(189) <= \<const0>\;
  cfg_vf_flr_in_process(188) <= \<const0>\;
  cfg_vf_flr_in_process(187) <= \<const0>\;
  cfg_vf_flr_in_process(186) <= \<const0>\;
  cfg_vf_flr_in_process(185) <= \<const0>\;
  cfg_vf_flr_in_process(184) <= \<const0>\;
  cfg_vf_flr_in_process(183) <= \<const0>\;
  cfg_vf_flr_in_process(182) <= \<const0>\;
  cfg_vf_flr_in_process(181) <= \<const0>\;
  cfg_vf_flr_in_process(180) <= \<const0>\;
  cfg_vf_flr_in_process(179) <= \<const0>\;
  cfg_vf_flr_in_process(178) <= \<const0>\;
  cfg_vf_flr_in_process(177) <= \<const0>\;
  cfg_vf_flr_in_process(176) <= \<const0>\;
  cfg_vf_flr_in_process(175) <= \<const0>\;
  cfg_vf_flr_in_process(174) <= \<const0>\;
  cfg_vf_flr_in_process(173) <= \<const0>\;
  cfg_vf_flr_in_process(172) <= \<const0>\;
  cfg_vf_flr_in_process(171) <= \<const0>\;
  cfg_vf_flr_in_process(170) <= \<const0>\;
  cfg_vf_flr_in_process(169) <= \<const0>\;
  cfg_vf_flr_in_process(168) <= \<const0>\;
  cfg_vf_flr_in_process(167) <= \<const0>\;
  cfg_vf_flr_in_process(166) <= \<const0>\;
  cfg_vf_flr_in_process(165) <= \<const0>\;
  cfg_vf_flr_in_process(164) <= \<const0>\;
  cfg_vf_flr_in_process(163) <= \<const0>\;
  cfg_vf_flr_in_process(162) <= \<const0>\;
  cfg_vf_flr_in_process(161) <= \<const0>\;
  cfg_vf_flr_in_process(160) <= \<const0>\;
  cfg_vf_flr_in_process(159) <= \<const0>\;
  cfg_vf_flr_in_process(158) <= \<const0>\;
  cfg_vf_flr_in_process(157) <= \<const0>\;
  cfg_vf_flr_in_process(156) <= \<const0>\;
  cfg_vf_flr_in_process(155) <= \<const0>\;
  cfg_vf_flr_in_process(154) <= \<const0>\;
  cfg_vf_flr_in_process(153) <= \<const0>\;
  cfg_vf_flr_in_process(152) <= \<const0>\;
  cfg_vf_flr_in_process(151) <= \<const0>\;
  cfg_vf_flr_in_process(150) <= \<const0>\;
  cfg_vf_flr_in_process(149) <= \<const0>\;
  cfg_vf_flr_in_process(148) <= \<const0>\;
  cfg_vf_flr_in_process(147) <= \<const0>\;
  cfg_vf_flr_in_process(146) <= \<const0>\;
  cfg_vf_flr_in_process(145) <= \<const0>\;
  cfg_vf_flr_in_process(144) <= \<const0>\;
  cfg_vf_flr_in_process(143) <= \<const0>\;
  cfg_vf_flr_in_process(142) <= \<const0>\;
  cfg_vf_flr_in_process(141) <= \<const0>\;
  cfg_vf_flr_in_process(140) <= \<const0>\;
  cfg_vf_flr_in_process(139) <= \<const0>\;
  cfg_vf_flr_in_process(138) <= \<const0>\;
  cfg_vf_flr_in_process(137) <= \<const0>\;
  cfg_vf_flr_in_process(136) <= \<const0>\;
  cfg_vf_flr_in_process(135) <= \<const0>\;
  cfg_vf_flr_in_process(134) <= \<const0>\;
  cfg_vf_flr_in_process(133) <= \<const0>\;
  cfg_vf_flr_in_process(132) <= \<const0>\;
  cfg_vf_flr_in_process(131) <= \<const0>\;
  cfg_vf_flr_in_process(130) <= \<const0>\;
  cfg_vf_flr_in_process(129) <= \<const0>\;
  cfg_vf_flr_in_process(128) <= \<const0>\;
  cfg_vf_flr_in_process(127) <= \<const0>\;
  cfg_vf_flr_in_process(126) <= \<const0>\;
  cfg_vf_flr_in_process(125) <= \<const0>\;
  cfg_vf_flr_in_process(124) <= \<const0>\;
  cfg_vf_flr_in_process(123) <= \<const0>\;
  cfg_vf_flr_in_process(122) <= \<const0>\;
  cfg_vf_flr_in_process(121) <= \<const0>\;
  cfg_vf_flr_in_process(120) <= \<const0>\;
  cfg_vf_flr_in_process(119) <= \<const0>\;
  cfg_vf_flr_in_process(118) <= \<const0>\;
  cfg_vf_flr_in_process(117) <= \<const0>\;
  cfg_vf_flr_in_process(116) <= \<const0>\;
  cfg_vf_flr_in_process(115) <= \<const0>\;
  cfg_vf_flr_in_process(114) <= \<const0>\;
  cfg_vf_flr_in_process(113) <= \<const0>\;
  cfg_vf_flr_in_process(112) <= \<const0>\;
  cfg_vf_flr_in_process(111) <= \<const0>\;
  cfg_vf_flr_in_process(110) <= \<const0>\;
  cfg_vf_flr_in_process(109) <= \<const0>\;
  cfg_vf_flr_in_process(108) <= \<const0>\;
  cfg_vf_flr_in_process(107) <= \<const0>\;
  cfg_vf_flr_in_process(106) <= \<const0>\;
  cfg_vf_flr_in_process(105) <= \<const0>\;
  cfg_vf_flr_in_process(104) <= \<const0>\;
  cfg_vf_flr_in_process(103) <= \<const0>\;
  cfg_vf_flr_in_process(102) <= \<const0>\;
  cfg_vf_flr_in_process(101) <= \<const0>\;
  cfg_vf_flr_in_process(100) <= \<const0>\;
  cfg_vf_flr_in_process(99) <= \<const0>\;
  cfg_vf_flr_in_process(98) <= \<const0>\;
  cfg_vf_flr_in_process(97) <= \<const0>\;
  cfg_vf_flr_in_process(96) <= \<const0>\;
  cfg_vf_flr_in_process(95) <= \<const0>\;
  cfg_vf_flr_in_process(94) <= \<const0>\;
  cfg_vf_flr_in_process(93) <= \<const0>\;
  cfg_vf_flr_in_process(92) <= \<const0>\;
  cfg_vf_flr_in_process(91) <= \<const0>\;
  cfg_vf_flr_in_process(90) <= \<const0>\;
  cfg_vf_flr_in_process(89) <= \<const0>\;
  cfg_vf_flr_in_process(88) <= \<const0>\;
  cfg_vf_flr_in_process(87) <= \<const0>\;
  cfg_vf_flr_in_process(86) <= \<const0>\;
  cfg_vf_flr_in_process(85) <= \<const0>\;
  cfg_vf_flr_in_process(84) <= \<const0>\;
  cfg_vf_flr_in_process(83) <= \<const0>\;
  cfg_vf_flr_in_process(82) <= \<const0>\;
  cfg_vf_flr_in_process(81) <= \<const0>\;
  cfg_vf_flr_in_process(80) <= \<const0>\;
  cfg_vf_flr_in_process(79) <= \<const0>\;
  cfg_vf_flr_in_process(78) <= \<const0>\;
  cfg_vf_flr_in_process(77) <= \<const0>\;
  cfg_vf_flr_in_process(76) <= \<const0>\;
  cfg_vf_flr_in_process(75) <= \<const0>\;
  cfg_vf_flr_in_process(74) <= \<const0>\;
  cfg_vf_flr_in_process(73) <= \<const0>\;
  cfg_vf_flr_in_process(72) <= \<const0>\;
  cfg_vf_flr_in_process(71) <= \<const0>\;
  cfg_vf_flr_in_process(70) <= \<const0>\;
  cfg_vf_flr_in_process(69) <= \<const0>\;
  cfg_vf_flr_in_process(68) <= \<const0>\;
  cfg_vf_flr_in_process(67) <= \<const0>\;
  cfg_vf_flr_in_process(66) <= \<const0>\;
  cfg_vf_flr_in_process(65) <= \<const0>\;
  cfg_vf_flr_in_process(64) <= \<const0>\;
  cfg_vf_flr_in_process(63) <= \<const0>\;
  cfg_vf_flr_in_process(62) <= \<const0>\;
  cfg_vf_flr_in_process(61) <= \<const0>\;
  cfg_vf_flr_in_process(60) <= \<const0>\;
  cfg_vf_flr_in_process(59) <= \<const0>\;
  cfg_vf_flr_in_process(58) <= \<const0>\;
  cfg_vf_flr_in_process(57) <= \<const0>\;
  cfg_vf_flr_in_process(56) <= \<const0>\;
  cfg_vf_flr_in_process(55) <= \<const0>\;
  cfg_vf_flr_in_process(54) <= \<const0>\;
  cfg_vf_flr_in_process(53) <= \<const0>\;
  cfg_vf_flr_in_process(52) <= \<const0>\;
  cfg_vf_flr_in_process(51) <= \<const0>\;
  cfg_vf_flr_in_process(50) <= \<const0>\;
  cfg_vf_flr_in_process(49) <= \<const0>\;
  cfg_vf_flr_in_process(48) <= \<const0>\;
  cfg_vf_flr_in_process(47) <= \<const0>\;
  cfg_vf_flr_in_process(46) <= \<const0>\;
  cfg_vf_flr_in_process(45) <= \<const0>\;
  cfg_vf_flr_in_process(44) <= \<const0>\;
  cfg_vf_flr_in_process(43) <= \<const0>\;
  cfg_vf_flr_in_process(42) <= \<const0>\;
  cfg_vf_flr_in_process(41) <= \<const0>\;
  cfg_vf_flr_in_process(40) <= \<const0>\;
  cfg_vf_flr_in_process(39) <= \<const0>\;
  cfg_vf_flr_in_process(38) <= \<const0>\;
  cfg_vf_flr_in_process(37) <= \<const0>\;
  cfg_vf_flr_in_process(36) <= \<const0>\;
  cfg_vf_flr_in_process(35) <= \<const0>\;
  cfg_vf_flr_in_process(34) <= \<const0>\;
  cfg_vf_flr_in_process(33) <= \<const0>\;
  cfg_vf_flr_in_process(32) <= \<const0>\;
  cfg_vf_flr_in_process(31) <= \<const0>\;
  cfg_vf_flr_in_process(30) <= \<const0>\;
  cfg_vf_flr_in_process(29) <= \<const0>\;
  cfg_vf_flr_in_process(28) <= \<const0>\;
  cfg_vf_flr_in_process(27) <= \<const0>\;
  cfg_vf_flr_in_process(26) <= \<const0>\;
  cfg_vf_flr_in_process(25) <= \<const0>\;
  cfg_vf_flr_in_process(24) <= \<const0>\;
  cfg_vf_flr_in_process(23) <= \<const0>\;
  cfg_vf_flr_in_process(22) <= \<const0>\;
  cfg_vf_flr_in_process(21) <= \<const0>\;
  cfg_vf_flr_in_process(20) <= \<const0>\;
  cfg_vf_flr_in_process(19) <= \<const0>\;
  cfg_vf_flr_in_process(18) <= \<const0>\;
  cfg_vf_flr_in_process(17) <= \<const0>\;
  cfg_vf_flr_in_process(16) <= \<const0>\;
  cfg_vf_flr_in_process(15) <= \<const0>\;
  cfg_vf_flr_in_process(14) <= \<const0>\;
  cfg_vf_flr_in_process(13) <= \<const0>\;
  cfg_vf_flr_in_process(12) <= \<const0>\;
  cfg_vf_flr_in_process(11) <= \<const0>\;
  cfg_vf_flr_in_process(10) <= \<const0>\;
  cfg_vf_flr_in_process(9) <= \<const0>\;
  cfg_vf_flr_in_process(8) <= \<const0>\;
  cfg_vf_flr_in_process(7) <= \<const0>\;
  cfg_vf_flr_in_process(6) <= \<const0>\;
  cfg_vf_flr_in_process(5) <= \<const0>\;
  cfg_vf_flr_in_process(4) <= \<const0>\;
  cfg_vf_flr_in_process(3) <= \<const0>\;
  cfg_vf_flr_in_process(2) <= \<const0>\;
  cfg_vf_flr_in_process(1) <= \<const0>\;
  cfg_vf_flr_in_process(0) <= \<const0>\;
  common_commands_out(25) <= \<const0>\;
  common_commands_out(24) <= \<const0>\;
  common_commands_out(23) <= \<const0>\;
  common_commands_out(22) <= \<const0>\;
  common_commands_out(21) <= \<const0>\;
  common_commands_out(20) <= \<const0>\;
  common_commands_out(19) <= \<const0>\;
  common_commands_out(18) <= \<const0>\;
  common_commands_out(17) <= \<const0>\;
  common_commands_out(16) <= \<const0>\;
  common_commands_out(15) <= \<const0>\;
  common_commands_out(14) <= \<const0>\;
  common_commands_out(13) <= \<const0>\;
  common_commands_out(12) <= \<const0>\;
  common_commands_out(11) <= \<const0>\;
  common_commands_out(10) <= \<const0>\;
  common_commands_out(9) <= \<const0>\;
  common_commands_out(8) <= \<const0>\;
  common_commands_out(7) <= \<const0>\;
  common_commands_out(6) <= \<const0>\;
  common_commands_out(5) <= \<const0>\;
  common_commands_out(4) <= \<const0>\;
  common_commands_out(3) <= \<const0>\;
  common_commands_out(2) <= \<const0>\;
  common_commands_out(1) <= \<const0>\;
  common_commands_out(0) <= \<const0>\;
  core_clk <= \<const0>\;
  cpllfreqlock_usp_in(1) <= \<const0>\;
  cpllfreqlock_usp_in(0) <= \<const0>\;
  cpllpd_us_in(1) <= \<const0>\;
  cpllpd_us_in(0) <= \<const0>\;
  cpllpd_usp_in(1) <= \<const0>\;
  cpllpd_usp_in(0) <= \<const0>\;
  cpllreset_us_in(1) <= \<const0>\;
  cpllreset_us_in(0) <= \<const0>\;
  cpllreset_usp_in(1) <= \<const0>\;
  cpllreset_usp_in(0) <= \<const0>\;
  cxs0_active_ack_tx <= \<const0>\;
  cxs0_active_req_rx <= \<const0>\;
  cxs0_cntl_chk_rx <= \<const0>\;
  cxs0_cntl_rx(13) <= \<const0>\;
  cxs0_cntl_rx(12) <= \<const0>\;
  cxs0_cntl_rx(11) <= \<const0>\;
  cxs0_cntl_rx(10) <= \<const0>\;
  cxs0_cntl_rx(9) <= \<const0>\;
  cxs0_cntl_rx(8) <= \<const0>\;
  cxs0_cntl_rx(7) <= \<const0>\;
  cxs0_cntl_rx(6) <= \<const0>\;
  cxs0_cntl_rx(5) <= \<const0>\;
  cxs0_cntl_rx(4) <= \<const0>\;
  cxs0_cntl_rx(3) <= \<const0>\;
  cxs0_cntl_rx(2) <= \<const0>\;
  cxs0_cntl_rx(1) <= \<const0>\;
  cxs0_cntl_rx(0) <= \<const0>\;
  cxs0_crdgnt_chk_tx <= \<const0>\;
  cxs0_crdgnt_tx <= \<const0>\;
  cxs0_crdrtn_chk_rx <= \<const0>\;
  cxs0_crdrtn_rx <= \<const0>\;
  cxs0_data_chk_rx(31) <= \<const0>\;
  cxs0_data_chk_rx(30) <= \<const0>\;
  cxs0_data_chk_rx(29) <= \<const0>\;
  cxs0_data_chk_rx(28) <= \<const0>\;
  cxs0_data_chk_rx(27) <= \<const0>\;
  cxs0_data_chk_rx(26) <= \<const0>\;
  cxs0_data_chk_rx(25) <= \<const0>\;
  cxs0_data_chk_rx(24) <= \<const0>\;
  cxs0_data_chk_rx(23) <= \<const0>\;
  cxs0_data_chk_rx(22) <= \<const0>\;
  cxs0_data_chk_rx(21) <= \<const0>\;
  cxs0_data_chk_rx(20) <= \<const0>\;
  cxs0_data_chk_rx(19) <= \<const0>\;
  cxs0_data_chk_rx(18) <= \<const0>\;
  cxs0_data_chk_rx(17) <= \<const0>\;
  cxs0_data_chk_rx(16) <= \<const0>\;
  cxs0_data_chk_rx(15) <= \<const0>\;
  cxs0_data_chk_rx(14) <= \<const0>\;
  cxs0_data_chk_rx(13) <= \<const0>\;
  cxs0_data_chk_rx(12) <= \<const0>\;
  cxs0_data_chk_rx(11) <= \<const0>\;
  cxs0_data_chk_rx(10) <= \<const0>\;
  cxs0_data_chk_rx(9) <= \<const0>\;
  cxs0_data_chk_rx(8) <= \<const0>\;
  cxs0_data_chk_rx(7) <= \<const0>\;
  cxs0_data_chk_rx(6) <= \<const0>\;
  cxs0_data_chk_rx(5) <= \<const0>\;
  cxs0_data_chk_rx(4) <= \<const0>\;
  cxs0_data_chk_rx(3) <= \<const0>\;
  cxs0_data_chk_rx(2) <= \<const0>\;
  cxs0_data_chk_rx(1) <= \<const0>\;
  cxs0_data_chk_rx(0) <= \<const0>\;
  cxs0_data_rx(255) <= \<const0>\;
  cxs0_data_rx(254) <= \<const0>\;
  cxs0_data_rx(253) <= \<const0>\;
  cxs0_data_rx(252) <= \<const0>\;
  cxs0_data_rx(251) <= \<const0>\;
  cxs0_data_rx(250) <= \<const0>\;
  cxs0_data_rx(249) <= \<const0>\;
  cxs0_data_rx(248) <= \<const0>\;
  cxs0_data_rx(247) <= \<const0>\;
  cxs0_data_rx(246) <= \<const0>\;
  cxs0_data_rx(245) <= \<const0>\;
  cxs0_data_rx(244) <= \<const0>\;
  cxs0_data_rx(243) <= \<const0>\;
  cxs0_data_rx(242) <= \<const0>\;
  cxs0_data_rx(241) <= \<const0>\;
  cxs0_data_rx(240) <= \<const0>\;
  cxs0_data_rx(239) <= \<const0>\;
  cxs0_data_rx(238) <= \<const0>\;
  cxs0_data_rx(237) <= \<const0>\;
  cxs0_data_rx(236) <= \<const0>\;
  cxs0_data_rx(235) <= \<const0>\;
  cxs0_data_rx(234) <= \<const0>\;
  cxs0_data_rx(233) <= \<const0>\;
  cxs0_data_rx(232) <= \<const0>\;
  cxs0_data_rx(231) <= \<const0>\;
  cxs0_data_rx(230) <= \<const0>\;
  cxs0_data_rx(229) <= \<const0>\;
  cxs0_data_rx(228) <= \<const0>\;
  cxs0_data_rx(227) <= \<const0>\;
  cxs0_data_rx(226) <= \<const0>\;
  cxs0_data_rx(225) <= \<const0>\;
  cxs0_data_rx(224) <= \<const0>\;
  cxs0_data_rx(223) <= \<const0>\;
  cxs0_data_rx(222) <= \<const0>\;
  cxs0_data_rx(221) <= \<const0>\;
  cxs0_data_rx(220) <= \<const0>\;
  cxs0_data_rx(219) <= \<const0>\;
  cxs0_data_rx(218) <= \<const0>\;
  cxs0_data_rx(217) <= \<const0>\;
  cxs0_data_rx(216) <= \<const0>\;
  cxs0_data_rx(215) <= \<const0>\;
  cxs0_data_rx(214) <= \<const0>\;
  cxs0_data_rx(213) <= \<const0>\;
  cxs0_data_rx(212) <= \<const0>\;
  cxs0_data_rx(211) <= \<const0>\;
  cxs0_data_rx(210) <= \<const0>\;
  cxs0_data_rx(209) <= \<const0>\;
  cxs0_data_rx(208) <= \<const0>\;
  cxs0_data_rx(207) <= \<const0>\;
  cxs0_data_rx(206) <= \<const0>\;
  cxs0_data_rx(205) <= \<const0>\;
  cxs0_data_rx(204) <= \<const0>\;
  cxs0_data_rx(203) <= \<const0>\;
  cxs0_data_rx(202) <= \<const0>\;
  cxs0_data_rx(201) <= \<const0>\;
  cxs0_data_rx(200) <= \<const0>\;
  cxs0_data_rx(199) <= \<const0>\;
  cxs0_data_rx(198) <= \<const0>\;
  cxs0_data_rx(197) <= \<const0>\;
  cxs0_data_rx(196) <= \<const0>\;
  cxs0_data_rx(195) <= \<const0>\;
  cxs0_data_rx(194) <= \<const0>\;
  cxs0_data_rx(193) <= \<const0>\;
  cxs0_data_rx(192) <= \<const0>\;
  cxs0_data_rx(191) <= \<const0>\;
  cxs0_data_rx(190) <= \<const0>\;
  cxs0_data_rx(189) <= \<const0>\;
  cxs0_data_rx(188) <= \<const0>\;
  cxs0_data_rx(187) <= \<const0>\;
  cxs0_data_rx(186) <= \<const0>\;
  cxs0_data_rx(185) <= \<const0>\;
  cxs0_data_rx(184) <= \<const0>\;
  cxs0_data_rx(183) <= \<const0>\;
  cxs0_data_rx(182) <= \<const0>\;
  cxs0_data_rx(181) <= \<const0>\;
  cxs0_data_rx(180) <= \<const0>\;
  cxs0_data_rx(179) <= \<const0>\;
  cxs0_data_rx(178) <= \<const0>\;
  cxs0_data_rx(177) <= \<const0>\;
  cxs0_data_rx(176) <= \<const0>\;
  cxs0_data_rx(175) <= \<const0>\;
  cxs0_data_rx(174) <= \<const0>\;
  cxs0_data_rx(173) <= \<const0>\;
  cxs0_data_rx(172) <= \<const0>\;
  cxs0_data_rx(171) <= \<const0>\;
  cxs0_data_rx(170) <= \<const0>\;
  cxs0_data_rx(169) <= \<const0>\;
  cxs0_data_rx(168) <= \<const0>\;
  cxs0_data_rx(167) <= \<const0>\;
  cxs0_data_rx(166) <= \<const0>\;
  cxs0_data_rx(165) <= \<const0>\;
  cxs0_data_rx(164) <= \<const0>\;
  cxs0_data_rx(163) <= \<const0>\;
  cxs0_data_rx(162) <= \<const0>\;
  cxs0_data_rx(161) <= \<const0>\;
  cxs0_data_rx(160) <= \<const0>\;
  cxs0_data_rx(159) <= \<const0>\;
  cxs0_data_rx(158) <= \<const0>\;
  cxs0_data_rx(157) <= \<const0>\;
  cxs0_data_rx(156) <= \<const0>\;
  cxs0_data_rx(155) <= \<const0>\;
  cxs0_data_rx(154) <= \<const0>\;
  cxs0_data_rx(153) <= \<const0>\;
  cxs0_data_rx(152) <= \<const0>\;
  cxs0_data_rx(151) <= \<const0>\;
  cxs0_data_rx(150) <= \<const0>\;
  cxs0_data_rx(149) <= \<const0>\;
  cxs0_data_rx(148) <= \<const0>\;
  cxs0_data_rx(147) <= \<const0>\;
  cxs0_data_rx(146) <= \<const0>\;
  cxs0_data_rx(145) <= \<const0>\;
  cxs0_data_rx(144) <= \<const0>\;
  cxs0_data_rx(143) <= \<const0>\;
  cxs0_data_rx(142) <= \<const0>\;
  cxs0_data_rx(141) <= \<const0>\;
  cxs0_data_rx(140) <= \<const0>\;
  cxs0_data_rx(139) <= \<const0>\;
  cxs0_data_rx(138) <= \<const0>\;
  cxs0_data_rx(137) <= \<const0>\;
  cxs0_data_rx(136) <= \<const0>\;
  cxs0_data_rx(135) <= \<const0>\;
  cxs0_data_rx(134) <= \<const0>\;
  cxs0_data_rx(133) <= \<const0>\;
  cxs0_data_rx(132) <= \<const0>\;
  cxs0_data_rx(131) <= \<const0>\;
  cxs0_data_rx(130) <= \<const0>\;
  cxs0_data_rx(129) <= \<const0>\;
  cxs0_data_rx(128) <= \<const0>\;
  cxs0_data_rx(127) <= \<const0>\;
  cxs0_data_rx(126) <= \<const0>\;
  cxs0_data_rx(125) <= \<const0>\;
  cxs0_data_rx(124) <= \<const0>\;
  cxs0_data_rx(123) <= \<const0>\;
  cxs0_data_rx(122) <= \<const0>\;
  cxs0_data_rx(121) <= \<const0>\;
  cxs0_data_rx(120) <= \<const0>\;
  cxs0_data_rx(119) <= \<const0>\;
  cxs0_data_rx(118) <= \<const0>\;
  cxs0_data_rx(117) <= \<const0>\;
  cxs0_data_rx(116) <= \<const0>\;
  cxs0_data_rx(115) <= \<const0>\;
  cxs0_data_rx(114) <= \<const0>\;
  cxs0_data_rx(113) <= \<const0>\;
  cxs0_data_rx(112) <= \<const0>\;
  cxs0_data_rx(111) <= \<const0>\;
  cxs0_data_rx(110) <= \<const0>\;
  cxs0_data_rx(109) <= \<const0>\;
  cxs0_data_rx(108) <= \<const0>\;
  cxs0_data_rx(107) <= \<const0>\;
  cxs0_data_rx(106) <= \<const0>\;
  cxs0_data_rx(105) <= \<const0>\;
  cxs0_data_rx(104) <= \<const0>\;
  cxs0_data_rx(103) <= \<const0>\;
  cxs0_data_rx(102) <= \<const0>\;
  cxs0_data_rx(101) <= \<const0>\;
  cxs0_data_rx(100) <= \<const0>\;
  cxs0_data_rx(99) <= \<const0>\;
  cxs0_data_rx(98) <= \<const0>\;
  cxs0_data_rx(97) <= \<const0>\;
  cxs0_data_rx(96) <= \<const0>\;
  cxs0_data_rx(95) <= \<const0>\;
  cxs0_data_rx(94) <= \<const0>\;
  cxs0_data_rx(93) <= \<const0>\;
  cxs0_data_rx(92) <= \<const0>\;
  cxs0_data_rx(91) <= \<const0>\;
  cxs0_data_rx(90) <= \<const0>\;
  cxs0_data_rx(89) <= \<const0>\;
  cxs0_data_rx(88) <= \<const0>\;
  cxs0_data_rx(87) <= \<const0>\;
  cxs0_data_rx(86) <= \<const0>\;
  cxs0_data_rx(85) <= \<const0>\;
  cxs0_data_rx(84) <= \<const0>\;
  cxs0_data_rx(83) <= \<const0>\;
  cxs0_data_rx(82) <= \<const0>\;
  cxs0_data_rx(81) <= \<const0>\;
  cxs0_data_rx(80) <= \<const0>\;
  cxs0_data_rx(79) <= \<const0>\;
  cxs0_data_rx(78) <= \<const0>\;
  cxs0_data_rx(77) <= \<const0>\;
  cxs0_data_rx(76) <= \<const0>\;
  cxs0_data_rx(75) <= \<const0>\;
  cxs0_data_rx(74) <= \<const0>\;
  cxs0_data_rx(73) <= \<const0>\;
  cxs0_data_rx(72) <= \<const0>\;
  cxs0_data_rx(71) <= \<const0>\;
  cxs0_data_rx(70) <= \<const0>\;
  cxs0_data_rx(69) <= \<const0>\;
  cxs0_data_rx(68) <= \<const0>\;
  cxs0_data_rx(67) <= \<const0>\;
  cxs0_data_rx(66) <= \<const0>\;
  cxs0_data_rx(65) <= \<const0>\;
  cxs0_data_rx(64) <= \<const0>\;
  cxs0_data_rx(63) <= \<const0>\;
  cxs0_data_rx(62) <= \<const0>\;
  cxs0_data_rx(61) <= \<const0>\;
  cxs0_data_rx(60) <= \<const0>\;
  cxs0_data_rx(59) <= \<const0>\;
  cxs0_data_rx(58) <= \<const0>\;
  cxs0_data_rx(57) <= \<const0>\;
  cxs0_data_rx(56) <= \<const0>\;
  cxs0_data_rx(55) <= \<const0>\;
  cxs0_data_rx(54) <= \<const0>\;
  cxs0_data_rx(53) <= \<const0>\;
  cxs0_data_rx(52) <= \<const0>\;
  cxs0_data_rx(51) <= \<const0>\;
  cxs0_data_rx(50) <= \<const0>\;
  cxs0_data_rx(49) <= \<const0>\;
  cxs0_data_rx(48) <= \<const0>\;
  cxs0_data_rx(47) <= \<const0>\;
  cxs0_data_rx(46) <= \<const0>\;
  cxs0_data_rx(45) <= \<const0>\;
  cxs0_data_rx(44) <= \<const0>\;
  cxs0_data_rx(43) <= \<const0>\;
  cxs0_data_rx(42) <= \<const0>\;
  cxs0_data_rx(41) <= \<const0>\;
  cxs0_data_rx(40) <= \<const0>\;
  cxs0_data_rx(39) <= \<const0>\;
  cxs0_data_rx(38) <= \<const0>\;
  cxs0_data_rx(37) <= \<const0>\;
  cxs0_data_rx(36) <= \<const0>\;
  cxs0_data_rx(35) <= \<const0>\;
  cxs0_data_rx(34) <= \<const0>\;
  cxs0_data_rx(33) <= \<const0>\;
  cxs0_data_rx(32) <= \<const0>\;
  cxs0_data_rx(31) <= \<const0>\;
  cxs0_data_rx(30) <= \<const0>\;
  cxs0_data_rx(29) <= \<const0>\;
  cxs0_data_rx(28) <= \<const0>\;
  cxs0_data_rx(27) <= \<const0>\;
  cxs0_data_rx(26) <= \<const0>\;
  cxs0_data_rx(25) <= \<const0>\;
  cxs0_data_rx(24) <= \<const0>\;
  cxs0_data_rx(23) <= \<const0>\;
  cxs0_data_rx(22) <= \<const0>\;
  cxs0_data_rx(21) <= \<const0>\;
  cxs0_data_rx(20) <= \<const0>\;
  cxs0_data_rx(19) <= \<const0>\;
  cxs0_data_rx(18) <= \<const0>\;
  cxs0_data_rx(17) <= \<const0>\;
  cxs0_data_rx(16) <= \<const0>\;
  cxs0_data_rx(15) <= \<const0>\;
  cxs0_data_rx(14) <= \<const0>\;
  cxs0_data_rx(13) <= \<const0>\;
  cxs0_data_rx(12) <= \<const0>\;
  cxs0_data_rx(11) <= \<const0>\;
  cxs0_data_rx(10) <= \<const0>\;
  cxs0_data_rx(9) <= \<const0>\;
  cxs0_data_rx(8) <= \<const0>\;
  cxs0_data_rx(7) <= \<const0>\;
  cxs0_data_rx(6) <= \<const0>\;
  cxs0_data_rx(5) <= \<const0>\;
  cxs0_data_rx(4) <= \<const0>\;
  cxs0_data_rx(3) <= \<const0>\;
  cxs0_data_rx(2) <= \<const0>\;
  cxs0_data_rx(1) <= \<const0>\;
  cxs0_data_rx(0) <= \<const0>\;
  cxs0_deact_hint_tx <= \<const0>\;
  cxs0_valid_chk_rx <= \<const0>\;
  cxs0_valid_rx <= \<const0>\;
  dmonfiforeset_us_in(1) <= \<const0>\;
  dmonfiforeset_us_in(0) <= \<const0>\;
  dmonfiforeset_usp_in(1) <= \<const0>\;
  dmonfiforeset_usp_in(0) <= \<const0>\;
  dmonitorclk_us_in(1) <= \<const0>\;
  dmonitorclk_us_in(0) <= \<const0>\;
  dmonitorclk_usp_in(1) <= \<const0>\;
  dmonitorclk_usp_in(0) <= \<const0>\;
  drp_do(15) <= \<const0>\;
  drp_do(14) <= \<const0>\;
  drp_do(13) <= \<const0>\;
  drp_do(12) <= \<const0>\;
  drp_do(11) <= \<const0>\;
  drp_do(10) <= \<const0>\;
  drp_do(9) <= \<const0>\;
  drp_do(8) <= \<const0>\;
  drp_do(7) <= \<const0>\;
  drp_do(6) <= \<const0>\;
  drp_do(5) <= \<const0>\;
  drp_do(4) <= \<const0>\;
  drp_do(3) <= \<const0>\;
  drp_do(2) <= \<const0>\;
  drp_do(1) <= \<const0>\;
  drp_do(0) <= \<const0>\;
  drp_rdy <= \<const0>\;
  drpaddr_us_in(17) <= \<const0>\;
  drpaddr_us_in(16) <= \<const0>\;
  drpaddr_us_in(15) <= \<const0>\;
  drpaddr_us_in(14) <= \<const0>\;
  drpaddr_us_in(13) <= \<const0>\;
  drpaddr_us_in(12) <= \<const0>\;
  drpaddr_us_in(11) <= \<const0>\;
  drpaddr_us_in(10) <= \<const0>\;
  drpaddr_us_in(9) <= \<const0>\;
  drpaddr_us_in(8) <= \<const0>\;
  drpaddr_us_in(7) <= \<const0>\;
  drpaddr_us_in(6) <= \<const0>\;
  drpaddr_us_in(5) <= \<const0>\;
  drpaddr_us_in(4) <= \<const0>\;
  drpaddr_us_in(3) <= \<const0>\;
  drpaddr_us_in(2) <= \<const0>\;
  drpaddr_us_in(1) <= \<const0>\;
  drpaddr_us_in(0) <= \<const0>\;
  drpaddr_usp_in(19) <= \<const0>\;
  drpaddr_usp_in(18) <= \<const0>\;
  drpaddr_usp_in(17) <= \<const0>\;
  drpaddr_usp_in(16) <= \<const0>\;
  drpaddr_usp_in(15) <= \<const0>\;
  drpaddr_usp_in(14) <= \<const0>\;
  drpaddr_usp_in(13) <= \<const0>\;
  drpaddr_usp_in(12) <= \<const0>\;
  drpaddr_usp_in(11) <= \<const0>\;
  drpaddr_usp_in(10) <= \<const0>\;
  drpaddr_usp_in(9) <= \<const0>\;
  drpaddr_usp_in(8) <= \<const0>\;
  drpaddr_usp_in(7) <= \<const0>\;
  drpaddr_usp_in(6) <= \<const0>\;
  drpaddr_usp_in(5) <= \<const0>\;
  drpaddr_usp_in(4) <= \<const0>\;
  drpaddr_usp_in(3) <= \<const0>\;
  drpaddr_usp_in(2) <= \<const0>\;
  drpaddr_usp_in(1) <= \<const0>\;
  drpaddr_usp_in(0) <= \<const0>\;
  drpclk_us_in(1) <= \<const0>\;
  drpclk_us_in(0) <= \<const0>\;
  drpclk_usp_in <= \<const0>\;
  drpdi_us_in(31) <= \<const0>\;
  drpdi_us_in(30) <= \<const0>\;
  drpdi_us_in(29) <= \<const0>\;
  drpdi_us_in(28) <= \<const0>\;
  drpdi_us_in(27) <= \<const0>\;
  drpdi_us_in(26) <= \<const0>\;
  drpdi_us_in(25) <= \<const0>\;
  drpdi_us_in(24) <= \<const0>\;
  drpdi_us_in(23) <= \<const0>\;
  drpdi_us_in(22) <= \<const0>\;
  drpdi_us_in(21) <= \<const0>\;
  drpdi_us_in(20) <= \<const0>\;
  drpdi_us_in(19) <= \<const0>\;
  drpdi_us_in(18) <= \<const0>\;
  drpdi_us_in(17) <= \<const0>\;
  drpdi_us_in(16) <= \<const0>\;
  drpdi_us_in(15) <= \<const0>\;
  drpdi_us_in(14) <= \<const0>\;
  drpdi_us_in(13) <= \<const0>\;
  drpdi_us_in(12) <= \<const0>\;
  drpdi_us_in(11) <= \<const0>\;
  drpdi_us_in(10) <= \<const0>\;
  drpdi_us_in(9) <= \<const0>\;
  drpdi_us_in(8) <= \<const0>\;
  drpdi_us_in(7) <= \<const0>\;
  drpdi_us_in(6) <= \<const0>\;
  drpdi_us_in(5) <= \<const0>\;
  drpdi_us_in(4) <= \<const0>\;
  drpdi_us_in(3) <= \<const0>\;
  drpdi_us_in(2) <= \<const0>\;
  drpdi_us_in(1) <= \<const0>\;
  drpdi_us_in(0) <= \<const0>\;
  drpdi_usp_in(31) <= \<const0>\;
  drpdi_usp_in(30) <= \<const0>\;
  drpdi_usp_in(29) <= \<const0>\;
  drpdi_usp_in(28) <= \<const0>\;
  drpdi_usp_in(27) <= \<const0>\;
  drpdi_usp_in(26) <= \<const0>\;
  drpdi_usp_in(25) <= \<const0>\;
  drpdi_usp_in(24) <= \<const0>\;
  drpdi_usp_in(23) <= \<const0>\;
  drpdi_usp_in(22) <= \<const0>\;
  drpdi_usp_in(21) <= \<const0>\;
  drpdi_usp_in(20) <= \<const0>\;
  drpdi_usp_in(19) <= \<const0>\;
  drpdi_usp_in(18) <= \<const0>\;
  drpdi_usp_in(17) <= \<const0>\;
  drpdi_usp_in(16) <= \<const0>\;
  drpdi_usp_in(15) <= \<const0>\;
  drpdi_usp_in(14) <= \<const0>\;
  drpdi_usp_in(13) <= \<const0>\;
  drpdi_usp_in(12) <= \<const0>\;
  drpdi_usp_in(11) <= \<const0>\;
  drpdi_usp_in(10) <= \<const0>\;
  drpdi_usp_in(9) <= \<const0>\;
  drpdi_usp_in(8) <= \<const0>\;
  drpdi_usp_in(7) <= \<const0>\;
  drpdi_usp_in(6) <= \<const0>\;
  drpdi_usp_in(5) <= \<const0>\;
  drpdi_usp_in(4) <= \<const0>\;
  drpdi_usp_in(3) <= \<const0>\;
  drpdi_usp_in(2) <= \<const0>\;
  drpdi_usp_in(1) <= \<const0>\;
  drpdi_usp_in(0) <= \<const0>\;
  drpen_us_in(1) <= \<const0>\;
  drpen_us_in(0) <= \<const0>\;
  drpen_usp_in(1) <= \<const0>\;
  drpen_usp_in(0) <= \<const0>\;
  drprst_usp_in(1) <= \<const0>\;
  drprst_usp_in(0) <= \<const0>\;
  drpwe_us_in(1) <= \<const0>\;
  drpwe_us_in(0) <= \<const0>\;
  drpwe_usp_in(1) <= \<const0>\;
  drpwe_usp_in(0) <= \<const0>\;
  ext_ch_gt_drpclk <= \<const0>\;
  ext_ch_gt_drpdo(31) <= \<const0>\;
  ext_ch_gt_drpdo(30) <= \<const0>\;
  ext_ch_gt_drpdo(29) <= \<const0>\;
  ext_ch_gt_drpdo(28) <= \<const0>\;
  ext_ch_gt_drpdo(27) <= \<const0>\;
  ext_ch_gt_drpdo(26) <= \<const0>\;
  ext_ch_gt_drpdo(25) <= \<const0>\;
  ext_ch_gt_drpdo(24) <= \<const0>\;
  ext_ch_gt_drpdo(23) <= \<const0>\;
  ext_ch_gt_drpdo(22) <= \<const0>\;
  ext_ch_gt_drpdo(21) <= \<const0>\;
  ext_ch_gt_drpdo(20) <= \<const0>\;
  ext_ch_gt_drpdo(19) <= \<const0>\;
  ext_ch_gt_drpdo(18) <= \<const0>\;
  ext_ch_gt_drpdo(17) <= \<const0>\;
  ext_ch_gt_drpdo(16) <= \<const0>\;
  ext_ch_gt_drpdo(15) <= \<const0>\;
  ext_ch_gt_drpdo(14) <= \<const0>\;
  ext_ch_gt_drpdo(13) <= \<const0>\;
  ext_ch_gt_drpdo(12) <= \<const0>\;
  ext_ch_gt_drpdo(11) <= \<const0>\;
  ext_ch_gt_drpdo(10) <= \<const0>\;
  ext_ch_gt_drpdo(9) <= \<const0>\;
  ext_ch_gt_drpdo(8) <= \<const0>\;
  ext_ch_gt_drpdo(7) <= \<const0>\;
  ext_ch_gt_drpdo(6) <= \<const0>\;
  ext_ch_gt_drpdo(5) <= \<const0>\;
  ext_ch_gt_drpdo(4) <= \<const0>\;
  ext_ch_gt_drpdo(3) <= \<const0>\;
  ext_ch_gt_drpdo(2) <= \<const0>\;
  ext_ch_gt_drpdo(1) <= \<const0>\;
  ext_ch_gt_drpdo(0) <= \<const0>\;
  ext_ch_gt_drprdy(1) <= \<const0>\;
  ext_ch_gt_drprdy(0) <= \<const0>\;
  ext_phy_clk_bufg_gt_ce <= \<const0>\;
  ext_phy_clk_bufg_gt_reset <= \<const0>\;
  ext_phy_clk_bufgtcemask <= \<const0>\;
  ext_phy_clk_bufgtdiv(8) <= \<const0>\;
  ext_phy_clk_bufgtdiv(7) <= \<const0>\;
  ext_phy_clk_bufgtdiv(6) <= \<const0>\;
  ext_phy_clk_bufgtdiv(5) <= \<const0>\;
  ext_phy_clk_bufgtdiv(4) <= \<const0>\;
  ext_phy_clk_bufgtdiv(3) <= \<const0>\;
  ext_phy_clk_bufgtdiv(2) <= \<const0>\;
  ext_phy_clk_bufgtdiv(1) <= \<const0>\;
  ext_phy_clk_bufgtdiv(0) <= \<const0>\;
  ext_phy_clk_gt_bufgtrstmask <= \<const0>\;
  ext_phy_clk_rst_idle <= \<const0>\;
  ext_phy_clk_txoutclk <= \<const0>\;
  ext_qpll1pd(0) <= \<const0>\;
  ext_qpll1rate(2) <= \<const0>\;
  ext_qpll1rate(1) <= \<const0>\;
  ext_qpll1rate(0) <= \<const0>\;
  ext_qpll1refclk(0) <= \<const0>\;
  ext_qpll1reset(0) <= \<const0>\;
  ext_usp_qpll0pd(0) <= \<const0>\;
  ext_usp_qpll0reset(0) <= \<const0>\;
  ext_usp_qpll1pd(0) <= \<const0>\;
  ext_usp_qpll1reset(0) <= \<const0>\;
  ext_usp_qpllxrate(2) <= \<const0>\;
  ext_usp_qpllxrate(1) <= \<const0>\;
  ext_usp_qpllxrate(0) <= \<const0>\;
  ext_usp_qpllxrcalenb <= \<const0>\;
  ext_usp_qpllxrefclk(0) <= \<const0>\;
  eyescanreset_us_in(1) <= \<const0>\;
  eyescanreset_us_in(0) <= \<const0>\;
  eyescanreset_usp_in(1) <= \<const0>\;
  eyescanreset_usp_in(0) <= \<const0>\;
  gt_bufgtdiv(8) <= \<const0>\;
  gt_bufgtdiv(7) <= \<const0>\;
  gt_bufgtdiv(6) <= \<const0>\;
  gt_bufgtdiv(5) <= \<const0>\;
  gt_bufgtdiv(4) <= \<const0>\;
  gt_bufgtdiv(3) <= \<const0>\;
  gt_bufgtdiv(2) <= \<const0>\;
  gt_bufgtdiv(1) <= \<const0>\;
  gt_bufgtdiv(0) <= \<const0>\;
  gt_ch_drp_rdy(1) <= \<const0>\;
  gt_ch_drp_rdy(0) <= \<const0>\;
  gt_cplllock(1) <= \<const0>\;
  gt_cplllock(0) <= \<const0>\;
  gt_dmonitorout(33) <= \<const0>\;
  gt_dmonitorout(32) <= \<const0>\;
  gt_dmonitorout(31) <= \<const0>\;
  gt_dmonitorout(30) <= \<const0>\;
  gt_dmonitorout(29) <= \<const0>\;
  gt_dmonitorout(28) <= \<const0>\;
  gt_dmonitorout(27) <= \<const0>\;
  gt_dmonitorout(26) <= \<const0>\;
  gt_dmonitorout(25) <= \<const0>\;
  gt_dmonitorout(24) <= \<const0>\;
  gt_dmonitorout(23) <= \<const0>\;
  gt_dmonitorout(22) <= \<const0>\;
  gt_dmonitorout(21) <= \<const0>\;
  gt_dmonitorout(20) <= \<const0>\;
  gt_dmonitorout(19) <= \<const0>\;
  gt_dmonitorout(18) <= \<const0>\;
  gt_dmonitorout(17) <= \<const0>\;
  gt_dmonitorout(16) <= \<const0>\;
  gt_dmonitorout(15) <= \<const0>\;
  gt_dmonitorout(14) <= \<const0>\;
  gt_dmonitorout(13) <= \<const0>\;
  gt_dmonitorout(12) <= \<const0>\;
  gt_dmonitorout(11) <= \<const0>\;
  gt_dmonitorout(10) <= \<const0>\;
  gt_dmonitorout(9) <= \<const0>\;
  gt_dmonitorout(8) <= \<const0>\;
  gt_dmonitorout(7) <= \<const0>\;
  gt_dmonitorout(6) <= \<const0>\;
  gt_dmonitorout(5) <= \<const0>\;
  gt_dmonitorout(4) <= \<const0>\;
  gt_dmonitorout(3) <= \<const0>\;
  gt_dmonitorout(2) <= \<const0>\;
  gt_dmonitorout(1) <= \<const0>\;
  gt_dmonitorout(0) <= \<const0>\;
  gt_drp_clk <= \<const0>\;
  gt_eyescandataerror(1) <= \<const0>\;
  gt_eyescandataerror(0) <= \<const0>\;
  gt_gen34_eios_det(1) <= \<const0>\;
  gt_gen34_eios_det(0) <= \<const0>\;
  gt_gtpowergood(1) <= \<const0>\;
  gt_gtpowergood(0) <= \<const0>\;
  gt_pcierateidle(1) <= \<const0>\;
  gt_pcierateidle(0) <= \<const0>\;
  gt_pcieuserratestart(1) <= \<const0>\;
  gt_pcieuserratestart(0) <= \<const0>\;
  gt_phystatus(1) <= \<const0>\;
  gt_phystatus(0) <= \<const0>\;
  gt_qpll0lock(0) <= \<const0>\;
  gt_qpll1lock(0) <= \<const0>\;
  gt_rxbufstatus(5) <= \<const0>\;
  gt_rxbufstatus(4) <= \<const0>\;
  gt_rxbufstatus(3) <= \<const0>\;
  gt_rxbufstatus(2) <= \<const0>\;
  gt_rxbufstatus(1) <= \<const0>\;
  gt_rxbufstatus(0) <= \<const0>\;
  gt_rxcdrlock(1) <= \<const0>\;
  gt_rxcdrlock(0) <= \<const0>\;
  gt_rxcommadet(1) <= \<const0>\;
  gt_rxcommadet(0) <= \<const0>\;
  gt_rxdlysresetdone(1) <= \<const0>\;
  gt_rxdlysresetdone(0) <= \<const0>\;
  gt_rxoutclk(1) <= \<const0>\;
  gt_rxoutclk(0) <= \<const0>\;
  gt_rxoutclkfabric(1) <= \<const0>\;
  gt_rxoutclkfabric(0) <= \<const0>\;
  gt_rxoutclkpcs(1) <= \<const0>\;
  gt_rxoutclkpcs(0) <= \<const0>\;
  gt_rxphaligndone(1) <= \<const0>\;
  gt_rxphaligndone(0) <= \<const0>\;
  gt_rxpmaresetdone(1) <= \<const0>\;
  gt_rxpmaresetdone(0) <= \<const0>\;
  gt_rxprbserr(1) <= \<const0>\;
  gt_rxprbserr(0) <= \<const0>\;
  gt_rxprbslocked(1) <= \<const0>\;
  gt_rxprbslocked(0) <= \<const0>\;
  gt_rxrecclkout(1) <= \<const0>\;
  gt_rxrecclkout(0) <= \<const0>\;
  gt_rxresetdone(1) <= \<const0>\;
  gt_rxresetdone(0) <= \<const0>\;
  gt_rxstatus(5) <= \<const0>\;
  gt_rxstatus(4) <= \<const0>\;
  gt_rxstatus(3) <= \<const0>\;
  gt_rxstatus(2) <= \<const0>\;
  gt_rxstatus(1) <= \<const0>\;
  gt_rxstatus(0) <= \<const0>\;
  gt_rxsyncdone(1) <= \<const0>\;
  gt_rxsyncdone(0) <= \<const0>\;
  gt_rxvalid(1) <= \<const0>\;
  gt_rxvalid(0) <= \<const0>\;
  gt_txdlysresetdone(1) <= \<const0>\;
  gt_txdlysresetdone(0) <= \<const0>\;
  gt_txelecidle(1) <= \<const0>\;
  gt_txelecidle(0) <= \<const0>\;
  gt_txoutclk(1) <= \<const0>\;
  gt_txoutclk(0) <= \<const0>\;
  gt_txoutclkfabric(1) <= \<const0>\;
  gt_txoutclkfabric(0) <= \<const0>\;
  gt_txoutclkpcs(1) <= \<const0>\;
  gt_txoutclkpcs(0) <= \<const0>\;
  gt_txphaligndone(1) <= \<const0>\;
  gt_txphaligndone(0) <= \<const0>\;
  gt_txphinitdone(1) <= \<const0>\;
  gt_txphinitdone(0) <= \<const0>\;
  gt_txpmaresetdone(1) <= \<const0>\;
  gt_txpmaresetdone(0) <= \<const0>\;
  gt_txprogdivresetdone(1) <= \<const0>\;
  gt_txprogdivresetdone(0) <= \<const0>\;
  gt_txresetdone(1) <= \<const0>\;
  gt_txresetdone(0) <= \<const0>\;
  gt_txsyncdone(1) <= \<const0>\;
  gt_txsyncdone(0) <= \<const0>\;
  gthrxn_us_in(1) <= \<const0>\;
  gthrxn_us_in(0) <= \<const0>\;
  gthrxp_us_in(1) <= \<const0>\;
  gthrxp_us_in(0) <= \<const0>\;
  gtrefclk00_usp_in(0) <= \<const0>\;
  gtrefclk01_us_in(0) <= \<const0>\;
  gtrefclk01_usp_in(0) <= \<const0>\;
  gtrefclk0_us_in(1) <= \<const0>\;
  gtrefclk0_us_in(0) <= \<const0>\;
  gtrefclk0_usp_in(1) <= \<const0>\;
  gtrefclk0_usp_in(0) <= \<const0>\;
  gtrxreset_us_in(1) <= \<const0>\;
  gtrxreset_us_in(0) <= \<const0>\;
  gtrxreset_usp_in(1) <= \<const0>\;
  gtrxreset_usp_in(0) <= \<const0>\;
  gttxreset_us_in(1) <= \<const0>\;
  gttxreset_us_in(0) <= \<const0>\;
  gttxreset_usp_in(1) <= \<const0>\;
  gttxreset_usp_in(0) <= \<const0>\;
  gtwiz_reset_rx_done_us_in <= \<const0>\;
  gtwiz_reset_rx_done_usp_in <= \<const0>\;
  gtwiz_reset_tx_done_us_in <= \<const0>\;
  gtwiz_reset_tx_done_usp_in <= \<const0>\;
  gtwiz_userclk_rx_active_us_in <= \<const0>\;
  gtwiz_userclk_rx_active_usp_in <= \<const0>\;
  gtwiz_userclk_tx_active_us_in <= \<const0>\;
  gtwiz_userclk_tx_active_usp_in <= \<const0>\;
  gtwiz_userclk_tx_reset_us_in <= \<const0>\;
  h2c_dsc_byp_ready_0 <= \<const0>\;
  h2c_dsc_byp_ready_1 <= \<const0>\;
  h2c_dsc_byp_ready_2 <= \<const0>\;
  h2c_dsc_byp_ready_3 <= \<const0>\;
  h2c_sts_0(7) <= \<const0>\;
  h2c_sts_0(6) <= \<const0>\;
  h2c_sts_0(5) <= \<const0>\;
  h2c_sts_0(4) <= \<const0>\;
  h2c_sts_0(3) <= \<const0>\;
  h2c_sts_0(2) <= \<const0>\;
  h2c_sts_0(1) <= \<const0>\;
  h2c_sts_0(0) <= \<const0>\;
  h2c_sts_1(7) <= \<const0>\;
  h2c_sts_1(6) <= \<const0>\;
  h2c_sts_1(5) <= \<const0>\;
  h2c_sts_1(4) <= \<const0>\;
  h2c_sts_1(3) <= \<const0>\;
  h2c_sts_1(2) <= \<const0>\;
  h2c_sts_1(1) <= \<const0>\;
  h2c_sts_1(0) <= \<const0>\;
  h2c_sts_2(7) <= \<const0>\;
  h2c_sts_2(6) <= \<const0>\;
  h2c_sts_2(5) <= \<const0>\;
  h2c_sts_2(4) <= \<const0>\;
  h2c_sts_2(3) <= \<const0>\;
  h2c_sts_2(2) <= \<const0>\;
  h2c_sts_2(1) <= \<const0>\;
  h2c_sts_2(0) <= \<const0>\;
  h2c_sts_3(7) <= \<const0>\;
  h2c_sts_3(6) <= \<const0>\;
  h2c_sts_3(5) <= \<const0>\;
  h2c_sts_3(4) <= \<const0>\;
  h2c_sts_3(3) <= \<const0>\;
  h2c_sts_3(2) <= \<const0>\;
  h2c_sts_3(1) <= \<const0>\;
  h2c_sts_3(0) <= \<const0>\;
  int_dclk_out <= \<const0>\;
  int_oobclk_out <= \<const0>\;
  int_pclk_out_slave <= \<const0>\;
  int_pipe_rxusrclk_out <= \<const0>\;
  int_qpll1lock_out(0) <= \<const0>\;
  int_qpll1outclk_out(0) <= \<const0>\;
  int_qpll1outrefclk_out(0) <= \<const0>\;
  int_qplllock_out(1) <= \<const0>\;
  int_qplllock_out(0) <= \<const0>\;
  int_qplloutclk_out(1) <= \<const0>\;
  int_qplloutclk_out(0) <= \<const0>\;
  int_qplloutrefclk_out(1) <= \<const0>\;
  int_qplloutrefclk_out(0) <= \<const0>\;
  int_rxoutclk_out(1) <= \<const0>\;
  int_rxoutclk_out(0) <= \<const0>\;
  int_userclk1_out <= \<const0>\;
  int_userclk2_out <= \<const0>\;
  int_usp_qpll0lock_out(0) <= \<const0>\;
  int_usp_qpll0outclk_out(0) <= \<const0>\;
  int_usp_qpll0outrefclk_out(0) <= \<const0>\;
  int_usp_qpll1lock_out(0) <= \<const0>\;
  int_usp_qpll1outclk_out(0) <= \<const0>\;
  int_usp_qpll1outrefclk_out(0) <= \<const0>\;
  interrupt_out <= \<const0>\;
  interrupt_out_msi_vec0to31 <= \<const0>\;
  interrupt_out_msi_vec32to63 <= \<const0>\;
  interrupt_out_msix_0 <= \<const0>\;
  interrupt_out_msix_1 <= \<const0>\;
  interrupt_out_msix_2 <= \<const0>\;
  interrupt_out_msix_3 <= \<const0>\;
  loopback_us_in(5) <= \<const0>\;
  loopback_us_in(4) <= \<const0>\;
  loopback_us_in(3) <= \<const0>\;
  loopback_us_in(2) <= \<const0>\;
  loopback_us_in(1) <= \<const0>\;
  loopback_us_in(0) <= \<const0>\;
  loopback_usp_in(5) <= \<const0>\;
  loopback_usp_in(4) <= \<const0>\;
  loopback_usp_in(3) <= \<const0>\;
  loopback_usp_in(2) <= \<const0>\;
  loopback_usp_in(1) <= \<const0>\;
  loopback_usp_in(0) <= \<const0>\;
  m_axi_araddr(63 downto 0) <= m_axi_araddr_temp(63 downto 0);
  m_axi_arburst(1) <= \<const0>\;
  m_axi_arburst(0) <= \^m_axi_arburst\(0);
  m_axi_arcache(3) <= \<const0>\;
  m_axi_arcache(2) <= \<const0>\;
  m_axi_arcache(1) <= \<const1>\;
  m_axi_arcache(0) <= \<const1>\;
  m_axi_arid(3) <= \<const0>\;
  m_axi_arid(2) <= \<const0>\;
  m_axi_arid(1) <= \<const0>\;
  m_axi_arid(0) <= \<const0>\;
  m_axi_arlock <= \<const0>\;
  m_axi_arprot(2) <= \<const0>\;
  m_axi_arprot(1) <= \<const0>\;
  m_axi_arprot(0) <= \<const0>\;
  m_axi_arsize(2) <= \<const0>\;
  m_axi_arsize(1 downto 0) <= \^m_axi_arsize\(1 downto 0);
  m_axi_awaddr(63 downto 0) <= m_axi_awaddr_temp(63 downto 0);
  m_axi_awburst(1) <= \<const0>\;
  m_axi_awburst(0) <= \^m_axi_awburst\(0);
  m_axi_awcache(3) <= \<const0>\;
  m_axi_awcache(2) <= \<const0>\;
  m_axi_awcache(1) <= \<const1>\;
  m_axi_awcache(0) <= \<const1>\;
  m_axi_awid(3) <= \<const0>\;
  m_axi_awid(2) <= \<const0>\;
  m_axi_awid(1) <= \<const0>\;
  m_axi_awid(0) <= \<const0>\;
  m_axi_awlock <= \<const0>\;
  m_axi_awprot(2) <= \<const0>\;
  m_axi_awprot(1) <= \<const0>\;
  m_axi_awprot(0) <= \<const0>\;
  m_axi_awsize(2) <= \<const0>\;
  m_axi_awsize(1 downto 0) <= \^m_axi_awsize\(1 downto 0);
  m_axi_wuser(7) <= \<const0>\;
  m_axi_wuser(6) <= \<const0>\;
  m_axi_wuser(5) <= \<const0>\;
  m_axi_wuser(4) <= \<const0>\;
  m_axi_wuser(3) <= \<const0>\;
  m_axi_wuser(2) <= \<const0>\;
  m_axi_wuser(1) <= \<const0>\;
  m_axi_wuser(0) <= \<const0>\;
  m_axib_araddr(63 downto 0) <= m_axib_araddr_temp(63 downto 0);
  m_axib_arburst(1) <= \<const0>\;
  m_axib_arburst(0) <= \<const1>\;
  m_axib_arcache(3) <= \<const0>\;
  m_axib_arcache(2) <= \<const0>\;
  m_axib_arcache(1) <= \<const1>\;
  m_axib_arcache(0) <= \<const1>\;
  m_axib_arid(3) <= \<const0>\;
  m_axib_arid(2) <= \<const0>\;
  m_axib_arid(1) <= \<const0>\;
  m_axib_arid(0) <= \<const0>\;
  m_axib_arlock <= \<const0>\;
  m_axib_arprot(2) <= \<const0>\;
  m_axib_arprot(1 downto 0) <= \^m_axib_arprot\(1 downto 0);
  m_axib_arsize(2) <= \<const0>\;
  m_axib_arsize(1 downto 0) <= \^m_axib_arsize\(1 downto 0);
  m_axib_aruser(7) <= \<const0>\;
  m_axib_aruser(6) <= \<const0>\;
  m_axib_aruser(5) <= \<const0>\;
  m_axib_aruser(4) <= \<const0>\;
  m_axib_aruser(3) <= \<const0>\;
  m_axib_aruser(2) <= \<const0>\;
  m_axib_aruser(1) <= \<const0>\;
  m_axib_aruser(0) <= \<const0>\;
  m_axib_awaddr(63 downto 0) <= m_axib_awaddr_temp(63 downto 0);
  m_axib_awburst(1) <= \<const0>\;
  m_axib_awburst(0) <= \<const1>\;
  m_axib_awcache(3) <= \<const0>\;
  m_axib_awcache(2) <= \<const0>\;
  m_axib_awcache(1) <= \<const1>\;
  m_axib_awcache(0) <= \<const1>\;
  m_axib_awid(3) <= \<const0>\;
  m_axib_awid(2) <= \<const0>\;
  m_axib_awid(1) <= \<const0>\;
  m_axib_awid(0) <= \<const0>\;
  m_axib_awlock <= \<const0>\;
  m_axib_awprot(2) <= \<const0>\;
  m_axib_awprot(1 downto 0) <= \^m_axib_awprot\(1 downto 0);
  m_axib_awsize(2) <= \<const0>\;
  m_axib_awsize(1 downto 0) <= \^m_axib_awsize\(1 downto 0);
  m_axib_awuser(7) <= \<const0>\;
  m_axib_awuser(6) <= \<const0>\;
  m_axib_awuser(5) <= \<const0>\;
  m_axib_awuser(4) <= \<const0>\;
  m_axib_awuser(3) <= \<const0>\;
  m_axib_awuser(2) <= \<const0>\;
  m_axib_awuser(1) <= \<const0>\;
  m_axib_awuser(0) <= \<const0>\;
  m_axib_wuser(7) <= \<const0>\;
  m_axib_wuser(6) <= \<const0>\;
  m_axib_wuser(5) <= \<const0>\;
  m_axib_wuser(4) <= \<const0>\;
  m_axib_wuser(3) <= \<const0>\;
  m_axib_wuser(2) <= \<const0>\;
  m_axib_wuser(1) <= \<const0>\;
  m_axib_wuser(0) <= \<const0>\;
  m_axil_araddr(31) <= \<const0>\;
  m_axil_araddr(30) <= \<const0>\;
  m_axil_araddr(29) <= \<const0>\;
  m_axil_araddr(28) <= \<const0>\;
  m_axil_araddr(27) <= \<const0>\;
  m_axil_araddr(26) <= \<const0>\;
  m_axil_araddr(25) <= \<const0>\;
  m_axil_araddr(24) <= \<const0>\;
  m_axil_araddr(23) <= \<const0>\;
  m_axil_araddr(22) <= \<const0>\;
  m_axil_araddr(21) <= \<const0>\;
  m_axil_araddr(20) <= \<const0>\;
  m_axil_araddr(19) <= \<const0>\;
  m_axil_araddr(18) <= \<const0>\;
  m_axil_araddr(17) <= \<const0>\;
  m_axil_araddr(16) <= \<const0>\;
  m_axil_araddr(15) <= \<const0>\;
  m_axil_araddr(14) <= \<const0>\;
  m_axil_araddr(13) <= \<const0>\;
  m_axil_araddr(12) <= \<const0>\;
  m_axil_araddr(11) <= \<const0>\;
  m_axil_araddr(10) <= \<const0>\;
  m_axil_araddr(9) <= \<const0>\;
  m_axil_araddr(8) <= \<const0>\;
  m_axil_araddr(7) <= \<const0>\;
  m_axil_araddr(6) <= \<const0>\;
  m_axil_araddr(5) <= \<const0>\;
  m_axil_araddr(4) <= \<const0>\;
  m_axil_araddr(3) <= \<const0>\;
  m_axil_araddr(2) <= \<const0>\;
  m_axil_araddr(1) <= \<const0>\;
  m_axil_araddr(0) <= \<const0>\;
  m_axil_arprot(2) <= \<const0>\;
  m_axil_arprot(1) <= \<const0>\;
  m_axil_arprot(0) <= \<const0>\;
  m_axil_aruser(10) <= \<const0>\;
  m_axil_aruser(9) <= \<const0>\;
  m_axil_aruser(8) <= \<const0>\;
  m_axil_aruser(7) <= \<const0>\;
  m_axil_aruser(6) <= \<const0>\;
  m_axil_aruser(5) <= \<const0>\;
  m_axil_aruser(4) <= \<const0>\;
  m_axil_aruser(3) <= \<const0>\;
  m_axil_aruser(2) <= \<const0>\;
  m_axil_aruser(1) <= \<const0>\;
  m_axil_aruser(0) <= \<const0>\;
  m_axil_arvalid <= \<const0>\;
  m_axil_awaddr(31) <= \<const0>\;
  m_axil_awaddr(30) <= \<const0>\;
  m_axil_awaddr(29) <= \<const0>\;
  m_axil_awaddr(28) <= \<const0>\;
  m_axil_awaddr(27) <= \<const0>\;
  m_axil_awaddr(26) <= \<const0>\;
  m_axil_awaddr(25) <= \<const0>\;
  m_axil_awaddr(24) <= \<const0>\;
  m_axil_awaddr(23) <= \<const0>\;
  m_axil_awaddr(22) <= \<const0>\;
  m_axil_awaddr(21) <= \<const0>\;
  m_axil_awaddr(20) <= \<const0>\;
  m_axil_awaddr(19) <= \<const0>\;
  m_axil_awaddr(18) <= \<const0>\;
  m_axil_awaddr(17) <= \<const0>\;
  m_axil_awaddr(16) <= \<const0>\;
  m_axil_awaddr(15) <= \<const0>\;
  m_axil_awaddr(14) <= \<const0>\;
  m_axil_awaddr(13) <= \<const0>\;
  m_axil_awaddr(12) <= \<const0>\;
  m_axil_awaddr(11) <= \<const0>\;
  m_axil_awaddr(10) <= \<const0>\;
  m_axil_awaddr(9) <= \<const0>\;
  m_axil_awaddr(8) <= \<const0>\;
  m_axil_awaddr(7) <= \<const0>\;
  m_axil_awaddr(6) <= \<const0>\;
  m_axil_awaddr(5) <= \<const0>\;
  m_axil_awaddr(4) <= \<const0>\;
  m_axil_awaddr(3) <= \<const0>\;
  m_axil_awaddr(2) <= \<const0>\;
  m_axil_awaddr(1) <= \<const0>\;
  m_axil_awaddr(0) <= \<const0>\;
  m_axil_awprot(2) <= \<const0>\;
  m_axil_awprot(1) <= \<const0>\;
  m_axil_awprot(0) <= \<const0>\;
  m_axil_awuser(10) <= \<const0>\;
  m_axil_awuser(9) <= \<const0>\;
  m_axil_awuser(8) <= \<const0>\;
  m_axil_awuser(7) <= \<const0>\;
  m_axil_awuser(6) <= \<const0>\;
  m_axil_awuser(5) <= \<const0>\;
  m_axil_awuser(4) <= \<const0>\;
  m_axil_awuser(3) <= \<const0>\;
  m_axil_awuser(2) <= \<const0>\;
  m_axil_awuser(1) <= \<const0>\;
  m_axil_awuser(0) <= \<const0>\;
  m_axil_awvalid <= \<const0>\;
  m_axil_bready <= \<const0>\;
  m_axil_rready <= \<const0>\;
  m_axil_wdata(31) <= \<const0>\;
  m_axil_wdata(30) <= \<const0>\;
  m_axil_wdata(29) <= \<const0>\;
  m_axil_wdata(28) <= \<const0>\;
  m_axil_wdata(27) <= \<const0>\;
  m_axil_wdata(26) <= \<const0>\;
  m_axil_wdata(25) <= \<const0>\;
  m_axil_wdata(24) <= \<const0>\;
  m_axil_wdata(23) <= \<const0>\;
  m_axil_wdata(22) <= \<const0>\;
  m_axil_wdata(21) <= \<const0>\;
  m_axil_wdata(20) <= \<const0>\;
  m_axil_wdata(19) <= \<const0>\;
  m_axil_wdata(18) <= \<const0>\;
  m_axil_wdata(17) <= \<const0>\;
  m_axil_wdata(16) <= \<const0>\;
  m_axil_wdata(15) <= \<const0>\;
  m_axil_wdata(14) <= \<const0>\;
  m_axil_wdata(13) <= \<const0>\;
  m_axil_wdata(12) <= \<const0>\;
  m_axil_wdata(11) <= \<const0>\;
  m_axil_wdata(10) <= \<const0>\;
  m_axil_wdata(9) <= \<const0>\;
  m_axil_wdata(8) <= \<const0>\;
  m_axil_wdata(7) <= \<const0>\;
  m_axil_wdata(6) <= \<const0>\;
  m_axil_wdata(5) <= \<const0>\;
  m_axil_wdata(4) <= \<const0>\;
  m_axil_wdata(3) <= \<const0>\;
  m_axil_wdata(2) <= \<const0>\;
  m_axil_wdata(1) <= \<const0>\;
  m_axil_wdata(0) <= \<const0>\;
  m_axil_wstrb(3) <= \<const0>\;
  m_axil_wstrb(2) <= \<const0>\;
  m_axil_wstrb(1) <= \<const0>\;
  m_axil_wstrb(0) <= \<const0>\;
  m_axil_wvalid <= \<const0>\;
  m_axis_cc_tdata_out(63) <= \<const0>\;
  m_axis_cc_tdata_out(62) <= \<const0>\;
  m_axis_cc_tdata_out(61) <= \<const0>\;
  m_axis_cc_tdata_out(60) <= \<const0>\;
  m_axis_cc_tdata_out(59) <= \<const0>\;
  m_axis_cc_tdata_out(58) <= \<const0>\;
  m_axis_cc_tdata_out(57) <= \<const0>\;
  m_axis_cc_tdata_out(56) <= \<const0>\;
  m_axis_cc_tdata_out(55) <= \<const0>\;
  m_axis_cc_tdata_out(54) <= \<const0>\;
  m_axis_cc_tdata_out(53) <= \<const0>\;
  m_axis_cc_tdata_out(52) <= \<const0>\;
  m_axis_cc_tdata_out(51) <= \<const0>\;
  m_axis_cc_tdata_out(50) <= \<const0>\;
  m_axis_cc_tdata_out(49) <= \<const0>\;
  m_axis_cc_tdata_out(48) <= \<const0>\;
  m_axis_cc_tdata_out(47) <= \<const0>\;
  m_axis_cc_tdata_out(46) <= \<const0>\;
  m_axis_cc_tdata_out(45) <= \<const0>\;
  m_axis_cc_tdata_out(44) <= \<const0>\;
  m_axis_cc_tdata_out(43) <= \<const0>\;
  m_axis_cc_tdata_out(42) <= \<const0>\;
  m_axis_cc_tdata_out(41) <= \<const0>\;
  m_axis_cc_tdata_out(40) <= \<const0>\;
  m_axis_cc_tdata_out(39) <= \<const0>\;
  m_axis_cc_tdata_out(38) <= \<const0>\;
  m_axis_cc_tdata_out(37) <= \<const0>\;
  m_axis_cc_tdata_out(36) <= \<const0>\;
  m_axis_cc_tdata_out(35) <= \<const0>\;
  m_axis_cc_tdata_out(34) <= \<const0>\;
  m_axis_cc_tdata_out(33) <= \<const0>\;
  m_axis_cc_tdata_out(32) <= \<const0>\;
  m_axis_cc_tdata_out(31) <= \<const0>\;
  m_axis_cc_tdata_out(30) <= \<const0>\;
  m_axis_cc_tdata_out(29) <= \<const0>\;
  m_axis_cc_tdata_out(28) <= \<const0>\;
  m_axis_cc_tdata_out(27) <= \<const0>\;
  m_axis_cc_tdata_out(26) <= \<const0>\;
  m_axis_cc_tdata_out(25) <= \<const0>\;
  m_axis_cc_tdata_out(24) <= \<const0>\;
  m_axis_cc_tdata_out(23) <= \<const0>\;
  m_axis_cc_tdata_out(22) <= \<const0>\;
  m_axis_cc_tdata_out(21) <= \<const0>\;
  m_axis_cc_tdata_out(20) <= \<const0>\;
  m_axis_cc_tdata_out(19) <= \<const0>\;
  m_axis_cc_tdata_out(18) <= \<const0>\;
  m_axis_cc_tdata_out(17) <= \<const0>\;
  m_axis_cc_tdata_out(16) <= \<const0>\;
  m_axis_cc_tdata_out(15) <= \<const0>\;
  m_axis_cc_tdata_out(14) <= \<const0>\;
  m_axis_cc_tdata_out(13) <= \<const0>\;
  m_axis_cc_tdata_out(12) <= \<const0>\;
  m_axis_cc_tdata_out(11) <= \<const0>\;
  m_axis_cc_tdata_out(10) <= \<const0>\;
  m_axis_cc_tdata_out(9) <= \<const0>\;
  m_axis_cc_tdata_out(8) <= \<const0>\;
  m_axis_cc_tdata_out(7) <= \<const0>\;
  m_axis_cc_tdata_out(6) <= \<const0>\;
  m_axis_cc_tdata_out(5) <= \<const0>\;
  m_axis_cc_tdata_out(4) <= \<const0>\;
  m_axis_cc_tdata_out(3) <= \<const0>\;
  m_axis_cc_tdata_out(2) <= \<const0>\;
  m_axis_cc_tdata_out(1) <= \<const0>\;
  m_axis_cc_tdata_out(0) <= \<const0>\;
  m_axis_cc_tkeep_out(1) <= \<const0>\;
  m_axis_cc_tkeep_out(0) <= \<const0>\;
  m_axis_cc_tlast_out <= \<const0>\;
  m_axis_cc_tready_out(3) <= \<const0>\;
  m_axis_cc_tready_out(2) <= \<const0>\;
  m_axis_cc_tready_out(1) <= \<const0>\;
  m_axis_cc_tready_out(0) <= \<const0>\;
  m_axis_cc_tuser_out(32) <= \<const0>\;
  m_axis_cc_tuser_out(31) <= \<const0>\;
  m_axis_cc_tuser_out(30) <= \<const0>\;
  m_axis_cc_tuser_out(29) <= \<const0>\;
  m_axis_cc_tuser_out(28) <= \<const0>\;
  m_axis_cc_tuser_out(27) <= \<const0>\;
  m_axis_cc_tuser_out(26) <= \<const0>\;
  m_axis_cc_tuser_out(25) <= \<const0>\;
  m_axis_cc_tuser_out(24) <= \<const0>\;
  m_axis_cc_tuser_out(23) <= \<const0>\;
  m_axis_cc_tuser_out(22) <= \<const0>\;
  m_axis_cc_tuser_out(21) <= \<const0>\;
  m_axis_cc_tuser_out(20) <= \<const0>\;
  m_axis_cc_tuser_out(19) <= \<const0>\;
  m_axis_cc_tuser_out(18) <= \<const0>\;
  m_axis_cc_tuser_out(17) <= \<const0>\;
  m_axis_cc_tuser_out(16) <= \<const0>\;
  m_axis_cc_tuser_out(15) <= \<const0>\;
  m_axis_cc_tuser_out(14) <= \<const0>\;
  m_axis_cc_tuser_out(13) <= \<const0>\;
  m_axis_cc_tuser_out(12) <= \<const0>\;
  m_axis_cc_tuser_out(11) <= \<const0>\;
  m_axis_cc_tuser_out(10) <= \<const0>\;
  m_axis_cc_tuser_out(9) <= \<const0>\;
  m_axis_cc_tuser_out(8) <= \<const0>\;
  m_axis_cc_tuser_out(7) <= \<const0>\;
  m_axis_cc_tuser_out(6) <= \<const0>\;
  m_axis_cc_tuser_out(5) <= \<const0>\;
  m_axis_cc_tuser_out(4) <= \<const0>\;
  m_axis_cc_tuser_out(3) <= \<const0>\;
  m_axis_cc_tuser_out(2) <= \<const0>\;
  m_axis_cc_tuser_out(1) <= \<const0>\;
  m_axis_cc_tuser_out(0) <= \<const0>\;
  m_axis_cc_tvalid_out <= \<const0>\;
  m_axis_cq_tready_sd <= \<const0>\;
  m_axis_h2c_tdata_0(63) <= \<const0>\;
  m_axis_h2c_tdata_0(62) <= \<const0>\;
  m_axis_h2c_tdata_0(61) <= \<const0>\;
  m_axis_h2c_tdata_0(60) <= \<const0>\;
  m_axis_h2c_tdata_0(59) <= \<const0>\;
  m_axis_h2c_tdata_0(58) <= \<const0>\;
  m_axis_h2c_tdata_0(57) <= \<const0>\;
  m_axis_h2c_tdata_0(56) <= \<const0>\;
  m_axis_h2c_tdata_0(55) <= \<const0>\;
  m_axis_h2c_tdata_0(54) <= \<const0>\;
  m_axis_h2c_tdata_0(53) <= \<const0>\;
  m_axis_h2c_tdata_0(52) <= \<const0>\;
  m_axis_h2c_tdata_0(51) <= \<const0>\;
  m_axis_h2c_tdata_0(50) <= \<const0>\;
  m_axis_h2c_tdata_0(49) <= \<const0>\;
  m_axis_h2c_tdata_0(48) <= \<const0>\;
  m_axis_h2c_tdata_0(47) <= \<const0>\;
  m_axis_h2c_tdata_0(46) <= \<const0>\;
  m_axis_h2c_tdata_0(45) <= \<const0>\;
  m_axis_h2c_tdata_0(44) <= \<const0>\;
  m_axis_h2c_tdata_0(43) <= \<const0>\;
  m_axis_h2c_tdata_0(42) <= \<const0>\;
  m_axis_h2c_tdata_0(41) <= \<const0>\;
  m_axis_h2c_tdata_0(40) <= \<const0>\;
  m_axis_h2c_tdata_0(39) <= \<const0>\;
  m_axis_h2c_tdata_0(38) <= \<const0>\;
  m_axis_h2c_tdata_0(37) <= \<const0>\;
  m_axis_h2c_tdata_0(36) <= \<const0>\;
  m_axis_h2c_tdata_0(35) <= \<const0>\;
  m_axis_h2c_tdata_0(34) <= \<const0>\;
  m_axis_h2c_tdata_0(33) <= \<const0>\;
  m_axis_h2c_tdata_0(32) <= \<const0>\;
  m_axis_h2c_tdata_0(31) <= \<const0>\;
  m_axis_h2c_tdata_0(30) <= \<const0>\;
  m_axis_h2c_tdata_0(29) <= \<const0>\;
  m_axis_h2c_tdata_0(28) <= \<const0>\;
  m_axis_h2c_tdata_0(27) <= \<const0>\;
  m_axis_h2c_tdata_0(26) <= \<const0>\;
  m_axis_h2c_tdata_0(25) <= \<const0>\;
  m_axis_h2c_tdata_0(24) <= \<const0>\;
  m_axis_h2c_tdata_0(23) <= \<const0>\;
  m_axis_h2c_tdata_0(22) <= \<const0>\;
  m_axis_h2c_tdata_0(21) <= \<const0>\;
  m_axis_h2c_tdata_0(20) <= \<const0>\;
  m_axis_h2c_tdata_0(19) <= \<const0>\;
  m_axis_h2c_tdata_0(18) <= \<const0>\;
  m_axis_h2c_tdata_0(17) <= \<const0>\;
  m_axis_h2c_tdata_0(16) <= \<const0>\;
  m_axis_h2c_tdata_0(15) <= \<const0>\;
  m_axis_h2c_tdata_0(14) <= \<const0>\;
  m_axis_h2c_tdata_0(13) <= \<const0>\;
  m_axis_h2c_tdata_0(12) <= \<const0>\;
  m_axis_h2c_tdata_0(11) <= \<const0>\;
  m_axis_h2c_tdata_0(10) <= \<const0>\;
  m_axis_h2c_tdata_0(9) <= \<const0>\;
  m_axis_h2c_tdata_0(8) <= \<const0>\;
  m_axis_h2c_tdata_0(7) <= \<const0>\;
  m_axis_h2c_tdata_0(6) <= \<const0>\;
  m_axis_h2c_tdata_0(5) <= \<const0>\;
  m_axis_h2c_tdata_0(4) <= \<const0>\;
  m_axis_h2c_tdata_0(3) <= \<const0>\;
  m_axis_h2c_tdata_0(2) <= \<const0>\;
  m_axis_h2c_tdata_0(1) <= \<const0>\;
  m_axis_h2c_tdata_0(0) <= \<const0>\;
  m_axis_h2c_tdata_1(63) <= \<const0>\;
  m_axis_h2c_tdata_1(62) <= \<const0>\;
  m_axis_h2c_tdata_1(61) <= \<const0>\;
  m_axis_h2c_tdata_1(60) <= \<const0>\;
  m_axis_h2c_tdata_1(59) <= \<const0>\;
  m_axis_h2c_tdata_1(58) <= \<const0>\;
  m_axis_h2c_tdata_1(57) <= \<const0>\;
  m_axis_h2c_tdata_1(56) <= \<const0>\;
  m_axis_h2c_tdata_1(55) <= \<const0>\;
  m_axis_h2c_tdata_1(54) <= \<const0>\;
  m_axis_h2c_tdata_1(53) <= \<const0>\;
  m_axis_h2c_tdata_1(52) <= \<const0>\;
  m_axis_h2c_tdata_1(51) <= \<const0>\;
  m_axis_h2c_tdata_1(50) <= \<const0>\;
  m_axis_h2c_tdata_1(49) <= \<const0>\;
  m_axis_h2c_tdata_1(48) <= \<const0>\;
  m_axis_h2c_tdata_1(47) <= \<const0>\;
  m_axis_h2c_tdata_1(46) <= \<const0>\;
  m_axis_h2c_tdata_1(45) <= \<const0>\;
  m_axis_h2c_tdata_1(44) <= \<const0>\;
  m_axis_h2c_tdata_1(43) <= \<const0>\;
  m_axis_h2c_tdata_1(42) <= \<const0>\;
  m_axis_h2c_tdata_1(41) <= \<const0>\;
  m_axis_h2c_tdata_1(40) <= \<const0>\;
  m_axis_h2c_tdata_1(39) <= \<const0>\;
  m_axis_h2c_tdata_1(38) <= \<const0>\;
  m_axis_h2c_tdata_1(37) <= \<const0>\;
  m_axis_h2c_tdata_1(36) <= \<const0>\;
  m_axis_h2c_tdata_1(35) <= \<const0>\;
  m_axis_h2c_tdata_1(34) <= \<const0>\;
  m_axis_h2c_tdata_1(33) <= \<const0>\;
  m_axis_h2c_tdata_1(32) <= \<const0>\;
  m_axis_h2c_tdata_1(31) <= \<const0>\;
  m_axis_h2c_tdata_1(30) <= \<const0>\;
  m_axis_h2c_tdata_1(29) <= \<const0>\;
  m_axis_h2c_tdata_1(28) <= \<const0>\;
  m_axis_h2c_tdata_1(27) <= \<const0>\;
  m_axis_h2c_tdata_1(26) <= \<const0>\;
  m_axis_h2c_tdata_1(25) <= \<const0>\;
  m_axis_h2c_tdata_1(24) <= \<const0>\;
  m_axis_h2c_tdata_1(23) <= \<const0>\;
  m_axis_h2c_tdata_1(22) <= \<const0>\;
  m_axis_h2c_tdata_1(21) <= \<const0>\;
  m_axis_h2c_tdata_1(20) <= \<const0>\;
  m_axis_h2c_tdata_1(19) <= \<const0>\;
  m_axis_h2c_tdata_1(18) <= \<const0>\;
  m_axis_h2c_tdata_1(17) <= \<const0>\;
  m_axis_h2c_tdata_1(16) <= \<const0>\;
  m_axis_h2c_tdata_1(15) <= \<const0>\;
  m_axis_h2c_tdata_1(14) <= \<const0>\;
  m_axis_h2c_tdata_1(13) <= \<const0>\;
  m_axis_h2c_tdata_1(12) <= \<const0>\;
  m_axis_h2c_tdata_1(11) <= \<const0>\;
  m_axis_h2c_tdata_1(10) <= \<const0>\;
  m_axis_h2c_tdata_1(9) <= \<const0>\;
  m_axis_h2c_tdata_1(8) <= \<const0>\;
  m_axis_h2c_tdata_1(7) <= \<const0>\;
  m_axis_h2c_tdata_1(6) <= \<const0>\;
  m_axis_h2c_tdata_1(5) <= \<const0>\;
  m_axis_h2c_tdata_1(4) <= \<const0>\;
  m_axis_h2c_tdata_1(3) <= \<const0>\;
  m_axis_h2c_tdata_1(2) <= \<const0>\;
  m_axis_h2c_tdata_1(1) <= \<const0>\;
  m_axis_h2c_tdata_1(0) <= \<const0>\;
  m_axis_h2c_tdata_2(63) <= \<const0>\;
  m_axis_h2c_tdata_2(62) <= \<const0>\;
  m_axis_h2c_tdata_2(61) <= \<const0>\;
  m_axis_h2c_tdata_2(60) <= \<const0>\;
  m_axis_h2c_tdata_2(59) <= \<const0>\;
  m_axis_h2c_tdata_2(58) <= \<const0>\;
  m_axis_h2c_tdata_2(57) <= \<const0>\;
  m_axis_h2c_tdata_2(56) <= \<const0>\;
  m_axis_h2c_tdata_2(55) <= \<const0>\;
  m_axis_h2c_tdata_2(54) <= \<const0>\;
  m_axis_h2c_tdata_2(53) <= \<const0>\;
  m_axis_h2c_tdata_2(52) <= \<const0>\;
  m_axis_h2c_tdata_2(51) <= \<const0>\;
  m_axis_h2c_tdata_2(50) <= \<const0>\;
  m_axis_h2c_tdata_2(49) <= \<const0>\;
  m_axis_h2c_tdata_2(48) <= \<const0>\;
  m_axis_h2c_tdata_2(47) <= \<const0>\;
  m_axis_h2c_tdata_2(46) <= \<const0>\;
  m_axis_h2c_tdata_2(45) <= \<const0>\;
  m_axis_h2c_tdata_2(44) <= \<const0>\;
  m_axis_h2c_tdata_2(43) <= \<const0>\;
  m_axis_h2c_tdata_2(42) <= \<const0>\;
  m_axis_h2c_tdata_2(41) <= \<const0>\;
  m_axis_h2c_tdata_2(40) <= \<const0>\;
  m_axis_h2c_tdata_2(39) <= \<const0>\;
  m_axis_h2c_tdata_2(38) <= \<const0>\;
  m_axis_h2c_tdata_2(37) <= \<const0>\;
  m_axis_h2c_tdata_2(36) <= \<const0>\;
  m_axis_h2c_tdata_2(35) <= \<const0>\;
  m_axis_h2c_tdata_2(34) <= \<const0>\;
  m_axis_h2c_tdata_2(33) <= \<const0>\;
  m_axis_h2c_tdata_2(32) <= \<const0>\;
  m_axis_h2c_tdata_2(31) <= \<const0>\;
  m_axis_h2c_tdata_2(30) <= \<const0>\;
  m_axis_h2c_tdata_2(29) <= \<const0>\;
  m_axis_h2c_tdata_2(28) <= \<const0>\;
  m_axis_h2c_tdata_2(27) <= \<const0>\;
  m_axis_h2c_tdata_2(26) <= \<const0>\;
  m_axis_h2c_tdata_2(25) <= \<const0>\;
  m_axis_h2c_tdata_2(24) <= \<const0>\;
  m_axis_h2c_tdata_2(23) <= \<const0>\;
  m_axis_h2c_tdata_2(22) <= \<const0>\;
  m_axis_h2c_tdata_2(21) <= \<const0>\;
  m_axis_h2c_tdata_2(20) <= \<const0>\;
  m_axis_h2c_tdata_2(19) <= \<const0>\;
  m_axis_h2c_tdata_2(18) <= \<const0>\;
  m_axis_h2c_tdata_2(17) <= \<const0>\;
  m_axis_h2c_tdata_2(16) <= \<const0>\;
  m_axis_h2c_tdata_2(15) <= \<const0>\;
  m_axis_h2c_tdata_2(14) <= \<const0>\;
  m_axis_h2c_tdata_2(13) <= \<const0>\;
  m_axis_h2c_tdata_2(12) <= \<const0>\;
  m_axis_h2c_tdata_2(11) <= \<const0>\;
  m_axis_h2c_tdata_2(10) <= \<const0>\;
  m_axis_h2c_tdata_2(9) <= \<const0>\;
  m_axis_h2c_tdata_2(8) <= \<const0>\;
  m_axis_h2c_tdata_2(7) <= \<const0>\;
  m_axis_h2c_tdata_2(6) <= \<const0>\;
  m_axis_h2c_tdata_2(5) <= \<const0>\;
  m_axis_h2c_tdata_2(4) <= \<const0>\;
  m_axis_h2c_tdata_2(3) <= \<const0>\;
  m_axis_h2c_tdata_2(2) <= \<const0>\;
  m_axis_h2c_tdata_2(1) <= \<const0>\;
  m_axis_h2c_tdata_2(0) <= \<const0>\;
  m_axis_h2c_tdata_3(63) <= \<const0>\;
  m_axis_h2c_tdata_3(62) <= \<const0>\;
  m_axis_h2c_tdata_3(61) <= \<const0>\;
  m_axis_h2c_tdata_3(60) <= \<const0>\;
  m_axis_h2c_tdata_3(59) <= \<const0>\;
  m_axis_h2c_tdata_3(58) <= \<const0>\;
  m_axis_h2c_tdata_3(57) <= \<const0>\;
  m_axis_h2c_tdata_3(56) <= \<const0>\;
  m_axis_h2c_tdata_3(55) <= \<const0>\;
  m_axis_h2c_tdata_3(54) <= \<const0>\;
  m_axis_h2c_tdata_3(53) <= \<const0>\;
  m_axis_h2c_tdata_3(52) <= \<const0>\;
  m_axis_h2c_tdata_3(51) <= \<const0>\;
  m_axis_h2c_tdata_3(50) <= \<const0>\;
  m_axis_h2c_tdata_3(49) <= \<const0>\;
  m_axis_h2c_tdata_3(48) <= \<const0>\;
  m_axis_h2c_tdata_3(47) <= \<const0>\;
  m_axis_h2c_tdata_3(46) <= \<const0>\;
  m_axis_h2c_tdata_3(45) <= \<const0>\;
  m_axis_h2c_tdata_3(44) <= \<const0>\;
  m_axis_h2c_tdata_3(43) <= \<const0>\;
  m_axis_h2c_tdata_3(42) <= \<const0>\;
  m_axis_h2c_tdata_3(41) <= \<const0>\;
  m_axis_h2c_tdata_3(40) <= \<const0>\;
  m_axis_h2c_tdata_3(39) <= \<const0>\;
  m_axis_h2c_tdata_3(38) <= \<const0>\;
  m_axis_h2c_tdata_3(37) <= \<const0>\;
  m_axis_h2c_tdata_3(36) <= \<const0>\;
  m_axis_h2c_tdata_3(35) <= \<const0>\;
  m_axis_h2c_tdata_3(34) <= \<const0>\;
  m_axis_h2c_tdata_3(33) <= \<const0>\;
  m_axis_h2c_tdata_3(32) <= \<const0>\;
  m_axis_h2c_tdata_3(31) <= \<const0>\;
  m_axis_h2c_tdata_3(30) <= \<const0>\;
  m_axis_h2c_tdata_3(29) <= \<const0>\;
  m_axis_h2c_tdata_3(28) <= \<const0>\;
  m_axis_h2c_tdata_3(27) <= \<const0>\;
  m_axis_h2c_tdata_3(26) <= \<const0>\;
  m_axis_h2c_tdata_3(25) <= \<const0>\;
  m_axis_h2c_tdata_3(24) <= \<const0>\;
  m_axis_h2c_tdata_3(23) <= \<const0>\;
  m_axis_h2c_tdata_3(22) <= \<const0>\;
  m_axis_h2c_tdata_3(21) <= \<const0>\;
  m_axis_h2c_tdata_3(20) <= \<const0>\;
  m_axis_h2c_tdata_3(19) <= \<const0>\;
  m_axis_h2c_tdata_3(18) <= \<const0>\;
  m_axis_h2c_tdata_3(17) <= \<const0>\;
  m_axis_h2c_tdata_3(16) <= \<const0>\;
  m_axis_h2c_tdata_3(15) <= \<const0>\;
  m_axis_h2c_tdata_3(14) <= \<const0>\;
  m_axis_h2c_tdata_3(13) <= \<const0>\;
  m_axis_h2c_tdata_3(12) <= \<const0>\;
  m_axis_h2c_tdata_3(11) <= \<const0>\;
  m_axis_h2c_tdata_3(10) <= \<const0>\;
  m_axis_h2c_tdata_3(9) <= \<const0>\;
  m_axis_h2c_tdata_3(8) <= \<const0>\;
  m_axis_h2c_tdata_3(7) <= \<const0>\;
  m_axis_h2c_tdata_3(6) <= \<const0>\;
  m_axis_h2c_tdata_3(5) <= \<const0>\;
  m_axis_h2c_tdata_3(4) <= \<const0>\;
  m_axis_h2c_tdata_3(3) <= \<const0>\;
  m_axis_h2c_tdata_3(2) <= \<const0>\;
  m_axis_h2c_tdata_3(1) <= \<const0>\;
  m_axis_h2c_tdata_3(0) <= \<const0>\;
  m_axis_h2c_tkeep_0(7) <= \<const0>\;
  m_axis_h2c_tkeep_0(6) <= \<const0>\;
  m_axis_h2c_tkeep_0(5) <= \<const0>\;
  m_axis_h2c_tkeep_0(4) <= \<const0>\;
  m_axis_h2c_tkeep_0(3) <= \<const0>\;
  m_axis_h2c_tkeep_0(2) <= \<const0>\;
  m_axis_h2c_tkeep_0(1) <= \<const0>\;
  m_axis_h2c_tkeep_0(0) <= \<const0>\;
  m_axis_h2c_tkeep_1(7) <= \<const0>\;
  m_axis_h2c_tkeep_1(6) <= \<const0>\;
  m_axis_h2c_tkeep_1(5) <= \<const0>\;
  m_axis_h2c_tkeep_1(4) <= \<const0>\;
  m_axis_h2c_tkeep_1(3) <= \<const0>\;
  m_axis_h2c_tkeep_1(2) <= \<const0>\;
  m_axis_h2c_tkeep_1(1) <= \<const0>\;
  m_axis_h2c_tkeep_1(0) <= \<const0>\;
  m_axis_h2c_tkeep_2(7) <= \<const0>\;
  m_axis_h2c_tkeep_2(6) <= \<const0>\;
  m_axis_h2c_tkeep_2(5) <= \<const0>\;
  m_axis_h2c_tkeep_2(4) <= \<const0>\;
  m_axis_h2c_tkeep_2(3) <= \<const0>\;
  m_axis_h2c_tkeep_2(2) <= \<const0>\;
  m_axis_h2c_tkeep_2(1) <= \<const0>\;
  m_axis_h2c_tkeep_2(0) <= \<const0>\;
  m_axis_h2c_tkeep_3(7) <= \<const0>\;
  m_axis_h2c_tkeep_3(6) <= \<const0>\;
  m_axis_h2c_tkeep_3(5) <= \<const0>\;
  m_axis_h2c_tkeep_3(4) <= \<const0>\;
  m_axis_h2c_tkeep_3(3) <= \<const0>\;
  m_axis_h2c_tkeep_3(2) <= \<const0>\;
  m_axis_h2c_tkeep_3(1) <= \<const0>\;
  m_axis_h2c_tkeep_3(0) <= \<const0>\;
  m_axis_h2c_tlast_0 <= \<const0>\;
  m_axis_h2c_tlast_1 <= \<const0>\;
  m_axis_h2c_tlast_2 <= \<const0>\;
  m_axis_h2c_tlast_3 <= \<const0>\;
  m_axis_h2c_tuser_0(7) <= \<const0>\;
  m_axis_h2c_tuser_0(6) <= \<const0>\;
  m_axis_h2c_tuser_0(5) <= \<const0>\;
  m_axis_h2c_tuser_0(4) <= \<const0>\;
  m_axis_h2c_tuser_0(3) <= \<const0>\;
  m_axis_h2c_tuser_0(2) <= \<const0>\;
  m_axis_h2c_tuser_0(1) <= \<const0>\;
  m_axis_h2c_tuser_0(0) <= \<const0>\;
  m_axis_h2c_tuser_1(7) <= \<const0>\;
  m_axis_h2c_tuser_1(6) <= \<const0>\;
  m_axis_h2c_tuser_1(5) <= \<const0>\;
  m_axis_h2c_tuser_1(4) <= \<const0>\;
  m_axis_h2c_tuser_1(3) <= \<const0>\;
  m_axis_h2c_tuser_1(2) <= \<const0>\;
  m_axis_h2c_tuser_1(1) <= \<const0>\;
  m_axis_h2c_tuser_1(0) <= \<const0>\;
  m_axis_h2c_tuser_2(7) <= \<const0>\;
  m_axis_h2c_tuser_2(6) <= \<const0>\;
  m_axis_h2c_tuser_2(5) <= \<const0>\;
  m_axis_h2c_tuser_2(4) <= \<const0>\;
  m_axis_h2c_tuser_2(3) <= \<const0>\;
  m_axis_h2c_tuser_2(2) <= \<const0>\;
  m_axis_h2c_tuser_2(1) <= \<const0>\;
  m_axis_h2c_tuser_2(0) <= \<const0>\;
  m_axis_h2c_tuser_3(7) <= \<const0>\;
  m_axis_h2c_tuser_3(6) <= \<const0>\;
  m_axis_h2c_tuser_3(5) <= \<const0>\;
  m_axis_h2c_tuser_3(4) <= \<const0>\;
  m_axis_h2c_tuser_3(3) <= \<const0>\;
  m_axis_h2c_tuser_3(2) <= \<const0>\;
  m_axis_h2c_tuser_3(1) <= \<const0>\;
  m_axis_h2c_tuser_3(0) <= \<const0>\;
  m_axis_h2c_tvalid_0 <= \<const0>\;
  m_axis_h2c_tvalid_1 <= \<const0>\;
  m_axis_h2c_tvalid_2 <= \<const0>\;
  m_axis_h2c_tvalid_3 <= \<const0>\;
  m_axis_rc_tready_sd <= \<const0>\;
  m_axis_rq_tdata_out(63) <= \<const0>\;
  m_axis_rq_tdata_out(62) <= \<const0>\;
  m_axis_rq_tdata_out(61) <= \<const0>\;
  m_axis_rq_tdata_out(60) <= \<const0>\;
  m_axis_rq_tdata_out(59) <= \<const0>\;
  m_axis_rq_tdata_out(58) <= \<const0>\;
  m_axis_rq_tdata_out(57) <= \<const0>\;
  m_axis_rq_tdata_out(56) <= \<const0>\;
  m_axis_rq_tdata_out(55) <= \<const0>\;
  m_axis_rq_tdata_out(54) <= \<const0>\;
  m_axis_rq_tdata_out(53) <= \<const0>\;
  m_axis_rq_tdata_out(52) <= \<const0>\;
  m_axis_rq_tdata_out(51) <= \<const0>\;
  m_axis_rq_tdata_out(50) <= \<const0>\;
  m_axis_rq_tdata_out(49) <= \<const0>\;
  m_axis_rq_tdata_out(48) <= \<const0>\;
  m_axis_rq_tdata_out(47) <= \<const0>\;
  m_axis_rq_tdata_out(46) <= \<const0>\;
  m_axis_rq_tdata_out(45) <= \<const0>\;
  m_axis_rq_tdata_out(44) <= \<const0>\;
  m_axis_rq_tdata_out(43) <= \<const0>\;
  m_axis_rq_tdata_out(42) <= \<const0>\;
  m_axis_rq_tdata_out(41) <= \<const0>\;
  m_axis_rq_tdata_out(40) <= \<const0>\;
  m_axis_rq_tdata_out(39) <= \<const0>\;
  m_axis_rq_tdata_out(38) <= \<const0>\;
  m_axis_rq_tdata_out(37) <= \<const0>\;
  m_axis_rq_tdata_out(36) <= \<const0>\;
  m_axis_rq_tdata_out(35) <= \<const0>\;
  m_axis_rq_tdata_out(34) <= \<const0>\;
  m_axis_rq_tdata_out(33) <= \<const0>\;
  m_axis_rq_tdata_out(32) <= \<const0>\;
  m_axis_rq_tdata_out(31) <= \<const0>\;
  m_axis_rq_tdata_out(30) <= \<const0>\;
  m_axis_rq_tdata_out(29) <= \<const0>\;
  m_axis_rq_tdata_out(28) <= \<const0>\;
  m_axis_rq_tdata_out(27) <= \<const0>\;
  m_axis_rq_tdata_out(26) <= \<const0>\;
  m_axis_rq_tdata_out(25) <= \<const0>\;
  m_axis_rq_tdata_out(24) <= \<const0>\;
  m_axis_rq_tdata_out(23) <= \<const0>\;
  m_axis_rq_tdata_out(22) <= \<const0>\;
  m_axis_rq_tdata_out(21) <= \<const0>\;
  m_axis_rq_tdata_out(20) <= \<const0>\;
  m_axis_rq_tdata_out(19) <= \<const0>\;
  m_axis_rq_tdata_out(18) <= \<const0>\;
  m_axis_rq_tdata_out(17) <= \<const0>\;
  m_axis_rq_tdata_out(16) <= \<const0>\;
  m_axis_rq_tdata_out(15) <= \<const0>\;
  m_axis_rq_tdata_out(14) <= \<const0>\;
  m_axis_rq_tdata_out(13) <= \<const0>\;
  m_axis_rq_tdata_out(12) <= \<const0>\;
  m_axis_rq_tdata_out(11) <= \<const0>\;
  m_axis_rq_tdata_out(10) <= \<const0>\;
  m_axis_rq_tdata_out(9) <= \<const0>\;
  m_axis_rq_tdata_out(8) <= \<const0>\;
  m_axis_rq_tdata_out(7) <= \<const0>\;
  m_axis_rq_tdata_out(6) <= \<const0>\;
  m_axis_rq_tdata_out(5) <= \<const0>\;
  m_axis_rq_tdata_out(4) <= \<const0>\;
  m_axis_rq_tdata_out(3) <= \<const0>\;
  m_axis_rq_tdata_out(2) <= \<const0>\;
  m_axis_rq_tdata_out(1) <= \<const0>\;
  m_axis_rq_tdata_out(0) <= \<const0>\;
  m_axis_rq_tkeep_out(1) <= \<const0>\;
  m_axis_rq_tkeep_out(0) <= \<const0>\;
  m_axis_rq_tlast_out <= \<const0>\;
  m_axis_rq_tready_out(3) <= \<const0>\;
  m_axis_rq_tready_out(2) <= \<const0>\;
  m_axis_rq_tready_out(1) <= \<const0>\;
  m_axis_rq_tready_out(0) <= \<const0>\;
  m_axis_rq_tuser_out(59) <= \<const0>\;
  m_axis_rq_tuser_out(58) <= \<const0>\;
  m_axis_rq_tuser_out(57) <= \<const0>\;
  m_axis_rq_tuser_out(56) <= \<const0>\;
  m_axis_rq_tuser_out(55) <= \<const0>\;
  m_axis_rq_tuser_out(54) <= \<const0>\;
  m_axis_rq_tuser_out(53) <= \<const0>\;
  m_axis_rq_tuser_out(52) <= \<const0>\;
  m_axis_rq_tuser_out(51) <= \<const0>\;
  m_axis_rq_tuser_out(50) <= \<const0>\;
  m_axis_rq_tuser_out(49) <= \<const0>\;
  m_axis_rq_tuser_out(48) <= \<const0>\;
  m_axis_rq_tuser_out(47) <= \<const0>\;
  m_axis_rq_tuser_out(46) <= \<const0>\;
  m_axis_rq_tuser_out(45) <= \<const0>\;
  m_axis_rq_tuser_out(44) <= \<const0>\;
  m_axis_rq_tuser_out(43) <= \<const0>\;
  m_axis_rq_tuser_out(42) <= \<const0>\;
  m_axis_rq_tuser_out(41) <= \<const0>\;
  m_axis_rq_tuser_out(40) <= \<const0>\;
  m_axis_rq_tuser_out(39) <= \<const0>\;
  m_axis_rq_tuser_out(38) <= \<const0>\;
  m_axis_rq_tuser_out(37) <= \<const0>\;
  m_axis_rq_tuser_out(36) <= \<const0>\;
  m_axis_rq_tuser_out(35) <= \<const0>\;
  m_axis_rq_tuser_out(34) <= \<const0>\;
  m_axis_rq_tuser_out(33) <= \<const0>\;
  m_axis_rq_tuser_out(32) <= \<const0>\;
  m_axis_rq_tuser_out(31) <= \<const0>\;
  m_axis_rq_tuser_out(30) <= \<const0>\;
  m_axis_rq_tuser_out(29) <= \<const0>\;
  m_axis_rq_tuser_out(28) <= \<const0>\;
  m_axis_rq_tuser_out(27) <= \<const0>\;
  m_axis_rq_tuser_out(26) <= \<const0>\;
  m_axis_rq_tuser_out(25) <= \<const0>\;
  m_axis_rq_tuser_out(24) <= \<const0>\;
  m_axis_rq_tuser_out(23) <= \<const0>\;
  m_axis_rq_tuser_out(22) <= \<const0>\;
  m_axis_rq_tuser_out(21) <= \<const0>\;
  m_axis_rq_tuser_out(20) <= \<const0>\;
  m_axis_rq_tuser_out(19) <= \<const0>\;
  m_axis_rq_tuser_out(18) <= \<const0>\;
  m_axis_rq_tuser_out(17) <= \<const0>\;
  m_axis_rq_tuser_out(16) <= \<const0>\;
  m_axis_rq_tuser_out(15) <= \<const0>\;
  m_axis_rq_tuser_out(14) <= \<const0>\;
  m_axis_rq_tuser_out(13) <= \<const0>\;
  m_axis_rq_tuser_out(12) <= \<const0>\;
  m_axis_rq_tuser_out(11) <= \<const0>\;
  m_axis_rq_tuser_out(10) <= \<const0>\;
  m_axis_rq_tuser_out(9) <= \<const0>\;
  m_axis_rq_tuser_out(8) <= \<const0>\;
  m_axis_rq_tuser_out(7) <= \<const0>\;
  m_axis_rq_tuser_out(6) <= \<const0>\;
  m_axis_rq_tuser_out(5) <= \<const0>\;
  m_axis_rq_tuser_out(4) <= \<const0>\;
  m_axis_rq_tuser_out(3) <= \<const0>\;
  m_axis_rq_tuser_out(2) <= \<const0>\;
  m_axis_rq_tuser_out(1) <= \<const0>\;
  m_axis_rq_tuser_out(0) <= \<const0>\;
  m_axis_rq_tvalid_out <= \<const0>\;
  m_axis_rx_tkeep_o(7 downto 4) <= \^m_axis_rx_tkeep_o\(7 downto 4);
  m_axis_rx_tkeep_o(3) <= \<const0>\;
  m_axis_rx_tkeep_o(2) <= \<const0>\;
  m_axis_rx_tkeep_o(1) <= \<const0>\;
  m_axis_rx_tkeep_o(0) <= \<const0>\;
  m_axis_rx_tuser_o(21) <= \^m_axis_rx_tuser_o\(21);
  m_axis_rx_tuser_o(20) <= \<const0>\;
  m_axis_rx_tuser_o(19 downto 17) <= \^m_axis_rx_tuser_o\(19 downto 17);
  m_axis_rx_tuser_o(16) <= \<const0>\;
  m_axis_rx_tuser_o(15) <= \<const0>\;
  m_axis_rx_tuser_o(14) <= \^m_axis_rx_tuser_o\(14);
  m_axis_rx_tuser_o(13) <= \<const0>\;
  m_axis_rx_tuser_o(12) <= \<const0>\;
  m_axis_rx_tuser_o(11) <= \<const0>\;
  m_axis_rx_tuser_o(10) <= \<const0>\;
  m_axis_rx_tuser_o(9) <= \<const0>\;
  m_axis_rx_tuser_o(8 downto 0) <= \^m_axis_rx_tuser_o\(8 downto 0);
  mcap_design_switch <= \<const0>\;
  msi_enable <= \^msi_enable\;
  msix_enable <= \<const0>\;
  pcie4_cxs0_active_ack_rx_sd <= \<const0>\;
  pcie4_cxs0_active_req_tx_sd <= \<const0>\;
  pcie4_cxs0_cntl_chk_tx_sd <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(13) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(12) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(11) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(10) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(9) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(8) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(7) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(6) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(5) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(4) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(3) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(2) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(1) <= \<const0>\;
  pcie4_cxs0_cntl_tx_sd(0) <= \<const0>\;
  pcie4_cxs0_crdgnt_chk_rx_sd <= \<const0>\;
  pcie4_cxs0_crdgnt_rx_sd <= \<const0>\;
  pcie4_cxs0_crdrtn_chk_tx_sd <= \<const0>\;
  pcie4_cxs0_crdrtn_tx_sd <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(31) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(30) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(29) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(28) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(27) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(26) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(25) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(24) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(23) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(22) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(21) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(20) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(19) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(18) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(17) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(16) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(15) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(14) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(13) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(12) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(11) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(10) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(9) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(8) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(7) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(6) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(5) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(4) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(3) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(2) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(1) <= \<const0>\;
  pcie4_cxs0_data_chk_tx_sd(0) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(255) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(254) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(253) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(252) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(251) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(250) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(249) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(248) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(247) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(246) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(245) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(244) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(243) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(242) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(241) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(240) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(239) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(238) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(237) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(236) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(235) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(234) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(233) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(232) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(231) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(230) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(229) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(228) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(227) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(226) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(225) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(224) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(223) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(222) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(221) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(220) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(219) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(218) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(217) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(216) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(215) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(214) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(213) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(212) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(211) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(210) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(209) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(208) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(207) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(206) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(205) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(204) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(203) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(202) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(201) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(200) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(199) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(198) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(197) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(196) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(195) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(194) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(193) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(192) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(191) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(190) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(189) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(188) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(187) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(186) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(185) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(184) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(183) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(182) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(181) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(180) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(179) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(178) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(177) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(176) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(175) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(174) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(173) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(172) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(171) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(170) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(169) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(168) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(167) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(166) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(165) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(164) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(163) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(162) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(161) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(160) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(159) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(158) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(157) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(156) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(155) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(154) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(153) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(152) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(151) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(150) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(149) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(148) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(147) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(146) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(145) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(144) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(143) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(142) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(141) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(140) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(139) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(138) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(137) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(136) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(135) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(134) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(133) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(132) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(131) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(130) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(129) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(128) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(127) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(126) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(125) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(124) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(123) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(122) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(121) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(120) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(119) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(118) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(117) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(116) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(115) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(114) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(113) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(112) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(111) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(110) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(109) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(108) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(107) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(106) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(105) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(104) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(103) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(102) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(101) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(100) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(99) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(98) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(97) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(96) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(95) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(94) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(93) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(92) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(91) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(90) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(89) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(88) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(87) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(86) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(85) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(84) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(83) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(82) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(81) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(80) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(79) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(78) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(77) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(76) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(75) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(74) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(73) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(72) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(71) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(70) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(69) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(68) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(67) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(66) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(65) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(64) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(63) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(62) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(61) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(60) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(59) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(58) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(57) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(56) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(55) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(54) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(53) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(52) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(51) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(50) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(49) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(48) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(47) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(46) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(45) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(44) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(43) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(42) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(41) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(40) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(39) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(38) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(37) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(36) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(35) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(34) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(33) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(32) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(31) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(30) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(29) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(28) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(27) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(26) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(25) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(24) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(23) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(22) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(21) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(20) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(19) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(18) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(17) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(16) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(15) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(14) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(13) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(12) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(11) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(10) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(9) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(8) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(7) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(6) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(5) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(4) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(3) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(2) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(1) <= \<const0>\;
  pcie4_cxs0_data_tx_sd(0) <= \<const0>\;
  pcie4_cxs0_deact_hint_rx_sd <= \<const0>\;
  pcie4_cxs0_valid_chk_tx_sd <= \<const0>\;
  pcie4_cxs0_valid_tx_sd <= \<const0>\;
  pcie_cq_np_req_sd(1) <= \<const0>\;
  pcie_cq_np_req_sd(0) <= \<const0>\;
  pcieeqrxeqadaptdone_us_in(1) <= \<const0>\;
  pcieeqrxeqadaptdone_us_in(0) <= \<const0>\;
  pcieeqrxeqadaptdone_usp_in(1) <= \<const0>\;
  pcieeqrxeqadaptdone_usp_in(0) <= \<const0>\;
  pcierateqpll0_usp_in(2) <= \<const0>\;
  pcierateqpll0_usp_in(1) <= \<const0>\;
  pcierateqpll0_usp_in(0) <= \<const0>\;
  pcierateqpll1_usp_in(2) <= \<const0>\;
  pcierateqpll1_usp_in(1) <= \<const0>\;
  pcierateqpll1_usp_in(0) <= \<const0>\;
  pcierstidle_us_in(1) <= \<const0>\;
  pcierstidle_us_in(0) <= \<const0>\;
  pcierstidle_usp_in(1) <= \<const0>\;
  pcierstidle_usp_in(0) <= \<const0>\;
  pciersttxsyncstart_us_in(1) <= \<const0>\;
  pciersttxsyncstart_us_in(0) <= \<const0>\;
  pciersttxsyncstart_usp_in(1) <= \<const0>\;
  pciersttxsyncstart_usp_in(0) <= \<const0>\;
  pcieuserratedone_us_in(1) <= \<const0>\;
  pcieuserratedone_us_in(0) <= \<const0>\;
  pcieuserratedone_usp_in(1) <= \<const0>\;
  pcieuserratedone_usp_in(0) <= \<const0>\;
  pcsrsvdin_us_in(31) <= \<const0>\;
  pcsrsvdin_us_in(30) <= \<const0>\;
  pcsrsvdin_us_in(29) <= \<const0>\;
  pcsrsvdin_us_in(28) <= \<const0>\;
  pcsrsvdin_us_in(27) <= \<const0>\;
  pcsrsvdin_us_in(26) <= \<const0>\;
  pcsrsvdin_us_in(25) <= \<const0>\;
  pcsrsvdin_us_in(24) <= \<const0>\;
  pcsrsvdin_us_in(23) <= \<const0>\;
  pcsrsvdin_us_in(22) <= \<const0>\;
  pcsrsvdin_us_in(21) <= \<const0>\;
  pcsrsvdin_us_in(20) <= \<const0>\;
  pcsrsvdin_us_in(19) <= \<const0>\;
  pcsrsvdin_us_in(18) <= \<const0>\;
  pcsrsvdin_us_in(17) <= \<const0>\;
  pcsrsvdin_us_in(16) <= \<const0>\;
  pcsrsvdin_us_in(15) <= \<const0>\;
  pcsrsvdin_us_in(14) <= \<const0>\;
  pcsrsvdin_us_in(13) <= \<const0>\;
  pcsrsvdin_us_in(12) <= \<const0>\;
  pcsrsvdin_us_in(11) <= \<const0>\;
  pcsrsvdin_us_in(10) <= \<const0>\;
  pcsrsvdin_us_in(9) <= \<const0>\;
  pcsrsvdin_us_in(8) <= \<const0>\;
  pcsrsvdin_us_in(7) <= \<const0>\;
  pcsrsvdin_us_in(6) <= \<const0>\;
  pcsrsvdin_us_in(5) <= \<const0>\;
  pcsrsvdin_us_in(4) <= \<const0>\;
  pcsrsvdin_us_in(3) <= \<const0>\;
  pcsrsvdin_us_in(2) <= \<const0>\;
  pcsrsvdin_us_in(1) <= \<const0>\;
  pcsrsvdin_us_in(0) <= \<const0>\;
  phy_prst_n <= \<const0>\;
  phy_rrst_n <= \<const0>\;
  phy_rst_fsm(3) <= \<const0>\;
  phy_rst_fsm(2) <= \<const0>\;
  phy_rst_fsm(1) <= \<const0>\;
  phy_rst_fsm(0) <= \<const0>\;
  phy_rst_idle <= \<const0>\;
  phy_rxeq_fsm(5) <= \<const0>\;
  phy_rxeq_fsm(4) <= \<const0>\;
  phy_rxeq_fsm(3) <= \<const0>\;
  phy_rxeq_fsm(2) <= \<const0>\;
  phy_rxeq_fsm(1) <= \<const0>\;
  phy_rxeq_fsm(0) <= \<const0>\;
  phy_txeq_ctrl(3) <= \<const0>\;
  phy_txeq_ctrl(2) <= \<const0>\;
  phy_txeq_ctrl(1) <= \<const0>\;
  phy_txeq_ctrl(0) <= \<const0>\;
  phy_txeq_fsm(5) <= \<const0>\;
  phy_txeq_fsm(4) <= \<const0>\;
  phy_txeq_fsm(3) <= \<const0>\;
  phy_txeq_fsm(2) <= \<const0>\;
  phy_txeq_fsm(1) <= \<const0>\;
  phy_txeq_fsm(0) <= \<const0>\;
  phy_txeq_preset(7) <= \<const0>\;
  phy_txeq_preset(6) <= \<const0>\;
  phy_txeq_preset(5) <= \<const0>\;
  phy_txeq_preset(4) <= \<const0>\;
  phy_txeq_preset(3) <= \<const0>\;
  phy_txeq_preset(2) <= \<const0>\;
  phy_txeq_preset(1) <= \<const0>\;
  phy_txeq_preset(0) <= \<const0>\;
  pipe_clk <= \<const0>\;
  pipe_cpll_lock(1) <= \<const0>\;
  pipe_cpll_lock(0) <= \<const0>\;
  pipe_debug(31) <= \<const0>\;
  pipe_debug(30) <= \<const0>\;
  pipe_debug(29) <= \<const0>\;
  pipe_debug(28) <= \<const0>\;
  pipe_debug(27) <= \<const0>\;
  pipe_debug(26) <= \<const0>\;
  pipe_debug(25) <= \<const0>\;
  pipe_debug(24) <= \<const0>\;
  pipe_debug(23) <= \<const0>\;
  pipe_debug(22) <= \<const0>\;
  pipe_debug(21) <= \<const0>\;
  pipe_debug(20) <= \<const0>\;
  pipe_debug(19) <= \<const0>\;
  pipe_debug(18) <= \<const0>\;
  pipe_debug(17) <= \<const0>\;
  pipe_debug(16) <= \<const0>\;
  pipe_debug(15) <= \<const0>\;
  pipe_debug(14) <= \<const0>\;
  pipe_debug(13) <= \<const0>\;
  pipe_debug(12) <= \<const0>\;
  pipe_debug(11) <= \<const0>\;
  pipe_debug(10) <= \<const0>\;
  pipe_debug(9) <= \<const0>\;
  pipe_debug(8) <= \<const0>\;
  pipe_debug(7) <= \<const0>\;
  pipe_debug(6) <= \<const0>\;
  pipe_debug(5) <= \<const0>\;
  pipe_debug(4) <= \<const0>\;
  pipe_debug(3) <= \<const0>\;
  pipe_debug(2) <= \<const0>\;
  pipe_debug(1) <= \<const0>\;
  pipe_debug(0) <= \<const0>\;
  pipe_debug_0(1) <= \<const0>\;
  pipe_debug_0(0) <= \<const0>\;
  pipe_debug_1(1) <= \<const0>\;
  pipe_debug_1(0) <= \<const0>\;
  pipe_debug_2(1) <= \<const0>\;
  pipe_debug_2(0) <= \<const0>\;
  pipe_debug_3(1) <= \<const0>\;
  pipe_debug_3(0) <= \<const0>\;
  pipe_debug_4(1) <= \<const0>\;
  pipe_debug_4(0) <= \<const0>\;
  pipe_debug_5(1) <= \<const0>\;
  pipe_debug_5(0) <= \<const0>\;
  pipe_debug_6(1) <= \<const0>\;
  pipe_debug_6(0) <= \<const0>\;
  pipe_debug_7(1) <= \<const0>\;
  pipe_debug_7(0) <= \<const0>\;
  pipe_debug_8(1) <= \<const0>\;
  pipe_debug_8(0) <= \<const0>\;
  pipe_debug_9(1) <= \<const0>\;
  pipe_debug_9(0) <= \<const0>\;
  pipe_debug_debug_out_128_0(127) <= \<const0>\;
  pipe_debug_debug_out_128_0(126) <= \<const0>\;
  pipe_debug_debug_out_128_0(125) <= \<const0>\;
  pipe_debug_debug_out_128_0(124) <= \<const0>\;
  pipe_debug_debug_out_128_0(123) <= \<const0>\;
  pipe_debug_debug_out_128_0(122) <= \<const0>\;
  pipe_debug_debug_out_128_0(121) <= \<const0>\;
  pipe_debug_debug_out_128_0(120) <= \<const0>\;
  pipe_debug_debug_out_128_0(119) <= \<const0>\;
  pipe_debug_debug_out_128_0(118) <= \<const0>\;
  pipe_debug_debug_out_128_0(117) <= \<const0>\;
  pipe_debug_debug_out_128_0(116) <= \<const0>\;
  pipe_debug_debug_out_128_0(115) <= \<const0>\;
  pipe_debug_debug_out_128_0(114) <= \<const0>\;
  pipe_debug_debug_out_128_0(113) <= \<const0>\;
  pipe_debug_debug_out_128_0(112) <= \<const0>\;
  pipe_debug_debug_out_128_0(111) <= \<const0>\;
  pipe_debug_debug_out_128_0(110) <= \<const0>\;
  pipe_debug_debug_out_128_0(109) <= \<const0>\;
  pipe_debug_debug_out_128_0(108) <= \<const0>\;
  pipe_debug_debug_out_128_0(107) <= \<const0>\;
  pipe_debug_debug_out_128_0(106) <= \<const0>\;
  pipe_debug_debug_out_128_0(105) <= \<const0>\;
  pipe_debug_debug_out_128_0(104) <= \<const0>\;
  pipe_debug_debug_out_128_0(103) <= \<const0>\;
  pipe_debug_debug_out_128_0(102) <= \<const0>\;
  pipe_debug_debug_out_128_0(101) <= \<const0>\;
  pipe_debug_debug_out_128_0(100) <= \<const0>\;
  pipe_debug_debug_out_128_0(99) <= \<const0>\;
  pipe_debug_debug_out_128_0(98) <= \<const0>\;
  pipe_debug_debug_out_128_0(97) <= \<const0>\;
  pipe_debug_debug_out_128_0(96) <= \<const0>\;
  pipe_debug_debug_out_128_0(95) <= \<const0>\;
  pipe_debug_debug_out_128_0(94) <= \<const0>\;
  pipe_debug_debug_out_128_0(93) <= \<const0>\;
  pipe_debug_debug_out_128_0(92) <= \<const0>\;
  pipe_debug_debug_out_128_0(91) <= \<const0>\;
  pipe_debug_debug_out_128_0(90) <= \<const0>\;
  pipe_debug_debug_out_128_0(89) <= \<const0>\;
  pipe_debug_debug_out_128_0(88) <= \<const0>\;
  pipe_debug_debug_out_128_0(87) <= \<const0>\;
  pipe_debug_debug_out_128_0(86) <= \<const0>\;
  pipe_debug_debug_out_128_0(85) <= \<const0>\;
  pipe_debug_debug_out_128_0(84) <= \<const0>\;
  pipe_debug_debug_out_128_0(83) <= \<const0>\;
  pipe_debug_debug_out_128_0(82) <= \<const0>\;
  pipe_debug_debug_out_128_0(81) <= \<const0>\;
  pipe_debug_debug_out_128_0(80) <= \<const0>\;
  pipe_debug_debug_out_128_0(79) <= \<const0>\;
  pipe_debug_debug_out_128_0(78) <= \<const0>\;
  pipe_debug_debug_out_128_0(77) <= \<const0>\;
  pipe_debug_debug_out_128_0(76) <= \<const0>\;
  pipe_debug_debug_out_128_0(75) <= \<const0>\;
  pipe_debug_debug_out_128_0(74) <= \<const0>\;
  pipe_debug_debug_out_128_0(73) <= \<const0>\;
  pipe_debug_debug_out_128_0(72) <= \<const0>\;
  pipe_debug_debug_out_128_0(71) <= \<const0>\;
  pipe_debug_debug_out_128_0(70) <= \<const0>\;
  pipe_debug_debug_out_128_0(69) <= \<const0>\;
  pipe_debug_debug_out_128_0(68) <= \<const0>\;
  pipe_debug_debug_out_128_0(67) <= \<const0>\;
  pipe_debug_debug_out_128_0(66) <= \<const0>\;
  pipe_debug_debug_out_128_0(65) <= \<const0>\;
  pipe_debug_debug_out_128_0(64) <= \<const0>\;
  pipe_debug_debug_out_128_0(63) <= \<const0>\;
  pipe_debug_debug_out_128_0(62) <= \<const0>\;
  pipe_debug_debug_out_128_0(61) <= \<const0>\;
  pipe_debug_debug_out_128_0(60) <= \<const0>\;
  pipe_debug_debug_out_128_0(59) <= \<const0>\;
  pipe_debug_debug_out_128_0(58) <= \<const0>\;
  pipe_debug_debug_out_128_0(57) <= \<const0>\;
  pipe_debug_debug_out_128_0(56) <= \<const0>\;
  pipe_debug_debug_out_128_0(55) <= \<const0>\;
  pipe_debug_debug_out_128_0(54) <= \<const0>\;
  pipe_debug_debug_out_128_0(53) <= \<const0>\;
  pipe_debug_debug_out_128_0(52) <= \<const0>\;
  pipe_debug_debug_out_128_0(51) <= \<const0>\;
  pipe_debug_debug_out_128_0(50) <= \<const0>\;
  pipe_debug_debug_out_128_0(49) <= \<const0>\;
  pipe_debug_debug_out_128_0(48) <= \<const0>\;
  pipe_debug_debug_out_128_0(47) <= \<const0>\;
  pipe_debug_debug_out_128_0(46) <= \<const0>\;
  pipe_debug_debug_out_128_0(45) <= \<const0>\;
  pipe_debug_debug_out_128_0(44) <= \<const0>\;
  pipe_debug_debug_out_128_0(43) <= \<const0>\;
  pipe_debug_debug_out_128_0(42) <= \<const0>\;
  pipe_debug_debug_out_128_0(41) <= \<const0>\;
  pipe_debug_debug_out_128_0(40) <= \<const0>\;
  pipe_debug_debug_out_128_0(39) <= \<const0>\;
  pipe_debug_debug_out_128_0(38) <= \<const0>\;
  pipe_debug_debug_out_128_0(37) <= \<const0>\;
  pipe_debug_debug_out_128_0(36) <= \<const0>\;
  pipe_debug_debug_out_128_0(35) <= \<const0>\;
  pipe_debug_debug_out_128_0(34) <= \<const0>\;
  pipe_debug_debug_out_128_0(33) <= \<const0>\;
  pipe_debug_debug_out_128_0(32) <= \<const0>\;
  pipe_debug_debug_out_128_0(31) <= \<const0>\;
  pipe_debug_debug_out_128_0(30) <= \<const0>\;
  pipe_debug_debug_out_128_0(29) <= \<const0>\;
  pipe_debug_debug_out_128_0(28) <= \<const0>\;
  pipe_debug_debug_out_128_0(27) <= \<const0>\;
  pipe_debug_debug_out_128_0(26) <= \<const0>\;
  pipe_debug_debug_out_128_0(25) <= \<const0>\;
  pipe_debug_debug_out_128_0(24) <= \<const0>\;
  pipe_debug_debug_out_128_0(23) <= \<const0>\;
  pipe_debug_debug_out_128_0(22) <= \<const0>\;
  pipe_debug_debug_out_128_0(21) <= \<const0>\;
  pipe_debug_debug_out_128_0(20) <= \<const0>\;
  pipe_debug_debug_out_128_0(19) <= \<const0>\;
  pipe_debug_debug_out_128_0(18) <= \<const0>\;
  pipe_debug_debug_out_128_0(17) <= \<const0>\;
  pipe_debug_debug_out_128_0(16) <= \<const0>\;
  pipe_debug_debug_out_128_0(15) <= \<const0>\;
  pipe_debug_debug_out_128_0(14) <= \<const0>\;
  pipe_debug_debug_out_128_0(13) <= \<const0>\;
  pipe_debug_debug_out_128_0(12) <= \<const0>\;
  pipe_debug_debug_out_128_0(11) <= \<const0>\;
  pipe_debug_debug_out_128_0(10) <= \<const0>\;
  pipe_debug_debug_out_128_0(9) <= \<const0>\;
  pipe_debug_debug_out_128_0(8) <= \<const0>\;
  pipe_debug_debug_out_128_0(7) <= \<const0>\;
  pipe_debug_debug_out_128_0(6) <= \<const0>\;
  pipe_debug_debug_out_128_0(5) <= \<const0>\;
  pipe_debug_debug_out_128_0(4) <= \<const0>\;
  pipe_debug_debug_out_128_0(3) <= \<const0>\;
  pipe_debug_debug_out_128_0(2) <= \<const0>\;
  pipe_debug_debug_out_128_0(1) <= \<const0>\;
  pipe_debug_debug_out_128_0(0) <= \<const0>\;
  pipe_debug_debug_out_128_1(127) <= \<const0>\;
  pipe_debug_debug_out_128_1(126) <= \<const0>\;
  pipe_debug_debug_out_128_1(125) <= \<const0>\;
  pipe_debug_debug_out_128_1(124) <= \<const0>\;
  pipe_debug_debug_out_128_1(123) <= \<const0>\;
  pipe_debug_debug_out_128_1(122) <= \<const0>\;
  pipe_debug_debug_out_128_1(121) <= \<const0>\;
  pipe_debug_debug_out_128_1(120) <= \<const0>\;
  pipe_debug_debug_out_128_1(119) <= \<const0>\;
  pipe_debug_debug_out_128_1(118) <= \<const0>\;
  pipe_debug_debug_out_128_1(117) <= \<const0>\;
  pipe_debug_debug_out_128_1(116) <= \<const0>\;
  pipe_debug_debug_out_128_1(115) <= \<const0>\;
  pipe_debug_debug_out_128_1(114) <= \<const0>\;
  pipe_debug_debug_out_128_1(113) <= \<const0>\;
  pipe_debug_debug_out_128_1(112) <= \<const0>\;
  pipe_debug_debug_out_128_1(111) <= \<const0>\;
  pipe_debug_debug_out_128_1(110) <= \<const0>\;
  pipe_debug_debug_out_128_1(109) <= \<const0>\;
  pipe_debug_debug_out_128_1(108) <= \<const0>\;
  pipe_debug_debug_out_128_1(107) <= \<const0>\;
  pipe_debug_debug_out_128_1(106) <= \<const0>\;
  pipe_debug_debug_out_128_1(105) <= \<const0>\;
  pipe_debug_debug_out_128_1(104) <= \<const0>\;
  pipe_debug_debug_out_128_1(103) <= \<const0>\;
  pipe_debug_debug_out_128_1(102) <= \<const0>\;
  pipe_debug_debug_out_128_1(101) <= \<const0>\;
  pipe_debug_debug_out_128_1(100) <= \<const0>\;
  pipe_debug_debug_out_128_1(99) <= \<const0>\;
  pipe_debug_debug_out_128_1(98) <= \<const0>\;
  pipe_debug_debug_out_128_1(97) <= \<const0>\;
  pipe_debug_debug_out_128_1(96) <= \<const0>\;
  pipe_debug_debug_out_128_1(95) <= \<const0>\;
  pipe_debug_debug_out_128_1(94) <= \<const0>\;
  pipe_debug_debug_out_128_1(93) <= \<const0>\;
  pipe_debug_debug_out_128_1(92) <= \<const0>\;
  pipe_debug_debug_out_128_1(91) <= \<const0>\;
  pipe_debug_debug_out_128_1(90) <= \<const0>\;
  pipe_debug_debug_out_128_1(89) <= \<const0>\;
  pipe_debug_debug_out_128_1(88) <= \<const0>\;
  pipe_debug_debug_out_128_1(87) <= \<const0>\;
  pipe_debug_debug_out_128_1(86) <= \<const0>\;
  pipe_debug_debug_out_128_1(85) <= \<const0>\;
  pipe_debug_debug_out_128_1(84) <= \<const0>\;
  pipe_debug_debug_out_128_1(83) <= \<const0>\;
  pipe_debug_debug_out_128_1(82) <= \<const0>\;
  pipe_debug_debug_out_128_1(81) <= \<const0>\;
  pipe_debug_debug_out_128_1(80) <= \<const0>\;
  pipe_debug_debug_out_128_1(79) <= \<const0>\;
  pipe_debug_debug_out_128_1(78) <= \<const0>\;
  pipe_debug_debug_out_128_1(77) <= \<const0>\;
  pipe_debug_debug_out_128_1(76) <= \<const0>\;
  pipe_debug_debug_out_128_1(75) <= \<const0>\;
  pipe_debug_debug_out_128_1(74) <= \<const0>\;
  pipe_debug_debug_out_128_1(73) <= \<const0>\;
  pipe_debug_debug_out_128_1(72) <= \<const0>\;
  pipe_debug_debug_out_128_1(71) <= \<const0>\;
  pipe_debug_debug_out_128_1(70) <= \<const0>\;
  pipe_debug_debug_out_128_1(69) <= \<const0>\;
  pipe_debug_debug_out_128_1(68) <= \<const0>\;
  pipe_debug_debug_out_128_1(67) <= \<const0>\;
  pipe_debug_debug_out_128_1(66) <= \<const0>\;
  pipe_debug_debug_out_128_1(65) <= \<const0>\;
  pipe_debug_debug_out_128_1(64) <= \<const0>\;
  pipe_debug_debug_out_128_1(63) <= \<const0>\;
  pipe_debug_debug_out_128_1(62) <= \<const0>\;
  pipe_debug_debug_out_128_1(61) <= \<const0>\;
  pipe_debug_debug_out_128_1(60) <= \<const0>\;
  pipe_debug_debug_out_128_1(59) <= \<const0>\;
  pipe_debug_debug_out_128_1(58) <= \<const0>\;
  pipe_debug_debug_out_128_1(57) <= \<const0>\;
  pipe_debug_debug_out_128_1(56) <= \<const0>\;
  pipe_debug_debug_out_128_1(55) <= \<const0>\;
  pipe_debug_debug_out_128_1(54) <= \<const0>\;
  pipe_debug_debug_out_128_1(53) <= \<const0>\;
  pipe_debug_debug_out_128_1(52) <= \<const0>\;
  pipe_debug_debug_out_128_1(51) <= \<const0>\;
  pipe_debug_debug_out_128_1(50) <= \<const0>\;
  pipe_debug_debug_out_128_1(49) <= \<const0>\;
  pipe_debug_debug_out_128_1(48) <= \<const0>\;
  pipe_debug_debug_out_128_1(47) <= \<const0>\;
  pipe_debug_debug_out_128_1(46) <= \<const0>\;
  pipe_debug_debug_out_128_1(45) <= \<const0>\;
  pipe_debug_debug_out_128_1(44) <= \<const0>\;
  pipe_debug_debug_out_128_1(43) <= \<const0>\;
  pipe_debug_debug_out_128_1(42) <= \<const0>\;
  pipe_debug_debug_out_128_1(41) <= \<const0>\;
  pipe_debug_debug_out_128_1(40) <= \<const0>\;
  pipe_debug_debug_out_128_1(39) <= \<const0>\;
  pipe_debug_debug_out_128_1(38) <= \<const0>\;
  pipe_debug_debug_out_128_1(37) <= \<const0>\;
  pipe_debug_debug_out_128_1(36) <= \<const0>\;
  pipe_debug_debug_out_128_1(35) <= \<const0>\;
  pipe_debug_debug_out_128_1(34) <= \<const0>\;
  pipe_debug_debug_out_128_1(33) <= \<const0>\;
  pipe_debug_debug_out_128_1(32) <= \<const0>\;
  pipe_debug_debug_out_128_1(31) <= \<const0>\;
  pipe_debug_debug_out_128_1(30) <= \<const0>\;
  pipe_debug_debug_out_128_1(29) <= \<const0>\;
  pipe_debug_debug_out_128_1(28) <= \<const0>\;
  pipe_debug_debug_out_128_1(27) <= \<const0>\;
  pipe_debug_debug_out_128_1(26) <= \<const0>\;
  pipe_debug_debug_out_128_1(25) <= \<const0>\;
  pipe_debug_debug_out_128_1(24) <= \<const0>\;
  pipe_debug_debug_out_128_1(23) <= \<const0>\;
  pipe_debug_debug_out_128_1(22) <= \<const0>\;
  pipe_debug_debug_out_128_1(21) <= \<const0>\;
  pipe_debug_debug_out_128_1(20) <= \<const0>\;
  pipe_debug_debug_out_128_1(19) <= \<const0>\;
  pipe_debug_debug_out_128_1(18) <= \<const0>\;
  pipe_debug_debug_out_128_1(17) <= \<const0>\;
  pipe_debug_debug_out_128_1(16) <= \<const0>\;
  pipe_debug_debug_out_128_1(15) <= \<const0>\;
  pipe_debug_debug_out_128_1(14) <= \<const0>\;
  pipe_debug_debug_out_128_1(13) <= \<const0>\;
  pipe_debug_debug_out_128_1(12) <= \<const0>\;
  pipe_debug_debug_out_128_1(11) <= \<const0>\;
  pipe_debug_debug_out_128_1(10) <= \<const0>\;
  pipe_debug_debug_out_128_1(9) <= \<const0>\;
  pipe_debug_debug_out_128_1(8) <= \<const0>\;
  pipe_debug_debug_out_128_1(7) <= \<const0>\;
  pipe_debug_debug_out_128_1(6) <= \<const0>\;
  pipe_debug_debug_out_128_1(5) <= \<const0>\;
  pipe_debug_debug_out_128_1(4) <= \<const0>\;
  pipe_debug_debug_out_128_1(3) <= \<const0>\;
  pipe_debug_debug_out_128_1(2) <= \<const0>\;
  pipe_debug_debug_out_128_1(1) <= \<const0>\;
  pipe_debug_debug_out_128_1(0) <= \<const0>\;
  pipe_debug_debug_out_128_2(127) <= \<const0>\;
  pipe_debug_debug_out_128_2(126) <= \<const0>\;
  pipe_debug_debug_out_128_2(125) <= \<const0>\;
  pipe_debug_debug_out_128_2(124) <= \<const0>\;
  pipe_debug_debug_out_128_2(123) <= \<const0>\;
  pipe_debug_debug_out_128_2(122) <= \<const0>\;
  pipe_debug_debug_out_128_2(121) <= \<const0>\;
  pipe_debug_debug_out_128_2(120) <= \<const0>\;
  pipe_debug_debug_out_128_2(119) <= \<const0>\;
  pipe_debug_debug_out_128_2(118) <= \<const0>\;
  pipe_debug_debug_out_128_2(117) <= \<const0>\;
  pipe_debug_debug_out_128_2(116) <= \<const0>\;
  pipe_debug_debug_out_128_2(115) <= \<const0>\;
  pipe_debug_debug_out_128_2(114) <= \<const0>\;
  pipe_debug_debug_out_128_2(113) <= \<const0>\;
  pipe_debug_debug_out_128_2(112) <= \<const0>\;
  pipe_debug_debug_out_128_2(111) <= \<const0>\;
  pipe_debug_debug_out_128_2(110) <= \<const0>\;
  pipe_debug_debug_out_128_2(109) <= \<const0>\;
  pipe_debug_debug_out_128_2(108) <= \<const0>\;
  pipe_debug_debug_out_128_2(107) <= \<const0>\;
  pipe_debug_debug_out_128_2(106) <= \<const0>\;
  pipe_debug_debug_out_128_2(105) <= \<const0>\;
  pipe_debug_debug_out_128_2(104) <= \<const0>\;
  pipe_debug_debug_out_128_2(103) <= \<const0>\;
  pipe_debug_debug_out_128_2(102) <= \<const0>\;
  pipe_debug_debug_out_128_2(101) <= \<const0>\;
  pipe_debug_debug_out_128_2(100) <= \<const0>\;
  pipe_debug_debug_out_128_2(99) <= \<const0>\;
  pipe_debug_debug_out_128_2(98) <= \<const0>\;
  pipe_debug_debug_out_128_2(97) <= \<const0>\;
  pipe_debug_debug_out_128_2(96) <= \<const0>\;
  pipe_debug_debug_out_128_2(95) <= \<const0>\;
  pipe_debug_debug_out_128_2(94) <= \<const0>\;
  pipe_debug_debug_out_128_2(93) <= \<const0>\;
  pipe_debug_debug_out_128_2(92) <= \<const0>\;
  pipe_debug_debug_out_128_2(91) <= \<const0>\;
  pipe_debug_debug_out_128_2(90) <= \<const0>\;
  pipe_debug_debug_out_128_2(89) <= \<const0>\;
  pipe_debug_debug_out_128_2(88) <= \<const0>\;
  pipe_debug_debug_out_128_2(87) <= \<const0>\;
  pipe_debug_debug_out_128_2(86) <= \<const0>\;
  pipe_debug_debug_out_128_2(85) <= \<const0>\;
  pipe_debug_debug_out_128_2(84) <= \<const0>\;
  pipe_debug_debug_out_128_2(83) <= \<const0>\;
  pipe_debug_debug_out_128_2(82) <= \<const0>\;
  pipe_debug_debug_out_128_2(81) <= \<const0>\;
  pipe_debug_debug_out_128_2(80) <= \<const0>\;
  pipe_debug_debug_out_128_2(79) <= \<const0>\;
  pipe_debug_debug_out_128_2(78) <= \<const0>\;
  pipe_debug_debug_out_128_2(77) <= \<const0>\;
  pipe_debug_debug_out_128_2(76) <= \<const0>\;
  pipe_debug_debug_out_128_2(75) <= \<const0>\;
  pipe_debug_debug_out_128_2(74) <= \<const0>\;
  pipe_debug_debug_out_128_2(73) <= \<const0>\;
  pipe_debug_debug_out_128_2(72) <= \<const0>\;
  pipe_debug_debug_out_128_2(71) <= \<const0>\;
  pipe_debug_debug_out_128_2(70) <= \<const0>\;
  pipe_debug_debug_out_128_2(69) <= \<const0>\;
  pipe_debug_debug_out_128_2(68) <= \<const0>\;
  pipe_debug_debug_out_128_2(67) <= \<const0>\;
  pipe_debug_debug_out_128_2(66) <= \<const0>\;
  pipe_debug_debug_out_128_2(65) <= \<const0>\;
  pipe_debug_debug_out_128_2(64) <= \<const0>\;
  pipe_debug_debug_out_128_2(63) <= \<const0>\;
  pipe_debug_debug_out_128_2(62) <= \<const0>\;
  pipe_debug_debug_out_128_2(61) <= \<const0>\;
  pipe_debug_debug_out_128_2(60) <= \<const0>\;
  pipe_debug_debug_out_128_2(59) <= \<const0>\;
  pipe_debug_debug_out_128_2(58) <= \<const0>\;
  pipe_debug_debug_out_128_2(57) <= \<const0>\;
  pipe_debug_debug_out_128_2(56) <= \<const0>\;
  pipe_debug_debug_out_128_2(55) <= \<const0>\;
  pipe_debug_debug_out_128_2(54) <= \<const0>\;
  pipe_debug_debug_out_128_2(53) <= \<const0>\;
  pipe_debug_debug_out_128_2(52) <= \<const0>\;
  pipe_debug_debug_out_128_2(51) <= \<const0>\;
  pipe_debug_debug_out_128_2(50) <= \<const0>\;
  pipe_debug_debug_out_128_2(49) <= \<const0>\;
  pipe_debug_debug_out_128_2(48) <= \<const0>\;
  pipe_debug_debug_out_128_2(47) <= \<const0>\;
  pipe_debug_debug_out_128_2(46) <= \<const0>\;
  pipe_debug_debug_out_128_2(45) <= \<const0>\;
  pipe_debug_debug_out_128_2(44) <= \<const0>\;
  pipe_debug_debug_out_128_2(43) <= \<const0>\;
  pipe_debug_debug_out_128_2(42) <= \<const0>\;
  pipe_debug_debug_out_128_2(41) <= \<const0>\;
  pipe_debug_debug_out_128_2(40) <= \<const0>\;
  pipe_debug_debug_out_128_2(39) <= \<const0>\;
  pipe_debug_debug_out_128_2(38) <= \<const0>\;
  pipe_debug_debug_out_128_2(37) <= \<const0>\;
  pipe_debug_debug_out_128_2(36) <= \<const0>\;
  pipe_debug_debug_out_128_2(35) <= \<const0>\;
  pipe_debug_debug_out_128_2(34) <= \<const0>\;
  pipe_debug_debug_out_128_2(33) <= \<const0>\;
  pipe_debug_debug_out_128_2(32) <= \<const0>\;
  pipe_debug_debug_out_128_2(31) <= \<const0>\;
  pipe_debug_debug_out_128_2(30) <= \<const0>\;
  pipe_debug_debug_out_128_2(29) <= \<const0>\;
  pipe_debug_debug_out_128_2(28) <= \<const0>\;
  pipe_debug_debug_out_128_2(27) <= \<const0>\;
  pipe_debug_debug_out_128_2(26) <= \<const0>\;
  pipe_debug_debug_out_128_2(25) <= \<const0>\;
  pipe_debug_debug_out_128_2(24) <= \<const0>\;
  pipe_debug_debug_out_128_2(23) <= \<const0>\;
  pipe_debug_debug_out_128_2(22) <= \<const0>\;
  pipe_debug_debug_out_128_2(21) <= \<const0>\;
  pipe_debug_debug_out_128_2(20) <= \<const0>\;
  pipe_debug_debug_out_128_2(19) <= \<const0>\;
  pipe_debug_debug_out_128_2(18) <= \<const0>\;
  pipe_debug_debug_out_128_2(17) <= \<const0>\;
  pipe_debug_debug_out_128_2(16) <= \<const0>\;
  pipe_debug_debug_out_128_2(15) <= \<const0>\;
  pipe_debug_debug_out_128_2(14) <= \<const0>\;
  pipe_debug_debug_out_128_2(13) <= \<const0>\;
  pipe_debug_debug_out_128_2(12) <= \<const0>\;
  pipe_debug_debug_out_128_2(11) <= \<const0>\;
  pipe_debug_debug_out_128_2(10) <= \<const0>\;
  pipe_debug_debug_out_128_2(9) <= \<const0>\;
  pipe_debug_debug_out_128_2(8) <= \<const0>\;
  pipe_debug_debug_out_128_2(7) <= \<const0>\;
  pipe_debug_debug_out_128_2(6) <= \<const0>\;
  pipe_debug_debug_out_128_2(5) <= \<const0>\;
  pipe_debug_debug_out_128_2(4) <= \<const0>\;
  pipe_debug_debug_out_128_2(3) <= \<const0>\;
  pipe_debug_debug_out_128_2(2) <= \<const0>\;
  pipe_debug_debug_out_128_2(1) <= \<const0>\;
  pipe_debug_debug_out_128_2(0) <= \<const0>\;
  pipe_debug_debug_out_128_3(127) <= \<const0>\;
  pipe_debug_debug_out_128_3(126) <= \<const0>\;
  pipe_debug_debug_out_128_3(125) <= \<const0>\;
  pipe_debug_debug_out_128_3(124) <= \<const0>\;
  pipe_debug_debug_out_128_3(123) <= \<const0>\;
  pipe_debug_debug_out_128_3(122) <= \<const0>\;
  pipe_debug_debug_out_128_3(121) <= \<const0>\;
  pipe_debug_debug_out_128_3(120) <= \<const0>\;
  pipe_debug_debug_out_128_3(119) <= \<const0>\;
  pipe_debug_debug_out_128_3(118) <= \<const0>\;
  pipe_debug_debug_out_128_3(117) <= \<const0>\;
  pipe_debug_debug_out_128_3(116) <= \<const0>\;
  pipe_debug_debug_out_128_3(115) <= \<const0>\;
  pipe_debug_debug_out_128_3(114) <= \<const0>\;
  pipe_debug_debug_out_128_3(113) <= \<const0>\;
  pipe_debug_debug_out_128_3(112) <= \<const0>\;
  pipe_debug_debug_out_128_3(111) <= \<const0>\;
  pipe_debug_debug_out_128_3(110) <= \<const0>\;
  pipe_debug_debug_out_128_3(109) <= \<const0>\;
  pipe_debug_debug_out_128_3(108) <= \<const0>\;
  pipe_debug_debug_out_128_3(107) <= \<const0>\;
  pipe_debug_debug_out_128_3(106) <= \<const0>\;
  pipe_debug_debug_out_128_3(105) <= \<const0>\;
  pipe_debug_debug_out_128_3(104) <= \<const0>\;
  pipe_debug_debug_out_128_3(103) <= \<const0>\;
  pipe_debug_debug_out_128_3(102) <= \<const0>\;
  pipe_debug_debug_out_128_3(101) <= \<const0>\;
  pipe_debug_debug_out_128_3(100) <= \<const0>\;
  pipe_debug_debug_out_128_3(99) <= \<const0>\;
  pipe_debug_debug_out_128_3(98) <= \<const0>\;
  pipe_debug_debug_out_128_3(97) <= \<const0>\;
  pipe_debug_debug_out_128_3(96) <= \<const0>\;
  pipe_debug_debug_out_128_3(95) <= \<const0>\;
  pipe_debug_debug_out_128_3(94) <= \<const0>\;
  pipe_debug_debug_out_128_3(93) <= \<const0>\;
  pipe_debug_debug_out_128_3(92) <= \<const0>\;
  pipe_debug_debug_out_128_3(91) <= \<const0>\;
  pipe_debug_debug_out_128_3(90) <= \<const0>\;
  pipe_debug_debug_out_128_3(89) <= \<const0>\;
  pipe_debug_debug_out_128_3(88) <= \<const0>\;
  pipe_debug_debug_out_128_3(87) <= \<const0>\;
  pipe_debug_debug_out_128_3(86) <= \<const0>\;
  pipe_debug_debug_out_128_3(85) <= \<const0>\;
  pipe_debug_debug_out_128_3(84) <= \<const0>\;
  pipe_debug_debug_out_128_3(83) <= \<const0>\;
  pipe_debug_debug_out_128_3(82) <= \<const0>\;
  pipe_debug_debug_out_128_3(81) <= \<const0>\;
  pipe_debug_debug_out_128_3(80) <= \<const0>\;
  pipe_debug_debug_out_128_3(79) <= \<const0>\;
  pipe_debug_debug_out_128_3(78) <= \<const0>\;
  pipe_debug_debug_out_128_3(77) <= \<const0>\;
  pipe_debug_debug_out_128_3(76) <= \<const0>\;
  pipe_debug_debug_out_128_3(75) <= \<const0>\;
  pipe_debug_debug_out_128_3(74) <= \<const0>\;
  pipe_debug_debug_out_128_3(73) <= \<const0>\;
  pipe_debug_debug_out_128_3(72) <= \<const0>\;
  pipe_debug_debug_out_128_3(71) <= \<const0>\;
  pipe_debug_debug_out_128_3(70) <= \<const0>\;
  pipe_debug_debug_out_128_3(69) <= \<const0>\;
  pipe_debug_debug_out_128_3(68) <= \<const0>\;
  pipe_debug_debug_out_128_3(67) <= \<const0>\;
  pipe_debug_debug_out_128_3(66) <= \<const0>\;
  pipe_debug_debug_out_128_3(65) <= \<const0>\;
  pipe_debug_debug_out_128_3(64) <= \<const0>\;
  pipe_debug_debug_out_128_3(63) <= \<const0>\;
  pipe_debug_debug_out_128_3(62) <= \<const0>\;
  pipe_debug_debug_out_128_3(61) <= \<const0>\;
  pipe_debug_debug_out_128_3(60) <= \<const0>\;
  pipe_debug_debug_out_128_3(59) <= \<const0>\;
  pipe_debug_debug_out_128_3(58) <= \<const0>\;
  pipe_debug_debug_out_128_3(57) <= \<const0>\;
  pipe_debug_debug_out_128_3(56) <= \<const0>\;
  pipe_debug_debug_out_128_3(55) <= \<const0>\;
  pipe_debug_debug_out_128_3(54) <= \<const0>\;
  pipe_debug_debug_out_128_3(53) <= \<const0>\;
  pipe_debug_debug_out_128_3(52) <= \<const0>\;
  pipe_debug_debug_out_128_3(51) <= \<const0>\;
  pipe_debug_debug_out_128_3(50) <= \<const0>\;
  pipe_debug_debug_out_128_3(49) <= \<const0>\;
  pipe_debug_debug_out_128_3(48) <= \<const0>\;
  pipe_debug_debug_out_128_3(47) <= \<const0>\;
  pipe_debug_debug_out_128_3(46) <= \<const0>\;
  pipe_debug_debug_out_128_3(45) <= \<const0>\;
  pipe_debug_debug_out_128_3(44) <= \<const0>\;
  pipe_debug_debug_out_128_3(43) <= \<const0>\;
  pipe_debug_debug_out_128_3(42) <= \<const0>\;
  pipe_debug_debug_out_128_3(41) <= \<const0>\;
  pipe_debug_debug_out_128_3(40) <= \<const0>\;
  pipe_debug_debug_out_128_3(39) <= \<const0>\;
  pipe_debug_debug_out_128_3(38) <= \<const0>\;
  pipe_debug_debug_out_128_3(37) <= \<const0>\;
  pipe_debug_debug_out_128_3(36) <= \<const0>\;
  pipe_debug_debug_out_128_3(35) <= \<const0>\;
  pipe_debug_debug_out_128_3(34) <= \<const0>\;
  pipe_debug_debug_out_128_3(33) <= \<const0>\;
  pipe_debug_debug_out_128_3(32) <= \<const0>\;
  pipe_debug_debug_out_128_3(31) <= \<const0>\;
  pipe_debug_debug_out_128_3(30) <= \<const0>\;
  pipe_debug_debug_out_128_3(29) <= \<const0>\;
  pipe_debug_debug_out_128_3(28) <= \<const0>\;
  pipe_debug_debug_out_128_3(27) <= \<const0>\;
  pipe_debug_debug_out_128_3(26) <= \<const0>\;
  pipe_debug_debug_out_128_3(25) <= \<const0>\;
  pipe_debug_debug_out_128_3(24) <= \<const0>\;
  pipe_debug_debug_out_128_3(23) <= \<const0>\;
  pipe_debug_debug_out_128_3(22) <= \<const0>\;
  pipe_debug_debug_out_128_3(21) <= \<const0>\;
  pipe_debug_debug_out_128_3(20) <= \<const0>\;
  pipe_debug_debug_out_128_3(19) <= \<const0>\;
  pipe_debug_debug_out_128_3(18) <= \<const0>\;
  pipe_debug_debug_out_128_3(17) <= \<const0>\;
  pipe_debug_debug_out_128_3(16) <= \<const0>\;
  pipe_debug_debug_out_128_3(15) <= \<const0>\;
  pipe_debug_debug_out_128_3(14) <= \<const0>\;
  pipe_debug_debug_out_128_3(13) <= \<const0>\;
  pipe_debug_debug_out_128_3(12) <= \<const0>\;
  pipe_debug_debug_out_128_3(11) <= \<const0>\;
  pipe_debug_debug_out_128_3(10) <= \<const0>\;
  pipe_debug_debug_out_128_3(9) <= \<const0>\;
  pipe_debug_debug_out_128_3(8) <= \<const0>\;
  pipe_debug_debug_out_128_3(7) <= \<const0>\;
  pipe_debug_debug_out_128_3(6) <= \<const0>\;
  pipe_debug_debug_out_128_3(5) <= \<const0>\;
  pipe_debug_debug_out_128_3(4) <= \<const0>\;
  pipe_debug_debug_out_128_3(3) <= \<const0>\;
  pipe_debug_debug_out_128_3(2) <= \<const0>\;
  pipe_debug_debug_out_128_3(1) <= \<const0>\;
  pipe_debug_debug_out_128_3(0) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(15) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(14) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(13) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(12) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(11) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(10) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(9) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(8) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(7) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(6) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(5) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(4) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(3) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(2) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(1) <= \<const0>\;
  pipe_debug_debug_out_ext_16_0(0) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(15) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(14) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(13) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(12) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(11) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(10) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(9) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(8) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(7) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(6) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(5) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(4) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(3) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(2) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(1) <= \<const0>\;
  pipe_debug_debug_out_ext_16_1(0) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(15) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(14) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(13) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(12) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(11) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(10) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(9) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(8) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(7) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(6) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(5) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(4) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(3) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(2) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(1) <= \<const0>\;
  pipe_debug_debug_out_ext_16_2(0) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(15) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(14) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(13) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(12) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(11) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(10) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(9) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(8) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(7) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(6) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(5) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(4) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(3) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(2) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(1) <= \<const0>\;
  pipe_debug_debug_out_ext_16_3(0) <= \<const0>\;
  pipe_debug_inject_rx_status(7) <= \<const0>\;
  pipe_debug_inject_rx_status(6) <= \<const0>\;
  pipe_debug_inject_rx_status(5) <= \<const0>\;
  pipe_debug_inject_rx_status(4) <= \<const0>\;
  pipe_debug_inject_rx_status(3) <= \<const0>\;
  pipe_debug_inject_rx_status(2) <= \<const0>\;
  pipe_debug_inject_rx_status(1) <= \<const0>\;
  pipe_debug_inject_rx_status(0) <= \<const0>\;
  pipe_debug_inject_tx_status(7) <= \<const0>\;
  pipe_debug_inject_tx_status(6) <= \<const0>\;
  pipe_debug_inject_tx_status(5) <= \<const0>\;
  pipe_debug_inject_tx_status(4) <= \<const0>\;
  pipe_debug_inject_tx_status(3) <= \<const0>\;
  pipe_debug_inject_tx_status(2) <= \<const0>\;
  pipe_debug_inject_tx_status(1) <= \<const0>\;
  pipe_debug_inject_tx_status(0) <= \<const0>\;
  pipe_dmonitorout(29) <= \<const0>\;
  pipe_dmonitorout(28) <= \<const0>\;
  pipe_dmonitorout(27) <= \<const0>\;
  pipe_dmonitorout(26) <= \<const0>\;
  pipe_dmonitorout(25) <= \<const0>\;
  pipe_dmonitorout(24) <= \<const0>\;
  pipe_dmonitorout(23) <= \<const0>\;
  pipe_dmonitorout(22) <= \<const0>\;
  pipe_dmonitorout(21) <= \<const0>\;
  pipe_dmonitorout(20) <= \<const0>\;
  pipe_dmonitorout(19) <= \<const0>\;
  pipe_dmonitorout(18) <= \<const0>\;
  pipe_dmonitorout(17) <= \<const0>\;
  pipe_dmonitorout(16) <= \<const0>\;
  pipe_dmonitorout(15) <= \<const0>\;
  pipe_dmonitorout(14) <= \<const0>\;
  pipe_dmonitorout(13) <= \<const0>\;
  pipe_dmonitorout(12) <= \<const0>\;
  pipe_dmonitorout(11) <= \<const0>\;
  pipe_dmonitorout(10) <= \<const0>\;
  pipe_dmonitorout(9) <= \<const0>\;
  pipe_dmonitorout(8) <= \<const0>\;
  pipe_dmonitorout(7) <= \<const0>\;
  pipe_dmonitorout(6) <= \<const0>\;
  pipe_dmonitorout(5) <= \<const0>\;
  pipe_dmonitorout(4) <= \<const0>\;
  pipe_dmonitorout(3) <= \<const0>\;
  pipe_dmonitorout(2) <= \<const0>\;
  pipe_dmonitorout(1) <= \<const0>\;
  pipe_dmonitorout(0) <= \<const0>\;
  pipe_drp_fsm(13) <= \<const0>\;
  pipe_drp_fsm(12) <= \<const0>\;
  pipe_drp_fsm(11) <= \<const0>\;
  pipe_drp_fsm(10) <= \<const0>\;
  pipe_drp_fsm(9) <= \<const0>\;
  pipe_drp_fsm(8) <= \<const0>\;
  pipe_drp_fsm(7) <= \<const0>\;
  pipe_drp_fsm(6) <= \<const0>\;
  pipe_drp_fsm(5) <= \<const0>\;
  pipe_drp_fsm(4) <= \<const0>\;
  pipe_drp_fsm(3) <= \<const0>\;
  pipe_drp_fsm(2) <= \<const0>\;
  pipe_drp_fsm(1) <= \<const0>\;
  pipe_drp_fsm(0) <= \<const0>\;
  pipe_eyescandataerror(1) <= \<const0>\;
  pipe_eyescandataerror(0) <= \<const0>\;
  pipe_gen3_out <= \<const0>\;
  pipe_pclk_sel_out(1) <= \<const0>\;
  pipe_pclk_sel_out(0) <= \<const0>\;
  pipe_qpll_lock(0) <= \<const0>\;
  pipe_qrst_fsm(11) <= \<const0>\;
  pipe_qrst_fsm(10) <= \<const0>\;
  pipe_qrst_fsm(9) <= \<const0>\;
  pipe_qrst_fsm(8) <= \<const0>\;
  pipe_qrst_fsm(7) <= \<const0>\;
  pipe_qrst_fsm(6) <= \<const0>\;
  pipe_qrst_fsm(5) <= \<const0>\;
  pipe_qrst_fsm(4) <= \<const0>\;
  pipe_qrst_fsm(3) <= \<const0>\;
  pipe_qrst_fsm(2) <= \<const0>\;
  pipe_qrst_fsm(1) <= \<const0>\;
  pipe_qrst_fsm(0) <= \<const0>\;
  pipe_qrst_idle <= \<const0>\;
  pipe_rate_fsm(9) <= \<const0>\;
  pipe_rate_fsm(8) <= \<const0>\;
  pipe_rate_fsm(7) <= \<const0>\;
  pipe_rate_fsm(6) <= \<const0>\;
  pipe_rate_fsm(5) <= \<const0>\;
  pipe_rate_fsm(4) <= \<const0>\;
  pipe_rate_fsm(3) <= \<const0>\;
  pipe_rate_fsm(2) <= \<const0>\;
  pipe_rate_fsm(1) <= \<const0>\;
  pipe_rate_fsm(0) <= \<const0>\;
  pipe_rate_idle <= \<const0>\;
  pipe_rst_fsm(4) <= \<const0>\;
  pipe_rst_fsm(3) <= \<const0>\;
  pipe_rst_fsm(2) <= \<const0>\;
  pipe_rst_fsm(1) <= \<const0>\;
  pipe_rst_fsm(0) <= \<const0>\;
  pipe_rst_idle <= \<const0>\;
  pipe_rxbufstatus(5) <= \<const0>\;
  pipe_rxbufstatus(4) <= \<const0>\;
  pipe_rxbufstatus(3) <= \<const0>\;
  pipe_rxbufstatus(2) <= \<const0>\;
  pipe_rxbufstatus(1) <= \<const0>\;
  pipe_rxbufstatus(0) <= \<const0>\;
  pipe_rxcommadet(1) <= \<const0>\;
  pipe_rxcommadet(0) <= \<const0>\;
  pipe_rxdisperr(15) <= \<const0>\;
  pipe_rxdisperr(14) <= \<const0>\;
  pipe_rxdisperr(13) <= \<const0>\;
  pipe_rxdisperr(12) <= \<const0>\;
  pipe_rxdisperr(11) <= \<const0>\;
  pipe_rxdisperr(10) <= \<const0>\;
  pipe_rxdisperr(9) <= \<const0>\;
  pipe_rxdisperr(8) <= \<const0>\;
  pipe_rxdisperr(7) <= \<const0>\;
  pipe_rxdisperr(6) <= \<const0>\;
  pipe_rxdisperr(5) <= \<const0>\;
  pipe_rxdisperr(4) <= \<const0>\;
  pipe_rxdisperr(3) <= \<const0>\;
  pipe_rxdisperr(2) <= \<const0>\;
  pipe_rxdisperr(1) <= \<const0>\;
  pipe_rxdisperr(0) <= \<const0>\;
  pipe_rxdlysresetdone(1) <= \<const0>\;
  pipe_rxdlysresetdone(0) <= \<const0>\;
  pipe_rxnotintable(15) <= \<const0>\;
  pipe_rxnotintable(14) <= \<const0>\;
  pipe_rxnotintable(13) <= \<const0>\;
  pipe_rxnotintable(12) <= \<const0>\;
  pipe_rxnotintable(11) <= \<const0>\;
  pipe_rxnotintable(10) <= \<const0>\;
  pipe_rxnotintable(9) <= \<const0>\;
  pipe_rxnotintable(8) <= \<const0>\;
  pipe_rxnotintable(7) <= \<const0>\;
  pipe_rxnotintable(6) <= \<const0>\;
  pipe_rxnotintable(5) <= \<const0>\;
  pipe_rxnotintable(4) <= \<const0>\;
  pipe_rxnotintable(3) <= \<const0>\;
  pipe_rxnotintable(2) <= \<const0>\;
  pipe_rxnotintable(1) <= \<const0>\;
  pipe_rxnotintable(0) <= \<const0>\;
  pipe_rxoutclk_out(1) <= \<const0>\;
  pipe_rxoutclk_out(0) <= \<const0>\;
  pipe_rxphaligndone(1) <= \<const0>\;
  pipe_rxphaligndone(0) <= \<const0>\;
  pipe_rxpmaresetdone(1) <= \<const0>\;
  pipe_rxpmaresetdone(0) <= \<const0>\;
  pipe_rxprbserr(1) <= \<const0>\;
  pipe_rxprbserr(0) <= \<const0>\;
  pipe_rxstatus(5) <= \<const0>\;
  pipe_rxstatus(4) <= \<const0>\;
  pipe_rxstatus(3) <= \<const0>\;
  pipe_rxstatus(2) <= \<const0>\;
  pipe_rxstatus(1) <= \<const0>\;
  pipe_rxstatus(0) <= \<const0>\;
  pipe_rxsyncdone(1) <= \<const0>\;
  pipe_rxsyncdone(0) <= \<const0>\;
  pipe_sync_fsm_rx(13) <= \<const0>\;
  pipe_sync_fsm_rx(12) <= \<const0>\;
  pipe_sync_fsm_rx(11) <= \<const0>\;
  pipe_sync_fsm_rx(10) <= \<const0>\;
  pipe_sync_fsm_rx(9) <= \<const0>\;
  pipe_sync_fsm_rx(8) <= \<const0>\;
  pipe_sync_fsm_rx(7) <= \<const0>\;
  pipe_sync_fsm_rx(6) <= \<const0>\;
  pipe_sync_fsm_rx(5) <= \<const0>\;
  pipe_sync_fsm_rx(4) <= \<const0>\;
  pipe_sync_fsm_rx(3) <= \<const0>\;
  pipe_sync_fsm_rx(2) <= \<const0>\;
  pipe_sync_fsm_rx(1) <= \<const0>\;
  pipe_sync_fsm_rx(0) <= \<const0>\;
  pipe_sync_fsm_tx(11) <= \<const0>\;
  pipe_sync_fsm_tx(10) <= \<const0>\;
  pipe_sync_fsm_tx(9) <= \<const0>\;
  pipe_sync_fsm_tx(8) <= \<const0>\;
  pipe_sync_fsm_tx(7) <= \<const0>\;
  pipe_sync_fsm_tx(6) <= \<const0>\;
  pipe_sync_fsm_tx(5) <= \<const0>\;
  pipe_sync_fsm_tx(4) <= \<const0>\;
  pipe_sync_fsm_tx(3) <= \<const0>\;
  pipe_sync_fsm_tx(2) <= \<const0>\;
  pipe_sync_fsm_tx(1) <= \<const0>\;
  pipe_sync_fsm_tx(0) <= \<const0>\;
  pipe_tx0_powerdown(1) <= \<const0>\;
  pipe_tx0_powerdown(0) <= \<const0>\;
  pipe_tx0_rcvr_det <= \<const0>\;
  pipe_tx_0_sigs(83) <= \<const0>\;
  pipe_tx_0_sigs(82) <= \<const0>\;
  pipe_tx_0_sigs(81) <= \<const0>\;
  pipe_tx_0_sigs(80) <= \<const0>\;
  pipe_tx_0_sigs(79) <= \<const0>\;
  pipe_tx_0_sigs(78) <= \<const0>\;
  pipe_tx_0_sigs(77) <= \<const0>\;
  pipe_tx_0_sigs(76) <= \<const0>\;
  pipe_tx_0_sigs(75) <= \<const0>\;
  pipe_tx_0_sigs(74) <= \<const0>\;
  pipe_tx_0_sigs(73) <= \<const0>\;
  pipe_tx_0_sigs(72) <= \<const0>\;
  pipe_tx_0_sigs(71) <= \<const0>\;
  pipe_tx_0_sigs(70) <= \<const0>\;
  pipe_tx_0_sigs(69) <= \<const0>\;
  pipe_tx_0_sigs(68) <= \<const0>\;
  pipe_tx_0_sigs(67) <= \<const0>\;
  pipe_tx_0_sigs(66) <= \<const0>\;
  pipe_tx_0_sigs(65) <= \<const0>\;
  pipe_tx_0_sigs(64) <= \<const0>\;
  pipe_tx_0_sigs(63) <= \<const0>\;
  pipe_tx_0_sigs(62) <= \<const0>\;
  pipe_tx_0_sigs(61) <= \<const0>\;
  pipe_tx_0_sigs(60) <= \<const0>\;
  pipe_tx_0_sigs(59) <= \<const0>\;
  pipe_tx_0_sigs(58) <= \<const0>\;
  pipe_tx_0_sigs(57) <= \<const0>\;
  pipe_tx_0_sigs(56) <= \<const0>\;
  pipe_tx_0_sigs(55) <= \<const0>\;
  pipe_tx_0_sigs(54) <= \<const0>\;
  pipe_tx_0_sigs(53) <= \<const0>\;
  pipe_tx_0_sigs(52) <= \<const0>\;
  pipe_tx_0_sigs(51) <= \<const0>\;
  pipe_tx_0_sigs(50) <= \<const0>\;
  pipe_tx_0_sigs(49) <= \<const0>\;
  pipe_tx_0_sigs(48) <= \<const0>\;
  pipe_tx_0_sigs(47) <= \<const0>\;
  pipe_tx_0_sigs(46) <= \<const0>\;
  pipe_tx_0_sigs(45) <= \<const0>\;
  pipe_tx_0_sigs(44) <= \<const0>\;
  pipe_tx_0_sigs(43) <= \<const0>\;
  pipe_tx_0_sigs(42) <= \<const0>\;
  pipe_tx_0_sigs(41) <= \<const0>\;
  pipe_tx_0_sigs(40) <= \<const0>\;
  pipe_tx_0_sigs(39) <= \<const0>\;
  pipe_tx_0_sigs(38) <= \<const0>\;
  pipe_tx_0_sigs(37) <= \<const0>\;
  pipe_tx_0_sigs(36) <= \<const0>\;
  pipe_tx_0_sigs(35) <= \<const0>\;
  pipe_tx_0_sigs(34) <= \<const0>\;
  pipe_tx_0_sigs(33) <= \<const0>\;
  pipe_tx_0_sigs(32) <= \<const0>\;
  pipe_tx_0_sigs(31) <= \<const0>\;
  pipe_tx_0_sigs(30) <= \<const0>\;
  pipe_tx_0_sigs(29) <= \<const0>\;
  pipe_tx_0_sigs(28) <= \<const0>\;
  pipe_tx_0_sigs(27) <= \<const0>\;
  pipe_tx_0_sigs(26) <= \<const0>\;
  pipe_tx_0_sigs(25) <= \<const0>\;
  pipe_tx_0_sigs(24) <= \<const0>\;
  pipe_tx_0_sigs(23) <= \<const0>\;
  pipe_tx_0_sigs(22) <= \<const0>\;
  pipe_tx_0_sigs(21) <= \<const0>\;
  pipe_tx_0_sigs(20) <= \<const0>\;
  pipe_tx_0_sigs(19) <= \<const0>\;
  pipe_tx_0_sigs(18) <= \<const0>\;
  pipe_tx_0_sigs(17) <= \<const0>\;
  pipe_tx_0_sigs(16) <= \<const0>\;
  pipe_tx_0_sigs(15) <= \<const0>\;
  pipe_tx_0_sigs(14) <= \<const0>\;
  pipe_tx_0_sigs(13) <= \<const0>\;
  pipe_tx_0_sigs(12) <= \<const0>\;
  pipe_tx_0_sigs(11) <= \<const0>\;
  pipe_tx_0_sigs(10) <= \<const0>\;
  pipe_tx_0_sigs(9) <= \<const0>\;
  pipe_tx_0_sigs(8) <= \<const0>\;
  pipe_tx_0_sigs(7) <= \<const0>\;
  pipe_tx_0_sigs(6) <= \<const0>\;
  pipe_tx_0_sigs(5) <= \<const0>\;
  pipe_tx_0_sigs(4) <= \<const0>\;
  pipe_tx_0_sigs(3) <= \<const0>\;
  pipe_tx_0_sigs(2) <= \<const0>\;
  pipe_tx_0_sigs(1) <= \<const0>\;
  pipe_tx_0_sigs(0) <= \<const0>\;
  pipe_tx_10_sigs(83) <= \<const0>\;
  pipe_tx_10_sigs(82) <= \<const0>\;
  pipe_tx_10_sigs(81) <= \<const0>\;
  pipe_tx_10_sigs(80) <= \<const0>\;
  pipe_tx_10_sigs(79) <= \<const0>\;
  pipe_tx_10_sigs(78) <= \<const0>\;
  pipe_tx_10_sigs(77) <= \<const0>\;
  pipe_tx_10_sigs(76) <= \<const0>\;
  pipe_tx_10_sigs(75) <= \<const0>\;
  pipe_tx_10_sigs(74) <= \<const0>\;
  pipe_tx_10_sigs(73) <= \<const0>\;
  pipe_tx_10_sigs(72) <= \<const0>\;
  pipe_tx_10_sigs(71) <= \<const0>\;
  pipe_tx_10_sigs(70) <= \<const0>\;
  pipe_tx_10_sigs(69) <= \<const0>\;
  pipe_tx_10_sigs(68) <= \<const0>\;
  pipe_tx_10_sigs(67) <= \<const0>\;
  pipe_tx_10_sigs(66) <= \<const0>\;
  pipe_tx_10_sigs(65) <= \<const0>\;
  pipe_tx_10_sigs(64) <= \<const0>\;
  pipe_tx_10_sigs(63) <= \<const0>\;
  pipe_tx_10_sigs(62) <= \<const0>\;
  pipe_tx_10_sigs(61) <= \<const0>\;
  pipe_tx_10_sigs(60) <= \<const0>\;
  pipe_tx_10_sigs(59) <= \<const0>\;
  pipe_tx_10_sigs(58) <= \<const0>\;
  pipe_tx_10_sigs(57) <= \<const0>\;
  pipe_tx_10_sigs(56) <= \<const0>\;
  pipe_tx_10_sigs(55) <= \<const0>\;
  pipe_tx_10_sigs(54) <= \<const0>\;
  pipe_tx_10_sigs(53) <= \<const0>\;
  pipe_tx_10_sigs(52) <= \<const0>\;
  pipe_tx_10_sigs(51) <= \<const0>\;
  pipe_tx_10_sigs(50) <= \<const0>\;
  pipe_tx_10_sigs(49) <= \<const0>\;
  pipe_tx_10_sigs(48) <= \<const0>\;
  pipe_tx_10_sigs(47) <= \<const0>\;
  pipe_tx_10_sigs(46) <= \<const0>\;
  pipe_tx_10_sigs(45) <= \<const0>\;
  pipe_tx_10_sigs(44) <= \<const0>\;
  pipe_tx_10_sigs(43) <= \<const0>\;
  pipe_tx_10_sigs(42) <= \<const0>\;
  pipe_tx_10_sigs(41) <= \<const0>\;
  pipe_tx_10_sigs(40) <= \<const0>\;
  pipe_tx_10_sigs(39) <= \<const0>\;
  pipe_tx_10_sigs(38) <= \<const0>\;
  pipe_tx_10_sigs(37) <= \<const0>\;
  pipe_tx_10_sigs(36) <= \<const0>\;
  pipe_tx_10_sigs(35) <= \<const0>\;
  pipe_tx_10_sigs(34) <= \<const0>\;
  pipe_tx_10_sigs(33) <= \<const0>\;
  pipe_tx_10_sigs(32) <= \<const0>\;
  pipe_tx_10_sigs(31) <= \<const0>\;
  pipe_tx_10_sigs(30) <= \<const0>\;
  pipe_tx_10_sigs(29) <= \<const0>\;
  pipe_tx_10_sigs(28) <= \<const0>\;
  pipe_tx_10_sigs(27) <= \<const0>\;
  pipe_tx_10_sigs(26) <= \<const0>\;
  pipe_tx_10_sigs(25) <= \<const0>\;
  pipe_tx_10_sigs(24) <= \<const0>\;
  pipe_tx_10_sigs(23) <= \<const0>\;
  pipe_tx_10_sigs(22) <= \<const0>\;
  pipe_tx_10_sigs(21) <= \<const0>\;
  pipe_tx_10_sigs(20) <= \<const0>\;
  pipe_tx_10_sigs(19) <= \<const0>\;
  pipe_tx_10_sigs(18) <= \<const0>\;
  pipe_tx_10_sigs(17) <= \<const0>\;
  pipe_tx_10_sigs(16) <= \<const0>\;
  pipe_tx_10_sigs(15) <= \<const0>\;
  pipe_tx_10_sigs(14) <= \<const0>\;
  pipe_tx_10_sigs(13) <= \<const0>\;
  pipe_tx_10_sigs(12) <= \<const0>\;
  pipe_tx_10_sigs(11) <= \<const0>\;
  pipe_tx_10_sigs(10) <= \<const0>\;
  pipe_tx_10_sigs(9) <= \<const0>\;
  pipe_tx_10_sigs(8) <= \<const0>\;
  pipe_tx_10_sigs(7) <= \<const0>\;
  pipe_tx_10_sigs(6) <= \<const0>\;
  pipe_tx_10_sigs(5) <= \<const0>\;
  pipe_tx_10_sigs(4) <= \<const0>\;
  pipe_tx_10_sigs(3) <= \<const0>\;
  pipe_tx_10_sigs(2) <= \<const0>\;
  pipe_tx_10_sigs(1) <= \<const0>\;
  pipe_tx_10_sigs(0) <= \<const0>\;
  pipe_tx_11_sigs(83) <= \<const0>\;
  pipe_tx_11_sigs(82) <= \<const0>\;
  pipe_tx_11_sigs(81) <= \<const0>\;
  pipe_tx_11_sigs(80) <= \<const0>\;
  pipe_tx_11_sigs(79) <= \<const0>\;
  pipe_tx_11_sigs(78) <= \<const0>\;
  pipe_tx_11_sigs(77) <= \<const0>\;
  pipe_tx_11_sigs(76) <= \<const0>\;
  pipe_tx_11_sigs(75) <= \<const0>\;
  pipe_tx_11_sigs(74) <= \<const0>\;
  pipe_tx_11_sigs(73) <= \<const0>\;
  pipe_tx_11_sigs(72) <= \<const0>\;
  pipe_tx_11_sigs(71) <= \<const0>\;
  pipe_tx_11_sigs(70) <= \<const0>\;
  pipe_tx_11_sigs(69) <= \<const0>\;
  pipe_tx_11_sigs(68) <= \<const0>\;
  pipe_tx_11_sigs(67) <= \<const0>\;
  pipe_tx_11_sigs(66) <= \<const0>\;
  pipe_tx_11_sigs(65) <= \<const0>\;
  pipe_tx_11_sigs(64) <= \<const0>\;
  pipe_tx_11_sigs(63) <= \<const0>\;
  pipe_tx_11_sigs(62) <= \<const0>\;
  pipe_tx_11_sigs(61) <= \<const0>\;
  pipe_tx_11_sigs(60) <= \<const0>\;
  pipe_tx_11_sigs(59) <= \<const0>\;
  pipe_tx_11_sigs(58) <= \<const0>\;
  pipe_tx_11_sigs(57) <= \<const0>\;
  pipe_tx_11_sigs(56) <= \<const0>\;
  pipe_tx_11_sigs(55) <= \<const0>\;
  pipe_tx_11_sigs(54) <= \<const0>\;
  pipe_tx_11_sigs(53) <= \<const0>\;
  pipe_tx_11_sigs(52) <= \<const0>\;
  pipe_tx_11_sigs(51) <= \<const0>\;
  pipe_tx_11_sigs(50) <= \<const0>\;
  pipe_tx_11_sigs(49) <= \<const0>\;
  pipe_tx_11_sigs(48) <= \<const0>\;
  pipe_tx_11_sigs(47) <= \<const0>\;
  pipe_tx_11_sigs(46) <= \<const0>\;
  pipe_tx_11_sigs(45) <= \<const0>\;
  pipe_tx_11_sigs(44) <= \<const0>\;
  pipe_tx_11_sigs(43) <= \<const0>\;
  pipe_tx_11_sigs(42) <= \<const0>\;
  pipe_tx_11_sigs(41) <= \<const0>\;
  pipe_tx_11_sigs(40) <= \<const0>\;
  pipe_tx_11_sigs(39) <= \<const0>\;
  pipe_tx_11_sigs(38) <= \<const0>\;
  pipe_tx_11_sigs(37) <= \<const0>\;
  pipe_tx_11_sigs(36) <= \<const0>\;
  pipe_tx_11_sigs(35) <= \<const0>\;
  pipe_tx_11_sigs(34) <= \<const0>\;
  pipe_tx_11_sigs(33) <= \<const0>\;
  pipe_tx_11_sigs(32) <= \<const0>\;
  pipe_tx_11_sigs(31) <= \<const0>\;
  pipe_tx_11_sigs(30) <= \<const0>\;
  pipe_tx_11_sigs(29) <= \<const0>\;
  pipe_tx_11_sigs(28) <= \<const0>\;
  pipe_tx_11_sigs(27) <= \<const0>\;
  pipe_tx_11_sigs(26) <= \<const0>\;
  pipe_tx_11_sigs(25) <= \<const0>\;
  pipe_tx_11_sigs(24) <= \<const0>\;
  pipe_tx_11_sigs(23) <= \<const0>\;
  pipe_tx_11_sigs(22) <= \<const0>\;
  pipe_tx_11_sigs(21) <= \<const0>\;
  pipe_tx_11_sigs(20) <= \<const0>\;
  pipe_tx_11_sigs(19) <= \<const0>\;
  pipe_tx_11_sigs(18) <= \<const0>\;
  pipe_tx_11_sigs(17) <= \<const0>\;
  pipe_tx_11_sigs(16) <= \<const0>\;
  pipe_tx_11_sigs(15) <= \<const0>\;
  pipe_tx_11_sigs(14) <= \<const0>\;
  pipe_tx_11_sigs(13) <= \<const0>\;
  pipe_tx_11_sigs(12) <= \<const0>\;
  pipe_tx_11_sigs(11) <= \<const0>\;
  pipe_tx_11_sigs(10) <= \<const0>\;
  pipe_tx_11_sigs(9) <= \<const0>\;
  pipe_tx_11_sigs(8) <= \<const0>\;
  pipe_tx_11_sigs(7) <= \<const0>\;
  pipe_tx_11_sigs(6) <= \<const0>\;
  pipe_tx_11_sigs(5) <= \<const0>\;
  pipe_tx_11_sigs(4) <= \<const0>\;
  pipe_tx_11_sigs(3) <= \<const0>\;
  pipe_tx_11_sigs(2) <= \<const0>\;
  pipe_tx_11_sigs(1) <= \<const0>\;
  pipe_tx_11_sigs(0) <= \<const0>\;
  pipe_tx_12_sigs(83) <= \<const0>\;
  pipe_tx_12_sigs(82) <= \<const0>\;
  pipe_tx_12_sigs(81) <= \<const0>\;
  pipe_tx_12_sigs(80) <= \<const0>\;
  pipe_tx_12_sigs(79) <= \<const0>\;
  pipe_tx_12_sigs(78) <= \<const0>\;
  pipe_tx_12_sigs(77) <= \<const0>\;
  pipe_tx_12_sigs(76) <= \<const0>\;
  pipe_tx_12_sigs(75) <= \<const0>\;
  pipe_tx_12_sigs(74) <= \<const0>\;
  pipe_tx_12_sigs(73) <= \<const0>\;
  pipe_tx_12_sigs(72) <= \<const0>\;
  pipe_tx_12_sigs(71) <= \<const0>\;
  pipe_tx_12_sigs(70) <= \<const0>\;
  pipe_tx_12_sigs(69) <= \<const0>\;
  pipe_tx_12_sigs(68) <= \<const0>\;
  pipe_tx_12_sigs(67) <= \<const0>\;
  pipe_tx_12_sigs(66) <= \<const0>\;
  pipe_tx_12_sigs(65) <= \<const0>\;
  pipe_tx_12_sigs(64) <= \<const0>\;
  pipe_tx_12_sigs(63) <= \<const0>\;
  pipe_tx_12_sigs(62) <= \<const0>\;
  pipe_tx_12_sigs(61) <= \<const0>\;
  pipe_tx_12_sigs(60) <= \<const0>\;
  pipe_tx_12_sigs(59) <= \<const0>\;
  pipe_tx_12_sigs(58) <= \<const0>\;
  pipe_tx_12_sigs(57) <= \<const0>\;
  pipe_tx_12_sigs(56) <= \<const0>\;
  pipe_tx_12_sigs(55) <= \<const0>\;
  pipe_tx_12_sigs(54) <= \<const0>\;
  pipe_tx_12_sigs(53) <= \<const0>\;
  pipe_tx_12_sigs(52) <= \<const0>\;
  pipe_tx_12_sigs(51) <= \<const0>\;
  pipe_tx_12_sigs(50) <= \<const0>\;
  pipe_tx_12_sigs(49) <= \<const0>\;
  pipe_tx_12_sigs(48) <= \<const0>\;
  pipe_tx_12_sigs(47) <= \<const0>\;
  pipe_tx_12_sigs(46) <= \<const0>\;
  pipe_tx_12_sigs(45) <= \<const0>\;
  pipe_tx_12_sigs(44) <= \<const0>\;
  pipe_tx_12_sigs(43) <= \<const0>\;
  pipe_tx_12_sigs(42) <= \<const0>\;
  pipe_tx_12_sigs(41) <= \<const0>\;
  pipe_tx_12_sigs(40) <= \<const0>\;
  pipe_tx_12_sigs(39) <= \<const0>\;
  pipe_tx_12_sigs(38) <= \<const0>\;
  pipe_tx_12_sigs(37) <= \<const0>\;
  pipe_tx_12_sigs(36) <= \<const0>\;
  pipe_tx_12_sigs(35) <= \<const0>\;
  pipe_tx_12_sigs(34) <= \<const0>\;
  pipe_tx_12_sigs(33) <= \<const0>\;
  pipe_tx_12_sigs(32) <= \<const0>\;
  pipe_tx_12_sigs(31) <= \<const0>\;
  pipe_tx_12_sigs(30) <= \<const0>\;
  pipe_tx_12_sigs(29) <= \<const0>\;
  pipe_tx_12_sigs(28) <= \<const0>\;
  pipe_tx_12_sigs(27) <= \<const0>\;
  pipe_tx_12_sigs(26) <= \<const0>\;
  pipe_tx_12_sigs(25) <= \<const0>\;
  pipe_tx_12_sigs(24) <= \<const0>\;
  pipe_tx_12_sigs(23) <= \<const0>\;
  pipe_tx_12_sigs(22) <= \<const0>\;
  pipe_tx_12_sigs(21) <= \<const0>\;
  pipe_tx_12_sigs(20) <= \<const0>\;
  pipe_tx_12_sigs(19) <= \<const0>\;
  pipe_tx_12_sigs(18) <= \<const0>\;
  pipe_tx_12_sigs(17) <= \<const0>\;
  pipe_tx_12_sigs(16) <= \<const0>\;
  pipe_tx_12_sigs(15) <= \<const0>\;
  pipe_tx_12_sigs(14) <= \<const0>\;
  pipe_tx_12_sigs(13) <= \<const0>\;
  pipe_tx_12_sigs(12) <= \<const0>\;
  pipe_tx_12_sigs(11) <= \<const0>\;
  pipe_tx_12_sigs(10) <= \<const0>\;
  pipe_tx_12_sigs(9) <= \<const0>\;
  pipe_tx_12_sigs(8) <= \<const0>\;
  pipe_tx_12_sigs(7) <= \<const0>\;
  pipe_tx_12_sigs(6) <= \<const0>\;
  pipe_tx_12_sigs(5) <= \<const0>\;
  pipe_tx_12_sigs(4) <= \<const0>\;
  pipe_tx_12_sigs(3) <= \<const0>\;
  pipe_tx_12_sigs(2) <= \<const0>\;
  pipe_tx_12_sigs(1) <= \<const0>\;
  pipe_tx_12_sigs(0) <= \<const0>\;
  pipe_tx_13_sigs(83) <= \<const0>\;
  pipe_tx_13_sigs(82) <= \<const0>\;
  pipe_tx_13_sigs(81) <= \<const0>\;
  pipe_tx_13_sigs(80) <= \<const0>\;
  pipe_tx_13_sigs(79) <= \<const0>\;
  pipe_tx_13_sigs(78) <= \<const0>\;
  pipe_tx_13_sigs(77) <= \<const0>\;
  pipe_tx_13_sigs(76) <= \<const0>\;
  pipe_tx_13_sigs(75) <= \<const0>\;
  pipe_tx_13_sigs(74) <= \<const0>\;
  pipe_tx_13_sigs(73) <= \<const0>\;
  pipe_tx_13_sigs(72) <= \<const0>\;
  pipe_tx_13_sigs(71) <= \<const0>\;
  pipe_tx_13_sigs(70) <= \<const0>\;
  pipe_tx_13_sigs(69) <= \<const0>\;
  pipe_tx_13_sigs(68) <= \<const0>\;
  pipe_tx_13_sigs(67) <= \<const0>\;
  pipe_tx_13_sigs(66) <= \<const0>\;
  pipe_tx_13_sigs(65) <= \<const0>\;
  pipe_tx_13_sigs(64) <= \<const0>\;
  pipe_tx_13_sigs(63) <= \<const0>\;
  pipe_tx_13_sigs(62) <= \<const0>\;
  pipe_tx_13_sigs(61) <= \<const0>\;
  pipe_tx_13_sigs(60) <= \<const0>\;
  pipe_tx_13_sigs(59) <= \<const0>\;
  pipe_tx_13_sigs(58) <= \<const0>\;
  pipe_tx_13_sigs(57) <= \<const0>\;
  pipe_tx_13_sigs(56) <= \<const0>\;
  pipe_tx_13_sigs(55) <= \<const0>\;
  pipe_tx_13_sigs(54) <= \<const0>\;
  pipe_tx_13_sigs(53) <= \<const0>\;
  pipe_tx_13_sigs(52) <= \<const0>\;
  pipe_tx_13_sigs(51) <= \<const0>\;
  pipe_tx_13_sigs(50) <= \<const0>\;
  pipe_tx_13_sigs(49) <= \<const0>\;
  pipe_tx_13_sigs(48) <= \<const0>\;
  pipe_tx_13_sigs(47) <= \<const0>\;
  pipe_tx_13_sigs(46) <= \<const0>\;
  pipe_tx_13_sigs(45) <= \<const0>\;
  pipe_tx_13_sigs(44) <= \<const0>\;
  pipe_tx_13_sigs(43) <= \<const0>\;
  pipe_tx_13_sigs(42) <= \<const0>\;
  pipe_tx_13_sigs(41) <= \<const0>\;
  pipe_tx_13_sigs(40) <= \<const0>\;
  pipe_tx_13_sigs(39) <= \<const0>\;
  pipe_tx_13_sigs(38) <= \<const0>\;
  pipe_tx_13_sigs(37) <= \<const0>\;
  pipe_tx_13_sigs(36) <= \<const0>\;
  pipe_tx_13_sigs(35) <= \<const0>\;
  pipe_tx_13_sigs(34) <= \<const0>\;
  pipe_tx_13_sigs(33) <= \<const0>\;
  pipe_tx_13_sigs(32) <= \<const0>\;
  pipe_tx_13_sigs(31) <= \<const0>\;
  pipe_tx_13_sigs(30) <= \<const0>\;
  pipe_tx_13_sigs(29) <= \<const0>\;
  pipe_tx_13_sigs(28) <= \<const0>\;
  pipe_tx_13_sigs(27) <= \<const0>\;
  pipe_tx_13_sigs(26) <= \<const0>\;
  pipe_tx_13_sigs(25) <= \<const0>\;
  pipe_tx_13_sigs(24) <= \<const0>\;
  pipe_tx_13_sigs(23) <= \<const0>\;
  pipe_tx_13_sigs(22) <= \<const0>\;
  pipe_tx_13_sigs(21) <= \<const0>\;
  pipe_tx_13_sigs(20) <= \<const0>\;
  pipe_tx_13_sigs(19) <= \<const0>\;
  pipe_tx_13_sigs(18) <= \<const0>\;
  pipe_tx_13_sigs(17) <= \<const0>\;
  pipe_tx_13_sigs(16) <= \<const0>\;
  pipe_tx_13_sigs(15) <= \<const0>\;
  pipe_tx_13_sigs(14) <= \<const0>\;
  pipe_tx_13_sigs(13) <= \<const0>\;
  pipe_tx_13_sigs(12) <= \<const0>\;
  pipe_tx_13_sigs(11) <= \<const0>\;
  pipe_tx_13_sigs(10) <= \<const0>\;
  pipe_tx_13_sigs(9) <= \<const0>\;
  pipe_tx_13_sigs(8) <= \<const0>\;
  pipe_tx_13_sigs(7) <= \<const0>\;
  pipe_tx_13_sigs(6) <= \<const0>\;
  pipe_tx_13_sigs(5) <= \<const0>\;
  pipe_tx_13_sigs(4) <= \<const0>\;
  pipe_tx_13_sigs(3) <= \<const0>\;
  pipe_tx_13_sigs(2) <= \<const0>\;
  pipe_tx_13_sigs(1) <= \<const0>\;
  pipe_tx_13_sigs(0) <= \<const0>\;
  pipe_tx_14_sigs(83) <= \<const0>\;
  pipe_tx_14_sigs(82) <= \<const0>\;
  pipe_tx_14_sigs(81) <= \<const0>\;
  pipe_tx_14_sigs(80) <= \<const0>\;
  pipe_tx_14_sigs(79) <= \<const0>\;
  pipe_tx_14_sigs(78) <= \<const0>\;
  pipe_tx_14_sigs(77) <= \<const0>\;
  pipe_tx_14_sigs(76) <= \<const0>\;
  pipe_tx_14_sigs(75) <= \<const0>\;
  pipe_tx_14_sigs(74) <= \<const0>\;
  pipe_tx_14_sigs(73) <= \<const0>\;
  pipe_tx_14_sigs(72) <= \<const0>\;
  pipe_tx_14_sigs(71) <= \<const0>\;
  pipe_tx_14_sigs(70) <= \<const0>\;
  pipe_tx_14_sigs(69) <= \<const0>\;
  pipe_tx_14_sigs(68) <= \<const0>\;
  pipe_tx_14_sigs(67) <= \<const0>\;
  pipe_tx_14_sigs(66) <= \<const0>\;
  pipe_tx_14_sigs(65) <= \<const0>\;
  pipe_tx_14_sigs(64) <= \<const0>\;
  pipe_tx_14_sigs(63) <= \<const0>\;
  pipe_tx_14_sigs(62) <= \<const0>\;
  pipe_tx_14_sigs(61) <= \<const0>\;
  pipe_tx_14_sigs(60) <= \<const0>\;
  pipe_tx_14_sigs(59) <= \<const0>\;
  pipe_tx_14_sigs(58) <= \<const0>\;
  pipe_tx_14_sigs(57) <= \<const0>\;
  pipe_tx_14_sigs(56) <= \<const0>\;
  pipe_tx_14_sigs(55) <= \<const0>\;
  pipe_tx_14_sigs(54) <= \<const0>\;
  pipe_tx_14_sigs(53) <= \<const0>\;
  pipe_tx_14_sigs(52) <= \<const0>\;
  pipe_tx_14_sigs(51) <= \<const0>\;
  pipe_tx_14_sigs(50) <= \<const0>\;
  pipe_tx_14_sigs(49) <= \<const0>\;
  pipe_tx_14_sigs(48) <= \<const0>\;
  pipe_tx_14_sigs(47) <= \<const0>\;
  pipe_tx_14_sigs(46) <= \<const0>\;
  pipe_tx_14_sigs(45) <= \<const0>\;
  pipe_tx_14_sigs(44) <= \<const0>\;
  pipe_tx_14_sigs(43) <= \<const0>\;
  pipe_tx_14_sigs(42) <= \<const0>\;
  pipe_tx_14_sigs(41) <= \<const0>\;
  pipe_tx_14_sigs(40) <= \<const0>\;
  pipe_tx_14_sigs(39) <= \<const0>\;
  pipe_tx_14_sigs(38) <= \<const0>\;
  pipe_tx_14_sigs(37) <= \<const0>\;
  pipe_tx_14_sigs(36) <= \<const0>\;
  pipe_tx_14_sigs(35) <= \<const0>\;
  pipe_tx_14_sigs(34) <= \<const0>\;
  pipe_tx_14_sigs(33) <= \<const0>\;
  pipe_tx_14_sigs(32) <= \<const0>\;
  pipe_tx_14_sigs(31) <= \<const0>\;
  pipe_tx_14_sigs(30) <= \<const0>\;
  pipe_tx_14_sigs(29) <= \<const0>\;
  pipe_tx_14_sigs(28) <= \<const0>\;
  pipe_tx_14_sigs(27) <= \<const0>\;
  pipe_tx_14_sigs(26) <= \<const0>\;
  pipe_tx_14_sigs(25) <= \<const0>\;
  pipe_tx_14_sigs(24) <= \<const0>\;
  pipe_tx_14_sigs(23) <= \<const0>\;
  pipe_tx_14_sigs(22) <= \<const0>\;
  pipe_tx_14_sigs(21) <= \<const0>\;
  pipe_tx_14_sigs(20) <= \<const0>\;
  pipe_tx_14_sigs(19) <= \<const0>\;
  pipe_tx_14_sigs(18) <= \<const0>\;
  pipe_tx_14_sigs(17) <= \<const0>\;
  pipe_tx_14_sigs(16) <= \<const0>\;
  pipe_tx_14_sigs(15) <= \<const0>\;
  pipe_tx_14_sigs(14) <= \<const0>\;
  pipe_tx_14_sigs(13) <= \<const0>\;
  pipe_tx_14_sigs(12) <= \<const0>\;
  pipe_tx_14_sigs(11) <= \<const0>\;
  pipe_tx_14_sigs(10) <= \<const0>\;
  pipe_tx_14_sigs(9) <= \<const0>\;
  pipe_tx_14_sigs(8) <= \<const0>\;
  pipe_tx_14_sigs(7) <= \<const0>\;
  pipe_tx_14_sigs(6) <= \<const0>\;
  pipe_tx_14_sigs(5) <= \<const0>\;
  pipe_tx_14_sigs(4) <= \<const0>\;
  pipe_tx_14_sigs(3) <= \<const0>\;
  pipe_tx_14_sigs(2) <= \<const0>\;
  pipe_tx_14_sigs(1) <= \<const0>\;
  pipe_tx_14_sigs(0) <= \<const0>\;
  pipe_tx_15_sigs(83) <= \<const0>\;
  pipe_tx_15_sigs(82) <= \<const0>\;
  pipe_tx_15_sigs(81) <= \<const0>\;
  pipe_tx_15_sigs(80) <= \<const0>\;
  pipe_tx_15_sigs(79) <= \<const0>\;
  pipe_tx_15_sigs(78) <= \<const0>\;
  pipe_tx_15_sigs(77) <= \<const0>\;
  pipe_tx_15_sigs(76) <= \<const0>\;
  pipe_tx_15_sigs(75) <= \<const0>\;
  pipe_tx_15_sigs(74) <= \<const0>\;
  pipe_tx_15_sigs(73) <= \<const0>\;
  pipe_tx_15_sigs(72) <= \<const0>\;
  pipe_tx_15_sigs(71) <= \<const0>\;
  pipe_tx_15_sigs(70) <= \<const0>\;
  pipe_tx_15_sigs(69) <= \<const0>\;
  pipe_tx_15_sigs(68) <= \<const0>\;
  pipe_tx_15_sigs(67) <= \<const0>\;
  pipe_tx_15_sigs(66) <= \<const0>\;
  pipe_tx_15_sigs(65) <= \<const0>\;
  pipe_tx_15_sigs(64) <= \<const0>\;
  pipe_tx_15_sigs(63) <= \<const0>\;
  pipe_tx_15_sigs(62) <= \<const0>\;
  pipe_tx_15_sigs(61) <= \<const0>\;
  pipe_tx_15_sigs(60) <= \<const0>\;
  pipe_tx_15_sigs(59) <= \<const0>\;
  pipe_tx_15_sigs(58) <= \<const0>\;
  pipe_tx_15_sigs(57) <= \<const0>\;
  pipe_tx_15_sigs(56) <= \<const0>\;
  pipe_tx_15_sigs(55) <= \<const0>\;
  pipe_tx_15_sigs(54) <= \<const0>\;
  pipe_tx_15_sigs(53) <= \<const0>\;
  pipe_tx_15_sigs(52) <= \<const0>\;
  pipe_tx_15_sigs(51) <= \<const0>\;
  pipe_tx_15_sigs(50) <= \<const0>\;
  pipe_tx_15_sigs(49) <= \<const0>\;
  pipe_tx_15_sigs(48) <= \<const0>\;
  pipe_tx_15_sigs(47) <= \<const0>\;
  pipe_tx_15_sigs(46) <= \<const0>\;
  pipe_tx_15_sigs(45) <= \<const0>\;
  pipe_tx_15_sigs(44) <= \<const0>\;
  pipe_tx_15_sigs(43) <= \<const0>\;
  pipe_tx_15_sigs(42) <= \<const0>\;
  pipe_tx_15_sigs(41) <= \<const0>\;
  pipe_tx_15_sigs(40) <= \<const0>\;
  pipe_tx_15_sigs(39) <= \<const0>\;
  pipe_tx_15_sigs(38) <= \<const0>\;
  pipe_tx_15_sigs(37) <= \<const0>\;
  pipe_tx_15_sigs(36) <= \<const0>\;
  pipe_tx_15_sigs(35) <= \<const0>\;
  pipe_tx_15_sigs(34) <= \<const0>\;
  pipe_tx_15_sigs(33) <= \<const0>\;
  pipe_tx_15_sigs(32) <= \<const0>\;
  pipe_tx_15_sigs(31) <= \<const0>\;
  pipe_tx_15_sigs(30) <= \<const0>\;
  pipe_tx_15_sigs(29) <= \<const0>\;
  pipe_tx_15_sigs(28) <= \<const0>\;
  pipe_tx_15_sigs(27) <= \<const0>\;
  pipe_tx_15_sigs(26) <= \<const0>\;
  pipe_tx_15_sigs(25) <= \<const0>\;
  pipe_tx_15_sigs(24) <= \<const0>\;
  pipe_tx_15_sigs(23) <= \<const0>\;
  pipe_tx_15_sigs(22) <= \<const0>\;
  pipe_tx_15_sigs(21) <= \<const0>\;
  pipe_tx_15_sigs(20) <= \<const0>\;
  pipe_tx_15_sigs(19) <= \<const0>\;
  pipe_tx_15_sigs(18) <= \<const0>\;
  pipe_tx_15_sigs(17) <= \<const0>\;
  pipe_tx_15_sigs(16) <= \<const0>\;
  pipe_tx_15_sigs(15) <= \<const0>\;
  pipe_tx_15_sigs(14) <= \<const0>\;
  pipe_tx_15_sigs(13) <= \<const0>\;
  pipe_tx_15_sigs(12) <= \<const0>\;
  pipe_tx_15_sigs(11) <= \<const0>\;
  pipe_tx_15_sigs(10) <= \<const0>\;
  pipe_tx_15_sigs(9) <= \<const0>\;
  pipe_tx_15_sigs(8) <= \<const0>\;
  pipe_tx_15_sigs(7) <= \<const0>\;
  pipe_tx_15_sigs(6) <= \<const0>\;
  pipe_tx_15_sigs(5) <= \<const0>\;
  pipe_tx_15_sigs(4) <= \<const0>\;
  pipe_tx_15_sigs(3) <= \<const0>\;
  pipe_tx_15_sigs(2) <= \<const0>\;
  pipe_tx_15_sigs(1) <= \<const0>\;
  pipe_tx_15_sigs(0) <= \<const0>\;
  pipe_tx_1_sigs(83) <= \<const0>\;
  pipe_tx_1_sigs(82) <= \<const0>\;
  pipe_tx_1_sigs(81) <= \<const0>\;
  pipe_tx_1_sigs(80) <= \<const0>\;
  pipe_tx_1_sigs(79) <= \<const0>\;
  pipe_tx_1_sigs(78) <= \<const0>\;
  pipe_tx_1_sigs(77) <= \<const0>\;
  pipe_tx_1_sigs(76) <= \<const0>\;
  pipe_tx_1_sigs(75) <= \<const0>\;
  pipe_tx_1_sigs(74) <= \<const0>\;
  pipe_tx_1_sigs(73) <= \<const0>\;
  pipe_tx_1_sigs(72) <= \<const0>\;
  pipe_tx_1_sigs(71) <= \<const0>\;
  pipe_tx_1_sigs(70) <= \<const0>\;
  pipe_tx_1_sigs(69) <= \<const0>\;
  pipe_tx_1_sigs(68) <= \<const0>\;
  pipe_tx_1_sigs(67) <= \<const0>\;
  pipe_tx_1_sigs(66) <= \<const0>\;
  pipe_tx_1_sigs(65) <= \<const0>\;
  pipe_tx_1_sigs(64) <= \<const0>\;
  pipe_tx_1_sigs(63) <= \<const0>\;
  pipe_tx_1_sigs(62) <= \<const0>\;
  pipe_tx_1_sigs(61) <= \<const0>\;
  pipe_tx_1_sigs(60) <= \<const0>\;
  pipe_tx_1_sigs(59) <= \<const0>\;
  pipe_tx_1_sigs(58) <= \<const0>\;
  pipe_tx_1_sigs(57) <= \<const0>\;
  pipe_tx_1_sigs(56) <= \<const0>\;
  pipe_tx_1_sigs(55) <= \<const0>\;
  pipe_tx_1_sigs(54) <= \<const0>\;
  pipe_tx_1_sigs(53) <= \<const0>\;
  pipe_tx_1_sigs(52) <= \<const0>\;
  pipe_tx_1_sigs(51) <= \<const0>\;
  pipe_tx_1_sigs(50) <= \<const0>\;
  pipe_tx_1_sigs(49) <= \<const0>\;
  pipe_tx_1_sigs(48) <= \<const0>\;
  pipe_tx_1_sigs(47) <= \<const0>\;
  pipe_tx_1_sigs(46) <= \<const0>\;
  pipe_tx_1_sigs(45) <= \<const0>\;
  pipe_tx_1_sigs(44) <= \<const0>\;
  pipe_tx_1_sigs(43) <= \<const0>\;
  pipe_tx_1_sigs(42) <= \<const0>\;
  pipe_tx_1_sigs(41) <= \<const0>\;
  pipe_tx_1_sigs(40) <= \<const0>\;
  pipe_tx_1_sigs(39) <= \<const0>\;
  pipe_tx_1_sigs(38) <= \<const0>\;
  pipe_tx_1_sigs(37) <= \<const0>\;
  pipe_tx_1_sigs(36) <= \<const0>\;
  pipe_tx_1_sigs(35) <= \<const0>\;
  pipe_tx_1_sigs(34) <= \<const0>\;
  pipe_tx_1_sigs(33) <= \<const0>\;
  pipe_tx_1_sigs(32) <= \<const0>\;
  pipe_tx_1_sigs(31) <= \<const0>\;
  pipe_tx_1_sigs(30) <= \<const0>\;
  pipe_tx_1_sigs(29) <= \<const0>\;
  pipe_tx_1_sigs(28) <= \<const0>\;
  pipe_tx_1_sigs(27) <= \<const0>\;
  pipe_tx_1_sigs(26) <= \<const0>\;
  pipe_tx_1_sigs(25) <= \<const0>\;
  pipe_tx_1_sigs(24) <= \<const0>\;
  pipe_tx_1_sigs(23) <= \<const0>\;
  pipe_tx_1_sigs(22) <= \<const0>\;
  pipe_tx_1_sigs(21) <= \<const0>\;
  pipe_tx_1_sigs(20) <= \<const0>\;
  pipe_tx_1_sigs(19) <= \<const0>\;
  pipe_tx_1_sigs(18) <= \<const0>\;
  pipe_tx_1_sigs(17) <= \<const0>\;
  pipe_tx_1_sigs(16) <= \<const0>\;
  pipe_tx_1_sigs(15) <= \<const0>\;
  pipe_tx_1_sigs(14) <= \<const0>\;
  pipe_tx_1_sigs(13) <= \<const0>\;
  pipe_tx_1_sigs(12) <= \<const0>\;
  pipe_tx_1_sigs(11) <= \<const0>\;
  pipe_tx_1_sigs(10) <= \<const0>\;
  pipe_tx_1_sigs(9) <= \<const0>\;
  pipe_tx_1_sigs(8) <= \<const0>\;
  pipe_tx_1_sigs(7) <= \<const0>\;
  pipe_tx_1_sigs(6) <= \<const0>\;
  pipe_tx_1_sigs(5) <= \<const0>\;
  pipe_tx_1_sigs(4) <= \<const0>\;
  pipe_tx_1_sigs(3) <= \<const0>\;
  pipe_tx_1_sigs(2) <= \<const0>\;
  pipe_tx_1_sigs(1) <= \<const0>\;
  pipe_tx_1_sigs(0) <= \<const0>\;
  pipe_tx_2_sigs(83) <= \<const0>\;
  pipe_tx_2_sigs(82) <= \<const0>\;
  pipe_tx_2_sigs(81) <= \<const0>\;
  pipe_tx_2_sigs(80) <= \<const0>\;
  pipe_tx_2_sigs(79) <= \<const0>\;
  pipe_tx_2_sigs(78) <= \<const0>\;
  pipe_tx_2_sigs(77) <= \<const0>\;
  pipe_tx_2_sigs(76) <= \<const0>\;
  pipe_tx_2_sigs(75) <= \<const0>\;
  pipe_tx_2_sigs(74) <= \<const0>\;
  pipe_tx_2_sigs(73) <= \<const0>\;
  pipe_tx_2_sigs(72) <= \<const0>\;
  pipe_tx_2_sigs(71) <= \<const0>\;
  pipe_tx_2_sigs(70) <= \<const0>\;
  pipe_tx_2_sigs(69) <= \<const0>\;
  pipe_tx_2_sigs(68) <= \<const0>\;
  pipe_tx_2_sigs(67) <= \<const0>\;
  pipe_tx_2_sigs(66) <= \<const0>\;
  pipe_tx_2_sigs(65) <= \<const0>\;
  pipe_tx_2_sigs(64) <= \<const0>\;
  pipe_tx_2_sigs(63) <= \<const0>\;
  pipe_tx_2_sigs(62) <= \<const0>\;
  pipe_tx_2_sigs(61) <= \<const0>\;
  pipe_tx_2_sigs(60) <= \<const0>\;
  pipe_tx_2_sigs(59) <= \<const0>\;
  pipe_tx_2_sigs(58) <= \<const0>\;
  pipe_tx_2_sigs(57) <= \<const0>\;
  pipe_tx_2_sigs(56) <= \<const0>\;
  pipe_tx_2_sigs(55) <= \<const0>\;
  pipe_tx_2_sigs(54) <= \<const0>\;
  pipe_tx_2_sigs(53) <= \<const0>\;
  pipe_tx_2_sigs(52) <= \<const0>\;
  pipe_tx_2_sigs(51) <= \<const0>\;
  pipe_tx_2_sigs(50) <= \<const0>\;
  pipe_tx_2_sigs(49) <= \<const0>\;
  pipe_tx_2_sigs(48) <= \<const0>\;
  pipe_tx_2_sigs(47) <= \<const0>\;
  pipe_tx_2_sigs(46) <= \<const0>\;
  pipe_tx_2_sigs(45) <= \<const0>\;
  pipe_tx_2_sigs(44) <= \<const0>\;
  pipe_tx_2_sigs(43) <= \<const0>\;
  pipe_tx_2_sigs(42) <= \<const0>\;
  pipe_tx_2_sigs(41) <= \<const0>\;
  pipe_tx_2_sigs(40) <= \<const0>\;
  pipe_tx_2_sigs(39) <= \<const0>\;
  pipe_tx_2_sigs(38) <= \<const0>\;
  pipe_tx_2_sigs(37) <= \<const0>\;
  pipe_tx_2_sigs(36) <= \<const0>\;
  pipe_tx_2_sigs(35) <= \<const0>\;
  pipe_tx_2_sigs(34) <= \<const0>\;
  pipe_tx_2_sigs(33) <= \<const0>\;
  pipe_tx_2_sigs(32) <= \<const0>\;
  pipe_tx_2_sigs(31) <= \<const0>\;
  pipe_tx_2_sigs(30) <= \<const0>\;
  pipe_tx_2_sigs(29) <= \<const0>\;
  pipe_tx_2_sigs(28) <= \<const0>\;
  pipe_tx_2_sigs(27) <= \<const0>\;
  pipe_tx_2_sigs(26) <= \<const0>\;
  pipe_tx_2_sigs(25) <= \<const0>\;
  pipe_tx_2_sigs(24) <= \<const0>\;
  pipe_tx_2_sigs(23) <= \<const0>\;
  pipe_tx_2_sigs(22) <= \<const0>\;
  pipe_tx_2_sigs(21) <= \<const0>\;
  pipe_tx_2_sigs(20) <= \<const0>\;
  pipe_tx_2_sigs(19) <= \<const0>\;
  pipe_tx_2_sigs(18) <= \<const0>\;
  pipe_tx_2_sigs(17) <= \<const0>\;
  pipe_tx_2_sigs(16) <= \<const0>\;
  pipe_tx_2_sigs(15) <= \<const0>\;
  pipe_tx_2_sigs(14) <= \<const0>\;
  pipe_tx_2_sigs(13) <= \<const0>\;
  pipe_tx_2_sigs(12) <= \<const0>\;
  pipe_tx_2_sigs(11) <= \<const0>\;
  pipe_tx_2_sigs(10) <= \<const0>\;
  pipe_tx_2_sigs(9) <= \<const0>\;
  pipe_tx_2_sigs(8) <= \<const0>\;
  pipe_tx_2_sigs(7) <= \<const0>\;
  pipe_tx_2_sigs(6) <= \<const0>\;
  pipe_tx_2_sigs(5) <= \<const0>\;
  pipe_tx_2_sigs(4) <= \<const0>\;
  pipe_tx_2_sigs(3) <= \<const0>\;
  pipe_tx_2_sigs(2) <= \<const0>\;
  pipe_tx_2_sigs(1) <= \<const0>\;
  pipe_tx_2_sigs(0) <= \<const0>\;
  pipe_tx_3_sigs(83) <= \<const0>\;
  pipe_tx_3_sigs(82) <= \<const0>\;
  pipe_tx_3_sigs(81) <= \<const0>\;
  pipe_tx_3_sigs(80) <= \<const0>\;
  pipe_tx_3_sigs(79) <= \<const0>\;
  pipe_tx_3_sigs(78) <= \<const0>\;
  pipe_tx_3_sigs(77) <= \<const0>\;
  pipe_tx_3_sigs(76) <= \<const0>\;
  pipe_tx_3_sigs(75) <= \<const0>\;
  pipe_tx_3_sigs(74) <= \<const0>\;
  pipe_tx_3_sigs(73) <= \<const0>\;
  pipe_tx_3_sigs(72) <= \<const0>\;
  pipe_tx_3_sigs(71) <= \<const0>\;
  pipe_tx_3_sigs(70) <= \<const0>\;
  pipe_tx_3_sigs(69) <= \<const0>\;
  pipe_tx_3_sigs(68) <= \<const0>\;
  pipe_tx_3_sigs(67) <= \<const0>\;
  pipe_tx_3_sigs(66) <= \<const0>\;
  pipe_tx_3_sigs(65) <= \<const0>\;
  pipe_tx_3_sigs(64) <= \<const0>\;
  pipe_tx_3_sigs(63) <= \<const0>\;
  pipe_tx_3_sigs(62) <= \<const0>\;
  pipe_tx_3_sigs(61) <= \<const0>\;
  pipe_tx_3_sigs(60) <= \<const0>\;
  pipe_tx_3_sigs(59) <= \<const0>\;
  pipe_tx_3_sigs(58) <= \<const0>\;
  pipe_tx_3_sigs(57) <= \<const0>\;
  pipe_tx_3_sigs(56) <= \<const0>\;
  pipe_tx_3_sigs(55) <= \<const0>\;
  pipe_tx_3_sigs(54) <= \<const0>\;
  pipe_tx_3_sigs(53) <= \<const0>\;
  pipe_tx_3_sigs(52) <= \<const0>\;
  pipe_tx_3_sigs(51) <= \<const0>\;
  pipe_tx_3_sigs(50) <= \<const0>\;
  pipe_tx_3_sigs(49) <= \<const0>\;
  pipe_tx_3_sigs(48) <= \<const0>\;
  pipe_tx_3_sigs(47) <= \<const0>\;
  pipe_tx_3_sigs(46) <= \<const0>\;
  pipe_tx_3_sigs(45) <= \<const0>\;
  pipe_tx_3_sigs(44) <= \<const0>\;
  pipe_tx_3_sigs(43) <= \<const0>\;
  pipe_tx_3_sigs(42) <= \<const0>\;
  pipe_tx_3_sigs(41) <= \<const0>\;
  pipe_tx_3_sigs(40) <= \<const0>\;
  pipe_tx_3_sigs(39) <= \<const0>\;
  pipe_tx_3_sigs(38) <= \<const0>\;
  pipe_tx_3_sigs(37) <= \<const0>\;
  pipe_tx_3_sigs(36) <= \<const0>\;
  pipe_tx_3_sigs(35) <= \<const0>\;
  pipe_tx_3_sigs(34) <= \<const0>\;
  pipe_tx_3_sigs(33) <= \<const0>\;
  pipe_tx_3_sigs(32) <= \<const0>\;
  pipe_tx_3_sigs(31) <= \<const0>\;
  pipe_tx_3_sigs(30) <= \<const0>\;
  pipe_tx_3_sigs(29) <= \<const0>\;
  pipe_tx_3_sigs(28) <= \<const0>\;
  pipe_tx_3_sigs(27) <= \<const0>\;
  pipe_tx_3_sigs(26) <= \<const0>\;
  pipe_tx_3_sigs(25) <= \<const0>\;
  pipe_tx_3_sigs(24) <= \<const0>\;
  pipe_tx_3_sigs(23) <= \<const0>\;
  pipe_tx_3_sigs(22) <= \<const0>\;
  pipe_tx_3_sigs(21) <= \<const0>\;
  pipe_tx_3_sigs(20) <= \<const0>\;
  pipe_tx_3_sigs(19) <= \<const0>\;
  pipe_tx_3_sigs(18) <= \<const0>\;
  pipe_tx_3_sigs(17) <= \<const0>\;
  pipe_tx_3_sigs(16) <= \<const0>\;
  pipe_tx_3_sigs(15) <= \<const0>\;
  pipe_tx_3_sigs(14) <= \<const0>\;
  pipe_tx_3_sigs(13) <= \<const0>\;
  pipe_tx_3_sigs(12) <= \<const0>\;
  pipe_tx_3_sigs(11) <= \<const0>\;
  pipe_tx_3_sigs(10) <= \<const0>\;
  pipe_tx_3_sigs(9) <= \<const0>\;
  pipe_tx_3_sigs(8) <= \<const0>\;
  pipe_tx_3_sigs(7) <= \<const0>\;
  pipe_tx_3_sigs(6) <= \<const0>\;
  pipe_tx_3_sigs(5) <= \<const0>\;
  pipe_tx_3_sigs(4) <= \<const0>\;
  pipe_tx_3_sigs(3) <= \<const0>\;
  pipe_tx_3_sigs(2) <= \<const0>\;
  pipe_tx_3_sigs(1) <= \<const0>\;
  pipe_tx_3_sigs(0) <= \<const0>\;
  pipe_tx_4_sigs(83) <= \<const0>\;
  pipe_tx_4_sigs(82) <= \<const0>\;
  pipe_tx_4_sigs(81) <= \<const0>\;
  pipe_tx_4_sigs(80) <= \<const0>\;
  pipe_tx_4_sigs(79) <= \<const0>\;
  pipe_tx_4_sigs(78) <= \<const0>\;
  pipe_tx_4_sigs(77) <= \<const0>\;
  pipe_tx_4_sigs(76) <= \<const0>\;
  pipe_tx_4_sigs(75) <= \<const0>\;
  pipe_tx_4_sigs(74) <= \<const0>\;
  pipe_tx_4_sigs(73) <= \<const0>\;
  pipe_tx_4_sigs(72) <= \<const0>\;
  pipe_tx_4_sigs(71) <= \<const0>\;
  pipe_tx_4_sigs(70) <= \<const0>\;
  pipe_tx_4_sigs(69) <= \<const0>\;
  pipe_tx_4_sigs(68) <= \<const0>\;
  pipe_tx_4_sigs(67) <= \<const0>\;
  pipe_tx_4_sigs(66) <= \<const0>\;
  pipe_tx_4_sigs(65) <= \<const0>\;
  pipe_tx_4_sigs(64) <= \<const0>\;
  pipe_tx_4_sigs(63) <= \<const0>\;
  pipe_tx_4_sigs(62) <= \<const0>\;
  pipe_tx_4_sigs(61) <= \<const0>\;
  pipe_tx_4_sigs(60) <= \<const0>\;
  pipe_tx_4_sigs(59) <= \<const0>\;
  pipe_tx_4_sigs(58) <= \<const0>\;
  pipe_tx_4_sigs(57) <= \<const0>\;
  pipe_tx_4_sigs(56) <= \<const0>\;
  pipe_tx_4_sigs(55) <= \<const0>\;
  pipe_tx_4_sigs(54) <= \<const0>\;
  pipe_tx_4_sigs(53) <= \<const0>\;
  pipe_tx_4_sigs(52) <= \<const0>\;
  pipe_tx_4_sigs(51) <= \<const0>\;
  pipe_tx_4_sigs(50) <= \<const0>\;
  pipe_tx_4_sigs(49) <= \<const0>\;
  pipe_tx_4_sigs(48) <= \<const0>\;
  pipe_tx_4_sigs(47) <= \<const0>\;
  pipe_tx_4_sigs(46) <= \<const0>\;
  pipe_tx_4_sigs(45) <= \<const0>\;
  pipe_tx_4_sigs(44) <= \<const0>\;
  pipe_tx_4_sigs(43) <= \<const0>\;
  pipe_tx_4_sigs(42) <= \<const0>\;
  pipe_tx_4_sigs(41) <= \<const0>\;
  pipe_tx_4_sigs(40) <= \<const0>\;
  pipe_tx_4_sigs(39) <= \<const0>\;
  pipe_tx_4_sigs(38) <= \<const0>\;
  pipe_tx_4_sigs(37) <= \<const0>\;
  pipe_tx_4_sigs(36) <= \<const0>\;
  pipe_tx_4_sigs(35) <= \<const0>\;
  pipe_tx_4_sigs(34) <= \<const0>\;
  pipe_tx_4_sigs(33) <= \<const0>\;
  pipe_tx_4_sigs(32) <= \<const0>\;
  pipe_tx_4_sigs(31) <= \<const0>\;
  pipe_tx_4_sigs(30) <= \<const0>\;
  pipe_tx_4_sigs(29) <= \<const0>\;
  pipe_tx_4_sigs(28) <= \<const0>\;
  pipe_tx_4_sigs(27) <= \<const0>\;
  pipe_tx_4_sigs(26) <= \<const0>\;
  pipe_tx_4_sigs(25) <= \<const0>\;
  pipe_tx_4_sigs(24) <= \<const0>\;
  pipe_tx_4_sigs(23) <= \<const0>\;
  pipe_tx_4_sigs(22) <= \<const0>\;
  pipe_tx_4_sigs(21) <= \<const0>\;
  pipe_tx_4_sigs(20) <= \<const0>\;
  pipe_tx_4_sigs(19) <= \<const0>\;
  pipe_tx_4_sigs(18) <= \<const0>\;
  pipe_tx_4_sigs(17) <= \<const0>\;
  pipe_tx_4_sigs(16) <= \<const0>\;
  pipe_tx_4_sigs(15) <= \<const0>\;
  pipe_tx_4_sigs(14) <= \<const0>\;
  pipe_tx_4_sigs(13) <= \<const0>\;
  pipe_tx_4_sigs(12) <= \<const0>\;
  pipe_tx_4_sigs(11) <= \<const0>\;
  pipe_tx_4_sigs(10) <= \<const0>\;
  pipe_tx_4_sigs(9) <= \<const0>\;
  pipe_tx_4_sigs(8) <= \<const0>\;
  pipe_tx_4_sigs(7) <= \<const0>\;
  pipe_tx_4_sigs(6) <= \<const0>\;
  pipe_tx_4_sigs(5) <= \<const0>\;
  pipe_tx_4_sigs(4) <= \<const0>\;
  pipe_tx_4_sigs(3) <= \<const0>\;
  pipe_tx_4_sigs(2) <= \<const0>\;
  pipe_tx_4_sigs(1) <= \<const0>\;
  pipe_tx_4_sigs(0) <= \<const0>\;
  pipe_tx_5_sigs(83) <= \<const0>\;
  pipe_tx_5_sigs(82) <= \<const0>\;
  pipe_tx_5_sigs(81) <= \<const0>\;
  pipe_tx_5_sigs(80) <= \<const0>\;
  pipe_tx_5_sigs(79) <= \<const0>\;
  pipe_tx_5_sigs(78) <= \<const0>\;
  pipe_tx_5_sigs(77) <= \<const0>\;
  pipe_tx_5_sigs(76) <= \<const0>\;
  pipe_tx_5_sigs(75) <= \<const0>\;
  pipe_tx_5_sigs(74) <= \<const0>\;
  pipe_tx_5_sigs(73) <= \<const0>\;
  pipe_tx_5_sigs(72) <= \<const0>\;
  pipe_tx_5_sigs(71) <= \<const0>\;
  pipe_tx_5_sigs(70) <= \<const0>\;
  pipe_tx_5_sigs(69) <= \<const0>\;
  pipe_tx_5_sigs(68) <= \<const0>\;
  pipe_tx_5_sigs(67) <= \<const0>\;
  pipe_tx_5_sigs(66) <= \<const0>\;
  pipe_tx_5_sigs(65) <= \<const0>\;
  pipe_tx_5_sigs(64) <= \<const0>\;
  pipe_tx_5_sigs(63) <= \<const0>\;
  pipe_tx_5_sigs(62) <= \<const0>\;
  pipe_tx_5_sigs(61) <= \<const0>\;
  pipe_tx_5_sigs(60) <= \<const0>\;
  pipe_tx_5_sigs(59) <= \<const0>\;
  pipe_tx_5_sigs(58) <= \<const0>\;
  pipe_tx_5_sigs(57) <= \<const0>\;
  pipe_tx_5_sigs(56) <= \<const0>\;
  pipe_tx_5_sigs(55) <= \<const0>\;
  pipe_tx_5_sigs(54) <= \<const0>\;
  pipe_tx_5_sigs(53) <= \<const0>\;
  pipe_tx_5_sigs(52) <= \<const0>\;
  pipe_tx_5_sigs(51) <= \<const0>\;
  pipe_tx_5_sigs(50) <= \<const0>\;
  pipe_tx_5_sigs(49) <= \<const0>\;
  pipe_tx_5_sigs(48) <= \<const0>\;
  pipe_tx_5_sigs(47) <= \<const0>\;
  pipe_tx_5_sigs(46) <= \<const0>\;
  pipe_tx_5_sigs(45) <= \<const0>\;
  pipe_tx_5_sigs(44) <= \<const0>\;
  pipe_tx_5_sigs(43) <= \<const0>\;
  pipe_tx_5_sigs(42) <= \<const0>\;
  pipe_tx_5_sigs(41) <= \<const0>\;
  pipe_tx_5_sigs(40) <= \<const0>\;
  pipe_tx_5_sigs(39) <= \<const0>\;
  pipe_tx_5_sigs(38) <= \<const0>\;
  pipe_tx_5_sigs(37) <= \<const0>\;
  pipe_tx_5_sigs(36) <= \<const0>\;
  pipe_tx_5_sigs(35) <= \<const0>\;
  pipe_tx_5_sigs(34) <= \<const0>\;
  pipe_tx_5_sigs(33) <= \<const0>\;
  pipe_tx_5_sigs(32) <= \<const0>\;
  pipe_tx_5_sigs(31) <= \<const0>\;
  pipe_tx_5_sigs(30) <= \<const0>\;
  pipe_tx_5_sigs(29) <= \<const0>\;
  pipe_tx_5_sigs(28) <= \<const0>\;
  pipe_tx_5_sigs(27) <= \<const0>\;
  pipe_tx_5_sigs(26) <= \<const0>\;
  pipe_tx_5_sigs(25) <= \<const0>\;
  pipe_tx_5_sigs(24) <= \<const0>\;
  pipe_tx_5_sigs(23) <= \<const0>\;
  pipe_tx_5_sigs(22) <= \<const0>\;
  pipe_tx_5_sigs(21) <= \<const0>\;
  pipe_tx_5_sigs(20) <= \<const0>\;
  pipe_tx_5_sigs(19) <= \<const0>\;
  pipe_tx_5_sigs(18) <= \<const0>\;
  pipe_tx_5_sigs(17) <= \<const0>\;
  pipe_tx_5_sigs(16) <= \<const0>\;
  pipe_tx_5_sigs(15) <= \<const0>\;
  pipe_tx_5_sigs(14) <= \<const0>\;
  pipe_tx_5_sigs(13) <= \<const0>\;
  pipe_tx_5_sigs(12) <= \<const0>\;
  pipe_tx_5_sigs(11) <= \<const0>\;
  pipe_tx_5_sigs(10) <= \<const0>\;
  pipe_tx_5_sigs(9) <= \<const0>\;
  pipe_tx_5_sigs(8) <= \<const0>\;
  pipe_tx_5_sigs(7) <= \<const0>\;
  pipe_tx_5_sigs(6) <= \<const0>\;
  pipe_tx_5_sigs(5) <= \<const0>\;
  pipe_tx_5_sigs(4) <= \<const0>\;
  pipe_tx_5_sigs(3) <= \<const0>\;
  pipe_tx_5_sigs(2) <= \<const0>\;
  pipe_tx_5_sigs(1) <= \<const0>\;
  pipe_tx_5_sigs(0) <= \<const0>\;
  pipe_tx_6_sigs(83) <= \<const0>\;
  pipe_tx_6_sigs(82) <= \<const0>\;
  pipe_tx_6_sigs(81) <= \<const0>\;
  pipe_tx_6_sigs(80) <= \<const0>\;
  pipe_tx_6_sigs(79) <= \<const0>\;
  pipe_tx_6_sigs(78) <= \<const0>\;
  pipe_tx_6_sigs(77) <= \<const0>\;
  pipe_tx_6_sigs(76) <= \<const0>\;
  pipe_tx_6_sigs(75) <= \<const0>\;
  pipe_tx_6_sigs(74) <= \<const0>\;
  pipe_tx_6_sigs(73) <= \<const0>\;
  pipe_tx_6_sigs(72) <= \<const0>\;
  pipe_tx_6_sigs(71) <= \<const0>\;
  pipe_tx_6_sigs(70) <= \<const0>\;
  pipe_tx_6_sigs(69) <= \<const0>\;
  pipe_tx_6_sigs(68) <= \<const0>\;
  pipe_tx_6_sigs(67) <= \<const0>\;
  pipe_tx_6_sigs(66) <= \<const0>\;
  pipe_tx_6_sigs(65) <= \<const0>\;
  pipe_tx_6_sigs(64) <= \<const0>\;
  pipe_tx_6_sigs(63) <= \<const0>\;
  pipe_tx_6_sigs(62) <= \<const0>\;
  pipe_tx_6_sigs(61) <= \<const0>\;
  pipe_tx_6_sigs(60) <= \<const0>\;
  pipe_tx_6_sigs(59) <= \<const0>\;
  pipe_tx_6_sigs(58) <= \<const0>\;
  pipe_tx_6_sigs(57) <= \<const0>\;
  pipe_tx_6_sigs(56) <= \<const0>\;
  pipe_tx_6_sigs(55) <= \<const0>\;
  pipe_tx_6_sigs(54) <= \<const0>\;
  pipe_tx_6_sigs(53) <= \<const0>\;
  pipe_tx_6_sigs(52) <= \<const0>\;
  pipe_tx_6_sigs(51) <= \<const0>\;
  pipe_tx_6_sigs(50) <= \<const0>\;
  pipe_tx_6_sigs(49) <= \<const0>\;
  pipe_tx_6_sigs(48) <= \<const0>\;
  pipe_tx_6_sigs(47) <= \<const0>\;
  pipe_tx_6_sigs(46) <= \<const0>\;
  pipe_tx_6_sigs(45) <= \<const0>\;
  pipe_tx_6_sigs(44) <= \<const0>\;
  pipe_tx_6_sigs(43) <= \<const0>\;
  pipe_tx_6_sigs(42) <= \<const0>\;
  pipe_tx_6_sigs(41) <= \<const0>\;
  pipe_tx_6_sigs(40) <= \<const0>\;
  pipe_tx_6_sigs(39) <= \<const0>\;
  pipe_tx_6_sigs(38) <= \<const0>\;
  pipe_tx_6_sigs(37) <= \<const0>\;
  pipe_tx_6_sigs(36) <= \<const0>\;
  pipe_tx_6_sigs(35) <= \<const0>\;
  pipe_tx_6_sigs(34) <= \<const0>\;
  pipe_tx_6_sigs(33) <= \<const0>\;
  pipe_tx_6_sigs(32) <= \<const0>\;
  pipe_tx_6_sigs(31) <= \<const0>\;
  pipe_tx_6_sigs(30) <= \<const0>\;
  pipe_tx_6_sigs(29) <= \<const0>\;
  pipe_tx_6_sigs(28) <= \<const0>\;
  pipe_tx_6_sigs(27) <= \<const0>\;
  pipe_tx_6_sigs(26) <= \<const0>\;
  pipe_tx_6_sigs(25) <= \<const0>\;
  pipe_tx_6_sigs(24) <= \<const0>\;
  pipe_tx_6_sigs(23) <= \<const0>\;
  pipe_tx_6_sigs(22) <= \<const0>\;
  pipe_tx_6_sigs(21) <= \<const0>\;
  pipe_tx_6_sigs(20) <= \<const0>\;
  pipe_tx_6_sigs(19) <= \<const0>\;
  pipe_tx_6_sigs(18) <= \<const0>\;
  pipe_tx_6_sigs(17) <= \<const0>\;
  pipe_tx_6_sigs(16) <= \<const0>\;
  pipe_tx_6_sigs(15) <= \<const0>\;
  pipe_tx_6_sigs(14) <= \<const0>\;
  pipe_tx_6_sigs(13) <= \<const0>\;
  pipe_tx_6_sigs(12) <= \<const0>\;
  pipe_tx_6_sigs(11) <= \<const0>\;
  pipe_tx_6_sigs(10) <= \<const0>\;
  pipe_tx_6_sigs(9) <= \<const0>\;
  pipe_tx_6_sigs(8) <= \<const0>\;
  pipe_tx_6_sigs(7) <= \<const0>\;
  pipe_tx_6_sigs(6) <= \<const0>\;
  pipe_tx_6_sigs(5) <= \<const0>\;
  pipe_tx_6_sigs(4) <= \<const0>\;
  pipe_tx_6_sigs(3) <= \<const0>\;
  pipe_tx_6_sigs(2) <= \<const0>\;
  pipe_tx_6_sigs(1) <= \<const0>\;
  pipe_tx_6_sigs(0) <= \<const0>\;
  pipe_tx_7_sigs(83) <= \<const0>\;
  pipe_tx_7_sigs(82) <= \<const0>\;
  pipe_tx_7_sigs(81) <= \<const0>\;
  pipe_tx_7_sigs(80) <= \<const0>\;
  pipe_tx_7_sigs(79) <= \<const0>\;
  pipe_tx_7_sigs(78) <= \<const0>\;
  pipe_tx_7_sigs(77) <= \<const0>\;
  pipe_tx_7_sigs(76) <= \<const0>\;
  pipe_tx_7_sigs(75) <= \<const0>\;
  pipe_tx_7_sigs(74) <= \<const0>\;
  pipe_tx_7_sigs(73) <= \<const0>\;
  pipe_tx_7_sigs(72) <= \<const0>\;
  pipe_tx_7_sigs(71) <= \<const0>\;
  pipe_tx_7_sigs(70) <= \<const0>\;
  pipe_tx_7_sigs(69) <= \<const0>\;
  pipe_tx_7_sigs(68) <= \<const0>\;
  pipe_tx_7_sigs(67) <= \<const0>\;
  pipe_tx_7_sigs(66) <= \<const0>\;
  pipe_tx_7_sigs(65) <= \<const0>\;
  pipe_tx_7_sigs(64) <= \<const0>\;
  pipe_tx_7_sigs(63) <= \<const0>\;
  pipe_tx_7_sigs(62) <= \<const0>\;
  pipe_tx_7_sigs(61) <= \<const0>\;
  pipe_tx_7_sigs(60) <= \<const0>\;
  pipe_tx_7_sigs(59) <= \<const0>\;
  pipe_tx_7_sigs(58) <= \<const0>\;
  pipe_tx_7_sigs(57) <= \<const0>\;
  pipe_tx_7_sigs(56) <= \<const0>\;
  pipe_tx_7_sigs(55) <= \<const0>\;
  pipe_tx_7_sigs(54) <= \<const0>\;
  pipe_tx_7_sigs(53) <= \<const0>\;
  pipe_tx_7_sigs(52) <= \<const0>\;
  pipe_tx_7_sigs(51) <= \<const0>\;
  pipe_tx_7_sigs(50) <= \<const0>\;
  pipe_tx_7_sigs(49) <= \<const0>\;
  pipe_tx_7_sigs(48) <= \<const0>\;
  pipe_tx_7_sigs(47) <= \<const0>\;
  pipe_tx_7_sigs(46) <= \<const0>\;
  pipe_tx_7_sigs(45) <= \<const0>\;
  pipe_tx_7_sigs(44) <= \<const0>\;
  pipe_tx_7_sigs(43) <= \<const0>\;
  pipe_tx_7_sigs(42) <= \<const0>\;
  pipe_tx_7_sigs(41) <= \<const0>\;
  pipe_tx_7_sigs(40) <= \<const0>\;
  pipe_tx_7_sigs(39) <= \<const0>\;
  pipe_tx_7_sigs(38) <= \<const0>\;
  pipe_tx_7_sigs(37) <= \<const0>\;
  pipe_tx_7_sigs(36) <= \<const0>\;
  pipe_tx_7_sigs(35) <= \<const0>\;
  pipe_tx_7_sigs(34) <= \<const0>\;
  pipe_tx_7_sigs(33) <= \<const0>\;
  pipe_tx_7_sigs(32) <= \<const0>\;
  pipe_tx_7_sigs(31) <= \<const0>\;
  pipe_tx_7_sigs(30) <= \<const0>\;
  pipe_tx_7_sigs(29) <= \<const0>\;
  pipe_tx_7_sigs(28) <= \<const0>\;
  pipe_tx_7_sigs(27) <= \<const0>\;
  pipe_tx_7_sigs(26) <= \<const0>\;
  pipe_tx_7_sigs(25) <= \<const0>\;
  pipe_tx_7_sigs(24) <= \<const0>\;
  pipe_tx_7_sigs(23) <= \<const0>\;
  pipe_tx_7_sigs(22) <= \<const0>\;
  pipe_tx_7_sigs(21) <= \<const0>\;
  pipe_tx_7_sigs(20) <= \<const0>\;
  pipe_tx_7_sigs(19) <= \<const0>\;
  pipe_tx_7_sigs(18) <= \<const0>\;
  pipe_tx_7_sigs(17) <= \<const0>\;
  pipe_tx_7_sigs(16) <= \<const0>\;
  pipe_tx_7_sigs(15) <= \<const0>\;
  pipe_tx_7_sigs(14) <= \<const0>\;
  pipe_tx_7_sigs(13) <= \<const0>\;
  pipe_tx_7_sigs(12) <= \<const0>\;
  pipe_tx_7_sigs(11) <= \<const0>\;
  pipe_tx_7_sigs(10) <= \<const0>\;
  pipe_tx_7_sigs(9) <= \<const0>\;
  pipe_tx_7_sigs(8) <= \<const0>\;
  pipe_tx_7_sigs(7) <= \<const0>\;
  pipe_tx_7_sigs(6) <= \<const0>\;
  pipe_tx_7_sigs(5) <= \<const0>\;
  pipe_tx_7_sigs(4) <= \<const0>\;
  pipe_tx_7_sigs(3) <= \<const0>\;
  pipe_tx_7_sigs(2) <= \<const0>\;
  pipe_tx_7_sigs(1) <= \<const0>\;
  pipe_tx_7_sigs(0) <= \<const0>\;
  pipe_tx_8_sigs(83) <= \<const0>\;
  pipe_tx_8_sigs(82) <= \<const0>\;
  pipe_tx_8_sigs(81) <= \<const0>\;
  pipe_tx_8_sigs(80) <= \<const0>\;
  pipe_tx_8_sigs(79) <= \<const0>\;
  pipe_tx_8_sigs(78) <= \<const0>\;
  pipe_tx_8_sigs(77) <= \<const0>\;
  pipe_tx_8_sigs(76) <= \<const0>\;
  pipe_tx_8_sigs(75) <= \<const0>\;
  pipe_tx_8_sigs(74) <= \<const0>\;
  pipe_tx_8_sigs(73) <= \<const0>\;
  pipe_tx_8_sigs(72) <= \<const0>\;
  pipe_tx_8_sigs(71) <= \<const0>\;
  pipe_tx_8_sigs(70) <= \<const0>\;
  pipe_tx_8_sigs(69) <= \<const0>\;
  pipe_tx_8_sigs(68) <= \<const0>\;
  pipe_tx_8_sigs(67) <= \<const0>\;
  pipe_tx_8_sigs(66) <= \<const0>\;
  pipe_tx_8_sigs(65) <= \<const0>\;
  pipe_tx_8_sigs(64) <= \<const0>\;
  pipe_tx_8_sigs(63) <= \<const0>\;
  pipe_tx_8_sigs(62) <= \<const0>\;
  pipe_tx_8_sigs(61) <= \<const0>\;
  pipe_tx_8_sigs(60) <= \<const0>\;
  pipe_tx_8_sigs(59) <= \<const0>\;
  pipe_tx_8_sigs(58) <= \<const0>\;
  pipe_tx_8_sigs(57) <= \<const0>\;
  pipe_tx_8_sigs(56) <= \<const0>\;
  pipe_tx_8_sigs(55) <= \<const0>\;
  pipe_tx_8_sigs(54) <= \<const0>\;
  pipe_tx_8_sigs(53) <= \<const0>\;
  pipe_tx_8_sigs(52) <= \<const0>\;
  pipe_tx_8_sigs(51) <= \<const0>\;
  pipe_tx_8_sigs(50) <= \<const0>\;
  pipe_tx_8_sigs(49) <= \<const0>\;
  pipe_tx_8_sigs(48) <= \<const0>\;
  pipe_tx_8_sigs(47) <= \<const0>\;
  pipe_tx_8_sigs(46) <= \<const0>\;
  pipe_tx_8_sigs(45) <= \<const0>\;
  pipe_tx_8_sigs(44) <= \<const0>\;
  pipe_tx_8_sigs(43) <= \<const0>\;
  pipe_tx_8_sigs(42) <= \<const0>\;
  pipe_tx_8_sigs(41) <= \<const0>\;
  pipe_tx_8_sigs(40) <= \<const0>\;
  pipe_tx_8_sigs(39) <= \<const0>\;
  pipe_tx_8_sigs(38) <= \<const0>\;
  pipe_tx_8_sigs(37) <= \<const0>\;
  pipe_tx_8_sigs(36) <= \<const0>\;
  pipe_tx_8_sigs(35) <= \<const0>\;
  pipe_tx_8_sigs(34) <= \<const0>\;
  pipe_tx_8_sigs(33) <= \<const0>\;
  pipe_tx_8_sigs(32) <= \<const0>\;
  pipe_tx_8_sigs(31) <= \<const0>\;
  pipe_tx_8_sigs(30) <= \<const0>\;
  pipe_tx_8_sigs(29) <= \<const0>\;
  pipe_tx_8_sigs(28) <= \<const0>\;
  pipe_tx_8_sigs(27) <= \<const0>\;
  pipe_tx_8_sigs(26) <= \<const0>\;
  pipe_tx_8_sigs(25) <= \<const0>\;
  pipe_tx_8_sigs(24) <= \<const0>\;
  pipe_tx_8_sigs(23) <= \<const0>\;
  pipe_tx_8_sigs(22) <= \<const0>\;
  pipe_tx_8_sigs(21) <= \<const0>\;
  pipe_tx_8_sigs(20) <= \<const0>\;
  pipe_tx_8_sigs(19) <= \<const0>\;
  pipe_tx_8_sigs(18) <= \<const0>\;
  pipe_tx_8_sigs(17) <= \<const0>\;
  pipe_tx_8_sigs(16) <= \<const0>\;
  pipe_tx_8_sigs(15) <= \<const0>\;
  pipe_tx_8_sigs(14) <= \<const0>\;
  pipe_tx_8_sigs(13) <= \<const0>\;
  pipe_tx_8_sigs(12) <= \<const0>\;
  pipe_tx_8_sigs(11) <= \<const0>\;
  pipe_tx_8_sigs(10) <= \<const0>\;
  pipe_tx_8_sigs(9) <= \<const0>\;
  pipe_tx_8_sigs(8) <= \<const0>\;
  pipe_tx_8_sigs(7) <= \<const0>\;
  pipe_tx_8_sigs(6) <= \<const0>\;
  pipe_tx_8_sigs(5) <= \<const0>\;
  pipe_tx_8_sigs(4) <= \<const0>\;
  pipe_tx_8_sigs(3) <= \<const0>\;
  pipe_tx_8_sigs(2) <= \<const0>\;
  pipe_tx_8_sigs(1) <= \<const0>\;
  pipe_tx_8_sigs(0) <= \<const0>\;
  pipe_tx_9_sigs(83) <= \<const0>\;
  pipe_tx_9_sigs(82) <= \<const0>\;
  pipe_tx_9_sigs(81) <= \<const0>\;
  pipe_tx_9_sigs(80) <= \<const0>\;
  pipe_tx_9_sigs(79) <= \<const0>\;
  pipe_tx_9_sigs(78) <= \<const0>\;
  pipe_tx_9_sigs(77) <= \<const0>\;
  pipe_tx_9_sigs(76) <= \<const0>\;
  pipe_tx_9_sigs(75) <= \<const0>\;
  pipe_tx_9_sigs(74) <= \<const0>\;
  pipe_tx_9_sigs(73) <= \<const0>\;
  pipe_tx_9_sigs(72) <= \<const0>\;
  pipe_tx_9_sigs(71) <= \<const0>\;
  pipe_tx_9_sigs(70) <= \<const0>\;
  pipe_tx_9_sigs(69) <= \<const0>\;
  pipe_tx_9_sigs(68) <= \<const0>\;
  pipe_tx_9_sigs(67) <= \<const0>\;
  pipe_tx_9_sigs(66) <= \<const0>\;
  pipe_tx_9_sigs(65) <= \<const0>\;
  pipe_tx_9_sigs(64) <= \<const0>\;
  pipe_tx_9_sigs(63) <= \<const0>\;
  pipe_tx_9_sigs(62) <= \<const0>\;
  pipe_tx_9_sigs(61) <= \<const0>\;
  pipe_tx_9_sigs(60) <= \<const0>\;
  pipe_tx_9_sigs(59) <= \<const0>\;
  pipe_tx_9_sigs(58) <= \<const0>\;
  pipe_tx_9_sigs(57) <= \<const0>\;
  pipe_tx_9_sigs(56) <= \<const0>\;
  pipe_tx_9_sigs(55) <= \<const0>\;
  pipe_tx_9_sigs(54) <= \<const0>\;
  pipe_tx_9_sigs(53) <= \<const0>\;
  pipe_tx_9_sigs(52) <= \<const0>\;
  pipe_tx_9_sigs(51) <= \<const0>\;
  pipe_tx_9_sigs(50) <= \<const0>\;
  pipe_tx_9_sigs(49) <= \<const0>\;
  pipe_tx_9_sigs(48) <= \<const0>\;
  pipe_tx_9_sigs(47) <= \<const0>\;
  pipe_tx_9_sigs(46) <= \<const0>\;
  pipe_tx_9_sigs(45) <= \<const0>\;
  pipe_tx_9_sigs(44) <= \<const0>\;
  pipe_tx_9_sigs(43) <= \<const0>\;
  pipe_tx_9_sigs(42) <= \<const0>\;
  pipe_tx_9_sigs(41) <= \<const0>\;
  pipe_tx_9_sigs(40) <= \<const0>\;
  pipe_tx_9_sigs(39) <= \<const0>\;
  pipe_tx_9_sigs(38) <= \<const0>\;
  pipe_tx_9_sigs(37) <= \<const0>\;
  pipe_tx_9_sigs(36) <= \<const0>\;
  pipe_tx_9_sigs(35) <= \<const0>\;
  pipe_tx_9_sigs(34) <= \<const0>\;
  pipe_tx_9_sigs(33) <= \<const0>\;
  pipe_tx_9_sigs(32) <= \<const0>\;
  pipe_tx_9_sigs(31) <= \<const0>\;
  pipe_tx_9_sigs(30) <= \<const0>\;
  pipe_tx_9_sigs(29) <= \<const0>\;
  pipe_tx_9_sigs(28) <= \<const0>\;
  pipe_tx_9_sigs(27) <= \<const0>\;
  pipe_tx_9_sigs(26) <= \<const0>\;
  pipe_tx_9_sigs(25) <= \<const0>\;
  pipe_tx_9_sigs(24) <= \<const0>\;
  pipe_tx_9_sigs(23) <= \<const0>\;
  pipe_tx_9_sigs(22) <= \<const0>\;
  pipe_tx_9_sigs(21) <= \<const0>\;
  pipe_tx_9_sigs(20) <= \<const0>\;
  pipe_tx_9_sigs(19) <= \<const0>\;
  pipe_tx_9_sigs(18) <= \<const0>\;
  pipe_tx_9_sigs(17) <= \<const0>\;
  pipe_tx_9_sigs(16) <= \<const0>\;
  pipe_tx_9_sigs(15) <= \<const0>\;
  pipe_tx_9_sigs(14) <= \<const0>\;
  pipe_tx_9_sigs(13) <= \<const0>\;
  pipe_tx_9_sigs(12) <= \<const0>\;
  pipe_tx_9_sigs(11) <= \<const0>\;
  pipe_tx_9_sigs(10) <= \<const0>\;
  pipe_tx_9_sigs(9) <= \<const0>\;
  pipe_tx_9_sigs(8) <= \<const0>\;
  pipe_tx_9_sigs(7) <= \<const0>\;
  pipe_tx_9_sigs(6) <= \<const0>\;
  pipe_tx_9_sigs(5) <= \<const0>\;
  pipe_tx_9_sigs(4) <= \<const0>\;
  pipe_tx_9_sigs(3) <= \<const0>\;
  pipe_tx_9_sigs(2) <= \<const0>\;
  pipe_tx_9_sigs(1) <= \<const0>\;
  pipe_tx_9_sigs(0) <= \<const0>\;
  pipe_txdlysresetdone(1) <= \<const0>\;
  pipe_txdlysresetdone(0) <= \<const0>\;
  pipe_txoutclk_out <= \<const0>\;
  pipe_txphaligndone(1) <= \<const0>\;
  pipe_txphaligndone(0) <= \<const0>\;
  pipe_txphinitdone(1) <= \<const0>\;
  pipe_txphinitdone(0) <= \<const0>\;
  qpll0clk_us_in(1) <= \<const0>\;
  qpll0clk_us_in(0) <= \<const0>\;
  qpll0freqlock_usp_in(1) <= \<const0>\;
  qpll0freqlock_usp_in(0) <= \<const0>\;
  qpll0pd_usp_in(0) <= \<const0>\;
  qpll0refclk_us_in(1) <= \<const0>\;
  qpll0refclk_us_in(0) <= \<const0>\;
  qpll0reset_usp_in(0) <= \<const0>\;
  qpll1clk_us_in(1) <= \<const0>\;
  qpll1clk_us_in(0) <= \<const0>\;
  qpll1freqlock_usp_in(1) <= \<const0>\;
  qpll1freqlock_usp_in(0) <= \<const0>\;
  qpll1pd_us_in(0) <= \<const0>\;
  qpll1pd_usp_in(0) <= \<const0>\;
  qpll1refclk_us_in(1) <= \<const0>\;
  qpll1refclk_us_in(0) <= \<const0>\;
  qpll1reset_us_in(0) <= \<const0>\;
  qpll1reset_usp_in(0) <= \<const0>\;
  qpll_drp_clk <= \<const0>\;
  qpll_drp_gen3 <= \<const0>\;
  qpll_drp_ovrd <= \<const0>\;
  qpll_drp_rst_n <= \<const0>\;
  qpll_drp_start <= \<const0>\;
  qpll_qplld <= \<const0>\;
  qpll_qpllreset(1) <= \<const0>\;
  qpll_qpllreset(0) <= \<const0>\;
  qpllrsvd2_us_in(4) <= \<const0>\;
  qpllrsvd2_us_in(3) <= \<const0>\;
  qpllrsvd2_us_in(2) <= \<const0>\;
  qpllrsvd2_us_in(1) <= \<const0>\;
  qpllrsvd2_us_in(0) <= \<const0>\;
  qpllrsvd3_us_in(4) <= \<const0>\;
  qpllrsvd3_us_in(3) <= \<const0>\;
  qpllrsvd3_us_in(2) <= \<const0>\;
  qpllrsvd3_us_in(1) <= \<const0>\;
  qpllrsvd3_us_in(0) <= \<const0>\;
  rcalenb_usp_in(0) <= \<const0>\;
  rd_interrupt <= \<const0>\;
  resetovrd_usp_in(1) <= \<const0>\;
  resetovrd_usp_in(0) <= \<const0>\;
  rx8b10ben_us_in(1) <= \<const0>\;
  rx8b10ben_us_in(0) <= \<const0>\;
  rx8b10ben_usp_in(1) <= \<const0>\;
  rx8b10ben_usp_in(0) <= \<const0>\;
  rxbufreset_us_in(1) <= \<const0>\;
  rxbufreset_us_in(0) <= \<const0>\;
  rxbufreset_usp_in(1) <= \<const0>\;
  rxbufreset_usp_in(0) <= \<const0>\;
  rxcdrfreqreset_usp_in(1) <= \<const0>\;
  rxcdrfreqreset_usp_in(0) <= \<const0>\;
  rxcdrhold_us_in(1) <= \<const0>\;
  rxcdrhold_us_in(0) <= \<const0>\;
  rxcdrhold_usp_in(1) <= \<const0>\;
  rxcdrhold_usp_in(0) <= \<const0>\;
  rxcdrreset_usp_in(1) <= \<const0>\;
  rxcdrreset_usp_in(0) <= \<const0>\;
  rxcommadeten_us_in(1) <= \<const0>\;
  rxcommadeten_us_in(0) <= \<const0>\;
  rxcommadeten_usp_in(1) <= \<const0>\;
  rxcommadeten_usp_in(0) <= \<const0>\;
  rxdfeagchold_us_in(1) <= \<const0>\;
  rxdfeagchold_us_in(0) <= \<const0>\;
  rxdfeagchold_usp_in(1) <= \<const0>\;
  rxdfeagchold_usp_in(0) <= \<const0>\;
  rxdfecfokhold_us_in(1) <= \<const0>\;
  rxdfecfokhold_us_in(0) <= \<const0>\;
  rxdfecfokhold_usp_in(1) <= \<const0>\;
  rxdfecfokhold_usp_in(0) <= \<const0>\;
  rxdfekhhold_us_in(1) <= \<const0>\;
  rxdfekhhold_us_in(0) <= \<const0>\;
  rxdfekhhold_usp_in(1) <= \<const0>\;
  rxdfekhhold_usp_in(0) <= \<const0>\;
  rxdfelfhold_us_in(1) <= \<const0>\;
  rxdfelfhold_us_in(0) <= \<const0>\;
  rxdfelfhold_usp_in(1) <= \<const0>\;
  rxdfelfhold_usp_in(0) <= \<const0>\;
  rxdfelpmreset_usp_in(1) <= \<const0>\;
  rxdfelpmreset_usp_in(0) <= \<const0>\;
  rxdfetap10hold_us_in(1) <= \<const0>\;
  rxdfetap10hold_us_in(0) <= \<const0>\;
  rxdfetap10hold_usp_in(1) <= \<const0>\;
  rxdfetap10hold_usp_in(0) <= \<const0>\;
  rxdfetap11hold_us_in(1) <= \<const0>\;
  rxdfetap11hold_us_in(0) <= \<const0>\;
  rxdfetap11hold_usp_in(1) <= \<const0>\;
  rxdfetap11hold_usp_in(0) <= \<const0>\;
  rxdfetap12hold_us_in(1) <= \<const0>\;
  rxdfetap12hold_us_in(0) <= \<const0>\;
  rxdfetap12hold_usp_in(1) <= \<const0>\;
  rxdfetap12hold_usp_in(0) <= \<const0>\;
  rxdfetap13hold_us_in(1) <= \<const0>\;
  rxdfetap13hold_us_in(0) <= \<const0>\;
  rxdfetap13hold_usp_in(1) <= \<const0>\;
  rxdfetap13hold_usp_in(0) <= \<const0>\;
  rxdfetap14hold_us_in(1) <= \<const0>\;
  rxdfetap14hold_us_in(0) <= \<const0>\;
  rxdfetap14hold_usp_in(1) <= \<const0>\;
  rxdfetap14hold_usp_in(0) <= \<const0>\;
  rxdfetap15hold_us_in(1) <= \<const0>\;
  rxdfetap15hold_us_in(0) <= \<const0>\;
  rxdfetap15hold_usp_in(1) <= \<const0>\;
  rxdfetap15hold_usp_in(0) <= \<const0>\;
  rxdfetap2hold_us_in(1) <= \<const0>\;
  rxdfetap2hold_us_in(0) <= \<const0>\;
  rxdfetap2hold_usp_in(1) <= \<const0>\;
  rxdfetap2hold_usp_in(0) <= \<const0>\;
  rxdfetap3hold_us_in(1) <= \<const0>\;
  rxdfetap3hold_us_in(0) <= \<const0>\;
  rxdfetap3hold_usp_in(1) <= \<const0>\;
  rxdfetap3hold_usp_in(0) <= \<const0>\;
  rxdfetap4hold_us_in(1) <= \<const0>\;
  rxdfetap4hold_us_in(0) <= \<const0>\;
  rxdfetap4hold_usp_in(1) <= \<const0>\;
  rxdfetap4hold_usp_in(0) <= \<const0>\;
  rxdfetap5hold_us_in(1) <= \<const0>\;
  rxdfetap5hold_us_in(0) <= \<const0>\;
  rxdfetap5hold_usp_in(1) <= \<const0>\;
  rxdfetap5hold_usp_in(0) <= \<const0>\;
  rxdfetap6hold_us_in(1) <= \<const0>\;
  rxdfetap6hold_us_in(0) <= \<const0>\;
  rxdfetap6hold_usp_in(1) <= \<const0>\;
  rxdfetap6hold_usp_in(0) <= \<const0>\;
  rxdfetap7hold_us_in(1) <= \<const0>\;
  rxdfetap7hold_us_in(0) <= \<const0>\;
  rxdfetap7hold_usp_in(1) <= \<const0>\;
  rxdfetap7hold_usp_in(0) <= \<const0>\;
  rxdfetap8hold_us_in(1) <= \<const0>\;
  rxdfetap8hold_us_in(0) <= \<const0>\;
  rxdfetap8hold_usp_in(1) <= \<const0>\;
  rxdfetap8hold_usp_in(0) <= \<const0>\;
  rxdfetap9hold_us_in(1) <= \<const0>\;
  rxdfetap9hold_us_in(0) <= \<const0>\;
  rxdfetap9hold_usp_in(1) <= \<const0>\;
  rxdfetap9hold_usp_in(0) <= \<const0>\;
  rxdfeuthold_us_in(1) <= \<const0>\;
  rxdfeuthold_us_in(0) <= \<const0>\;
  rxdfeuthold_usp_in(1) <= \<const0>\;
  rxdfeuthold_usp_in(0) <= \<const0>\;
  rxdfevphold_us_in(1) <= \<const0>\;
  rxdfevphold_us_in(0) <= \<const0>\;
  rxdfevphold_usp_in(1) <= \<const0>\;
  rxdfevphold_usp_in(0) <= \<const0>\;
  rxlpmen_us_in(1) <= \<const0>\;
  rxlpmen_us_in(0) <= \<const0>\;
  rxlpmen_usp_in(1) <= \<const0>\;
  rxlpmen_usp_in(0) <= \<const0>\;
  rxlpmgchold_us_in(1) <= \<const0>\;
  rxlpmgchold_us_in(0) <= \<const0>\;
  rxlpmgchold_usp_in(1) <= \<const0>\;
  rxlpmgchold_usp_in(0) <= \<const0>\;
  rxlpmhfhold_us_in(1) <= \<const0>\;
  rxlpmhfhold_us_in(0) <= \<const0>\;
  rxlpmhfhold_usp_in(1) <= \<const0>\;
  rxlpmhfhold_usp_in(0) <= \<const0>\;
  rxlpmlfhold_us_in(1) <= \<const0>\;
  rxlpmlfhold_us_in(0) <= \<const0>\;
  rxlpmlfhold_usp_in(1) <= \<const0>\;
  rxlpmlfhold_usp_in(0) <= \<const0>\;
  rxlpmoshold_us_in(1) <= \<const0>\;
  rxlpmoshold_us_in(0) <= \<const0>\;
  rxlpmoshold_usp_in(1) <= \<const0>\;
  rxlpmoshold_usp_in(0) <= \<const0>\;
  rxmcommaalignen_us_in(1) <= \<const0>\;
  rxmcommaalignen_us_in(0) <= \<const0>\;
  rxmcommaalignen_usp_in(1) <= \<const0>\;
  rxmcommaalignen_usp_in(0) <= \<const0>\;
  rxoshold_us_in(1) <= \<const0>\;
  rxoshold_us_in(0) <= \<const0>\;
  rxoshold_usp_in(1) <= \<const0>\;
  rxoshold_usp_in(0) <= \<const0>\;
  rxpcommaalignen_us_in(1) <= \<const0>\;
  rxpcommaalignen_us_in(0) <= \<const0>\;
  rxpcommaalignen_usp_in(1) <= \<const0>\;
  rxpcommaalignen_usp_in(0) <= \<const0>\;
  rxpcsreset_usp_in(1) <= \<const0>\;
  rxpcsreset_usp_in(0) <= \<const0>\;
  rxpd_us_in(3) <= \<const0>\;
  rxpd_us_in(2) <= \<const0>\;
  rxpd_us_in(1) <= \<const0>\;
  rxpd_us_in(0) <= \<const0>\;
  rxpd_usp_in(3) <= \<const0>\;
  rxpd_usp_in(2) <= \<const0>\;
  rxpd_usp_in(1) <= \<const0>\;
  rxpd_usp_in(0) <= \<const0>\;
  rxpmareset_usp_in(1) <= \<const0>\;
  rxpmareset_usp_in(0) <= \<const0>\;
  rxpolarity_us_in(1) <= \<const0>\;
  rxpolarity_us_in(0) <= \<const0>\;
  rxpolarity_usp_in(1) <= \<const0>\;
  rxpolarity_usp_in(0) <= \<const0>\;
  rxprbscntreset_us_in(1) <= \<const0>\;
  rxprbscntreset_us_in(0) <= \<const0>\;
  rxprbscntreset_usp_in(1) <= \<const0>\;
  rxprbscntreset_usp_in(0) <= \<const0>\;
  rxprbssel_us_in(7) <= \<const0>\;
  rxprbssel_us_in(6) <= \<const0>\;
  rxprbssel_us_in(5) <= \<const0>\;
  rxprbssel_us_in(4) <= \<const0>\;
  rxprbssel_us_in(3) <= \<const0>\;
  rxprbssel_us_in(2) <= \<const0>\;
  rxprbssel_us_in(1) <= \<const0>\;
  rxprbssel_us_in(0) <= \<const0>\;
  rxprbssel_usp_in(7) <= \<const0>\;
  rxprbssel_usp_in(6) <= \<const0>\;
  rxprbssel_usp_in(5) <= \<const0>\;
  rxprbssel_usp_in(4) <= \<const0>\;
  rxprbssel_usp_in(3) <= \<const0>\;
  rxprbssel_usp_in(2) <= \<const0>\;
  rxprbssel_usp_in(1) <= \<const0>\;
  rxprbssel_usp_in(0) <= \<const0>\;
  rxprogdivreset_us_in(1) <= \<const0>\;
  rxprogdivreset_us_in(0) <= \<const0>\;
  rxprogdivreset_usp_in(1) <= \<const0>\;
  rxprogdivreset_usp_in(0) <= \<const0>\;
  rxrate_us_in(5) <= \<const0>\;
  rxrate_us_in(4) <= \<const0>\;
  rxrate_us_in(3) <= \<const0>\;
  rxrate_us_in(2) <= \<const0>\;
  rxrate_us_in(1) <= \<const0>\;
  rxrate_us_in(0) <= \<const0>\;
  rxrate_usp_in(5) <= \<const0>\;
  rxrate_usp_in(4) <= \<const0>\;
  rxrate_usp_in(3) <= \<const0>\;
  rxrate_usp_in(2) <= \<const0>\;
  rxrate_usp_in(1) <= \<const0>\;
  rxrate_usp_in(0) <= \<const0>\;
  rxratemode_us_in(1) <= \<const0>\;
  rxratemode_us_in(0) <= \<const0>\;
  rxratemode_usp_in(1) <= \<const0>\;
  rxratemode_usp_in(0) <= \<const0>\;
  rxslide_us_in(1) <= \<const0>\;
  rxslide_us_in(0) <= \<const0>\;
  rxslide_usp_in(1) <= \<const0>\;
  rxslide_usp_in(0) <= \<const0>\;
  rxtermination_usp_in(1) <= \<const0>\;
  rxtermination_usp_in(0) <= \<const0>\;
  rxuserrdy_us_in(1) <= \<const0>\;
  rxuserrdy_us_in(0) <= \<const0>\;
  rxuserrdy_usp_in(1) <= \<const0>\;
  rxuserrdy_usp_in(0) <= \<const0>\;
  rxusrclk2_us_in(1) <= \<const0>\;
  rxusrclk2_us_in(0) <= \<const0>\;
  rxusrclk2_usp_in(1) <= \<const0>\;
  rxusrclk2_usp_in(0) <= \<const0>\;
  rxusrclk_us_in(1) <= \<const0>\;
  rxusrclk_us_in(0) <= \<const0>\;
  rxusrclk_usp_in(1) <= \<const0>\;
  rxusrclk_usp_in(0) <= \<const0>\;
  s_axi_arready <= \<const0>\;
  s_axi_awready <= \<const0>\;
  s_axi_bid(15) <= \<const0>\;
  s_axi_bid(14) <= \<const0>\;
  s_axi_bid(13) <= \<const0>\;
  s_axi_bid(12) <= \<const0>\;
  s_axi_bid(11) <= \<const0>\;
  s_axi_bid(10) <= \<const0>\;
  s_axi_bid(9) <= \<const0>\;
  s_axi_bid(8) <= \<const0>\;
  s_axi_bid(7) <= \<const0>\;
  s_axi_bid(6) <= \<const0>\;
  s_axi_bid(5) <= \<const0>\;
  s_axi_bid(4) <= \<const0>\;
  s_axi_bid(3) <= \<const0>\;
  s_axi_bid(2) <= \<const0>\;
  s_axi_bid(1) <= \<const0>\;
  s_axi_bid(0) <= \<const0>\;
  s_axi_bresp(1) <= \<const0>\;
  s_axi_bresp(0) <= \<const0>\;
  s_axi_bvalid <= \<const0>\;
  s_axi_rdata(31) <= \<const0>\;
  s_axi_rdata(30) <= \<const0>\;
  s_axi_rdata(29) <= \<const0>\;
  s_axi_rdata(28) <= \<const0>\;
  s_axi_rdata(27) <= \<const0>\;
  s_axi_rdata(26) <= \<const0>\;
  s_axi_rdata(25) <= \<const0>\;
  s_axi_rdata(24) <= \<const0>\;
  s_axi_rdata(23) <= \<const0>\;
  s_axi_rdata(22) <= \<const0>\;
  s_axi_rdata(21) <= \<const0>\;
  s_axi_rdata(20) <= \<const0>\;
  s_axi_rdata(19) <= \<const0>\;
  s_axi_rdata(18) <= \<const0>\;
  s_axi_rdata(17) <= \<const0>\;
  s_axi_rdata(16) <= \<const0>\;
  s_axi_rdata(15) <= \<const0>\;
  s_axi_rdata(14) <= \<const0>\;
  s_axi_rdata(13) <= \<const0>\;
  s_axi_rdata(12) <= \<const0>\;
  s_axi_rdata(11) <= \<const0>\;
  s_axi_rdata(10) <= \<const0>\;
  s_axi_rdata(9) <= \<const0>\;
  s_axi_rdata(8) <= \<const0>\;
  s_axi_rdata(7) <= \<const0>\;
  s_axi_rdata(6) <= \<const0>\;
  s_axi_rdata(5) <= \<const0>\;
  s_axi_rdata(4) <= \<const0>\;
  s_axi_rdata(3) <= \<const0>\;
  s_axi_rdata(2) <= \<const0>\;
  s_axi_rdata(1) <= \<const0>\;
  s_axi_rdata(0) <= \<const0>\;
  s_axi_rid(15) <= \<const0>\;
  s_axi_rid(14) <= \<const0>\;
  s_axi_rid(13) <= \<const0>\;
  s_axi_rid(12) <= \<const0>\;
  s_axi_rid(11) <= \<const0>\;
  s_axi_rid(10) <= \<const0>\;
  s_axi_rid(9) <= \<const0>\;
  s_axi_rid(8) <= \<const0>\;
  s_axi_rid(7) <= \<const0>\;
  s_axi_rid(6) <= \<const0>\;
  s_axi_rid(5) <= \<const0>\;
  s_axi_rid(4) <= \<const0>\;
  s_axi_rid(3) <= \<const0>\;
  s_axi_rid(2) <= \<const0>\;
  s_axi_rid(1) <= \<const0>\;
  s_axi_rid(0) <= \<const0>\;
  s_axi_rlast <= \<const0>\;
  s_axi_rresp(1) <= \<const0>\;
  s_axi_rresp(0) <= \<const0>\;
  s_axi_rvalid <= \<const0>\;
  s_axi_wready <= \<const0>\;
  s_axib_arready <= \<const0>\;
  s_axib_awready <= \<const0>\;
  s_axib_bid(3) <= \<const0>\;
  s_axib_bid(2) <= \<const0>\;
  s_axib_bid(1) <= \<const0>\;
  s_axib_bid(0) <= \<const0>\;
  s_axib_bresp(1) <= \<const0>\;
  s_axib_bresp(0) <= \<const0>\;
  s_axib_bvalid <= \<const0>\;
  s_axib_rdata(63) <= \<const0>\;
  s_axib_rdata(62) <= \<const0>\;
  s_axib_rdata(61) <= \<const0>\;
  s_axib_rdata(60) <= \<const0>\;
  s_axib_rdata(59) <= \<const0>\;
  s_axib_rdata(58) <= \<const0>\;
  s_axib_rdata(57) <= \<const0>\;
  s_axib_rdata(56) <= \<const0>\;
  s_axib_rdata(55) <= \<const0>\;
  s_axib_rdata(54) <= \<const0>\;
  s_axib_rdata(53) <= \<const0>\;
  s_axib_rdata(52) <= \<const0>\;
  s_axib_rdata(51) <= \<const0>\;
  s_axib_rdata(50) <= \<const0>\;
  s_axib_rdata(49) <= \<const0>\;
  s_axib_rdata(48) <= \<const0>\;
  s_axib_rdata(47) <= \<const0>\;
  s_axib_rdata(46) <= \<const0>\;
  s_axib_rdata(45) <= \<const0>\;
  s_axib_rdata(44) <= \<const0>\;
  s_axib_rdata(43) <= \<const0>\;
  s_axib_rdata(42) <= \<const0>\;
  s_axib_rdata(41) <= \<const0>\;
  s_axib_rdata(40) <= \<const0>\;
  s_axib_rdata(39) <= \<const0>\;
  s_axib_rdata(38) <= \<const0>\;
  s_axib_rdata(37) <= \<const0>\;
  s_axib_rdata(36) <= \<const0>\;
  s_axib_rdata(35) <= \<const0>\;
  s_axib_rdata(34) <= \<const0>\;
  s_axib_rdata(33) <= \<const0>\;
  s_axib_rdata(32) <= \<const0>\;
  s_axib_rdata(31) <= \<const0>\;
  s_axib_rdata(30) <= \<const0>\;
  s_axib_rdata(29) <= \<const0>\;
  s_axib_rdata(28) <= \<const0>\;
  s_axib_rdata(27) <= \<const0>\;
  s_axib_rdata(26) <= \<const0>\;
  s_axib_rdata(25) <= \<const0>\;
  s_axib_rdata(24) <= \<const0>\;
  s_axib_rdata(23) <= \<const0>\;
  s_axib_rdata(22) <= \<const0>\;
  s_axib_rdata(21) <= \<const0>\;
  s_axib_rdata(20) <= \<const0>\;
  s_axib_rdata(19) <= \<const0>\;
  s_axib_rdata(18) <= \<const0>\;
  s_axib_rdata(17) <= \<const0>\;
  s_axib_rdata(16) <= \<const0>\;
  s_axib_rdata(15) <= \<const0>\;
  s_axib_rdata(14) <= \<const0>\;
  s_axib_rdata(13) <= \<const0>\;
  s_axib_rdata(12) <= \<const0>\;
  s_axib_rdata(11) <= \<const0>\;
  s_axib_rdata(10) <= \<const0>\;
  s_axib_rdata(9) <= \<const0>\;
  s_axib_rdata(8) <= \<const0>\;
  s_axib_rdata(7) <= \<const0>\;
  s_axib_rdata(6) <= \<const0>\;
  s_axib_rdata(5) <= \<const0>\;
  s_axib_rdata(4) <= \<const0>\;
  s_axib_rdata(3) <= \<const0>\;
  s_axib_rdata(2) <= \<const0>\;
  s_axib_rdata(1) <= \<const0>\;
  s_axib_rdata(0) <= \<const0>\;
  s_axib_rid(3) <= \<const0>\;
  s_axib_rid(2) <= \<const0>\;
  s_axib_rid(1) <= \<const0>\;
  s_axib_rid(0) <= \<const0>\;
  s_axib_rlast <= \<const0>\;
  s_axib_rresp(1) <= \<const0>\;
  s_axib_rresp(0) <= \<const0>\;
  s_axib_ruser(7) <= \<const0>\;
  s_axib_ruser(6) <= \<const0>\;
  s_axib_ruser(5) <= \<const0>\;
  s_axib_ruser(4) <= \<const0>\;
  s_axib_ruser(3) <= \<const0>\;
  s_axib_ruser(2) <= \<const0>\;
  s_axib_ruser(1) <= \<const0>\;
  s_axib_ruser(0) <= \<const0>\;
  s_axib_rvalid <= \<const0>\;
  s_axib_wready <= \<const0>\;
  s_axil_arready <= \<const0>\;
  s_axil_awready <= \<const0>\;
  s_axil_bresp(1) <= \<const0>\;
  s_axil_bresp(0) <= \<const0>\;
  s_axil_bvalid <= \<const0>\;
  s_axil_rdata(31) <= \<const0>\;
  s_axil_rdata(30) <= \<const0>\;
  s_axil_rdata(29) <= \<const0>\;
  s_axil_rdata(28) <= \<const0>\;
  s_axil_rdata(27) <= \<const0>\;
  s_axil_rdata(26) <= \<const0>\;
  s_axil_rdata(25) <= \<const0>\;
  s_axil_rdata(24) <= \<const0>\;
  s_axil_rdata(23) <= \<const0>\;
  s_axil_rdata(22) <= \<const0>\;
  s_axil_rdata(21) <= \<const0>\;
  s_axil_rdata(20) <= \<const0>\;
  s_axil_rdata(19) <= \<const0>\;
  s_axil_rdata(18) <= \<const0>\;
  s_axil_rdata(17) <= \<const0>\;
  s_axil_rdata(16) <= \<const0>\;
  s_axil_rdata(15) <= \<const0>\;
  s_axil_rdata(14) <= \<const0>\;
  s_axil_rdata(13) <= \<const0>\;
  s_axil_rdata(12) <= \<const0>\;
  s_axil_rdata(11) <= \<const0>\;
  s_axil_rdata(10) <= \<const0>\;
  s_axil_rdata(9) <= \<const0>\;
  s_axil_rdata(8) <= \<const0>\;
  s_axil_rdata(7) <= \<const0>\;
  s_axil_rdata(6) <= \<const0>\;
  s_axil_rdata(5) <= \<const0>\;
  s_axil_rdata(4) <= \<const0>\;
  s_axil_rdata(3) <= \<const0>\;
  s_axil_rdata(2) <= \<const0>\;
  s_axil_rdata(1) <= \<const0>\;
  s_axil_rdata(0) <= \<const0>\;
  s_axil_rresp(1) <= \<const0>\;
  s_axil_rresp(0) <= \<const0>\;
  s_axil_rvalid <= \<const0>\;
  s_axil_wready <= \<const0>\;
  s_axis_c2h_tready_0 <= \<const0>\;
  s_axis_c2h_tready_1 <= \<const0>\;
  s_axis_c2h_tready_2 <= \<const0>\;
  s_axis_c2h_tready_3 <= \<const0>\;
  s_axis_cc_tdata_sd(63) <= \<const0>\;
  s_axis_cc_tdata_sd(62) <= \<const0>\;
  s_axis_cc_tdata_sd(61) <= \<const0>\;
  s_axis_cc_tdata_sd(60) <= \<const0>\;
  s_axis_cc_tdata_sd(59) <= \<const0>\;
  s_axis_cc_tdata_sd(58) <= \<const0>\;
  s_axis_cc_tdata_sd(57) <= \<const0>\;
  s_axis_cc_tdata_sd(56) <= \<const0>\;
  s_axis_cc_tdata_sd(55) <= \<const0>\;
  s_axis_cc_tdata_sd(54) <= \<const0>\;
  s_axis_cc_tdata_sd(53) <= \<const0>\;
  s_axis_cc_tdata_sd(52) <= \<const0>\;
  s_axis_cc_tdata_sd(51) <= \<const0>\;
  s_axis_cc_tdata_sd(50) <= \<const0>\;
  s_axis_cc_tdata_sd(49) <= \<const0>\;
  s_axis_cc_tdata_sd(48) <= \<const0>\;
  s_axis_cc_tdata_sd(47) <= \<const0>\;
  s_axis_cc_tdata_sd(46) <= \<const0>\;
  s_axis_cc_tdata_sd(45) <= \<const0>\;
  s_axis_cc_tdata_sd(44) <= \<const0>\;
  s_axis_cc_tdata_sd(43) <= \<const0>\;
  s_axis_cc_tdata_sd(42) <= \<const0>\;
  s_axis_cc_tdata_sd(41) <= \<const0>\;
  s_axis_cc_tdata_sd(40) <= \<const0>\;
  s_axis_cc_tdata_sd(39) <= \<const0>\;
  s_axis_cc_tdata_sd(38) <= \<const0>\;
  s_axis_cc_tdata_sd(37) <= \<const0>\;
  s_axis_cc_tdata_sd(36) <= \<const0>\;
  s_axis_cc_tdata_sd(35) <= \<const0>\;
  s_axis_cc_tdata_sd(34) <= \<const0>\;
  s_axis_cc_tdata_sd(33) <= \<const0>\;
  s_axis_cc_tdata_sd(32) <= \<const0>\;
  s_axis_cc_tdata_sd(31) <= \<const0>\;
  s_axis_cc_tdata_sd(30) <= \<const0>\;
  s_axis_cc_tdata_sd(29) <= \<const0>\;
  s_axis_cc_tdata_sd(28) <= \<const0>\;
  s_axis_cc_tdata_sd(27) <= \<const0>\;
  s_axis_cc_tdata_sd(26) <= \<const0>\;
  s_axis_cc_tdata_sd(25) <= \<const0>\;
  s_axis_cc_tdata_sd(24) <= \<const0>\;
  s_axis_cc_tdata_sd(23) <= \<const0>\;
  s_axis_cc_tdata_sd(22) <= \<const0>\;
  s_axis_cc_tdata_sd(21) <= \<const0>\;
  s_axis_cc_tdata_sd(20) <= \<const0>\;
  s_axis_cc_tdata_sd(19) <= \<const0>\;
  s_axis_cc_tdata_sd(18) <= \<const0>\;
  s_axis_cc_tdata_sd(17) <= \<const0>\;
  s_axis_cc_tdata_sd(16) <= \<const0>\;
  s_axis_cc_tdata_sd(15) <= \<const0>\;
  s_axis_cc_tdata_sd(14) <= \<const0>\;
  s_axis_cc_tdata_sd(13) <= \<const0>\;
  s_axis_cc_tdata_sd(12) <= \<const0>\;
  s_axis_cc_tdata_sd(11) <= \<const0>\;
  s_axis_cc_tdata_sd(10) <= \<const0>\;
  s_axis_cc_tdata_sd(9) <= \<const0>\;
  s_axis_cc_tdata_sd(8) <= \<const0>\;
  s_axis_cc_tdata_sd(7) <= \<const0>\;
  s_axis_cc_tdata_sd(6) <= \<const0>\;
  s_axis_cc_tdata_sd(5) <= \<const0>\;
  s_axis_cc_tdata_sd(4) <= \<const0>\;
  s_axis_cc_tdata_sd(3) <= \<const0>\;
  s_axis_cc_tdata_sd(2) <= \<const0>\;
  s_axis_cc_tdata_sd(1) <= \<const0>\;
  s_axis_cc_tdata_sd(0) <= \<const0>\;
  s_axis_cc_tkeep_sd(1) <= \<const0>\;
  s_axis_cc_tkeep_sd(0) <= \<const0>\;
  s_axis_cc_tlast_sd <= \<const0>\;
  s_axis_cc_tuser_sd(32) <= \<const0>\;
  s_axis_cc_tuser_sd(31) <= \<const0>\;
  s_axis_cc_tuser_sd(30) <= \<const0>\;
  s_axis_cc_tuser_sd(29) <= \<const0>\;
  s_axis_cc_tuser_sd(28) <= \<const0>\;
  s_axis_cc_tuser_sd(27) <= \<const0>\;
  s_axis_cc_tuser_sd(26) <= \<const0>\;
  s_axis_cc_tuser_sd(25) <= \<const0>\;
  s_axis_cc_tuser_sd(24) <= \<const0>\;
  s_axis_cc_tuser_sd(23) <= \<const0>\;
  s_axis_cc_tuser_sd(22) <= \<const0>\;
  s_axis_cc_tuser_sd(21) <= \<const0>\;
  s_axis_cc_tuser_sd(20) <= \<const0>\;
  s_axis_cc_tuser_sd(19) <= \<const0>\;
  s_axis_cc_tuser_sd(18) <= \<const0>\;
  s_axis_cc_tuser_sd(17) <= \<const0>\;
  s_axis_cc_tuser_sd(16) <= \<const0>\;
  s_axis_cc_tuser_sd(15) <= \<const0>\;
  s_axis_cc_tuser_sd(14) <= \<const0>\;
  s_axis_cc_tuser_sd(13) <= \<const0>\;
  s_axis_cc_tuser_sd(12) <= \<const0>\;
  s_axis_cc_tuser_sd(11) <= \<const0>\;
  s_axis_cc_tuser_sd(10) <= \<const0>\;
  s_axis_cc_tuser_sd(9) <= \<const0>\;
  s_axis_cc_tuser_sd(8) <= \<const0>\;
  s_axis_cc_tuser_sd(7) <= \<const0>\;
  s_axis_cc_tuser_sd(6) <= \<const0>\;
  s_axis_cc_tuser_sd(5) <= \<const0>\;
  s_axis_cc_tuser_sd(4) <= \<const0>\;
  s_axis_cc_tuser_sd(3) <= \<const0>\;
  s_axis_cc_tuser_sd(2) <= \<const0>\;
  s_axis_cc_tuser_sd(1) <= \<const0>\;
  s_axis_cc_tuser_sd(0) <= \<const0>\;
  s_axis_cc_tvalid_sd <= \<const0>\;
  s_axis_cq_tdata_out(63) <= \<const0>\;
  s_axis_cq_tdata_out(62) <= \<const0>\;
  s_axis_cq_tdata_out(61) <= \<const0>\;
  s_axis_cq_tdata_out(60) <= \<const0>\;
  s_axis_cq_tdata_out(59) <= \<const0>\;
  s_axis_cq_tdata_out(58) <= \<const0>\;
  s_axis_cq_tdata_out(57) <= \<const0>\;
  s_axis_cq_tdata_out(56) <= \<const0>\;
  s_axis_cq_tdata_out(55) <= \<const0>\;
  s_axis_cq_tdata_out(54) <= \<const0>\;
  s_axis_cq_tdata_out(53) <= \<const0>\;
  s_axis_cq_tdata_out(52) <= \<const0>\;
  s_axis_cq_tdata_out(51) <= \<const0>\;
  s_axis_cq_tdata_out(50) <= \<const0>\;
  s_axis_cq_tdata_out(49) <= \<const0>\;
  s_axis_cq_tdata_out(48) <= \<const0>\;
  s_axis_cq_tdata_out(47) <= \<const0>\;
  s_axis_cq_tdata_out(46) <= \<const0>\;
  s_axis_cq_tdata_out(45) <= \<const0>\;
  s_axis_cq_tdata_out(44) <= \<const0>\;
  s_axis_cq_tdata_out(43) <= \<const0>\;
  s_axis_cq_tdata_out(42) <= \<const0>\;
  s_axis_cq_tdata_out(41) <= \<const0>\;
  s_axis_cq_tdata_out(40) <= \<const0>\;
  s_axis_cq_tdata_out(39) <= \<const0>\;
  s_axis_cq_tdata_out(38) <= \<const0>\;
  s_axis_cq_tdata_out(37) <= \<const0>\;
  s_axis_cq_tdata_out(36) <= \<const0>\;
  s_axis_cq_tdata_out(35) <= \<const0>\;
  s_axis_cq_tdata_out(34) <= \<const0>\;
  s_axis_cq_tdata_out(33) <= \<const0>\;
  s_axis_cq_tdata_out(32) <= \<const0>\;
  s_axis_cq_tdata_out(31) <= \<const0>\;
  s_axis_cq_tdata_out(30) <= \<const0>\;
  s_axis_cq_tdata_out(29) <= \<const0>\;
  s_axis_cq_tdata_out(28) <= \<const0>\;
  s_axis_cq_tdata_out(27) <= \<const0>\;
  s_axis_cq_tdata_out(26) <= \<const0>\;
  s_axis_cq_tdata_out(25) <= \<const0>\;
  s_axis_cq_tdata_out(24) <= \<const0>\;
  s_axis_cq_tdata_out(23) <= \<const0>\;
  s_axis_cq_tdata_out(22) <= \<const0>\;
  s_axis_cq_tdata_out(21) <= \<const0>\;
  s_axis_cq_tdata_out(20) <= \<const0>\;
  s_axis_cq_tdata_out(19) <= \<const0>\;
  s_axis_cq_tdata_out(18) <= \<const0>\;
  s_axis_cq_tdata_out(17) <= \<const0>\;
  s_axis_cq_tdata_out(16) <= \<const0>\;
  s_axis_cq_tdata_out(15) <= \<const0>\;
  s_axis_cq_tdata_out(14) <= \<const0>\;
  s_axis_cq_tdata_out(13) <= \<const0>\;
  s_axis_cq_tdata_out(12) <= \<const0>\;
  s_axis_cq_tdata_out(11) <= \<const0>\;
  s_axis_cq_tdata_out(10) <= \<const0>\;
  s_axis_cq_tdata_out(9) <= \<const0>\;
  s_axis_cq_tdata_out(8) <= \<const0>\;
  s_axis_cq_tdata_out(7) <= \<const0>\;
  s_axis_cq_tdata_out(6) <= \<const0>\;
  s_axis_cq_tdata_out(5) <= \<const0>\;
  s_axis_cq_tdata_out(4) <= \<const0>\;
  s_axis_cq_tdata_out(3) <= \<const0>\;
  s_axis_cq_tdata_out(2) <= \<const0>\;
  s_axis_cq_tdata_out(1) <= \<const0>\;
  s_axis_cq_tdata_out(0) <= \<const0>\;
  s_axis_cq_tkeep_out(1) <= \<const0>\;
  s_axis_cq_tkeep_out(0) <= \<const0>\;
  s_axis_cq_tlast_out <= \<const0>\;
  s_axis_cq_tready_out <= \<const0>\;
  s_axis_cq_tuser_out(84) <= \<const0>\;
  s_axis_cq_tuser_out(83) <= \<const0>\;
  s_axis_cq_tuser_out(82) <= \<const0>\;
  s_axis_cq_tuser_out(81) <= \<const0>\;
  s_axis_cq_tuser_out(80) <= \<const0>\;
  s_axis_cq_tuser_out(79) <= \<const0>\;
  s_axis_cq_tuser_out(78) <= \<const0>\;
  s_axis_cq_tuser_out(77) <= \<const0>\;
  s_axis_cq_tuser_out(76) <= \<const0>\;
  s_axis_cq_tuser_out(75) <= \<const0>\;
  s_axis_cq_tuser_out(74) <= \<const0>\;
  s_axis_cq_tuser_out(73) <= \<const0>\;
  s_axis_cq_tuser_out(72) <= \<const0>\;
  s_axis_cq_tuser_out(71) <= \<const0>\;
  s_axis_cq_tuser_out(70) <= \<const0>\;
  s_axis_cq_tuser_out(69) <= \<const0>\;
  s_axis_cq_tuser_out(68) <= \<const0>\;
  s_axis_cq_tuser_out(67) <= \<const0>\;
  s_axis_cq_tuser_out(66) <= \<const0>\;
  s_axis_cq_tuser_out(65) <= \<const0>\;
  s_axis_cq_tuser_out(64) <= \<const0>\;
  s_axis_cq_tuser_out(63) <= \<const0>\;
  s_axis_cq_tuser_out(62) <= \<const0>\;
  s_axis_cq_tuser_out(61) <= \<const0>\;
  s_axis_cq_tuser_out(60) <= \<const0>\;
  s_axis_cq_tuser_out(59) <= \<const0>\;
  s_axis_cq_tuser_out(58) <= \<const0>\;
  s_axis_cq_tuser_out(57) <= \<const0>\;
  s_axis_cq_tuser_out(56) <= \<const0>\;
  s_axis_cq_tuser_out(55) <= \<const0>\;
  s_axis_cq_tuser_out(54) <= \<const0>\;
  s_axis_cq_tuser_out(53) <= \<const0>\;
  s_axis_cq_tuser_out(52) <= \<const0>\;
  s_axis_cq_tuser_out(51) <= \<const0>\;
  s_axis_cq_tuser_out(50) <= \<const0>\;
  s_axis_cq_tuser_out(49) <= \<const0>\;
  s_axis_cq_tuser_out(48) <= \<const0>\;
  s_axis_cq_tuser_out(47) <= \<const0>\;
  s_axis_cq_tuser_out(46) <= \<const0>\;
  s_axis_cq_tuser_out(45) <= \<const0>\;
  s_axis_cq_tuser_out(44) <= \<const0>\;
  s_axis_cq_tuser_out(43) <= \<const0>\;
  s_axis_cq_tuser_out(42) <= \<const0>\;
  s_axis_cq_tuser_out(41) <= \<const0>\;
  s_axis_cq_tuser_out(40) <= \<const0>\;
  s_axis_cq_tuser_out(39) <= \<const0>\;
  s_axis_cq_tuser_out(38) <= \<const0>\;
  s_axis_cq_tuser_out(37) <= \<const0>\;
  s_axis_cq_tuser_out(36) <= \<const0>\;
  s_axis_cq_tuser_out(35) <= \<const0>\;
  s_axis_cq_tuser_out(34) <= \<const0>\;
  s_axis_cq_tuser_out(33) <= \<const0>\;
  s_axis_cq_tuser_out(32) <= \<const0>\;
  s_axis_cq_tuser_out(31) <= \<const0>\;
  s_axis_cq_tuser_out(30) <= \<const0>\;
  s_axis_cq_tuser_out(29) <= \<const0>\;
  s_axis_cq_tuser_out(28) <= \<const0>\;
  s_axis_cq_tuser_out(27) <= \<const0>\;
  s_axis_cq_tuser_out(26) <= \<const0>\;
  s_axis_cq_tuser_out(25) <= \<const0>\;
  s_axis_cq_tuser_out(24) <= \<const0>\;
  s_axis_cq_tuser_out(23) <= \<const0>\;
  s_axis_cq_tuser_out(22) <= \<const0>\;
  s_axis_cq_tuser_out(21) <= \<const0>\;
  s_axis_cq_tuser_out(20) <= \<const0>\;
  s_axis_cq_tuser_out(19) <= \<const0>\;
  s_axis_cq_tuser_out(18) <= \<const0>\;
  s_axis_cq_tuser_out(17) <= \<const0>\;
  s_axis_cq_tuser_out(16) <= \<const0>\;
  s_axis_cq_tuser_out(15) <= \<const0>\;
  s_axis_cq_tuser_out(14) <= \<const0>\;
  s_axis_cq_tuser_out(13) <= \<const0>\;
  s_axis_cq_tuser_out(12) <= \<const0>\;
  s_axis_cq_tuser_out(11) <= \<const0>\;
  s_axis_cq_tuser_out(10) <= \<const0>\;
  s_axis_cq_tuser_out(9) <= \<const0>\;
  s_axis_cq_tuser_out(8) <= \<const0>\;
  s_axis_cq_tuser_out(7) <= \<const0>\;
  s_axis_cq_tuser_out(6) <= \<const0>\;
  s_axis_cq_tuser_out(5) <= \<const0>\;
  s_axis_cq_tuser_out(4) <= \<const0>\;
  s_axis_cq_tuser_out(3) <= \<const0>\;
  s_axis_cq_tuser_out(2) <= \<const0>\;
  s_axis_cq_tuser_out(1) <= \<const0>\;
  s_axis_cq_tuser_out(0) <= \<const0>\;
  s_axis_cq_tvalid_out <= \<const0>\;
  s_axis_rc_tdata_out(63) <= \<const0>\;
  s_axis_rc_tdata_out(62) <= \<const0>\;
  s_axis_rc_tdata_out(61) <= \<const0>\;
  s_axis_rc_tdata_out(60) <= \<const0>\;
  s_axis_rc_tdata_out(59) <= \<const0>\;
  s_axis_rc_tdata_out(58) <= \<const0>\;
  s_axis_rc_tdata_out(57) <= \<const0>\;
  s_axis_rc_tdata_out(56) <= \<const0>\;
  s_axis_rc_tdata_out(55) <= \<const0>\;
  s_axis_rc_tdata_out(54) <= \<const0>\;
  s_axis_rc_tdata_out(53) <= \<const0>\;
  s_axis_rc_tdata_out(52) <= \<const0>\;
  s_axis_rc_tdata_out(51) <= \<const0>\;
  s_axis_rc_tdata_out(50) <= \<const0>\;
  s_axis_rc_tdata_out(49) <= \<const0>\;
  s_axis_rc_tdata_out(48) <= \<const0>\;
  s_axis_rc_tdata_out(47) <= \<const0>\;
  s_axis_rc_tdata_out(46) <= \<const0>\;
  s_axis_rc_tdata_out(45) <= \<const0>\;
  s_axis_rc_tdata_out(44) <= \<const0>\;
  s_axis_rc_tdata_out(43) <= \<const0>\;
  s_axis_rc_tdata_out(42) <= \<const0>\;
  s_axis_rc_tdata_out(41) <= \<const0>\;
  s_axis_rc_tdata_out(40) <= \<const0>\;
  s_axis_rc_tdata_out(39) <= \<const0>\;
  s_axis_rc_tdata_out(38) <= \<const0>\;
  s_axis_rc_tdata_out(37) <= \<const0>\;
  s_axis_rc_tdata_out(36) <= \<const0>\;
  s_axis_rc_tdata_out(35) <= \<const0>\;
  s_axis_rc_tdata_out(34) <= \<const0>\;
  s_axis_rc_tdata_out(33) <= \<const0>\;
  s_axis_rc_tdata_out(32) <= \<const0>\;
  s_axis_rc_tdata_out(31) <= \<const0>\;
  s_axis_rc_tdata_out(30) <= \<const0>\;
  s_axis_rc_tdata_out(29) <= \<const0>\;
  s_axis_rc_tdata_out(28) <= \<const0>\;
  s_axis_rc_tdata_out(27) <= \<const0>\;
  s_axis_rc_tdata_out(26) <= \<const0>\;
  s_axis_rc_tdata_out(25) <= \<const0>\;
  s_axis_rc_tdata_out(24) <= \<const0>\;
  s_axis_rc_tdata_out(23) <= \<const0>\;
  s_axis_rc_tdata_out(22) <= \<const0>\;
  s_axis_rc_tdata_out(21) <= \<const0>\;
  s_axis_rc_tdata_out(20) <= \<const0>\;
  s_axis_rc_tdata_out(19) <= \<const0>\;
  s_axis_rc_tdata_out(18) <= \<const0>\;
  s_axis_rc_tdata_out(17) <= \<const0>\;
  s_axis_rc_tdata_out(16) <= \<const0>\;
  s_axis_rc_tdata_out(15) <= \<const0>\;
  s_axis_rc_tdata_out(14) <= \<const0>\;
  s_axis_rc_tdata_out(13) <= \<const0>\;
  s_axis_rc_tdata_out(12) <= \<const0>\;
  s_axis_rc_tdata_out(11) <= \<const0>\;
  s_axis_rc_tdata_out(10) <= \<const0>\;
  s_axis_rc_tdata_out(9) <= \<const0>\;
  s_axis_rc_tdata_out(8) <= \<const0>\;
  s_axis_rc_tdata_out(7) <= \<const0>\;
  s_axis_rc_tdata_out(6) <= \<const0>\;
  s_axis_rc_tdata_out(5) <= \<const0>\;
  s_axis_rc_tdata_out(4) <= \<const0>\;
  s_axis_rc_tdata_out(3) <= \<const0>\;
  s_axis_rc_tdata_out(2) <= \<const0>\;
  s_axis_rc_tdata_out(1) <= \<const0>\;
  s_axis_rc_tdata_out(0) <= \<const0>\;
  s_axis_rc_tkeep_out(1) <= \<const0>\;
  s_axis_rc_tkeep_out(0) <= \<const0>\;
  s_axis_rc_tlast_out <= \<const0>\;
  s_axis_rc_tready_out <= \<const0>\;
  s_axis_rc_tuser_out(74) <= \<const0>\;
  s_axis_rc_tuser_out(73) <= \<const0>\;
  s_axis_rc_tuser_out(72) <= \<const0>\;
  s_axis_rc_tuser_out(71) <= \<const0>\;
  s_axis_rc_tuser_out(70) <= \<const0>\;
  s_axis_rc_tuser_out(69) <= \<const0>\;
  s_axis_rc_tuser_out(68) <= \<const0>\;
  s_axis_rc_tuser_out(67) <= \<const0>\;
  s_axis_rc_tuser_out(66) <= \<const0>\;
  s_axis_rc_tuser_out(65) <= \<const0>\;
  s_axis_rc_tuser_out(64) <= \<const0>\;
  s_axis_rc_tuser_out(63) <= \<const0>\;
  s_axis_rc_tuser_out(62) <= \<const0>\;
  s_axis_rc_tuser_out(61) <= \<const0>\;
  s_axis_rc_tuser_out(60) <= \<const0>\;
  s_axis_rc_tuser_out(59) <= \<const0>\;
  s_axis_rc_tuser_out(58) <= \<const0>\;
  s_axis_rc_tuser_out(57) <= \<const0>\;
  s_axis_rc_tuser_out(56) <= \<const0>\;
  s_axis_rc_tuser_out(55) <= \<const0>\;
  s_axis_rc_tuser_out(54) <= \<const0>\;
  s_axis_rc_tuser_out(53) <= \<const0>\;
  s_axis_rc_tuser_out(52) <= \<const0>\;
  s_axis_rc_tuser_out(51) <= \<const0>\;
  s_axis_rc_tuser_out(50) <= \<const0>\;
  s_axis_rc_tuser_out(49) <= \<const0>\;
  s_axis_rc_tuser_out(48) <= \<const0>\;
  s_axis_rc_tuser_out(47) <= \<const0>\;
  s_axis_rc_tuser_out(46) <= \<const0>\;
  s_axis_rc_tuser_out(45) <= \<const0>\;
  s_axis_rc_tuser_out(44) <= \<const0>\;
  s_axis_rc_tuser_out(43) <= \<const0>\;
  s_axis_rc_tuser_out(42) <= \<const0>\;
  s_axis_rc_tuser_out(41) <= \<const0>\;
  s_axis_rc_tuser_out(40) <= \<const0>\;
  s_axis_rc_tuser_out(39) <= \<const0>\;
  s_axis_rc_tuser_out(38) <= \<const0>\;
  s_axis_rc_tuser_out(37) <= \<const0>\;
  s_axis_rc_tuser_out(36) <= \<const0>\;
  s_axis_rc_tuser_out(35) <= \<const0>\;
  s_axis_rc_tuser_out(34) <= \<const0>\;
  s_axis_rc_tuser_out(33) <= \<const0>\;
  s_axis_rc_tuser_out(32) <= \<const0>\;
  s_axis_rc_tuser_out(31) <= \<const0>\;
  s_axis_rc_tuser_out(30) <= \<const0>\;
  s_axis_rc_tuser_out(29) <= \<const0>\;
  s_axis_rc_tuser_out(28) <= \<const0>\;
  s_axis_rc_tuser_out(27) <= \<const0>\;
  s_axis_rc_tuser_out(26) <= \<const0>\;
  s_axis_rc_tuser_out(25) <= \<const0>\;
  s_axis_rc_tuser_out(24) <= \<const0>\;
  s_axis_rc_tuser_out(23) <= \<const0>\;
  s_axis_rc_tuser_out(22) <= \<const0>\;
  s_axis_rc_tuser_out(21) <= \<const0>\;
  s_axis_rc_tuser_out(20) <= \<const0>\;
  s_axis_rc_tuser_out(19) <= \<const0>\;
  s_axis_rc_tuser_out(18) <= \<const0>\;
  s_axis_rc_tuser_out(17) <= \<const0>\;
  s_axis_rc_tuser_out(16) <= \<const0>\;
  s_axis_rc_tuser_out(15) <= \<const0>\;
  s_axis_rc_tuser_out(14) <= \<const0>\;
  s_axis_rc_tuser_out(13) <= \<const0>\;
  s_axis_rc_tuser_out(12) <= \<const0>\;
  s_axis_rc_tuser_out(11) <= \<const0>\;
  s_axis_rc_tuser_out(10) <= \<const0>\;
  s_axis_rc_tuser_out(9) <= \<const0>\;
  s_axis_rc_tuser_out(8) <= \<const0>\;
  s_axis_rc_tuser_out(7) <= \<const0>\;
  s_axis_rc_tuser_out(6) <= \<const0>\;
  s_axis_rc_tuser_out(5) <= \<const0>\;
  s_axis_rc_tuser_out(4) <= \<const0>\;
  s_axis_rc_tuser_out(3) <= \<const0>\;
  s_axis_rc_tuser_out(2) <= \<const0>\;
  s_axis_rc_tuser_out(1) <= \<const0>\;
  s_axis_rc_tuser_out(0) <= \<const0>\;
  s_axis_rc_tvalid_out <= \<const0>\;
  s_axis_rq_tdata_sd(63) <= \<const0>\;
  s_axis_rq_tdata_sd(62) <= \<const0>\;
  s_axis_rq_tdata_sd(61) <= \<const0>\;
  s_axis_rq_tdata_sd(60) <= \<const0>\;
  s_axis_rq_tdata_sd(59) <= \<const0>\;
  s_axis_rq_tdata_sd(58) <= \<const0>\;
  s_axis_rq_tdata_sd(57) <= \<const0>\;
  s_axis_rq_tdata_sd(56) <= \<const0>\;
  s_axis_rq_tdata_sd(55) <= \<const0>\;
  s_axis_rq_tdata_sd(54) <= \<const0>\;
  s_axis_rq_tdata_sd(53) <= \<const0>\;
  s_axis_rq_tdata_sd(52) <= \<const0>\;
  s_axis_rq_tdata_sd(51) <= \<const0>\;
  s_axis_rq_tdata_sd(50) <= \<const0>\;
  s_axis_rq_tdata_sd(49) <= \<const0>\;
  s_axis_rq_tdata_sd(48) <= \<const0>\;
  s_axis_rq_tdata_sd(47) <= \<const0>\;
  s_axis_rq_tdata_sd(46) <= \<const0>\;
  s_axis_rq_tdata_sd(45) <= \<const0>\;
  s_axis_rq_tdata_sd(44) <= \<const0>\;
  s_axis_rq_tdata_sd(43) <= \<const0>\;
  s_axis_rq_tdata_sd(42) <= \<const0>\;
  s_axis_rq_tdata_sd(41) <= \<const0>\;
  s_axis_rq_tdata_sd(40) <= \<const0>\;
  s_axis_rq_tdata_sd(39) <= \<const0>\;
  s_axis_rq_tdata_sd(38) <= \<const0>\;
  s_axis_rq_tdata_sd(37) <= \<const0>\;
  s_axis_rq_tdata_sd(36) <= \<const0>\;
  s_axis_rq_tdata_sd(35) <= \<const0>\;
  s_axis_rq_tdata_sd(34) <= \<const0>\;
  s_axis_rq_tdata_sd(33) <= \<const0>\;
  s_axis_rq_tdata_sd(32) <= \<const0>\;
  s_axis_rq_tdata_sd(31) <= \<const0>\;
  s_axis_rq_tdata_sd(30) <= \<const0>\;
  s_axis_rq_tdata_sd(29) <= \<const0>\;
  s_axis_rq_tdata_sd(28) <= \<const0>\;
  s_axis_rq_tdata_sd(27) <= \<const0>\;
  s_axis_rq_tdata_sd(26) <= \<const0>\;
  s_axis_rq_tdata_sd(25) <= \<const0>\;
  s_axis_rq_tdata_sd(24) <= \<const0>\;
  s_axis_rq_tdata_sd(23) <= \<const0>\;
  s_axis_rq_tdata_sd(22) <= \<const0>\;
  s_axis_rq_tdata_sd(21) <= \<const0>\;
  s_axis_rq_tdata_sd(20) <= \<const0>\;
  s_axis_rq_tdata_sd(19) <= \<const0>\;
  s_axis_rq_tdata_sd(18) <= \<const0>\;
  s_axis_rq_tdata_sd(17) <= \<const0>\;
  s_axis_rq_tdata_sd(16) <= \<const0>\;
  s_axis_rq_tdata_sd(15) <= \<const0>\;
  s_axis_rq_tdata_sd(14) <= \<const0>\;
  s_axis_rq_tdata_sd(13) <= \<const0>\;
  s_axis_rq_tdata_sd(12) <= \<const0>\;
  s_axis_rq_tdata_sd(11) <= \<const0>\;
  s_axis_rq_tdata_sd(10) <= \<const0>\;
  s_axis_rq_tdata_sd(9) <= \<const0>\;
  s_axis_rq_tdata_sd(8) <= \<const0>\;
  s_axis_rq_tdata_sd(7) <= \<const0>\;
  s_axis_rq_tdata_sd(6) <= \<const0>\;
  s_axis_rq_tdata_sd(5) <= \<const0>\;
  s_axis_rq_tdata_sd(4) <= \<const0>\;
  s_axis_rq_tdata_sd(3) <= \<const0>\;
  s_axis_rq_tdata_sd(2) <= \<const0>\;
  s_axis_rq_tdata_sd(1) <= \<const0>\;
  s_axis_rq_tdata_sd(0) <= \<const0>\;
  s_axis_rq_tkeep_sd(1) <= \<const0>\;
  s_axis_rq_tkeep_sd(0) <= \<const0>\;
  s_axis_rq_tlast_sd <= \<const0>\;
  s_axis_rq_tuser_sd(59) <= \<const0>\;
  s_axis_rq_tuser_sd(58) <= \<const0>\;
  s_axis_rq_tuser_sd(57) <= \<const0>\;
  s_axis_rq_tuser_sd(56) <= \<const0>\;
  s_axis_rq_tuser_sd(55) <= \<const0>\;
  s_axis_rq_tuser_sd(54) <= \<const0>\;
  s_axis_rq_tuser_sd(53) <= \<const0>\;
  s_axis_rq_tuser_sd(52) <= \<const0>\;
  s_axis_rq_tuser_sd(51) <= \<const0>\;
  s_axis_rq_tuser_sd(50) <= \<const0>\;
  s_axis_rq_tuser_sd(49) <= \<const0>\;
  s_axis_rq_tuser_sd(48) <= \<const0>\;
  s_axis_rq_tuser_sd(47) <= \<const0>\;
  s_axis_rq_tuser_sd(46) <= \<const0>\;
  s_axis_rq_tuser_sd(45) <= \<const0>\;
  s_axis_rq_tuser_sd(44) <= \<const0>\;
  s_axis_rq_tuser_sd(43) <= \<const0>\;
  s_axis_rq_tuser_sd(42) <= \<const0>\;
  s_axis_rq_tuser_sd(41) <= \<const0>\;
  s_axis_rq_tuser_sd(40) <= \<const0>\;
  s_axis_rq_tuser_sd(39) <= \<const0>\;
  s_axis_rq_tuser_sd(38) <= \<const0>\;
  s_axis_rq_tuser_sd(37) <= \<const0>\;
  s_axis_rq_tuser_sd(36) <= \<const0>\;
  s_axis_rq_tuser_sd(35) <= \<const0>\;
  s_axis_rq_tuser_sd(34) <= \<const0>\;
  s_axis_rq_tuser_sd(33) <= \<const0>\;
  s_axis_rq_tuser_sd(32) <= \<const0>\;
  s_axis_rq_tuser_sd(31) <= \<const0>\;
  s_axis_rq_tuser_sd(30) <= \<const0>\;
  s_axis_rq_tuser_sd(29) <= \<const0>\;
  s_axis_rq_tuser_sd(28) <= \<const0>\;
  s_axis_rq_tuser_sd(27) <= \<const0>\;
  s_axis_rq_tuser_sd(26) <= \<const0>\;
  s_axis_rq_tuser_sd(25) <= \<const0>\;
  s_axis_rq_tuser_sd(24) <= \<const0>\;
  s_axis_rq_tuser_sd(23) <= \<const0>\;
  s_axis_rq_tuser_sd(22) <= \<const0>\;
  s_axis_rq_tuser_sd(21) <= \<const0>\;
  s_axis_rq_tuser_sd(20) <= \<const0>\;
  s_axis_rq_tuser_sd(19) <= \<const0>\;
  s_axis_rq_tuser_sd(18) <= \<const0>\;
  s_axis_rq_tuser_sd(17) <= \<const0>\;
  s_axis_rq_tuser_sd(16) <= \<const0>\;
  s_axis_rq_tuser_sd(15) <= \<const0>\;
  s_axis_rq_tuser_sd(14) <= \<const0>\;
  s_axis_rq_tuser_sd(13) <= \<const0>\;
  s_axis_rq_tuser_sd(12) <= \<const0>\;
  s_axis_rq_tuser_sd(11) <= \<const0>\;
  s_axis_rq_tuser_sd(10) <= \<const0>\;
  s_axis_rq_tuser_sd(9) <= \<const0>\;
  s_axis_rq_tuser_sd(8) <= \<const0>\;
  s_axis_rq_tuser_sd(7) <= \<const0>\;
  s_axis_rq_tuser_sd(6) <= \<const0>\;
  s_axis_rq_tuser_sd(5) <= \<const0>\;
  s_axis_rq_tuser_sd(4) <= \<const0>\;
  s_axis_rq_tuser_sd(3) <= \<const0>\;
  s_axis_rq_tuser_sd(2) <= \<const0>\;
  s_axis_rq_tuser_sd(1) <= \<const0>\;
  s_axis_rq_tuser_sd(0) <= \<const0>\;
  s_axis_rq_tvalid_sd <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(63) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(62) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(61) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(60) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(59) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(58) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(57) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(56) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(55) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(54) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(53) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(52) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(51) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(50) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(49) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(48) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(47) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(46) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(45) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(44) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(43) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(42) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(41) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(40) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(39) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(38) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(37) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(36) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(35) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(34) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(33) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(32) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(31) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(30) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(29) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(28) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(27) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(26) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(25) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(24) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(23) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(22) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(21) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(20) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(19) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(18) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(17) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(16) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(15) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(14) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(13) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(12) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(11) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(10) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(9) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(8) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(7) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(6) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(5) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(4) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(3) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(2) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(1) <= \<const0>\;
  sc0_ats_m_axis_cq_tdata(0) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(7) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(6) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(5) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(4) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(3) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(2) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(1) <= \<const0>\;
  sc0_ats_m_axis_cq_tkeep(0) <= \<const0>\;
  sc0_ats_m_axis_cq_tlast <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(84) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(83) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(82) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(81) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(80) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(79) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(78) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(77) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(76) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(75) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(74) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(73) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(72) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(71) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(70) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(69) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(68) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(67) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(66) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(65) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(64) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(63) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(62) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(61) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(60) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(59) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(58) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(57) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(56) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(55) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(54) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(53) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(52) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(51) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(50) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(49) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(48) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(47) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(46) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(45) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(44) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(43) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(42) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(41) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(40) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(39) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(38) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(37) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(36) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(35) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(34) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(33) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(32) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(31) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(30) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(29) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(28) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(27) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(26) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(25) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(24) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(23) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(22) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(21) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(20) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(19) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(18) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(17) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(16) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(15) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(14) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(13) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(12) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(11) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(10) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(9) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(8) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(7) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(6) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(5) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(4) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(3) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(2) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(1) <= \<const0>\;
  sc0_ats_m_axis_cq_tuser(0) <= \<const0>\;
  sc0_ats_m_axis_cq_tvalid <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(63) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(62) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(61) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(60) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(59) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(58) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(57) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(56) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(55) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(54) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(53) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(52) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(51) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(50) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(49) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(48) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(47) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(46) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(45) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(44) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(43) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(42) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(41) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(40) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(39) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(38) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(37) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(36) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(35) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(34) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(33) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(32) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(31) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(30) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(29) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(28) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(27) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(26) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(25) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(24) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(23) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(22) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(21) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(20) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(19) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(18) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(17) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(16) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(15) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(14) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(13) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(12) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(11) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(10) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(9) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(8) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(7) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(6) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(5) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(4) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(3) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(2) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(1) <= \<const0>\;
  sc0_ats_m_axis_rc_tdata(0) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(7) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(6) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(5) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(4) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(3) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(2) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(1) <= \<const0>\;
  sc0_ats_m_axis_rc_tkeep(0) <= \<const0>\;
  sc0_ats_m_axis_rc_tlast <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(74) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(73) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(72) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(71) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(70) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(69) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(68) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(67) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(66) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(65) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(64) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(63) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(62) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(61) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(60) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(59) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(58) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(57) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(56) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(55) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(54) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(53) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(52) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(51) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(50) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(49) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(48) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(47) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(46) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(45) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(44) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(43) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(42) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(41) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(40) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(39) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(38) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(37) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(36) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(35) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(34) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(33) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(32) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(31) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(30) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(29) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(28) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(27) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(26) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(25) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(24) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(23) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(22) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(21) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(20) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(19) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(18) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(17) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(16) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(15) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(14) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(13) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(12) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(11) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(10) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(9) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(8) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(7) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(6) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(5) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(4) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(3) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(2) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(1) <= \<const0>\;
  sc0_ats_m_axis_rc_tuser(0) <= \<const0>\;
  sc0_ats_m_axis_rc_tvalid <= \<const0>\;
  sc0_ats_s_axis_cc_tready <= \<const0>\;
  sc0_ats_s_axis_rq_tready <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(63) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(62) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(61) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(60) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(59) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(58) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(57) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(56) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(55) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(54) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(53) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(52) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(51) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(50) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(49) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(48) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(47) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(46) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(45) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(44) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(43) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(42) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(41) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(40) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(39) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(38) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(37) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(36) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(35) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(34) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(33) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(32) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(31) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(30) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(29) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(28) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(27) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(26) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(25) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(24) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(23) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(22) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(21) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(20) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(19) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(18) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(17) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(16) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(15) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(14) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(13) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(12) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(11) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(10) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(9) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(8) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(7) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(6) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(5) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(4) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(3) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(2) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(1) <= \<const0>\;
  sc1_ats_m_axis_cq_tdata(0) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(7) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(6) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(5) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(4) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(3) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(2) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(1) <= \<const0>\;
  sc1_ats_m_axis_cq_tkeep(0) <= \<const0>\;
  sc1_ats_m_axis_cq_tlast <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(84) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(83) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(82) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(81) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(80) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(79) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(78) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(77) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(76) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(75) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(74) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(73) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(72) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(71) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(70) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(69) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(68) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(67) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(66) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(65) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(64) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(63) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(62) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(61) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(60) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(59) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(58) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(57) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(56) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(55) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(54) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(53) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(52) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(51) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(50) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(49) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(48) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(47) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(46) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(45) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(44) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(43) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(42) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(41) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(40) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(39) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(38) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(37) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(36) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(35) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(34) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(33) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(32) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(31) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(30) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(29) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(28) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(27) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(26) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(25) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(24) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(23) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(22) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(21) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(20) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(19) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(18) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(17) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(16) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(15) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(14) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(13) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(12) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(11) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(10) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(9) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(8) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(7) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(6) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(5) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(4) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(3) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(2) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(1) <= \<const0>\;
  sc1_ats_m_axis_cq_tuser(0) <= \<const0>\;
  sc1_ats_m_axis_cq_tvalid <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(63) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(62) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(61) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(60) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(59) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(58) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(57) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(56) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(55) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(54) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(53) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(52) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(51) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(50) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(49) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(48) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(47) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(46) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(45) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(44) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(43) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(42) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(41) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(40) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(39) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(38) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(37) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(36) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(35) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(34) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(33) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(32) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(31) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(30) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(29) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(28) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(27) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(26) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(25) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(24) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(23) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(22) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(21) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(20) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(19) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(18) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(17) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(16) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(15) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(14) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(13) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(12) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(11) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(10) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(9) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(8) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(7) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(6) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(5) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(4) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(3) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(2) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(1) <= \<const0>\;
  sc1_ats_m_axis_rc_tdata(0) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(7) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(6) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(5) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(4) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(3) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(2) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(1) <= \<const0>\;
  sc1_ats_m_axis_rc_tkeep(0) <= \<const0>\;
  sc1_ats_m_axis_rc_tlast <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(74) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(73) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(72) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(71) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(70) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(69) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(68) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(67) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(66) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(65) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(64) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(63) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(62) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(61) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(60) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(59) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(58) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(57) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(56) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(55) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(54) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(53) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(52) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(51) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(50) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(49) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(48) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(47) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(46) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(45) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(44) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(43) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(42) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(41) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(40) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(39) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(38) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(37) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(36) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(35) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(34) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(33) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(32) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(31) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(30) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(29) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(28) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(27) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(26) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(25) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(24) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(23) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(22) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(21) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(20) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(19) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(18) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(17) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(16) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(15) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(14) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(13) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(12) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(11) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(10) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(9) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(8) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(7) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(6) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(5) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(4) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(3) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(2) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(1) <= \<const0>\;
  sc1_ats_m_axis_rc_tuser(0) <= \<const0>\;
  sc1_ats_m_axis_rc_tvalid <= \<const0>\;
  sc1_ats_s_axis_cc_tready <= \<const0>\;
  sc1_ats_s_axis_rq_tready <= \<const0>\;
  startup_cfgclk <= \<const0>\;
  startup_cfgmclk <= \<const0>\;
  startup_di(3) <= \<const0>\;
  startup_di(2) <= \<const0>\;
  startup_di(1) <= \<const0>\;
  startup_di(0) <= \<const0>\;
  startup_eos <= \<const0>\;
  startup_preq <= \<const0>\;
  sys_clk_bufg <= \<const0>\;
  sys_clk_ce_out <= \<const0>\;
  tx8b10ben_us_in(1) <= \<const0>\;
  tx8b10ben_us_in(0) <= \<const0>\;
  tx8b10ben_usp_in(1) <= \<const0>\;
  tx8b10ben_usp_in(0) <= \<const0>\;
  txctrl0_us_in(31) <= \<const0>\;
  txctrl0_us_in(30) <= \<const0>\;
  txctrl0_us_in(29) <= \<const0>\;
  txctrl0_us_in(28) <= \<const0>\;
  txctrl0_us_in(27) <= \<const0>\;
  txctrl0_us_in(26) <= \<const0>\;
  txctrl0_us_in(25) <= \<const0>\;
  txctrl0_us_in(24) <= \<const0>\;
  txctrl0_us_in(23) <= \<const0>\;
  txctrl0_us_in(22) <= \<const0>\;
  txctrl0_us_in(21) <= \<const0>\;
  txctrl0_us_in(20) <= \<const0>\;
  txctrl0_us_in(19) <= \<const0>\;
  txctrl0_us_in(18) <= \<const0>\;
  txctrl0_us_in(17) <= \<const0>\;
  txctrl0_us_in(16) <= \<const0>\;
  txctrl0_us_in(15) <= \<const0>\;
  txctrl0_us_in(14) <= \<const0>\;
  txctrl0_us_in(13) <= \<const0>\;
  txctrl0_us_in(12) <= \<const0>\;
  txctrl0_us_in(11) <= \<const0>\;
  txctrl0_us_in(10) <= \<const0>\;
  txctrl0_us_in(9) <= \<const0>\;
  txctrl0_us_in(8) <= \<const0>\;
  txctrl0_us_in(7) <= \<const0>\;
  txctrl0_us_in(6) <= \<const0>\;
  txctrl0_us_in(5) <= \<const0>\;
  txctrl0_us_in(4) <= \<const0>\;
  txctrl0_us_in(3) <= \<const0>\;
  txctrl0_us_in(2) <= \<const0>\;
  txctrl0_us_in(1) <= \<const0>\;
  txctrl0_us_in(0) <= \<const0>\;
  txctrl0_usp_in(31) <= \<const0>\;
  txctrl0_usp_in(30) <= \<const0>\;
  txctrl0_usp_in(29) <= \<const0>\;
  txctrl0_usp_in(28) <= \<const0>\;
  txctrl0_usp_in(27) <= \<const0>\;
  txctrl0_usp_in(26) <= \<const0>\;
  txctrl0_usp_in(25) <= \<const0>\;
  txctrl0_usp_in(24) <= \<const0>\;
  txctrl0_usp_in(23) <= \<const0>\;
  txctrl0_usp_in(22) <= \<const0>\;
  txctrl0_usp_in(21) <= \<const0>\;
  txctrl0_usp_in(20) <= \<const0>\;
  txctrl0_usp_in(19) <= \<const0>\;
  txctrl0_usp_in(18) <= \<const0>\;
  txctrl0_usp_in(17) <= \<const0>\;
  txctrl0_usp_in(16) <= \<const0>\;
  txctrl0_usp_in(15) <= \<const0>\;
  txctrl0_usp_in(14) <= \<const0>\;
  txctrl0_usp_in(13) <= \<const0>\;
  txctrl0_usp_in(12) <= \<const0>\;
  txctrl0_usp_in(11) <= \<const0>\;
  txctrl0_usp_in(10) <= \<const0>\;
  txctrl0_usp_in(9) <= \<const0>\;
  txctrl0_usp_in(8) <= \<const0>\;
  txctrl0_usp_in(7) <= \<const0>\;
  txctrl0_usp_in(6) <= \<const0>\;
  txctrl0_usp_in(5) <= \<const0>\;
  txctrl0_usp_in(4) <= \<const0>\;
  txctrl0_usp_in(3) <= \<const0>\;
  txctrl0_usp_in(2) <= \<const0>\;
  txctrl0_usp_in(1) <= \<const0>\;
  txctrl0_usp_in(0) <= \<const0>\;
  txctrl1_us_in(31) <= \<const0>\;
  txctrl1_us_in(30) <= \<const0>\;
  txctrl1_us_in(29) <= \<const0>\;
  txctrl1_us_in(28) <= \<const0>\;
  txctrl1_us_in(27) <= \<const0>\;
  txctrl1_us_in(26) <= \<const0>\;
  txctrl1_us_in(25) <= \<const0>\;
  txctrl1_us_in(24) <= \<const0>\;
  txctrl1_us_in(23) <= \<const0>\;
  txctrl1_us_in(22) <= \<const0>\;
  txctrl1_us_in(21) <= \<const0>\;
  txctrl1_us_in(20) <= \<const0>\;
  txctrl1_us_in(19) <= \<const0>\;
  txctrl1_us_in(18) <= \<const0>\;
  txctrl1_us_in(17) <= \<const0>\;
  txctrl1_us_in(16) <= \<const0>\;
  txctrl1_us_in(15) <= \<const0>\;
  txctrl1_us_in(14) <= \<const0>\;
  txctrl1_us_in(13) <= \<const0>\;
  txctrl1_us_in(12) <= \<const0>\;
  txctrl1_us_in(11) <= \<const0>\;
  txctrl1_us_in(10) <= \<const0>\;
  txctrl1_us_in(9) <= \<const0>\;
  txctrl1_us_in(8) <= \<const0>\;
  txctrl1_us_in(7) <= \<const0>\;
  txctrl1_us_in(6) <= \<const0>\;
  txctrl1_us_in(5) <= \<const0>\;
  txctrl1_us_in(4) <= \<const0>\;
  txctrl1_us_in(3) <= \<const0>\;
  txctrl1_us_in(2) <= \<const0>\;
  txctrl1_us_in(1) <= \<const0>\;
  txctrl1_us_in(0) <= \<const0>\;
  txctrl1_usp_in(31) <= \<const0>\;
  txctrl1_usp_in(30) <= \<const0>\;
  txctrl1_usp_in(29) <= \<const0>\;
  txctrl1_usp_in(28) <= \<const0>\;
  txctrl1_usp_in(27) <= \<const0>\;
  txctrl1_usp_in(26) <= \<const0>\;
  txctrl1_usp_in(25) <= \<const0>\;
  txctrl1_usp_in(24) <= \<const0>\;
  txctrl1_usp_in(23) <= \<const0>\;
  txctrl1_usp_in(22) <= \<const0>\;
  txctrl1_usp_in(21) <= \<const0>\;
  txctrl1_usp_in(20) <= \<const0>\;
  txctrl1_usp_in(19) <= \<const0>\;
  txctrl1_usp_in(18) <= \<const0>\;
  txctrl1_usp_in(17) <= \<const0>\;
  txctrl1_usp_in(16) <= \<const0>\;
  txctrl1_usp_in(15) <= \<const0>\;
  txctrl1_usp_in(14) <= \<const0>\;
  txctrl1_usp_in(13) <= \<const0>\;
  txctrl1_usp_in(12) <= \<const0>\;
  txctrl1_usp_in(11) <= \<const0>\;
  txctrl1_usp_in(10) <= \<const0>\;
  txctrl1_usp_in(9) <= \<const0>\;
  txctrl1_usp_in(8) <= \<const0>\;
  txctrl1_usp_in(7) <= \<const0>\;
  txctrl1_usp_in(6) <= \<const0>\;
  txctrl1_usp_in(5) <= \<const0>\;
  txctrl1_usp_in(4) <= \<const0>\;
  txctrl1_usp_in(3) <= \<const0>\;
  txctrl1_usp_in(2) <= \<const0>\;
  txctrl1_usp_in(1) <= \<const0>\;
  txctrl1_usp_in(0) <= \<const0>\;
  txctrl2_us_in(15) <= \<const0>\;
  txctrl2_us_in(14) <= \<const0>\;
  txctrl2_us_in(13) <= \<const0>\;
  txctrl2_us_in(12) <= \<const0>\;
  txctrl2_us_in(11) <= \<const0>\;
  txctrl2_us_in(10) <= \<const0>\;
  txctrl2_us_in(9) <= \<const0>\;
  txctrl2_us_in(8) <= \<const0>\;
  txctrl2_us_in(7) <= \<const0>\;
  txctrl2_us_in(6) <= \<const0>\;
  txctrl2_us_in(5) <= \<const0>\;
  txctrl2_us_in(4) <= \<const0>\;
  txctrl2_us_in(3) <= \<const0>\;
  txctrl2_us_in(2) <= \<const0>\;
  txctrl2_us_in(1) <= \<const0>\;
  txctrl2_us_in(0) <= \<const0>\;
  txctrl2_usp_in(15) <= \<const0>\;
  txctrl2_usp_in(14) <= \<const0>\;
  txctrl2_usp_in(13) <= \<const0>\;
  txctrl2_usp_in(12) <= \<const0>\;
  txctrl2_usp_in(11) <= \<const0>\;
  txctrl2_usp_in(10) <= \<const0>\;
  txctrl2_usp_in(9) <= \<const0>\;
  txctrl2_usp_in(8) <= \<const0>\;
  txctrl2_usp_in(7) <= \<const0>\;
  txctrl2_usp_in(6) <= \<const0>\;
  txctrl2_usp_in(5) <= \<const0>\;
  txctrl2_usp_in(4) <= \<const0>\;
  txctrl2_usp_in(3) <= \<const0>\;
  txctrl2_usp_in(2) <= \<const0>\;
  txctrl2_usp_in(1) <= \<const0>\;
  txctrl2_usp_in(0) <= \<const0>\;
  txdata_us_in(255) <= \<const0>\;
  txdata_us_in(254) <= \<const0>\;
  txdata_us_in(253) <= \<const0>\;
  txdata_us_in(252) <= \<const0>\;
  txdata_us_in(251) <= \<const0>\;
  txdata_us_in(250) <= \<const0>\;
  txdata_us_in(249) <= \<const0>\;
  txdata_us_in(248) <= \<const0>\;
  txdata_us_in(247) <= \<const0>\;
  txdata_us_in(246) <= \<const0>\;
  txdata_us_in(245) <= \<const0>\;
  txdata_us_in(244) <= \<const0>\;
  txdata_us_in(243) <= \<const0>\;
  txdata_us_in(242) <= \<const0>\;
  txdata_us_in(241) <= \<const0>\;
  txdata_us_in(240) <= \<const0>\;
  txdata_us_in(239) <= \<const0>\;
  txdata_us_in(238) <= \<const0>\;
  txdata_us_in(237) <= \<const0>\;
  txdata_us_in(236) <= \<const0>\;
  txdata_us_in(235) <= \<const0>\;
  txdata_us_in(234) <= \<const0>\;
  txdata_us_in(233) <= \<const0>\;
  txdata_us_in(232) <= \<const0>\;
  txdata_us_in(231) <= \<const0>\;
  txdata_us_in(230) <= \<const0>\;
  txdata_us_in(229) <= \<const0>\;
  txdata_us_in(228) <= \<const0>\;
  txdata_us_in(227) <= \<const0>\;
  txdata_us_in(226) <= \<const0>\;
  txdata_us_in(225) <= \<const0>\;
  txdata_us_in(224) <= \<const0>\;
  txdata_us_in(223) <= \<const0>\;
  txdata_us_in(222) <= \<const0>\;
  txdata_us_in(221) <= \<const0>\;
  txdata_us_in(220) <= \<const0>\;
  txdata_us_in(219) <= \<const0>\;
  txdata_us_in(218) <= \<const0>\;
  txdata_us_in(217) <= \<const0>\;
  txdata_us_in(216) <= \<const0>\;
  txdata_us_in(215) <= \<const0>\;
  txdata_us_in(214) <= \<const0>\;
  txdata_us_in(213) <= \<const0>\;
  txdata_us_in(212) <= \<const0>\;
  txdata_us_in(211) <= \<const0>\;
  txdata_us_in(210) <= \<const0>\;
  txdata_us_in(209) <= \<const0>\;
  txdata_us_in(208) <= \<const0>\;
  txdata_us_in(207) <= \<const0>\;
  txdata_us_in(206) <= \<const0>\;
  txdata_us_in(205) <= \<const0>\;
  txdata_us_in(204) <= \<const0>\;
  txdata_us_in(203) <= \<const0>\;
  txdata_us_in(202) <= \<const0>\;
  txdata_us_in(201) <= \<const0>\;
  txdata_us_in(200) <= \<const0>\;
  txdata_us_in(199) <= \<const0>\;
  txdata_us_in(198) <= \<const0>\;
  txdata_us_in(197) <= \<const0>\;
  txdata_us_in(196) <= \<const0>\;
  txdata_us_in(195) <= \<const0>\;
  txdata_us_in(194) <= \<const0>\;
  txdata_us_in(193) <= \<const0>\;
  txdata_us_in(192) <= \<const0>\;
  txdata_us_in(191) <= \<const0>\;
  txdata_us_in(190) <= \<const0>\;
  txdata_us_in(189) <= \<const0>\;
  txdata_us_in(188) <= \<const0>\;
  txdata_us_in(187) <= \<const0>\;
  txdata_us_in(186) <= \<const0>\;
  txdata_us_in(185) <= \<const0>\;
  txdata_us_in(184) <= \<const0>\;
  txdata_us_in(183) <= \<const0>\;
  txdata_us_in(182) <= \<const0>\;
  txdata_us_in(181) <= \<const0>\;
  txdata_us_in(180) <= \<const0>\;
  txdata_us_in(179) <= \<const0>\;
  txdata_us_in(178) <= \<const0>\;
  txdata_us_in(177) <= \<const0>\;
  txdata_us_in(176) <= \<const0>\;
  txdata_us_in(175) <= \<const0>\;
  txdata_us_in(174) <= \<const0>\;
  txdata_us_in(173) <= \<const0>\;
  txdata_us_in(172) <= \<const0>\;
  txdata_us_in(171) <= \<const0>\;
  txdata_us_in(170) <= \<const0>\;
  txdata_us_in(169) <= \<const0>\;
  txdata_us_in(168) <= \<const0>\;
  txdata_us_in(167) <= \<const0>\;
  txdata_us_in(166) <= \<const0>\;
  txdata_us_in(165) <= \<const0>\;
  txdata_us_in(164) <= \<const0>\;
  txdata_us_in(163) <= \<const0>\;
  txdata_us_in(162) <= \<const0>\;
  txdata_us_in(161) <= \<const0>\;
  txdata_us_in(160) <= \<const0>\;
  txdata_us_in(159) <= \<const0>\;
  txdata_us_in(158) <= \<const0>\;
  txdata_us_in(157) <= \<const0>\;
  txdata_us_in(156) <= \<const0>\;
  txdata_us_in(155) <= \<const0>\;
  txdata_us_in(154) <= \<const0>\;
  txdata_us_in(153) <= \<const0>\;
  txdata_us_in(152) <= \<const0>\;
  txdata_us_in(151) <= \<const0>\;
  txdata_us_in(150) <= \<const0>\;
  txdata_us_in(149) <= \<const0>\;
  txdata_us_in(148) <= \<const0>\;
  txdata_us_in(147) <= \<const0>\;
  txdata_us_in(146) <= \<const0>\;
  txdata_us_in(145) <= \<const0>\;
  txdata_us_in(144) <= \<const0>\;
  txdata_us_in(143) <= \<const0>\;
  txdata_us_in(142) <= \<const0>\;
  txdata_us_in(141) <= \<const0>\;
  txdata_us_in(140) <= \<const0>\;
  txdata_us_in(139) <= \<const0>\;
  txdata_us_in(138) <= \<const0>\;
  txdata_us_in(137) <= \<const0>\;
  txdata_us_in(136) <= \<const0>\;
  txdata_us_in(135) <= \<const0>\;
  txdata_us_in(134) <= \<const0>\;
  txdata_us_in(133) <= \<const0>\;
  txdata_us_in(132) <= \<const0>\;
  txdata_us_in(131) <= \<const0>\;
  txdata_us_in(130) <= \<const0>\;
  txdata_us_in(129) <= \<const0>\;
  txdata_us_in(128) <= \<const0>\;
  txdata_us_in(127) <= \<const0>\;
  txdata_us_in(126) <= \<const0>\;
  txdata_us_in(125) <= \<const0>\;
  txdata_us_in(124) <= \<const0>\;
  txdata_us_in(123) <= \<const0>\;
  txdata_us_in(122) <= \<const0>\;
  txdata_us_in(121) <= \<const0>\;
  txdata_us_in(120) <= \<const0>\;
  txdata_us_in(119) <= \<const0>\;
  txdata_us_in(118) <= \<const0>\;
  txdata_us_in(117) <= \<const0>\;
  txdata_us_in(116) <= \<const0>\;
  txdata_us_in(115) <= \<const0>\;
  txdata_us_in(114) <= \<const0>\;
  txdata_us_in(113) <= \<const0>\;
  txdata_us_in(112) <= \<const0>\;
  txdata_us_in(111) <= \<const0>\;
  txdata_us_in(110) <= \<const0>\;
  txdata_us_in(109) <= \<const0>\;
  txdata_us_in(108) <= \<const0>\;
  txdata_us_in(107) <= \<const0>\;
  txdata_us_in(106) <= \<const0>\;
  txdata_us_in(105) <= \<const0>\;
  txdata_us_in(104) <= \<const0>\;
  txdata_us_in(103) <= \<const0>\;
  txdata_us_in(102) <= \<const0>\;
  txdata_us_in(101) <= \<const0>\;
  txdata_us_in(100) <= \<const0>\;
  txdata_us_in(99) <= \<const0>\;
  txdata_us_in(98) <= \<const0>\;
  txdata_us_in(97) <= \<const0>\;
  txdata_us_in(96) <= \<const0>\;
  txdata_us_in(95) <= \<const0>\;
  txdata_us_in(94) <= \<const0>\;
  txdata_us_in(93) <= \<const0>\;
  txdata_us_in(92) <= \<const0>\;
  txdata_us_in(91) <= \<const0>\;
  txdata_us_in(90) <= \<const0>\;
  txdata_us_in(89) <= \<const0>\;
  txdata_us_in(88) <= \<const0>\;
  txdata_us_in(87) <= \<const0>\;
  txdata_us_in(86) <= \<const0>\;
  txdata_us_in(85) <= \<const0>\;
  txdata_us_in(84) <= \<const0>\;
  txdata_us_in(83) <= \<const0>\;
  txdata_us_in(82) <= \<const0>\;
  txdata_us_in(81) <= \<const0>\;
  txdata_us_in(80) <= \<const0>\;
  txdata_us_in(79) <= \<const0>\;
  txdata_us_in(78) <= \<const0>\;
  txdata_us_in(77) <= \<const0>\;
  txdata_us_in(76) <= \<const0>\;
  txdata_us_in(75) <= \<const0>\;
  txdata_us_in(74) <= \<const0>\;
  txdata_us_in(73) <= \<const0>\;
  txdata_us_in(72) <= \<const0>\;
  txdata_us_in(71) <= \<const0>\;
  txdata_us_in(70) <= \<const0>\;
  txdata_us_in(69) <= \<const0>\;
  txdata_us_in(68) <= \<const0>\;
  txdata_us_in(67) <= \<const0>\;
  txdata_us_in(66) <= \<const0>\;
  txdata_us_in(65) <= \<const0>\;
  txdata_us_in(64) <= \<const0>\;
  txdata_us_in(63) <= \<const0>\;
  txdata_us_in(62) <= \<const0>\;
  txdata_us_in(61) <= \<const0>\;
  txdata_us_in(60) <= \<const0>\;
  txdata_us_in(59) <= \<const0>\;
  txdata_us_in(58) <= \<const0>\;
  txdata_us_in(57) <= \<const0>\;
  txdata_us_in(56) <= \<const0>\;
  txdata_us_in(55) <= \<const0>\;
  txdata_us_in(54) <= \<const0>\;
  txdata_us_in(53) <= \<const0>\;
  txdata_us_in(52) <= \<const0>\;
  txdata_us_in(51) <= \<const0>\;
  txdata_us_in(50) <= \<const0>\;
  txdata_us_in(49) <= \<const0>\;
  txdata_us_in(48) <= \<const0>\;
  txdata_us_in(47) <= \<const0>\;
  txdata_us_in(46) <= \<const0>\;
  txdata_us_in(45) <= \<const0>\;
  txdata_us_in(44) <= \<const0>\;
  txdata_us_in(43) <= \<const0>\;
  txdata_us_in(42) <= \<const0>\;
  txdata_us_in(41) <= \<const0>\;
  txdata_us_in(40) <= \<const0>\;
  txdata_us_in(39) <= \<const0>\;
  txdata_us_in(38) <= \<const0>\;
  txdata_us_in(37) <= \<const0>\;
  txdata_us_in(36) <= \<const0>\;
  txdata_us_in(35) <= \<const0>\;
  txdata_us_in(34) <= \<const0>\;
  txdata_us_in(33) <= \<const0>\;
  txdata_us_in(32) <= \<const0>\;
  txdata_us_in(31) <= \<const0>\;
  txdata_us_in(30) <= \<const0>\;
  txdata_us_in(29) <= \<const0>\;
  txdata_us_in(28) <= \<const0>\;
  txdata_us_in(27) <= \<const0>\;
  txdata_us_in(26) <= \<const0>\;
  txdata_us_in(25) <= \<const0>\;
  txdata_us_in(24) <= \<const0>\;
  txdata_us_in(23) <= \<const0>\;
  txdata_us_in(22) <= \<const0>\;
  txdata_us_in(21) <= \<const0>\;
  txdata_us_in(20) <= \<const0>\;
  txdata_us_in(19) <= \<const0>\;
  txdata_us_in(18) <= \<const0>\;
  txdata_us_in(17) <= \<const0>\;
  txdata_us_in(16) <= \<const0>\;
  txdata_us_in(15) <= \<const0>\;
  txdata_us_in(14) <= \<const0>\;
  txdata_us_in(13) <= \<const0>\;
  txdata_us_in(12) <= \<const0>\;
  txdata_us_in(11) <= \<const0>\;
  txdata_us_in(10) <= \<const0>\;
  txdata_us_in(9) <= \<const0>\;
  txdata_us_in(8) <= \<const0>\;
  txdata_us_in(7) <= \<const0>\;
  txdata_us_in(6) <= \<const0>\;
  txdata_us_in(5) <= \<const0>\;
  txdata_us_in(4) <= \<const0>\;
  txdata_us_in(3) <= \<const0>\;
  txdata_us_in(2) <= \<const0>\;
  txdata_us_in(1) <= \<const0>\;
  txdata_us_in(0) <= \<const0>\;
  txdata_usp_in(255) <= \<const0>\;
  txdata_usp_in(254) <= \<const0>\;
  txdata_usp_in(253) <= \<const0>\;
  txdata_usp_in(252) <= \<const0>\;
  txdata_usp_in(251) <= \<const0>\;
  txdata_usp_in(250) <= \<const0>\;
  txdata_usp_in(249) <= \<const0>\;
  txdata_usp_in(248) <= \<const0>\;
  txdata_usp_in(247) <= \<const0>\;
  txdata_usp_in(246) <= \<const0>\;
  txdata_usp_in(245) <= \<const0>\;
  txdata_usp_in(244) <= \<const0>\;
  txdata_usp_in(243) <= \<const0>\;
  txdata_usp_in(242) <= \<const0>\;
  txdata_usp_in(241) <= \<const0>\;
  txdata_usp_in(240) <= \<const0>\;
  txdata_usp_in(239) <= \<const0>\;
  txdata_usp_in(238) <= \<const0>\;
  txdata_usp_in(237) <= \<const0>\;
  txdata_usp_in(236) <= \<const0>\;
  txdata_usp_in(235) <= \<const0>\;
  txdata_usp_in(234) <= \<const0>\;
  txdata_usp_in(233) <= \<const0>\;
  txdata_usp_in(232) <= \<const0>\;
  txdata_usp_in(231) <= \<const0>\;
  txdata_usp_in(230) <= \<const0>\;
  txdata_usp_in(229) <= \<const0>\;
  txdata_usp_in(228) <= \<const0>\;
  txdata_usp_in(227) <= \<const0>\;
  txdata_usp_in(226) <= \<const0>\;
  txdata_usp_in(225) <= \<const0>\;
  txdata_usp_in(224) <= \<const0>\;
  txdata_usp_in(223) <= \<const0>\;
  txdata_usp_in(222) <= \<const0>\;
  txdata_usp_in(221) <= \<const0>\;
  txdata_usp_in(220) <= \<const0>\;
  txdata_usp_in(219) <= \<const0>\;
  txdata_usp_in(218) <= \<const0>\;
  txdata_usp_in(217) <= \<const0>\;
  txdata_usp_in(216) <= \<const0>\;
  txdata_usp_in(215) <= \<const0>\;
  txdata_usp_in(214) <= \<const0>\;
  txdata_usp_in(213) <= \<const0>\;
  txdata_usp_in(212) <= \<const0>\;
  txdata_usp_in(211) <= \<const0>\;
  txdata_usp_in(210) <= \<const0>\;
  txdata_usp_in(209) <= \<const0>\;
  txdata_usp_in(208) <= \<const0>\;
  txdata_usp_in(207) <= \<const0>\;
  txdata_usp_in(206) <= \<const0>\;
  txdata_usp_in(205) <= \<const0>\;
  txdata_usp_in(204) <= \<const0>\;
  txdata_usp_in(203) <= \<const0>\;
  txdata_usp_in(202) <= \<const0>\;
  txdata_usp_in(201) <= \<const0>\;
  txdata_usp_in(200) <= \<const0>\;
  txdata_usp_in(199) <= \<const0>\;
  txdata_usp_in(198) <= \<const0>\;
  txdata_usp_in(197) <= \<const0>\;
  txdata_usp_in(196) <= \<const0>\;
  txdata_usp_in(195) <= \<const0>\;
  txdata_usp_in(194) <= \<const0>\;
  txdata_usp_in(193) <= \<const0>\;
  txdata_usp_in(192) <= \<const0>\;
  txdata_usp_in(191) <= \<const0>\;
  txdata_usp_in(190) <= \<const0>\;
  txdata_usp_in(189) <= \<const0>\;
  txdata_usp_in(188) <= \<const0>\;
  txdata_usp_in(187) <= \<const0>\;
  txdata_usp_in(186) <= \<const0>\;
  txdata_usp_in(185) <= \<const0>\;
  txdata_usp_in(184) <= \<const0>\;
  txdata_usp_in(183) <= \<const0>\;
  txdata_usp_in(182) <= \<const0>\;
  txdata_usp_in(181) <= \<const0>\;
  txdata_usp_in(180) <= \<const0>\;
  txdata_usp_in(179) <= \<const0>\;
  txdata_usp_in(178) <= \<const0>\;
  txdata_usp_in(177) <= \<const0>\;
  txdata_usp_in(176) <= \<const0>\;
  txdata_usp_in(175) <= \<const0>\;
  txdata_usp_in(174) <= \<const0>\;
  txdata_usp_in(173) <= \<const0>\;
  txdata_usp_in(172) <= \<const0>\;
  txdata_usp_in(171) <= \<const0>\;
  txdata_usp_in(170) <= \<const0>\;
  txdata_usp_in(169) <= \<const0>\;
  txdata_usp_in(168) <= \<const0>\;
  txdata_usp_in(167) <= \<const0>\;
  txdata_usp_in(166) <= \<const0>\;
  txdata_usp_in(165) <= \<const0>\;
  txdata_usp_in(164) <= \<const0>\;
  txdata_usp_in(163) <= \<const0>\;
  txdata_usp_in(162) <= \<const0>\;
  txdata_usp_in(161) <= \<const0>\;
  txdata_usp_in(160) <= \<const0>\;
  txdata_usp_in(159) <= \<const0>\;
  txdata_usp_in(158) <= \<const0>\;
  txdata_usp_in(157) <= \<const0>\;
  txdata_usp_in(156) <= \<const0>\;
  txdata_usp_in(155) <= \<const0>\;
  txdata_usp_in(154) <= \<const0>\;
  txdata_usp_in(153) <= \<const0>\;
  txdata_usp_in(152) <= \<const0>\;
  txdata_usp_in(151) <= \<const0>\;
  txdata_usp_in(150) <= \<const0>\;
  txdata_usp_in(149) <= \<const0>\;
  txdata_usp_in(148) <= \<const0>\;
  txdata_usp_in(147) <= \<const0>\;
  txdata_usp_in(146) <= \<const0>\;
  txdata_usp_in(145) <= \<const0>\;
  txdata_usp_in(144) <= \<const0>\;
  txdata_usp_in(143) <= \<const0>\;
  txdata_usp_in(142) <= \<const0>\;
  txdata_usp_in(141) <= \<const0>\;
  txdata_usp_in(140) <= \<const0>\;
  txdata_usp_in(139) <= \<const0>\;
  txdata_usp_in(138) <= \<const0>\;
  txdata_usp_in(137) <= \<const0>\;
  txdata_usp_in(136) <= \<const0>\;
  txdata_usp_in(135) <= \<const0>\;
  txdata_usp_in(134) <= \<const0>\;
  txdata_usp_in(133) <= \<const0>\;
  txdata_usp_in(132) <= \<const0>\;
  txdata_usp_in(131) <= \<const0>\;
  txdata_usp_in(130) <= \<const0>\;
  txdata_usp_in(129) <= \<const0>\;
  txdata_usp_in(128) <= \<const0>\;
  txdata_usp_in(127) <= \<const0>\;
  txdata_usp_in(126) <= \<const0>\;
  txdata_usp_in(125) <= \<const0>\;
  txdata_usp_in(124) <= \<const0>\;
  txdata_usp_in(123) <= \<const0>\;
  txdata_usp_in(122) <= \<const0>\;
  txdata_usp_in(121) <= \<const0>\;
  txdata_usp_in(120) <= \<const0>\;
  txdata_usp_in(119) <= \<const0>\;
  txdata_usp_in(118) <= \<const0>\;
  txdata_usp_in(117) <= \<const0>\;
  txdata_usp_in(116) <= \<const0>\;
  txdata_usp_in(115) <= \<const0>\;
  txdata_usp_in(114) <= \<const0>\;
  txdata_usp_in(113) <= \<const0>\;
  txdata_usp_in(112) <= \<const0>\;
  txdata_usp_in(111) <= \<const0>\;
  txdata_usp_in(110) <= \<const0>\;
  txdata_usp_in(109) <= \<const0>\;
  txdata_usp_in(108) <= \<const0>\;
  txdata_usp_in(107) <= \<const0>\;
  txdata_usp_in(106) <= \<const0>\;
  txdata_usp_in(105) <= \<const0>\;
  txdata_usp_in(104) <= \<const0>\;
  txdata_usp_in(103) <= \<const0>\;
  txdata_usp_in(102) <= \<const0>\;
  txdata_usp_in(101) <= \<const0>\;
  txdata_usp_in(100) <= \<const0>\;
  txdata_usp_in(99) <= \<const0>\;
  txdata_usp_in(98) <= \<const0>\;
  txdata_usp_in(97) <= \<const0>\;
  txdata_usp_in(96) <= \<const0>\;
  txdata_usp_in(95) <= \<const0>\;
  txdata_usp_in(94) <= \<const0>\;
  txdata_usp_in(93) <= \<const0>\;
  txdata_usp_in(92) <= \<const0>\;
  txdata_usp_in(91) <= \<const0>\;
  txdata_usp_in(90) <= \<const0>\;
  txdata_usp_in(89) <= \<const0>\;
  txdata_usp_in(88) <= \<const0>\;
  txdata_usp_in(87) <= \<const0>\;
  txdata_usp_in(86) <= \<const0>\;
  txdata_usp_in(85) <= \<const0>\;
  txdata_usp_in(84) <= \<const0>\;
  txdata_usp_in(83) <= \<const0>\;
  txdata_usp_in(82) <= \<const0>\;
  txdata_usp_in(81) <= \<const0>\;
  txdata_usp_in(80) <= \<const0>\;
  txdata_usp_in(79) <= \<const0>\;
  txdata_usp_in(78) <= \<const0>\;
  txdata_usp_in(77) <= \<const0>\;
  txdata_usp_in(76) <= \<const0>\;
  txdata_usp_in(75) <= \<const0>\;
  txdata_usp_in(74) <= \<const0>\;
  txdata_usp_in(73) <= \<const0>\;
  txdata_usp_in(72) <= \<const0>\;
  txdata_usp_in(71) <= \<const0>\;
  txdata_usp_in(70) <= \<const0>\;
  txdata_usp_in(69) <= \<const0>\;
  txdata_usp_in(68) <= \<const0>\;
  txdata_usp_in(67) <= \<const0>\;
  txdata_usp_in(66) <= \<const0>\;
  txdata_usp_in(65) <= \<const0>\;
  txdata_usp_in(64) <= \<const0>\;
  txdata_usp_in(63) <= \<const0>\;
  txdata_usp_in(62) <= \<const0>\;
  txdata_usp_in(61) <= \<const0>\;
  txdata_usp_in(60) <= \<const0>\;
  txdata_usp_in(59) <= \<const0>\;
  txdata_usp_in(58) <= \<const0>\;
  txdata_usp_in(57) <= \<const0>\;
  txdata_usp_in(56) <= \<const0>\;
  txdata_usp_in(55) <= \<const0>\;
  txdata_usp_in(54) <= \<const0>\;
  txdata_usp_in(53) <= \<const0>\;
  txdata_usp_in(52) <= \<const0>\;
  txdata_usp_in(51) <= \<const0>\;
  txdata_usp_in(50) <= \<const0>\;
  txdata_usp_in(49) <= \<const0>\;
  txdata_usp_in(48) <= \<const0>\;
  txdata_usp_in(47) <= \<const0>\;
  txdata_usp_in(46) <= \<const0>\;
  txdata_usp_in(45) <= \<const0>\;
  txdata_usp_in(44) <= \<const0>\;
  txdata_usp_in(43) <= \<const0>\;
  txdata_usp_in(42) <= \<const0>\;
  txdata_usp_in(41) <= \<const0>\;
  txdata_usp_in(40) <= \<const0>\;
  txdata_usp_in(39) <= \<const0>\;
  txdata_usp_in(38) <= \<const0>\;
  txdata_usp_in(37) <= \<const0>\;
  txdata_usp_in(36) <= \<const0>\;
  txdata_usp_in(35) <= \<const0>\;
  txdata_usp_in(34) <= \<const0>\;
  txdata_usp_in(33) <= \<const0>\;
  txdata_usp_in(32) <= \<const0>\;
  txdata_usp_in(31) <= \<const0>\;
  txdata_usp_in(30) <= \<const0>\;
  txdata_usp_in(29) <= \<const0>\;
  txdata_usp_in(28) <= \<const0>\;
  txdata_usp_in(27) <= \<const0>\;
  txdata_usp_in(26) <= \<const0>\;
  txdata_usp_in(25) <= \<const0>\;
  txdata_usp_in(24) <= \<const0>\;
  txdata_usp_in(23) <= \<const0>\;
  txdata_usp_in(22) <= \<const0>\;
  txdata_usp_in(21) <= \<const0>\;
  txdata_usp_in(20) <= \<const0>\;
  txdata_usp_in(19) <= \<const0>\;
  txdata_usp_in(18) <= \<const0>\;
  txdata_usp_in(17) <= \<const0>\;
  txdata_usp_in(16) <= \<const0>\;
  txdata_usp_in(15) <= \<const0>\;
  txdata_usp_in(14) <= \<const0>\;
  txdata_usp_in(13) <= \<const0>\;
  txdata_usp_in(12) <= \<const0>\;
  txdata_usp_in(11) <= \<const0>\;
  txdata_usp_in(10) <= \<const0>\;
  txdata_usp_in(9) <= \<const0>\;
  txdata_usp_in(8) <= \<const0>\;
  txdata_usp_in(7) <= \<const0>\;
  txdata_usp_in(6) <= \<const0>\;
  txdata_usp_in(5) <= \<const0>\;
  txdata_usp_in(4) <= \<const0>\;
  txdata_usp_in(3) <= \<const0>\;
  txdata_usp_in(2) <= \<const0>\;
  txdata_usp_in(1) <= \<const0>\;
  txdata_usp_in(0) <= \<const0>\;
  txdeemph_us_in(1) <= \<const0>\;
  txdeemph_us_in(0) <= \<const0>\;
  txdeemph_usp_in(3) <= \<const0>\;
  txdeemph_usp_in(2) <= \<const0>\;
  txdeemph_usp_in(1) <= \<const0>\;
  txdeemph_usp_in(0) <= \<const0>\;
  txdetectrx_us_in(1) <= \<const0>\;
  txdetectrx_us_in(0) <= \<const0>\;
  txdetectrx_usp_in(1) <= \<const0>\;
  txdetectrx_usp_in(0) <= \<const0>\;
  txdiffctrl_us_in(7) <= \<const0>\;
  txdiffctrl_us_in(6) <= \<const0>\;
  txdiffctrl_us_in(5) <= \<const0>\;
  txdiffctrl_us_in(4) <= \<const0>\;
  txdiffctrl_us_in(3) <= \<const0>\;
  txdiffctrl_us_in(2) <= \<const0>\;
  txdiffctrl_us_in(1) <= \<const0>\;
  txdiffctrl_us_in(0) <= \<const0>\;
  txdiffctrl_usp_in(9) <= \<const0>\;
  txdiffctrl_usp_in(8) <= \<const0>\;
  txdiffctrl_usp_in(7) <= \<const0>\;
  txdiffctrl_usp_in(6) <= \<const0>\;
  txdiffctrl_usp_in(5) <= \<const0>\;
  txdiffctrl_usp_in(4) <= \<const0>\;
  txdiffctrl_usp_in(3) <= \<const0>\;
  txdiffctrl_usp_in(2) <= \<const0>\;
  txdiffctrl_usp_in(1) <= \<const0>\;
  txdiffctrl_usp_in(0) <= \<const0>\;
  txdlybypass_us_in(1) <= \<const0>\;
  txdlybypass_us_in(0) <= \<const0>\;
  txdlybypass_usp_in(1) <= \<const0>\;
  txdlybypass_usp_in(0) <= \<const0>\;
  txdlyen_us_in(1) <= \<const0>\;
  txdlyen_us_in(0) <= \<const0>\;
  txdlyen_usp_in(1) <= \<const0>\;
  txdlyen_usp_in(0) <= \<const0>\;
  txdlyhold_us_in(1) <= \<const0>\;
  txdlyhold_us_in(0) <= \<const0>\;
  txdlyhold_usp_in(1) <= \<const0>\;
  txdlyhold_usp_in(0) <= \<const0>\;
  txdlyovrden_us_in(1) <= \<const0>\;
  txdlyovrden_us_in(0) <= \<const0>\;
  txdlyovrden_usp_in(1) <= \<const0>\;
  txdlyovrden_usp_in(0) <= \<const0>\;
  txdlysreset_us_in(1) <= \<const0>\;
  txdlysreset_us_in(0) <= \<const0>\;
  txdlysreset_usp_in(1) <= \<const0>\;
  txdlysreset_usp_in(0) <= \<const0>\;
  txdlyupdown_us_in(1) <= \<const0>\;
  txdlyupdown_us_in(0) <= \<const0>\;
  txdlyupdown_usp_in(1) <= \<const0>\;
  txdlyupdown_usp_in(0) <= \<const0>\;
  txelecidle_us_in(1) <= \<const0>\;
  txelecidle_us_in(0) <= \<const0>\;
  txelecidle_usp_in(1) <= \<const0>\;
  txelecidle_usp_in(0) <= \<const0>\;
  txinhibit_us_in(1) <= \<const0>\;
  txinhibit_us_in(0) <= \<const0>\;
  txmaincursor_us_in(13) <= \<const0>\;
  txmaincursor_us_in(12) <= \<const0>\;
  txmaincursor_us_in(11) <= \<const0>\;
  txmaincursor_us_in(10) <= \<const0>\;
  txmaincursor_us_in(9) <= \<const0>\;
  txmaincursor_us_in(8) <= \<const0>\;
  txmaincursor_us_in(7) <= \<const0>\;
  txmaincursor_us_in(6) <= \<const0>\;
  txmaincursor_us_in(5) <= \<const0>\;
  txmaincursor_us_in(4) <= \<const0>\;
  txmaincursor_us_in(3) <= \<const0>\;
  txmaincursor_us_in(2) <= \<const0>\;
  txmaincursor_us_in(1) <= \<const0>\;
  txmaincursor_us_in(0) <= \<const0>\;
  txmaincursor_usp_in(13) <= \<const0>\;
  txmaincursor_usp_in(12) <= \<const0>\;
  txmaincursor_usp_in(11) <= \<const0>\;
  txmaincursor_usp_in(10) <= \<const0>\;
  txmaincursor_usp_in(9) <= \<const0>\;
  txmaincursor_usp_in(8) <= \<const0>\;
  txmaincursor_usp_in(7) <= \<const0>\;
  txmaincursor_usp_in(6) <= \<const0>\;
  txmaincursor_usp_in(5) <= \<const0>\;
  txmaincursor_usp_in(4) <= \<const0>\;
  txmaincursor_usp_in(3) <= \<const0>\;
  txmaincursor_usp_in(2) <= \<const0>\;
  txmaincursor_usp_in(1) <= \<const0>\;
  txmaincursor_usp_in(0) <= \<const0>\;
  txmargin_us_in(5) <= \<const0>\;
  txmargin_us_in(4) <= \<const0>\;
  txmargin_us_in(3) <= \<const0>\;
  txmargin_us_in(2) <= \<const0>\;
  txmargin_us_in(1) <= \<const0>\;
  txmargin_us_in(0) <= \<const0>\;
  txmargin_usp_in(5) <= \<const0>\;
  txmargin_usp_in(4) <= \<const0>\;
  txmargin_usp_in(3) <= \<const0>\;
  txmargin_usp_in(2) <= \<const0>\;
  txmargin_usp_in(1) <= \<const0>\;
  txmargin_usp_in(0) <= \<const0>\;
  txoutclksel_us_in(5) <= \<const0>\;
  txoutclksel_us_in(4) <= \<const0>\;
  txoutclksel_us_in(3) <= \<const0>\;
  txoutclksel_us_in(2) <= \<const0>\;
  txoutclksel_us_in(1) <= \<const0>\;
  txoutclksel_us_in(0) <= \<const0>\;
  txoutclksel_usp_in(5) <= \<const0>\;
  txoutclksel_usp_in(4) <= \<const0>\;
  txoutclksel_usp_in(3) <= \<const0>\;
  txoutclksel_usp_in(2) <= \<const0>\;
  txoutclksel_usp_in(1) <= \<const0>\;
  txoutclksel_usp_in(0) <= \<const0>\;
  txpcsreset_usp_in(1) <= \<const0>\;
  txpcsreset_usp_in(0) <= \<const0>\;
  txpd_us_in(3) <= \<const0>\;
  txpd_us_in(2) <= \<const0>\;
  txpd_us_in(1) <= \<const0>\;
  txpd_us_in(0) <= \<const0>\;
  txpd_usp_in(3) <= \<const0>\;
  txpd_usp_in(2) <= \<const0>\;
  txpd_usp_in(1) <= \<const0>\;
  txpd_usp_in(0) <= \<const0>\;
  txpdelecidlemode_usp_in(1) <= \<const0>\;
  txpdelecidlemode_usp_in(0) <= \<const0>\;
  txphalign_us_in(1) <= \<const0>\;
  txphalign_us_in(0) <= \<const0>\;
  txphalign_usp_in(1) <= \<const0>\;
  txphalign_usp_in(0) <= \<const0>\;
  txphalignen_us_in(1) <= \<const0>\;
  txphalignen_us_in(0) <= \<const0>\;
  txphalignen_usp_in(1) <= \<const0>\;
  txphalignen_usp_in(0) <= \<const0>\;
  txphdlypd_us_in(1) <= \<const0>\;
  txphdlypd_us_in(0) <= \<const0>\;
  txphdlypd_usp_in(1) <= \<const0>\;
  txphdlypd_usp_in(0) <= \<const0>\;
  txphdlyreset_us_in(1) <= \<const0>\;
  txphdlyreset_us_in(0) <= \<const0>\;
  txphdlyreset_usp_in(1) <= \<const0>\;
  txphdlyreset_usp_in(0) <= \<const0>\;
  txphdlytstclk_us_in(1) <= \<const0>\;
  txphdlytstclk_us_in(0) <= \<const0>\;
  txphdlytstclk_usp_in(1) <= \<const0>\;
  txphdlytstclk_usp_in(0) <= \<const0>\;
  txphinit_us_in(1) <= \<const0>\;
  txphinit_us_in(0) <= \<const0>\;
  txphinit_usp_in(1) <= \<const0>\;
  txphinit_usp_in(0) <= \<const0>\;
  txphovrden_us_in(1) <= \<const0>\;
  txphovrden_us_in(0) <= \<const0>\;
  txphovrden_usp_in(1) <= \<const0>\;
  txphovrden_usp_in(0) <= \<const0>\;
  txpisopd_usp_in(1) <= \<const0>\;
  txpisopd_usp_in(0) <= \<const0>\;
  txpmareset_usp_in(1) <= \<const0>\;
  txpmareset_usp_in(0) <= \<const0>\;
  txpostcursor_us_in(9) <= \<const0>\;
  txpostcursor_us_in(8) <= \<const0>\;
  txpostcursor_us_in(7) <= \<const0>\;
  txpostcursor_us_in(6) <= \<const0>\;
  txpostcursor_us_in(5) <= \<const0>\;
  txpostcursor_us_in(4) <= \<const0>\;
  txpostcursor_us_in(3) <= \<const0>\;
  txpostcursor_us_in(2) <= \<const0>\;
  txpostcursor_us_in(1) <= \<const0>\;
  txpostcursor_us_in(0) <= \<const0>\;
  txpostcursor_usp_in(9) <= \<const0>\;
  txpostcursor_usp_in(8) <= \<const0>\;
  txpostcursor_usp_in(7) <= \<const0>\;
  txpostcursor_usp_in(6) <= \<const0>\;
  txpostcursor_usp_in(5) <= \<const0>\;
  txpostcursor_usp_in(4) <= \<const0>\;
  txpostcursor_usp_in(3) <= \<const0>\;
  txpostcursor_usp_in(2) <= \<const0>\;
  txpostcursor_usp_in(1) <= \<const0>\;
  txpostcursor_usp_in(0) <= \<const0>\;
  txprbsforceerr_us_in(1) <= \<const0>\;
  txprbsforceerr_us_in(0) <= \<const0>\;
  txprbsforceerr_usp_in(1) <= \<const0>\;
  txprbsforceerr_usp_in(0) <= \<const0>\;
  txprbssel_us_in(7) <= \<const0>\;
  txprbssel_us_in(6) <= \<const0>\;
  txprbssel_us_in(5) <= \<const0>\;
  txprbssel_us_in(4) <= \<const0>\;
  txprbssel_us_in(3) <= \<const0>\;
  txprbssel_us_in(2) <= \<const0>\;
  txprbssel_us_in(1) <= \<const0>\;
  txprbssel_us_in(0) <= \<const0>\;
  txprbssel_usp_in(7) <= \<const0>\;
  txprbssel_usp_in(6) <= \<const0>\;
  txprbssel_usp_in(5) <= \<const0>\;
  txprbssel_usp_in(4) <= \<const0>\;
  txprbssel_usp_in(3) <= \<const0>\;
  txprbssel_usp_in(2) <= \<const0>\;
  txprbssel_usp_in(1) <= \<const0>\;
  txprbssel_usp_in(0) <= \<const0>\;
  txprecursor_us_in(9) <= \<const0>\;
  txprecursor_us_in(8) <= \<const0>\;
  txprecursor_us_in(7) <= \<const0>\;
  txprecursor_us_in(6) <= \<const0>\;
  txprecursor_us_in(5) <= \<const0>\;
  txprecursor_us_in(4) <= \<const0>\;
  txprecursor_us_in(3) <= \<const0>\;
  txprecursor_us_in(2) <= \<const0>\;
  txprecursor_us_in(1) <= \<const0>\;
  txprecursor_us_in(0) <= \<const0>\;
  txprecursor_usp_in(9) <= \<const0>\;
  txprecursor_usp_in(8) <= \<const0>\;
  txprecursor_usp_in(7) <= \<const0>\;
  txprecursor_usp_in(6) <= \<const0>\;
  txprecursor_usp_in(5) <= \<const0>\;
  txprecursor_usp_in(4) <= \<const0>\;
  txprecursor_usp_in(3) <= \<const0>\;
  txprecursor_usp_in(2) <= \<const0>\;
  txprecursor_usp_in(1) <= \<const0>\;
  txprecursor_usp_in(0) <= \<const0>\;
  txprogdivreset_us_in(1) <= \<const0>\;
  txprogdivreset_us_in(0) <= \<const0>\;
  txprogdivreset_usp_in(1) <= \<const0>\;
  txprogdivreset_usp_in(0) <= \<const0>\;
  txrate_us_in(5) <= \<const0>\;
  txrate_us_in(4) <= \<const0>\;
  txrate_us_in(3) <= \<const0>\;
  txrate_us_in(2) <= \<const0>\;
  txrate_us_in(1) <= \<const0>\;
  txrate_us_in(0) <= \<const0>\;
  txrate_usp_in(5) <= \<const0>\;
  txrate_usp_in(4) <= \<const0>\;
  txrate_usp_in(3) <= \<const0>\;
  txrate_usp_in(2) <= \<const0>\;
  txrate_usp_in(1) <= \<const0>\;
  txrate_usp_in(0) <= \<const0>\;
  txswing_us_in(1) <= \<const0>\;
  txswing_us_in(0) <= \<const0>\;
  txswing_usp_in(1) <= \<const0>\;
  txswing_usp_in(0) <= \<const0>\;
  txsyncallin_us_in(1) <= \<const0>\;
  txsyncallin_us_in(0) <= \<const0>\;
  txsyncallin_usp_in(1) <= \<const0>\;
  txsyncallin_usp_in(0) <= \<const0>\;
  txsyncin_us_in(1) <= \<const0>\;
  txsyncin_us_in(0) <= \<const0>\;
  txsyncin_usp_in(1) <= \<const0>\;
  txsyncin_usp_in(0) <= \<const0>\;
  txsyncmode_us_in(1) <= \<const0>\;
  txsyncmode_us_in(0) <= \<const0>\;
  txsyncmode_usp_in(1) <= \<const0>\;
  txsyncmode_usp_in(0) <= \<const0>\;
  txuserrdy_us_in(1) <= \<const0>\;
  txuserrdy_us_in(0) <= \<const0>\;
  txuserrdy_usp_in(1) <= \<const0>\;
  txuserrdy_usp_in(0) <= \<const0>\;
  txusrclk2_us_in(1) <= \<const0>\;
  txusrclk2_us_in(0) <= \<const0>\;
  txusrclk2_usp_in(1) <= \<const0>\;
  txusrclk2_usp_in(0) <= \<const0>\;
  txusrclk_us_in(1) <= \<const0>\;
  txusrclk_us_in(0) <= \<const0>\;
  txusrclk_usp_in(1) <= \<const0>\;
  txusrclk_usp_in(0) <= \<const0>\;
  user_lnk_up <= \^user_lnk_up\;
  usr_flr_clr <= \<const0>\;
  usr_flr_fnc(7) <= \<const0>\;
  usr_flr_fnc(6) <= \<const0>\;
  usr_flr_fnc(5) <= \<const0>\;
  usr_flr_fnc(4) <= \<const0>\;
  usr_flr_fnc(3) <= \<const0>\;
  usr_flr_fnc(2) <= \<const0>\;
  usr_flr_fnc(1) <= \<const0>\;
  usr_flr_fnc(0) <= \<const0>\;
  usr_flr_set <= \<const0>\;
  wr_interrupt <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_0
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_1
    );
i_100: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_100
    );
i_101: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_101
    );
i_102: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_102
    );
i_103: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_103
    );
i_104: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_104
    );
i_105: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_105
    );
i_106: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_106
    );
i_107: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_107
    );
i_108: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_108
    );
i_109: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_109
    );
i_110: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_110
    );
i_111: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_111
    );
i_112: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_112
    );
i_113: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_113
    );
i_114: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_114
    );
i_115: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_115
    );
i_116: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_116
    );
i_117: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_117
    );
i_118: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_118
    );
i_119: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_119
    );
i_120: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_120
    );
i_121: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_121
    );
i_122: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_122
    );
i_123: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_123
    );
i_124: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_124
    );
i_125: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_125
    );
i_126: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_126
    );
i_127: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_127
    );
i_128: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_128
    );
i_129: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_129
    );
i_130: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_130
    );
i_131: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_131
    );
i_132: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_132
    );
i_133: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_133
    );
i_134: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_134
    );
i_135: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_135
    );
i_136: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_136
    );
i_137: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_137
    );
i_138: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_138
    );
i_139: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(31)
    );
i_140: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(30)
    );
i_141: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(29)
    );
i_142: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(28)
    );
i_143: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(27)
    );
i_144: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(26)
    );
i_145: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(25)
    );
i_146: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(24)
    );
i_147: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(23)
    );
i_148: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(22)
    );
i_149: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(21)
    );
i_150: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(20)
    );
i_151: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(19)
    );
i_152: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(18)
    );
i_153: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(17)
    );
i_154: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(16)
    );
i_155: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(15)
    );
i_156: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(14)
    );
i_157: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(13)
    );
i_158: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(12)
    );
i_159: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(11)
    );
i_16: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_16
    );
i_160: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(10)
    );
i_161: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(9)
    );
i_162: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(8)
    );
i_163: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(7)
    );
i_164: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(6)
    );
i_165: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(5)
    );
i_166: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(4)
    );
i_167: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(3)
    );
i_168: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(2)
    );
i_169: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(1)
    );
i_17: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_17
    );
i_170: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data(0)
    );
i_171: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_data_valid
    );
i_172: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_172
    );
i_173: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_173
    );
i_174: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_174
    );
i_175: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_175
    );
i_176: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_176
    );
i_177: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_177
    );
i_178: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_178
    );
i_179: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_179
    );
i_18: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_18
    );
i_180: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_180
    );
i_181: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_181
    );
i_182: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_182
    );
i_183: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_183
    );
i_184: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_184
    );
i_185: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_185
    );
i_186: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_186
    );
i_187: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_187
    );
i_188: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_188
    );
i_189: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_189
    );
i_19: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_19
    );
i_190: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_190
    );
i_191: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_191
    );
i_192: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_192
    );
i_193: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_193
    );
i_194: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_194
    );
i_195: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_195
    );
i_196: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_196
    );
i_197: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_197
    );
i_198: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_198
    );
i_199: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_199
    );
i_20: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_20
    );
i_200: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_200
    );
i_201: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_201
    );
i_202: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_202
    );
i_203: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_203
    );
i_204: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_204
    );
i_205: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_205
    );
i_206: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_206
    );
i_207: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_207
    );
i_208: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_208
    );
i_209: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_209
    );
i_21: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_21
    );
i_210: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_210
    );
i_211: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_211
    );
i_212: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_212
    );
i_213: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_213
    );
i_214: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_214
    );
i_215: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_215
    );
i_216: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_216
    );
i_217: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_217
    );
i_218: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_218
    );
i_219: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_219
    );
i_22: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_22
    );
i_220: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_220
    );
i_221: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_221
    );
i_222: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_222
    );
i_223: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_223
    );
i_224: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_224
    );
i_225: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_225
    );
i_226: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_226
    );
i_227: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_227
    );
i_228: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_228
    );
i_229: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_229
    );
i_23: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => n_0_23
    );
i_230: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_230
    );
i_231: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_231
    );
i_232: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_232
    );
i_233: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_233
    );
i_234: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_234
    );
i_235: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_235
    );
i_236: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_236
    );
i_237: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_237
    );
i_238: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_238
    );
i_239: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_239
    );
i_240: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_240
    );
i_241: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_241
    );
i_242: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_242
    );
i_243: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_243
    );
i_244: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_244
    );
i_245: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_245
    );
i_246: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_246
    );
i_247: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_247
    );
i_248: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_248
    );
i_249: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_249
    );
i_250: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_250
    );
i_251: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_251
    );
i_252: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_252
    );
i_253: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_253
    );
i_254: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_254
    );
i_255: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_255
    );
i_256: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_256
    );
i_257: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_257
    );
i_258: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_258
    );
i_259: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_259
    );
i_260: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_260
    );
i_261: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_261
    );
i_262: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_262
    );
i_263: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_263
    );
i_264: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_264
    );
i_265: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_265
    );
i_266: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_266
    );
i_267: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_267
    );
i_268: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_268
    );
i_269: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_269
    );
i_270: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_270
    );
i_271: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_271
    );
i_272: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_272
    );
i_273: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_273
    );
i_274: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_274
    );
i_275: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_275
    );
i_276: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_276
    );
i_277: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_277
    );
i_278: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_278
    );
i_279: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_279
    );
i_280: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_280
    );
i_281: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_281
    );
i_282: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_282
    );
i_283: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_283
    );
i_284: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_284
    );
i_285: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_285
    );
i_286: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_286
    );
i_287: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_287
    );
i_288: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_288
    );
i_289: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_289
    );
i_290: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_290
    );
i_291: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_291
    );
i_292: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_292
    );
i_293: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_293
    );
i_294: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_294
    );
i_295: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_295
    );
i_296: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_296
    );
i_297: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_297
    );
i_298: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_298
    );
i_299: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_299
    );
i_300: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_300
    );
i_301: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_301
    );
i_302: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_302
    );
i_303: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_303
    );
i_304: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_304
    );
i_305: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_305
    );
i_306: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_306
    );
i_307: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_307
    );
i_308: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_308
    );
i_309: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_309
    );
i_310: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_310
    );
i_311: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_311
    );
i_312: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_312
    );
i_313: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_313
    );
i_314: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_314
    );
i_315: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_315
    );
i_316: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_316
    );
i_317: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_317
    );
i_318: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_318
    );
i_319: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_319
    );
i_320: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_320
    );
i_321: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_321
    );
i_322: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_322
    );
i_323: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_323
    );
i_324: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_324
    );
i_325: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_325
    );
i_326: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_326
    );
i_327: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_327
    );
i_328: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_328
    );
i_329: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_329
    );
i_330: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_330
    );
i_331: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_331
    );
i_332: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_332
    );
i_333: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_333
    );
i_334: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_334
    );
i_335: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_335
    );
i_336: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_read_received
    );
i_337: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_received
    );
i_338: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(9)
    );
i_339: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(8)
    );
i_340: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(7)
    );
i_341: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(6)
    );
i_342: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(5)
    );
i_343: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(4)
    );
i_344: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(3)
    );
i_345: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(2)
    );
i_346: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(1)
    );
i_347: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_register_number(0)
    );
i_348: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(7)
    );
i_349: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(6)
    );
i_350: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(5)
    );
i_351: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(4)
    );
i_352: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(3)
    );
i_353: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(2)
    );
i_354: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(1)
    );
i_355: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_function_number(0)
    );
i_356: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(31)
    );
i_357: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(30)
    );
i_358: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(29)
    );
i_359: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(28)
    );
i_360: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(27)
    );
i_361: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(26)
    );
i_362: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(25)
    );
i_363: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(24)
    );
i_364: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(23)
    );
i_365: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(22)
    );
i_366: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(21)
    );
i_367: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(20)
    );
i_368: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(19)
    );
i_369: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(18)
    );
i_370: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(17)
    );
i_371: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(16)
    );
i_372: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(15)
    );
i_373: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(14)
    );
i_374: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(13)
    );
i_375: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(12)
    );
i_376: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(11)
    );
i_377: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(10)
    );
i_378: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(9)
    );
i_379: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(8)
    );
i_380: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(7)
    );
i_381: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(6)
    );
i_382: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(5)
    );
i_383: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(4)
    );
i_384: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(3)
    );
i_385: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(2)
    );
i_386: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(1)
    );
i_387: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_data(0)
    );
i_388: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_byte_enable(3)
    );
i_389: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_byte_enable(2)
    );
i_390: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_byte_enable(1)
    );
i_391: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => blk_cfg_ext_write_byte_enable(0)
    );
i_392: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_392
    );
i_393: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_393
    );
i_394: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_394
    );
i_395: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_395
    );
i_396: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_396
    );
i_397: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_397
    );
i_398: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_398
    );
i_399: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_399
    );
i_400: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_400
    );
i_401: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_401
    );
i_402: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_402
    );
i_403: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_403
    );
i_404: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_404
    );
i_405: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_405
    );
i_406: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_406
    );
i_407: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_407
    );
i_408: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_408
    );
i_409: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_409
    );
i_410: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_410
    );
i_411: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_411
    );
i_412: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_412
    );
i_413: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_413
    );
i_414: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_414
    );
i_415: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_415
    );
i_416: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_416
    );
i_417: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_417
    );
i_418: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_418
    );
i_419: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_419
    );
i_42: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_42
    );
i_420: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_420
    );
i_421: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_421
    );
i_422: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_422
    );
i_423: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_423
    );
i_424: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_424
    );
i_425: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_425
    );
i_426: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_426
    );
i_427: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_427
    );
i_428: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_428
    );
i_429: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_429
    );
i_43: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_43
    );
i_430: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_430
    );
i_431: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_431
    );
i_432: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_432
    );
i_433: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_433
    );
i_434: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_434
    );
i_435: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_435
    );
i_436: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_436
    );
i_437: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_437
    );
i_438: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_438
    );
i_439: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_439
    );
i_44: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_44
    );
i_440: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_440
    );
i_441: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_441
    );
i_442: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_442
    );
i_443: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_443
    );
i_444: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_444
    );
i_445: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_445
    );
i_446: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_446
    );
i_447: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_447
    );
i_448: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_448
    );
i_449: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_449
    );
i_45: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_45
    );
i_450: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_450
    );
i_451: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_451
    );
i_452: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_452
    );
i_453: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_453
    );
i_454: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_454
    );
i_455: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_455
    );
i_456: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_456
    );
i_457: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_457
    );
i_458: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_458
    );
i_459: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_459
    );
i_46: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_46
    );
i_460: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_460
    );
i_461: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_461
    );
i_462: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_462
    );
i_463: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_463
    );
i_464: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_464
    );
i_465: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_465
    );
i_466: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_466
    );
i_467: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_467
    );
i_468: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_468
    );
i_469: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_469
    );
i_47: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_47
    );
i_470: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_470
    );
i_471: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_471
    );
i_472: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_472
    );
i_473: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_473
    );
i_474: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_474
    );
i_475: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_475
    );
i_476: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_476
    );
i_477: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_477
    );
i_48: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_48
    );
i_49: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_49
    );
i_62: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_62
    );
i_63: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_63
    );
i_64: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_64
    );
i_65: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_65
    );
i_66: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_66
    );
i_67: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_67
    );
i_68: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_68
    );
i_69: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_69
    );
i_78: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_78
    );
i_79: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_79
    );
i_80: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_80
    );
i_81: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_81
    );
i_82: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_82
    );
i_83: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_83
    );
i_84: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_84
    );
i_85: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_85
    );
i_86: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_86
    );
i_87: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_87
    );
i_88: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_88
    );
i_89: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_89
    );
i_90: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_90
    );
i_91: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_91
    );
i_92: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_92
    );
i_93: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_93
    );
i_94: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_94
    );
i_95: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_95
    );
i_96: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_96
    );
i_97: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_97
    );
i_98: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_98
    );
i_99: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => n_0_99
    );
ram_top: entity work.xdma_0_xdma_v4_1_8_udma_ram_top
     port map (
      \mi_c2h0_dat\\.radr\(8 downto 0) => \mi_c2h0_dat\\.radr\(8 downto 0),
      \mi_c2h0_dat\\.rdat\(511 downto 64) => \NLW_ram_top_mi_c2h0_dat\\.rdat_UNCONNECTED\(511 downto 64),
      \mi_c2h0_dat\\.rdat\(63 downto 0) => \mi_c2h0_dat\\.rdat\(63 downto 0),
      \mi_c2h0_dat\\.rdbe\ => \NLW_ram_top_mi_c2h0_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h0_dat\\.ren\ => '0',
      \mi_c2h0_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h0_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h0_dat\\.rsbe\ => \NLW_ram_top_mi_c2h0_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h0_dat\\.wadr\(8 downto 0) => \mi_c2h0_dat\\.wadr\(8 downto 0),
      \mi_c2h0_dat\\.wdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h0_dat\\.wdat\(63 downto 0) => \mi_c2h0_dat\\.wdat\(63 downto 0),
      \mi_c2h0_dat\\.wen\(1) => '0',
      \mi_c2h0_dat\\.wen\(0) => \mi_c2h0_dat\\.wen\(0),
      \mi_c2h0_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h1_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_c2h1_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h1_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h1_dat\\.rdbe\ => \NLW_ram_top_mi_c2h1_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h1_dat\\.ren\ => '0',
      \mi_c2h1_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h1_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h1_dat\\.rsbe\ => \NLW_ram_top_mi_c2h1_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h1_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_c2h1_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h1_dat\\.wen\(1 downto 0) => B"00",
      \mi_c2h1_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h2_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_c2h2_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h2_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h2_dat\\.rdbe\ => \NLW_ram_top_mi_c2h2_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h2_dat\\.ren\ => '0',
      \mi_c2h2_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h2_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h2_dat\\.rsbe\ => \NLW_ram_top_mi_c2h2_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h2_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_c2h2_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h2_dat\\.wen\(1 downto 0) => B"00",
      \mi_c2h2_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h3_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_c2h3_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h3_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h3_dat\\.rdbe\ => \NLW_ram_top_mi_c2h3_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h3_dat\\.ren\ => '0',
      \mi_c2h3_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h3_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h3_dat\\.rsbe\ => \NLW_ram_top_mi_c2h3_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h3_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_c2h3_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h3_dat\\.wen\(1 downto 0) => B"00",
      \mi_c2h3_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpld\\.radr\(9 downto 0) => B"0000000000",
      \mi_c2h_axi_dsc_cpld\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_axi_dsc_cpld\\.rdbe\ => \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rdbe_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpld\\.ren\ => '0',
      \mi_c2h_axi_dsc_cpld\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_axi_dsc_cpld\\.rsbe\ => \NLW_ram_top_mi_c2h_axi_dsc_cpld\\.rsbe_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpld\\.wadr\(9 downto 0) => B"0000000000",
      \mi_c2h_axi_dsc_cpld\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpld\\.wen\(7 downto 0) => B"00000000",
      \mi_c2h_axi_dsc_cpld\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpli\\.radr\(9 downto 0) => B"0000000000",
      \mi_c2h_axi_dsc_cpli\\.rdat\(79 downto 0) => \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rdat_UNCONNECTED\(79 downto 0),
      \mi_c2h_axi_dsc_cpli\\.rdbe\ => \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rdbe_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpli\\.ren\ => '0',
      \mi_c2h_axi_dsc_cpli\\.rpar\(3 downto 0) => \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rpar_UNCONNECTED\(3 downto 0),
      \mi_c2h_axi_dsc_cpli\\.rsbe\ => \NLW_ram_top_mi_c2h_axi_dsc_cpli\\.rsbe_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpli\\.wadr\(9 downto 0) => B"0000000000",
      \mi_c2h_axi_dsc_cpli\\.wdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpli\\.wen\(7 downto 0) => B"00000000",
      \mi_c2h_axi_dsc_cpli\\.wpar\(3 downto 0) => B"0000",
      \mi_c2h_pcie_dsc_cpld\\.radr\(9) => '0',
      \mi_c2h_pcie_dsc_cpld\\.radr\(8 downto 0) => \mi_c2h_pcie_dsc_cpld\\.radr\(8 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.rdat\(511 downto 64) => \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rdat_UNCONNECTED\(511 downto 64),
      \mi_c2h_pcie_dsc_cpld\\.rdat\(63 downto 0) => \mi_c2h_pcie_dsc_cpld\\.rdat\(63 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.rdbe\ => \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rdbe_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpld\\.ren\ => '1',
      \mi_c2h_pcie_dsc_cpld\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.rsbe\ => \NLW_ram_top_mi_c2h_pcie_dsc_cpld\\.rsbe_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpld\\.wadr\(9) => '0',
      \mi_c2h_pcie_dsc_cpld\\.wadr\(8 downto 0) => \mi_c2h_pcie_dsc_cpld\\.wadr\(8 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.wdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpld\\.wdat\(63 downto 0) => \mi_c2h_pcie_dsc_cpld\\.wdat\(63 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.wen\(7 downto 1) => B"0000000",
      \mi_c2h_pcie_dsc_cpld\\.wen\(0) => \mi_c2h_pcie_dsc_cpld\\.wen\(0),
      \mi_c2h_pcie_dsc_cpld\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpli\\.radr\(9 downto 0) => B"0000000000",
      \mi_c2h_pcie_dsc_cpli\\.rdat\(79 downto 0) => \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rdat_UNCONNECTED\(79 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.rdbe\ => \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rdbe_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpli\\.ren\ => '0',
      \mi_c2h_pcie_dsc_cpli\\.rpar\(3 downto 0) => \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rpar_UNCONNECTED\(3 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.rsbe\ => \NLW_ram_top_mi_c2h_pcie_dsc_cpli\\.rsbe_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpli\\.wadr\(9 downto 0) => B"0000000000",
      \mi_c2h_pcie_dsc_cpli\\.wdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpli\\.wen\(7 downto 0) => B"00000000",
      \mi_c2h_pcie_dsc_cpli\\.wpar\(3 downto 0) => B"0000",
      \mi_c2h_rd_brg_dat\\.radr\(9 downto 0) => B"0000000000",
      \mi_c2h_rd_brg_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h_rd_brg_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_rd_brg_dat\\.rdbe\ => \NLW_ram_top_mi_c2h_rd_brg_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h_rd_brg_dat\\.ren\ => '0',
      \mi_c2h_rd_brg_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h_rd_brg_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_rd_brg_dat\\.rsbe\ => \NLW_ram_top_mi_c2h_rd_brg_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h_rd_brg_dat\\.wadr\(9 downto 0) => B"0000000000",
      \mi_c2h_rd_brg_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_rd_brg_dat\\.wen\(1 downto 0) => B"00",
      \mi_c2h_rd_brg_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_wr_brg_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_c2h_wr_brg_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_c2h_wr_brg_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_wr_brg_dat\\.rdbe\ => \NLW_ram_top_mi_c2h_wr_brg_dat\\.rdbe_UNCONNECTED\,
      \mi_c2h_wr_brg_dat\\.ren\ => '0',
      \mi_c2h_wr_brg_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_c2h_wr_brg_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_wr_brg_dat\\.rsbe\ => \NLW_ram_top_mi_c2h_wr_brg_dat\\.rsbe_UNCONNECTED\,
      \mi_c2h_wr_brg_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_c2h_wr_brg_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_wr_brg_dat\\.wen\(1 downto 0) => B"00",
      \mi_c2h_wr_brg_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_dsc_crd_rcv\\.radr\(11 downto 0) => B"000000000000",
      \mi_dsc_crd_rcv\\.rdat\(15 downto 0) => \NLW_ram_top_mi_dsc_crd_rcv\\.rdat_UNCONNECTED\(15 downto 0),
      \mi_dsc_crd_rcv\\.rdbe\ => \NLW_ram_top_mi_dsc_crd_rcv\\.rdbe_UNCONNECTED\,
      \mi_dsc_crd_rcv\\.ren\ => '0',
      \mi_dsc_crd_rcv\\.rpar\(1 downto 0) => \NLW_ram_top_mi_dsc_crd_rcv\\.rpar_UNCONNECTED\(1 downto 0),
      \mi_dsc_crd_rcv\\.rsbe\ => \NLW_ram_top_mi_dsc_crd_rcv\\.rsbe_UNCONNECTED\,
      \mi_dsc_crd_rcv\\.wadr\(11 downto 0) => B"000000000000",
      \mi_dsc_crd_rcv\\.wdat\(15 downto 0) => B"0000000000000000",
      \mi_dsc_crd_rcv\\.wen\ => '0',
      \mi_dsc_crd_rcv\\.wpar\(1 downto 0) => B"00",
      \mi_h2c0_dat\\.radr\(8 downto 0) => \mi_h2c0_dat\\.radr\(8 downto 0),
      \mi_h2c0_dat\\.rdat\(511 downto 64) => \NLW_ram_top_mi_h2c0_dat\\.rdat_UNCONNECTED\(511 downto 64),
      \mi_h2c0_dat\\.rdat\(63 downto 0) => \mi_h2c0_dat\\.rdat\(63 downto 0),
      \mi_h2c0_dat\\.rdbe\ => \NLW_ram_top_mi_h2c0_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c0_dat\\.ren\ => '0',
      \mi_h2c0_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c0_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c0_dat\\.rsbe\ => \NLW_ram_top_mi_h2c0_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c0_dat\\.wadr\(8 downto 0) => \mi_h2c0_dat\\.wadr\(8 downto 0),
      \mi_h2c0_dat\\.wdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c0_dat\\.wdat\(63 downto 0) => \mi_h2c0_dat\\.wdat\(63 downto 0),
      \mi_h2c0_dat\\.wen\(1) => '0',
      \mi_h2c0_dat\\.wen\(0) => \mi_h2c0_dat\\.wen\(0),
      \mi_h2c0_dat\\.wpar\(63 downto 8) => B"00000000000000000000000000000000000000000000000000000000",
      \mi_h2c0_dat\\.wpar\(7 downto 0) => \mi_h2c0_dat\\.wpar\(7 downto 0),
      \mi_h2c1_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_h2c1_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_h2c1_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_h2c1_dat\\.rdbe\ => \NLW_ram_top_mi_h2c1_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c1_dat\\.ren\ => '0',
      \mi_h2c1_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c1_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c1_dat\\.rsbe\ => \NLW_ram_top_mi_h2c1_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c1_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_h2c1_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c1_dat\\.wen\(1 downto 0) => B"00",
      \mi_h2c1_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c2_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_h2c2_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_h2c2_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_h2c2_dat\\.rdbe\ => \NLW_ram_top_mi_h2c2_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c2_dat\\.ren\ => '0',
      \mi_h2c2_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c2_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c2_dat\\.rsbe\ => \NLW_ram_top_mi_h2c2_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c2_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_h2c2_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c2_dat\\.wen\(1 downto 0) => B"00",
      \mi_h2c2_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c3_dat\\.radr\(8 downto 0) => B"000000000",
      \mi_h2c3_dat\\.rdat\(511 downto 0) => \NLW_ram_top_mi_h2c3_dat\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_h2c3_dat\\.rdbe\ => \NLW_ram_top_mi_h2c3_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c3_dat\\.ren\ => '0',
      \mi_h2c3_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c3_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c3_dat\\.rsbe\ => \NLW_ram_top_mi_h2c3_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c3_dat\\.wadr\(8 downto 0) => B"000000000",
      \mi_h2c3_dat\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c3_dat\\.wen\(1 downto 0) => B"00",
      \mi_h2c3_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpld\\.radr\(9 downto 0) => B"0000000000",
      \mi_h2c_axi_dsc_cpld\\.rdat\(511 downto 0) => \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_h2c_axi_dsc_cpld\\.rdbe\ => \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rdbe_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpld\\.ren\ => '0',
      \mi_h2c_axi_dsc_cpld\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_axi_dsc_cpld\\.rsbe\ => \NLW_ram_top_mi_h2c_axi_dsc_cpld\\.rsbe_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpld\\.wadr\(9 downto 0) => B"0000000000",
      \mi_h2c_axi_dsc_cpld\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpld\\.wen\(7 downto 0) => B"00000000",
      \mi_h2c_axi_dsc_cpld\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpli\\.radr\(9 downto 0) => B"0000000000",
      \mi_h2c_axi_dsc_cpli\\.rdat\(79 downto 0) => \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rdat_UNCONNECTED\(79 downto 0),
      \mi_h2c_axi_dsc_cpli\\.rdbe\ => \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rdbe_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpli\\.ren\ => '0',
      \mi_h2c_axi_dsc_cpli\\.rpar\(3 downto 0) => \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rpar_UNCONNECTED\(3 downto 0),
      \mi_h2c_axi_dsc_cpli\\.rsbe\ => \NLW_ram_top_mi_h2c_axi_dsc_cpli\\.rsbe_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpli\\.wadr\(9 downto 0) => B"0000000000",
      \mi_h2c_axi_dsc_cpli\\.wdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpli\\.wen\(7 downto 0) => B"00000000",
      \mi_h2c_axi_dsc_cpli\\.wpar\(3 downto 0) => B"0000",
      \mi_h2c_pcie_dsc_cpld\\.radr\(9 downto 0) => B"0000000000",
      \mi_h2c_pcie_dsc_cpld\\.rdat\(511 downto 0) => \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rdat_UNCONNECTED\(511 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.rdbe\ => \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rdbe_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpld\\.ren\ => '0',
      \mi_h2c_pcie_dsc_cpld\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.rsbe\ => \NLW_ram_top_mi_h2c_pcie_dsc_cpld\\.rsbe_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpld\\.wadr\(9 downto 0) => B"0000000000",
      \mi_h2c_pcie_dsc_cpld\\.wdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpld\\.wen\(7 downto 0) => B"00000000",
      \mi_h2c_pcie_dsc_cpld\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpli\\.radr\(9 downto 0) => B"0000000000",
      \mi_h2c_pcie_dsc_cpli\\.rdat\(79 downto 0) => \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rdat_UNCONNECTED\(79 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.rdbe\ => \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rdbe_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpli\\.ren\ => '0',
      \mi_h2c_pcie_dsc_cpli\\.rpar\(3 downto 0) => \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rpar_UNCONNECTED\(3 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.rsbe\ => \NLW_ram_top_mi_h2c_pcie_dsc_cpli\\.rsbe_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpli\\.wadr\(9 downto 0) => B"0000000000",
      \mi_h2c_pcie_dsc_cpli\\.wdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpli\\.wen\(7 downto 0) => B"00000000",
      \mi_h2c_pcie_dsc_cpli\\.wpar\(3 downto 0) => B"0000",
      \mi_h2c_rd_brg_dat\\.radr\(8 downto 0) => \mi_h2c_rd_brg_dat\\.radr\(8 downto 0),
      \mi_h2c_rd_brg_dat\\.rdat\(511 downto 64) => \NLW_ram_top_mi_h2c_rd_brg_dat\\.rdat_UNCONNECTED\(511 downto 64),
      \mi_h2c_rd_brg_dat\\.rdat\(63 downto 0) => \mi_h2c_rd_brg_dat\\.rdat\(63 downto 0),
      \mi_h2c_rd_brg_dat\\.rdbe\ => \NLW_ram_top_mi_h2c_rd_brg_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c_rd_brg_dat\\.ren\ => '1',
      \mi_h2c_rd_brg_dat\\.rpar\(63 downto 0) => \NLW_ram_top_mi_h2c_rd_brg_dat\\.rpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_rd_brg_dat\\.rsbe\ => \NLW_ram_top_mi_h2c_rd_brg_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c_rd_brg_dat\\.wadr\(8 downto 0) => \mi_h2c_rd_brg_dat\\.wadr\(8 downto 0),
      \mi_h2c_rd_brg_dat\\.wdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_rd_brg_dat\\.wdat\(63 downto 0) => \mi_h2c_rd_brg_dat\\.wdat\(63 downto 0),
      \mi_h2c_rd_brg_dat\\.wen\(1) => '0',
      \mi_h2c_rd_brg_dat\\.wen\(0) => \mi_h2c_rd_brg_dat\\.wen\(0),
      \mi_h2c_rd_brg_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_wr_brg_dat\\.radr\(10 downto 9) => B"00",
      \mi_h2c_wr_brg_dat\\.radr\(8 downto 0) => \mi_h2c_wr_brg_dat\\.radr\(8 downto 0),
      \mi_h2c_wr_brg_dat\\.rdat\(511 downto 64) => \NLW_ram_top_mi_h2c_wr_brg_dat\\.rdat_UNCONNECTED\(511 downto 64),
      \mi_h2c_wr_brg_dat\\.rdat\(63 downto 0) => \mi_h2c_wr_brg_dat\\.rdat\(63 downto 0),
      \mi_h2c_wr_brg_dat\\.rdbe\ => \NLW_ram_top_mi_h2c_wr_brg_dat\\.rdbe_UNCONNECTED\,
      \mi_h2c_wr_brg_dat\\.ren\ => '1',
      \mi_h2c_wr_brg_dat\\.rpar\(63 downto 8) => \NLW_ram_top_mi_h2c_wr_brg_dat\\.rpar_UNCONNECTED\(63 downto 8),
      \mi_h2c_wr_brg_dat\\.rpar\(7 downto 0) => \mi_h2c_wr_brg_dat\\.rpar\(7 downto 0),
      \mi_h2c_wr_brg_dat\\.rsbe\ => \NLW_ram_top_mi_h2c_wr_brg_dat\\.rsbe_UNCONNECTED\,
      \mi_h2c_wr_brg_dat\\.wadr\(10 downto 9) => B"00",
      \mi_h2c_wr_brg_dat\\.wadr\(8 downto 0) => \mi_h2c_wr_brg_dat\\.wadr\(8 downto 0),
      \mi_h2c_wr_brg_dat\\.wdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_wr_brg_dat\\.wdat\(63 downto 0) => \mi_h2c_wr_brg_dat\\.wdat\(63 downto 0),
      \mi_h2c_wr_brg_dat\\.wen\(1) => '0',
      \mi_h2c_wr_brg_dat\\.wen\(0) => \mi_h2c_wr_brg_dat\\.wen\(0),
      \mi_h2c_wr_brg_dat\\.wpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_hw_ctxt\\.radr\(11 downto 0) => B"000000000000",
      \mi_hw_ctxt\\.rdat\(31 downto 0) => \NLW_ram_top_mi_hw_ctxt\\.rdat_UNCONNECTED\(31 downto 0),
      \mi_hw_ctxt\\.rdbe\ => \NLW_ram_top_mi_hw_ctxt\\.rdbe_UNCONNECTED\,
      \mi_hw_ctxt\\.ren\ => '0',
      \mi_hw_ctxt\\.rpar\(7 downto 0) => \NLW_ram_top_mi_hw_ctxt\\.rpar_UNCONNECTED\(7 downto 0),
      \mi_hw_ctxt\\.rsbe\ => \NLW_ram_top_mi_hw_ctxt\\.rsbe_UNCONNECTED\,
      \mi_hw_ctxt\\.wadr\(11 downto 0) => B"000000000000",
      \mi_hw_ctxt\\.wdat\(31 downto 0) => B"00000000000000000000000000000000",
      \mi_hw_ctxt\\.wen\ => '0',
      \mi_hw_ctxt\\.wpar\(7 downto 0) => B"00000000",
      \mi_sw_ctxt\\.radr\(11 downto 0) => B"000000000000",
      \mi_sw_ctxt\\.rdat\(127 downto 0) => \NLW_ram_top_mi_sw_ctxt\\.rdat_UNCONNECTED\(127 downto 0),
      \mi_sw_ctxt\\.rdbe\ => \NLW_ram_top_mi_sw_ctxt\\.rdbe_UNCONNECTED\,
      \mi_sw_ctxt\\.ren\ => '0',
      \mi_sw_ctxt\\.rpar\(7 downto 0) => \NLW_ram_top_mi_sw_ctxt\\.rpar_UNCONNECTED\(7 downto 0),
      \mi_sw_ctxt\\.rsbe\ => \NLW_ram_top_mi_sw_ctxt\\.rsbe_UNCONNECTED\,
      \mi_sw_ctxt\\.wadr\(11 downto 0) => B"000000000000",
      \mi_sw_ctxt\\.wdat\(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_sw_ctxt\\.wen\(3 downto 0) => B"0000",
      \mi_sw_ctxt\\.wpar\(7 downto 0) => B"00000000",
      \mi_wb_base_ctxt\\.radr\(11 downto 0) => B"000000000000",
      \mi_wb_base_ctxt\\.rdat\(127 downto 0) => \NLW_ram_top_mi_wb_base_ctxt\\.rdat_UNCONNECTED\(127 downto 0),
      \mi_wb_base_ctxt\\.rdbe\ => \NLW_ram_top_mi_wb_base_ctxt\\.rdbe_UNCONNECTED\,
      \mi_wb_base_ctxt\\.ren\ => '0',
      \mi_wb_base_ctxt\\.rpar\(7 downto 0) => \NLW_ram_top_mi_wb_base_ctxt\\.rpar_UNCONNECTED\(7 downto 0),
      \mi_wb_base_ctxt\\.rsbe\ => \NLW_ram_top_mi_wb_base_ctxt\\.rsbe_UNCONNECTED\,
      \mi_wb_base_ctxt\\.wadr\(11 downto 0) => B"000000000000",
      \mi_wb_base_ctxt\\.wdat\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_wb_base_ctxt\\.wen\(1 downto 0) => B"00",
      \mi_wb_base_ctxt\\.wpar\(7 downto 0) => B"00000000",
      user_clk => \^axi_aclk\
    );
sys_rst_n_reg2_reg: unisim.vcomponents.FDCE
     port map (
      C => \^axi_aclk\,
      CE => '1',
      CLR => sys_rst_n_reg_i_1_n_0,
      D => sys_rst_n_reg,
      Q => sys_rst_n_reg2
    );
sys_rst_n_reg_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst_n,
      O => sys_rst_n_reg_i_1_n_0
    );
sys_rst_n_reg_reg: unisim.vcomponents.FDCE
     port map (
      C => \^axi_aclk\,
      CE => '1',
      CLR => sys_rst_n_reg_i_1_n_0,
      D => '1',
      Q => sys_rst_n_reg
    );
udma_wrapper: entity work.xdma_0_xdma_v4_1_8_udma_wrapper
     port map (
      \attr_dma[axi_slv_brdg_base_addr]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma[axi_slv_multq_base_addr]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma[axi_slv_xdma_base_addr]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma[axibar_num]\(2 downto 0) => B"000",
      \attr_dma[barlite0]\(2 downto 0) => B"111",
      \attr_dma[barlite1]\(2 downto 0) => B"000",
      \attr_dma[bypass_msix]\ => '0',
      \attr_dma[ch_c2h_axi_dsc]\(3 downto 0) => B"0000",
      \attr_dma[ch_en]\(3 downto 0) => B"0000",
      \attr_dma[ch_h2c_axi_dsc]\(3 downto 0) => B"0000",
      \attr_dma[ch_multq]\(3 downto 0) => B"0000",
      \attr_dma[ch_multq_ll]\(3 downto 0) => B"0000",
      \attr_dma[ch_multq_max][0]\(5 downto 0) => B"000000",
      \attr_dma[ch_multq_max][1]\(5 downto 0) => B"000000",
      \attr_dma[ch_multq_max][2]\(5 downto 0) => B"000000",
      \attr_dma[ch_multq_max][3]\(5 downto 0) => B"000000",
      \attr_dma[ch_pfid][0]\(1 downto 0) => B"00",
      \attr_dma[ch_pfid][1]\(1 downto 0) => B"00",
      \attr_dma[ch_pfid][2]\(1 downto 0) => B"00",
      \attr_dma[ch_pfid][3]\(1 downto 0) => B"00",
      \attr_dma[ch_stream]\(3 downto 0) => B"0000",
      \attr_dma[cq_rcfg_en]\ => '1',
      \attr_dma[data_width]\(2 downto 0) => B"000",
      \attr_dma[enable]\ => '0',
      \attr_dma[mask50]\(5 downto 0) => B"000111",
      \attr_dma[metering_enable]\ => '1',
      \attr_dma[msi_rx_decode_en]\ => '1',
      \attr_dma[pcie_if_parity_check]\ => '0',
      \attr_dma[pciebar_num]\(2 downto 0) => B"000",
      \attr_dma[root_port]\ => '0',
      \attr_dma[rq_rcfg_en]\ => '0',
      \attr_dma[slvlite_base0]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma[slvlite_base1]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma[spare][axi_parity_chk_dis]\ => '0',
      \attr_dma[spare][axi_slv_brdge_range]\ => '0',
      \attr_dma[spare][axim_auser_mode]\ => '0',
      \attr_dma[spare][axis_h2c_ext_cmp_en]\ => '0',
      \attr_dma[spare][bdg_mst_rw_rlx_dis]\ => '0',
      \attr_dma[spare][brdg_rro_en]\ => '0',
      \attr_dma[spare][brdg_slv_pasid_en]\ => '0',
      \attr_dma[spare][brdg_slv_pasid_offset]\(11 downto 0) => B"000000000000",
      \attr_dma[spare][brdg_slv_shared_rdwr_pasid_dis]\ => '0',
      \attr_dma[spare][brdg_slv_wr_pasid_offset]\(11 downto 0) => B"000000000000",
      \attr_dma[spare][cfg_mgmt_ep_wr_dis]\ => '0',
      \attr_dma[spare][cfg_space_delay_en]\ => '0',
      \attr_dma[spare][dis_acc_irq]\ => '0',
      \attr_dma[spare][dis_c2h_ctxt_mgr_fix]\ => '0',
      \attr_dma[spare][dis_crdt_coal_depth_fix]\ => '0',
      \attr_dma[spare][dis_h2c_sbe_dbe_err_fix]\ => '0',
      \attr_dma[spare][dis_h2c_wrb_on_src_err_fix]\ => '0',
      \attr_dma[spare][dis_pfch_evict_cache_fix]\ => '0',
      \attr_dma[spare][dis_pfch_evict_lru_fix]\ => '0',
      \attr_dma[spare][dis_timer_stall_fix]\ => '0',
      \attr_dma[spare][dis_wrb_bad_cidx_chk_fix]\ => '0',
      \attr_dma[spare][dis_wrb_prty_chk_fix]\ => '0',
      \attr_dma[spare][dis_xdma_wcp_err_bsy_clr]\ => '0',
      \attr_dma[spare][disable_port_id_check]\ => '0',
      \attr_dma[spare][dma_aximm_rsp_clr]\ => '0',
      \attr_dma[spare][dma_bar_ext_en]\ => '0',
      \attr_dma[spare][dma_mm_linkdown_reset_dis]\ => '0',
      \attr_dma[spare][dma_rq_0len_dis]\ => '0',
      \attr_dma[spare][dma_rst_rc_rdy]\ => '0',
      \attr_dma[spare][dsc_ctxt_err_on_rcp_flr_dis]\ => '0',
      \attr_dma[spare][dsc_ctxt_err_on_rcp_ur_ca_dis]\ => '0',
      \attr_dma[spare][dsc_ctxt_is_mm_en]\ => '0',
      \attr_dma[spare][dsc_ecc_chk_dis]\ => '0',
      \attr_dma[spare][dsc_qinv_on_err_dis]\ => '0',
      \attr_dma[spare][dsc_rcp_evt_pri]\ => '0',
      \attr_dma[spare][dsc_stall_irq_fl_dis]\ => '0',
      \attr_dma[spare][dsc_upd_ovf_dis]\ => '0',
      \attr_dma[spare][exp_rom_bar_to_axil]\ => '0',
      \attr_dma[spare][fab_wb_dis]\ => '0',
      \attr_dma[spare][fabric_reset_en]\ => '0',
      \attr_dma[spare][fix_dbe_parity_dis]\ => '0',
      \attr_dma[spare][full_upd_fix_dis]\ => '0',
      \attr_dma[spare][ign_byp_irq_arm]\ => '0',
      \attr_dma[spare][ign_pidx_upd_on_irq_arm]\ => '0',
      \attr_dma[spare][mdma_dsc_wb_chk_all]\ => '0',
      \attr_dma[spare][mdma_dsc_wb_imm_all]\ => '0',
      \attr_dma[spare][mdma_eng_err_halt]\ => '0',
      \attr_dma[spare][mdma_one_err_wb_dis]\ => '0',
      \attr_dma[spare][mdma_sw_ctxt_clr_all]\ => '0',
      \attr_dma[spare][mgmt_flr_done_en]\ => '0',
      \attr_dma[spare][mgmt_flr_done_src_dis]\(3 downto 0) => B"0000",
      \attr_dma[spare][misc_cap]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma[spare][mm_err_wbk_fix_dis]\ => '0',
      \attr_dma[spare][mm_wbrq_ovf_fix_dis]\ => '0',
      \attr_dma[spare][pasid_en]\ => '0',
      \attr_dma[spare][pcie_mpl_reg_en]\ => '0',
      \attr_dma[spare][pcie_mrs_reg_en]\ => '0',
      \attr_dma[spare][pcie_rc_unmask_uc]\ => '0',
      \attr_dma[spare][pcie_rq_pf_flr_check_dis]\ => '0',
      \attr_dma[spare][pcie_rq_vf_bme_check_dis]\ => '0',
      \attr_dma[spare][pcie_rq_vf_flr_check_dis]\ => '0',
      \attr_dma[spare][qinv_arb_stall]\ => '0',
      \attr_dma[spare][qinv_cnt_limit]\(3 downto 0) => B"0000",
      \attr_dma[spare][qinv_limit_en]\ => '0',
      \attr_dma[spare][rcv_crd_chk_dis]\ => '0',
      \attr_dma[spare][rq_flr_check_dis]\ => '0',
      \attr_dma[spare][rrq_disable_en]\ => '0',
      \attr_dma[spare][rsv_use_h2c_data_aln]\ => '0',
      \attr_dma[spare][shared_rdwr_pasid_dis]\ => '0',
      \attr_dma[spare][slv_bresp_fix_dis]\ => '0',
      \attr_dma[spare][slv_fnc_msk]\(7 downto 0) => B"00000000",
      \attr_dma[spare][st_rx_msg_if_en]\ => '0',
      \attr_dma[spare][sw_crdt_fix_dis]\ => '0',
      \attr_dma[spare][system_id]\(15 downto 0) => B"0000000000000000",
      \attr_dma[spare][system_id_ovr]\ => '0',
      \attr_dma[spare][tcp_timeout_exp]\(4 downto 0) => B"00000",
      \attr_dma[spare][tm_dsc_sts_pidx_en]\ => '0',
      \attr_dma[spare][trq_timeout_dat]\ => '0',
      \attr_dma[spare][trq_timeout_rsp]\ => '0',
      \attr_dma[spare][unused]\(255 downto 213) => B"0000000000000000000000000000000000000000000",
      \attr_dma[spare][use_stm_dsc_format]\ => '0',
      \attr_dma[spare][vf_bar_num]\(2 downto 0) => B"000",
      \attr_dma[spare][wb_sts_all]\ => '0',
      \attr_dma[spare][wr_cmp_fix_dis]\ => '0',
      \attr_dma[spare][xdma_byp_eng_flr_done]\ => '0',
      \attr_dma[spare][xdma_c2h_axi_wr_cache][0]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_c2h_axi_wr_cache][1]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_c2h_axi_wr_cache][2]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_c2h_axi_wr_cache][3]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_c2h_axi_wr_sec]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_drain_dat_en]\ => '0',
      \attr_dma[spare][xdma_drain_dsc_en]\ => '0',
      \attr_dma[spare][xdma_h2c_axi_rd_cache][0]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_h2c_axi_rd_cache][1]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_h2c_axi_rd_cache][2]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_h2c_axi_rd_cache][3]\(3 downto 0) => B"0000",
      \attr_dma[spare][xdma_h2c_axi_rd_sec]\(3 downto 0) => B"0000",
      \attr_dma_axibar2pciebar[0][as]\ => '0',
      \attr_dma_axibar2pciebar[0][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[0][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[0][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_axibar2pciebar[1][as]\ => '0',
      \attr_dma_axibar2pciebar[1][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[1][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[1][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_axibar2pciebar[2][as]\ => '0',
      \attr_dma_axibar2pciebar[2][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[2][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[2][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_axibar2pciebar[3][as]\ => '0',
      \attr_dma_axibar2pciebar[3][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[3][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[3][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_axibar2pciebar[4][as]\ => '0',
      \attr_dma_axibar2pciebar[4][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[4][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[4][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_axibar2pciebar[5][as]\ => '0',
      \attr_dma_axibar2pciebar[5][bar]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[5][base]\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \attr_dma_axibar2pciebar[5][highaddr]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][0][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][0][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][0][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][0][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][0][len]\(7 downto 0) => B"00010000",
      \attr_dma_pciebar2axibar_pf[0][0][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][0][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][0][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][1][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][1][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][1][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][1][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][1][len]\(7 downto 0) => B"00010100",
      \attr_dma_pciebar2axibar_pf[0][1][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][1][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][1][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][2][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][2][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][2][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][2][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][2][len]\(7 downto 0) => B"01000000",
      \attr_dma_pciebar2axibar_pf[0][2][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][2][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][2][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][3][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][3][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][3][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][3][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][3][len]\(7 downto 0) => B"01000000",
      \attr_dma_pciebar2axibar_pf[0][3][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][3][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][3][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][4][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][4][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][4][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][4][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][4][len]\(7 downto 0) => B"01000000",
      \attr_dma_pciebar2axibar_pf[0][4][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][4][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][4][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][5][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][5][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][5][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][5][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][5][len]\(7 downto 0) => B"01000000",
      \attr_dma_pciebar2axibar_pf[0][5][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][5][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][5][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][6][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][6][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[0][6][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][6][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[0][6][len]\(7 downto 0) => B"00000111",
      \attr_dma_pciebar2axibar_pf[0][6][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[0][6][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[0][6][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][0][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][0][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][0][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][0][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][0][len]\(7 downto 0) => B"00011001",
      \attr_dma_pciebar2axibar_pf[1][0][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][0][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][0][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][1][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][1][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][1][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][1][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][1][len]\(7 downto 0) => B"00010001",
      \attr_dma_pciebar2axibar_pf[1][1][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][1][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][1][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][2][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][2][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][2][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][2][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][2][len]\(7 downto 0) => B"00010001",
      \attr_dma_pciebar2axibar_pf[1][2][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][2][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][2][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][3][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][3][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][3][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][3][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][3][len]\(7 downto 0) => B"00010001",
      \attr_dma_pciebar2axibar_pf[1][3][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][3][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][3][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][4][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][4][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][4][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][4][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][4][len]\(7 downto 0) => B"00010001",
      \attr_dma_pciebar2axibar_pf[1][4][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][4][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][4][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][5][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][5][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][5][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][5][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][5][len]\(7 downto 0) => B"00010001",
      \attr_dma_pciebar2axibar_pf[1][5][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][5][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][5][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][6][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][6][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[1][6][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][6][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[1][6][len]\(7 downto 0) => B"00000111",
      \attr_dma_pciebar2axibar_pf[1][6][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[1][6][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[1][6][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][0][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][0][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][0][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][0][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][0][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][0][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][0][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][0][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][1][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][1][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][1][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][1][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][1][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][1][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][1][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][1][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][2][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][2][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][2][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][2][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][2][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][2][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][2][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][2][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][3][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][3][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][3][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][3][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][3][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][3][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][3][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][3][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][4][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][4][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][4][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][4][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][4][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][4][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][4][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][4][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][5][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][5][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][5][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][5][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][5][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][5][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][5][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][5][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][6][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][6][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[2][6][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][6][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[2][6][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][6][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[2][6][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[2][6][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][0][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][0][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][0][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][0][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][0][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][0][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][0][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][0][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][1][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][1][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][1][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][1][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][1][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][1][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][1][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][1][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][2][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][2][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][2][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][2][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][2][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][2][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][2][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][2][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][3][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][3][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][3][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][3][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][3][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][3][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][3][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][3][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][4][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][4][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][4][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][4][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][4][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][4][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][4][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][4][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][5][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][5][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][5][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][5][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][5][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][5][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][5][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][5][sec_vf]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][6][bar]\(63 downto 12) => B"0000000000000000000000000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][6][bar_vf]\(31 downto 0) => B"00000000000000000000000000000000",
      \attr_dma_pciebar2axibar_pf[3][6][cache]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][6][cache_vf]\(3 downto 0) => B"0000",
      \attr_dma_pciebar2axibar_pf[3][6][len]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][6][len_vf]\(7 downto 0) => B"00000000",
      \attr_dma_pciebar2axibar_pf[3][6][sec]\ => '0',
      \attr_dma_pciebar2axibar_pf[3][6][sec_vf]\ => '0',
      \attr_dma_pf[0][ch_alloc]\(3 downto 0) => B"0000",
      \attr_dma_pf[0][firstvf_offset]\(7 downto 0) => B"00000000",
      \attr_dma_pf[0][multq_bits]\(2 downto 0) => B"000",
      \attr_dma_pf[0][multq_chbits]\(1 downto 0) => B"00",
      \attr_dma_pf[0][multq_maxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[0][multq_vfqbits]\(2 downto 0) => B"000",
      \attr_dma_pf[0][num_vfs]\(7 downto 0) => B"00000000",
      \attr_dma_pf[0][vfmaxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[1][ch_alloc]\(3 downto 0) => B"0000",
      \attr_dma_pf[1][firstvf_offset]\(7 downto 0) => B"00000000",
      \attr_dma_pf[1][multq_bits]\(2 downto 0) => B"000",
      \attr_dma_pf[1][multq_chbits]\(1 downto 0) => B"00",
      \attr_dma_pf[1][multq_maxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[1][multq_vfqbits]\(2 downto 0) => B"000",
      \attr_dma_pf[1][num_vfs]\(7 downto 0) => B"00000000",
      \attr_dma_pf[1][vfmaxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[2][ch_alloc]\(3 downto 0) => B"0000",
      \attr_dma_pf[2][firstvf_offset]\(7 downto 0) => B"00000000",
      \attr_dma_pf[2][multq_bits]\(2 downto 0) => B"000",
      \attr_dma_pf[2][multq_chbits]\(1 downto 0) => B"00",
      \attr_dma_pf[2][multq_maxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[2][multq_vfqbits]\(2 downto 0) => B"000",
      \attr_dma_pf[2][num_vfs]\(7 downto 0) => B"00000000",
      \attr_dma_pf[2][vfmaxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[3][ch_alloc]\(3 downto 0) => B"0000",
      \attr_dma_pf[3][firstvf_offset]\(7 downto 0) => B"00000000",
      \attr_dma_pf[3][multq_bits]\(2 downto 0) => B"000",
      \attr_dma_pf[3][multq_chbits]\(1 downto 0) => B"00",
      \attr_dma_pf[3][multq_maxq]\(5 downto 0) => B"000000",
      \attr_dma_pf[3][multq_vfqbits]\(2 downto 0) => B"000",
      \attr_dma_pf[3][num_vfs]\(7 downto 0) => B"00000000",
      \attr_dma_pf[3][vfmaxq]\(5 downto 0) => B"000000",
      axi_aresetn => NLW_udma_wrapper_axi_aresetn_UNCONNECTED,
      blk_cfg_ext_function_number_i(7 downto 0) => B"00000000",
      blk_cfg_ext_read_data_o(31 downto 0) => NLW_udma_wrapper_blk_cfg_ext_read_data_o_UNCONNECTED(31 downto 0),
      blk_cfg_ext_read_data_valid_o => NLW_udma_wrapper_blk_cfg_ext_read_data_valid_o_UNCONNECTED,
      blk_cfg_ext_read_received_i => '0',
      blk_cfg_ext_register_number_i(9 downto 0) => B"0000000000",
      blk_cfg_ext_write_byte_enable_i(3 downto 0) => B"0000",
      blk_cfg_ext_write_data_i(31 downto 0) => B"00000000000000000000000000000000",
      blk_cfg_ext_write_received_i => '0',
      \c2h_desc_avail_inc_num[0]\(12 downto 0) => \NLW_udma_wrapper_c2h_desc_avail_inc_num[0]_UNCONNECTED\(12 downto 0),
      \c2h_desc_avail_inc_qid[0]\(4 downto 0) => \NLW_udma_wrapper_c2h_desc_avail_inc_qid[0]_UNCONNECTED\(4 downto 0),
      c2h_desc_avail_inc_vld(0) => NLW_udma_wrapper_c2h_desc_avail_inc_vld_UNCONNECTED(0),
      c2h_dsc_byp_ctl(15 downto 0) => B"0000000000000000",
      c2h_dsc_byp_dst_addr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_len(27 downto 0) => B"0000000000000000000000000000",
      c2h_dsc_byp_load(0) => '0',
      c2h_dsc_byp_ready(0) => NLW_udma_wrapper_c2h_dsc_byp_ready_UNCONNECTED(0),
      c2h_dsc_byp_src_addr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_pktin_accept(0) => NLW_udma_wrapper_c2h_pktin_accept_UNCONNECTED(0),
      \c2h_pktin_drop[0]\(7 downto 0) => \NLW_udma_wrapper_c2h_pktin_drop[0]_UNCONNECTED\(7 downto 0),
      c2h_sts(7 downto 0) => NLW_udma_wrapper_c2h_sts_UNCONNECTED(7 downto 0),
      cfg_status_ats_en => NLW_udma_wrapper_cfg_status_ats_en_UNCONNECTED,
      cfg_status_ats_stu(4 downto 0) => NLW_udma_wrapper_cfg_status_ats_stu_UNCONNECTED(4 downto 0),
      cfg_status_clr_s => '0',
      cfg_status_ost_pr_alloc(31 downto 0) => NLW_udma_wrapper_cfg_status_ost_pr_alloc_UNCONNECTED(31 downto 0),
      cfg_status_pr_en => NLW_udma_wrapper_cfg_status_pr_en_UNCONNECTED,
      cfg_status_pr_rf => NLW_udma_wrapper_cfg_status_pr_rf_UNCONNECTED,
      cfg_status_pr_rst => NLW_udma_wrapper_cfg_status_pr_rst_UNCONNECTED,
      cfg_status_pr_uprgi => NLW_udma_wrapper_cfg_status_pr_uprgi_UNCONNECTED,
      cfg_status_set_rf => '0',
      cfg_status_set_s => '0',
      cfg_status_set_uprgi => '0',
      \dsc_in\\.crd[num]\(8 downto 0) => \NLW_udma_wrapper_dsc_in\\.crd[num]_UNCONNECTED\(8 downto 0),
      \dsc_in\\.crd[qid]\(7 downto 0) => \NLW_udma_wrapper_dsc_in\\.crd[qid]_UNCONNECTED\(7 downto 0),
      \dsc_in\\.crd[vld]\ => \NLW_udma_wrapper_dsc_in\\.crd[vld]_UNCONNECTED\,
      \dsc_in\\.dsc[chn]\(1 downto 0) => B"00",
      \dsc_in\\.dsc[cidx]\(15 downto 0) => B"0000000000000000",
      \dsc_in\\.dsc[dir]\ => '0',
      \dsc_in\\.dsc[dsc]\(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \dsc_in\\.dsc[qid]\(7 downto 0) => B"00000000",
      \dsc_in\\.dsc[qst]\(3 downto 0) => B"0000",
      \dsc_in\\.dsc[siz]\(2 downto 0) => B"000",
      \dsc_in\\.dsc[vld]\(3 downto 0) => B"0000",
      \dsc_in\\.dsc[wbi]\ => '0',
      \dsc_in\\.dsc[wbi_chk]\ => '0',
      \dsc_out\\.crd[chn]\(1 downto 0) => B"00",
      \dsc_out\\.crd[clr]\ => '0',
      \dsc_out\\.crd[num]\(8 downto 0) => B"000000000",
      \dsc_out\\.crd[qid]\(7 downto 0) => B"00000000",
      \dsc_out\\.crd[vld]\ => '0',
      \dsc_out\\.dsc[chn]\(1 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[chn]_UNCONNECTED\(1 downto 0),
      \dsc_out\\.dsc[cidx]\(15 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[cidx]_UNCONNECTED\(15 downto 0),
      \dsc_out\\.dsc[dir]\ => \NLW_udma_wrapper_dsc_out\\.dsc[dir]_UNCONNECTED\,
      \dsc_out\\.dsc[dsc]\(255 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[dsc]_UNCONNECTED\(255 downto 0),
      \dsc_out\\.dsc[qid]\(7 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[qid]_UNCONNECTED\(7 downto 0),
      \dsc_out\\.dsc[qst]\(3 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[qst]_UNCONNECTED\(3 downto 0),
      \dsc_out\\.dsc[siz]\(2 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[siz]_UNCONNECTED\(2 downto 0),
      \dsc_out\\.dsc[vld]\(3 downto 0) => \NLW_udma_wrapper_dsc_out\\.dsc[vld]_UNCONNECTED\(3 downto 0),
      \dsc_out\\.dsc[wbi]\ => \NLW_udma_wrapper_dsc_out\\.dsc[wbi]_UNCONNECTED\,
      \dsc_out\\.dsc[wbi_chk]\ => \NLW_udma_wrapper_dsc_out\\.dsc[wbi_chk]_UNCONNECTED\,
      \fabric_in\\.flr_done_fnc\(7 downto 0) => B"00000000",
      \fabric_in\\.flr_done_vld\ => '0',
      \fabric_in\\.usr_irq_clr\ => '0',
      \fabric_in\\.usr_irq_fnc\(7 downto 0) => B"00000000",
      \fabric_in\\.usr_irq_set\ => '0',
      \fabric_in\\.usr_irq_vec\(4 downto 0) => B"00000",
      \fabric_out\\.c2h_dsc_avail_inc_chn\(1 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_chn_UNCONNECTED\(1 downto 0),
      \fabric_out\\.c2h_dsc_avail_inc_num\(15 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_num_UNCONNECTED\(15 downto 0),
      \fabric_out\\.c2h_dsc_avail_inc_qid\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_qid_UNCONNECTED\(7 downto 0),
      \fabric_out\\.c2h_dsc_avail_inc_state\(1 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_state_UNCONNECTED\(1 downto 0),
      \fabric_out\\.c2h_dsc_avail_inc_vld\ => \NLW_udma_wrapper_fabric_out\\.c2h_dsc_avail_inc_vld_UNCONNECTED\,
      \fabric_out\\.c2h_sts[0]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_sts[0]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.c2h_sts[1]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_sts[1]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.c2h_sts[2]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_sts[2]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.c2h_sts[3]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.c2h_sts[3]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.flr_clr\ => \NLW_udma_wrapper_fabric_out\\.flr_clr_UNCONNECTED\,
      \fabric_out\\.flr_fnc\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.flr_fnc_UNCONNECTED\(7 downto 0),
      \fabric_out\\.flr_set\ => \NLW_udma_wrapper_fabric_out\\.flr_set_UNCONNECTED\,
      \fabric_out\\.h2c_sts[0]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.h2c_sts[0]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.h2c_sts[1]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.h2c_sts[1]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.h2c_sts[2]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.h2c_sts[2]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.h2c_sts[3]\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.h2c_sts[3]_UNCONNECTED\(7 downto 0),
      \fabric_out\\.s_axis_c2h_tstat\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_UNCONNECTED\(7 downto 0),
      \fabric_out\\.s_axis_c2h_tstat_chn\(1 downto 0) => \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_chn_UNCONNECTED\(1 downto 0),
      \fabric_out\\.s_axis_c2h_tstat_qid\(4 downto 0) => \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_qid_UNCONNECTED\(4 downto 0),
      \fabric_out\\.s_axis_c2h_tstat_vld\ => \NLW_udma_wrapper_fabric_out\\.s_axis_c2h_tstat_vld_UNCONNECTED\,
      \fabric_out\\.usr_irq_fail\ => \NLW_udma_wrapper_fabric_out\\.usr_irq_fail_UNCONNECTED\,
      \fabric_out\\.usr_irq_rfnc\(7 downto 0) => \NLW_udma_wrapper_fabric_out\\.usr_irq_rfnc_UNCONNECTED\(7 downto 0),
      \fabric_out\\.usr_irq_rvec\(4 downto 0) => \NLW_udma_wrapper_fabric_out\\.usr_irq_rvec_UNCONNECTED\(4 downto 0),
      \fabric_out\\.usr_irq_sent\ => \NLW_udma_wrapper_fabric_out\\.usr_irq_sent_UNCONNECTED\,
      h2c_desc_cmd_in_data(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      h2c_desc_cmd_in_qid(4 downto 0) => B"00000",
      h2c_desc_cmd_in_rdy => NLW_udma_wrapper_h2c_desc_cmd_in_rdy_UNCONNECTED,
      h2c_desc_cmd_in_vld => '0',
      h2c_desc_cmd_out_data(127 downto 0) => NLW_udma_wrapper_h2c_desc_cmd_out_data_UNCONNECTED(127 downto 0),
      h2c_desc_cmd_out_qid(4 downto 0) => NLW_udma_wrapper_h2c_desc_cmd_out_qid_UNCONNECTED(4 downto 0),
      h2c_desc_cmd_out_qrdy(31 downto 0) => B"11111111111111111111111111111111",
      h2c_desc_cmd_out_rdy => '0',
      h2c_desc_cmd_out_vld => NLW_udma_wrapper_h2c_desc_cmd_out_vld_UNCONNECTED,
      h2c_dsc_byp_ctl(15 downto 0) => B"0000000000000000",
      h2c_dsc_byp_dst_addr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_len(27 downto 0) => B"0000000000000000000000000000",
      h2c_dsc_byp_load(0) => '0',
      h2c_dsc_byp_ready(0) => NLW_udma_wrapper_h2c_dsc_byp_ready_UNCONNECTED(0),
      h2c_dsc_byp_src_addr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_sts(7 downto 0) => NLW_udma_wrapper_h2c_sts_UNCONNECTED(7 downto 0),
      link_up => \^user_lnk_up\,
      m_axi_araddr(63 downto 0) => m_axi_araddr_temp(63 downto 0),
      m_axi_arburst(1) => NLW_udma_wrapper_m_axi_arburst_UNCONNECTED(1),
      m_axi_arburst(0) => \^m_axi_arburst\(0),
      m_axi_arcache(3 downto 0) => NLW_udma_wrapper_m_axi_arcache_UNCONNECTED(3 downto 0),
      m_axi_arid(3 downto 0) => NLW_udma_wrapper_m_axi_arid_UNCONNECTED(3 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock => NLW_udma_wrapper_m_axi_arlock_UNCONNECTED,
      m_axi_arprot(2 downto 0) => NLW_udma_wrapper_m_axi_arprot_UNCONNECTED(2 downto 0),
      m_axi_arready => m_axi_arready,
      m_axi_arsize(2) => NLW_udma_wrapper_m_axi_arsize_UNCONNECTED(2),
      m_axi_arsize(1 downto 0) => \^m_axi_arsize\(1 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(63 downto 0) => m_axi_awaddr_temp(63 downto 0),
      m_axi_awburst(1) => NLW_udma_wrapper_m_axi_awburst_UNCONNECTED(1),
      m_axi_awburst(0) => \^m_axi_awburst\(0),
      m_axi_awcache(3 downto 0) => NLW_udma_wrapper_m_axi_awcache_UNCONNECTED(3 downto 0),
      m_axi_awid(3 downto 0) => NLW_udma_wrapper_m_axi_awid_UNCONNECTED(3 downto 0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awlock => NLW_udma_wrapper_m_axi_awlock_UNCONNECTED,
      m_axi_awprot(2 downto 0) => NLW_udma_wrapper_m_axi_awprot_UNCONNECTED(2 downto 0),
      m_axi_awready => m_axi_awready,
      m_axi_awsize(2) => NLW_udma_wrapper_m_axi_awsize_UNCONNECTED(2),
      m_axi_awsize(1 downto 0) => \^m_axi_awsize\(1 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
      m_axi_bvalid => m_axi_bvalid,
      m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
      m_axi_rdataeccparity(7 downto 0) => B"00000000",
      m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
      m_axi_rlast => m_axi_rlast,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
      m_axi_rvalid => m_axi_rvalid,
      m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
      m_axi_wdataeccparity(7 downto 0) => NLW_udma_wrapper_m_axi_wdataeccparity_UNCONNECTED(7 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => m_axi_wready,
      m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      m_axib_araddr(63 downto 0) => m_axib_araddr_temp(63 downto 0),
      m_axib_arburst(1 downto 0) => NLW_udma_wrapper_m_axib_arburst_UNCONNECTED(1 downto 0),
      m_axib_arcache(3 downto 0) => NLW_udma_wrapper_m_axib_arcache_UNCONNECTED(3 downto 0),
      m_axib_arid(3 downto 0) => NLW_udma_wrapper_m_axib_arid_UNCONNECTED(3 downto 0),
      m_axib_arlen(7 downto 0) => m_axib_arlen(7 downto 0),
      m_axib_arlock => NLW_udma_wrapper_m_axib_arlock_UNCONNECTED,
      m_axib_arprot(2) => NLW_udma_wrapper_m_axib_arprot_UNCONNECTED(2),
      m_axib_arprot(1 downto 0) => \^m_axib_arprot\(1 downto 0),
      m_axib_arready => m_axib_arready,
      m_axib_arsize(2) => NLW_udma_wrapper_m_axib_arsize_UNCONNECTED(2),
      m_axib_arsize(1 downto 0) => \^m_axib_arsize\(1 downto 0),
      m_axib_aruser(7 downto 0) => NLW_udma_wrapper_m_axib_aruser_UNCONNECTED(7 downto 0),
      m_axib_arvalid => m_axib_arvalid,
      m_axib_awaddr(63 downto 0) => m_axib_awaddr_temp(63 downto 0),
      m_axib_awburst(1 downto 0) => NLW_udma_wrapper_m_axib_awburst_UNCONNECTED(1 downto 0),
      m_axib_awcache(3 downto 0) => NLW_udma_wrapper_m_axib_awcache_UNCONNECTED(3 downto 0),
      m_axib_awid(3 downto 0) => NLW_udma_wrapper_m_axib_awid_UNCONNECTED(3 downto 0),
      m_axib_awlen(7 downto 0) => m_axib_awlen(7 downto 0),
      m_axib_awlock => NLW_udma_wrapper_m_axib_awlock_UNCONNECTED,
      m_axib_awprot(2) => NLW_udma_wrapper_m_axib_awprot_UNCONNECTED(2),
      m_axib_awprot(1 downto 0) => \^m_axib_awprot\(1 downto 0),
      m_axib_awready => m_axib_awready,
      m_axib_awsize(2) => NLW_udma_wrapper_m_axib_awsize_UNCONNECTED(2),
      m_axib_awsize(1 downto 0) => \^m_axib_awsize\(1 downto 0),
      m_axib_awuser(7 downto 0) => NLW_udma_wrapper_m_axib_awuser_UNCONNECTED(7 downto 0),
      m_axib_awvalid => m_axib_awvalid,
      m_axib_bid(3 downto 0) => B"0000",
      m_axib_bready => m_axib_bready,
      m_axib_bresp(1 downto 0) => B"00",
      m_axib_bvalid => m_axib_bvalid,
      m_axib_rdata(63 downto 0) => m_axib_rdata(63 downto 0),
      m_axib_rdataeccparity(7 downto 0) => B"00000000",
      m_axib_rid(3 downto 0) => B"0000",
      m_axib_rlast => m_axib_rlast,
      m_axib_rready => m_axib_rready,
      m_axib_rresp(1 downto 0) => m_axib_rresp(1 downto 0),
      m_axib_rvalid => m_axib_rvalid,
      m_axib_wdata(63 downto 0) => m_axib_wdata(63 downto 0),
      m_axib_wdataeccparity(7) => udma_wrapper_n_12224,
      m_axib_wdataeccparity(6) => udma_wrapper_n_12225,
      m_axib_wdataeccparity(5) => udma_wrapper_n_12226,
      m_axib_wdataeccparity(4) => udma_wrapper_n_12227,
      m_axib_wdataeccparity(3) => udma_wrapper_n_12228,
      m_axib_wdataeccparity(2) => udma_wrapper_n_12229,
      m_axib_wdataeccparity(1) => udma_wrapper_n_12230,
      m_axib_wdataeccparity(0) => udma_wrapper_n_12231,
      m_axib_wlast => m_axib_wlast,
      m_axib_wready => m_axib_wready,
      m_axib_wstrb(7 downto 0) => m_axib_wstrb(7 downto 0),
      m_axib_wvalid => m_axib_wvalid,
      m_axil_araddr(31) => udma_wrapper_n_12673,
      m_axil_araddr(30) => udma_wrapper_n_12674,
      m_axil_araddr(29) => udma_wrapper_n_12675,
      m_axil_araddr(28) => udma_wrapper_n_12676,
      m_axil_araddr(27) => udma_wrapper_n_12677,
      m_axil_araddr(26) => udma_wrapper_n_12678,
      m_axil_araddr(25) => udma_wrapper_n_12679,
      m_axil_araddr(24) => udma_wrapper_n_12680,
      m_axil_araddr(23) => udma_wrapper_n_12681,
      m_axil_araddr(22) => udma_wrapper_n_12682,
      m_axil_araddr(21) => udma_wrapper_n_12683,
      m_axil_araddr(20) => udma_wrapper_n_12684,
      m_axil_araddr(19) => udma_wrapper_n_12685,
      m_axil_araddr(18) => udma_wrapper_n_12686,
      m_axil_araddr(17) => udma_wrapper_n_12687,
      m_axil_araddr(16) => udma_wrapper_n_12688,
      m_axil_araddr(15) => udma_wrapper_n_12689,
      m_axil_araddr(14) => udma_wrapper_n_12690,
      m_axil_araddr(13) => udma_wrapper_n_12691,
      m_axil_araddr(12) => udma_wrapper_n_12692,
      m_axil_araddr(11) => udma_wrapper_n_12693,
      m_axil_araddr(10) => udma_wrapper_n_12694,
      m_axil_araddr(9) => udma_wrapper_n_12695,
      m_axil_araddr(8) => udma_wrapper_n_12696,
      m_axil_araddr(7) => udma_wrapper_n_12697,
      m_axil_araddr(6) => udma_wrapper_n_12698,
      m_axil_araddr(5) => udma_wrapper_n_12699,
      m_axil_araddr(4) => udma_wrapper_n_12700,
      m_axil_araddr(3) => udma_wrapper_n_12701,
      m_axil_araddr(2) => udma_wrapper_n_12702,
      m_axil_araddr(1) => udma_wrapper_n_12703,
      m_axil_araddr(0) => udma_wrapper_n_12704,
      m_axil_arprot(2 downto 0) => NLW_udma_wrapper_m_axil_arprot_UNCONNECTED(2 downto 0),
      m_axil_arready => n_0_193,
      m_axil_aruser(7 downto 0) => NLW_udma_wrapper_m_axil_aruser_UNCONNECTED(7 downto 0),
      m_axil_arvalid => udma_wrapper_n_12716,
      m_axil_awaddr(31) => udma_wrapper_n_12591,
      m_axil_awaddr(30) => udma_wrapper_n_12592,
      m_axil_awaddr(29) => udma_wrapper_n_12593,
      m_axil_awaddr(28) => udma_wrapper_n_12594,
      m_axil_awaddr(27) => udma_wrapper_n_12595,
      m_axil_awaddr(26) => udma_wrapper_n_12596,
      m_axil_awaddr(25) => udma_wrapper_n_12597,
      m_axil_awaddr(24) => udma_wrapper_n_12598,
      m_axil_awaddr(23) => udma_wrapper_n_12599,
      m_axil_awaddr(22) => udma_wrapper_n_12600,
      m_axil_awaddr(21) => udma_wrapper_n_12601,
      m_axil_awaddr(20) => udma_wrapper_n_12602,
      m_axil_awaddr(19) => udma_wrapper_n_12603,
      m_axil_awaddr(18) => udma_wrapper_n_12604,
      m_axil_awaddr(17) => udma_wrapper_n_12605,
      m_axil_awaddr(16) => udma_wrapper_n_12606,
      m_axil_awaddr(15) => udma_wrapper_n_12607,
      m_axil_awaddr(14) => udma_wrapper_n_12608,
      m_axil_awaddr(13) => udma_wrapper_n_12609,
      m_axil_awaddr(12) => udma_wrapper_n_12610,
      m_axil_awaddr(11) => udma_wrapper_n_12611,
      m_axil_awaddr(10) => udma_wrapper_n_12612,
      m_axil_awaddr(9) => udma_wrapper_n_12613,
      m_axil_awaddr(8) => udma_wrapper_n_12614,
      m_axil_awaddr(7) => udma_wrapper_n_12615,
      m_axil_awaddr(6) => udma_wrapper_n_12616,
      m_axil_awaddr(5) => udma_wrapper_n_12617,
      m_axil_awaddr(4) => udma_wrapper_n_12618,
      m_axil_awaddr(3) => udma_wrapper_n_12619,
      m_axil_awaddr(2) => udma_wrapper_n_12620,
      m_axil_awaddr(1) => udma_wrapper_n_12621,
      m_axil_awaddr(0) => udma_wrapper_n_12622,
      m_axil_awprot(2 downto 0) => NLW_udma_wrapper_m_axil_awprot_UNCONNECTED(2 downto 0),
      m_axil_awready => n_0_188,
      m_axil_awuser(7 downto 0) => NLW_udma_wrapper_m_axil_awuser_UNCONNECTED(7 downto 0),
      m_axil_awvalid => udma_wrapper_n_12634,
      m_axil_bready => udma_wrapper_n_12672,
      m_axil_bresp(1 downto 0) => B"00",
      m_axil_bvalid => n_0_190,
      m_axil_rdata(31) => n_0_194,
      m_axil_rdata(30) => n_0_195,
      m_axil_rdata(29) => n_0_196,
      m_axil_rdata(28) => n_0_197,
      m_axil_rdata(27) => n_0_198,
      m_axil_rdata(26) => n_0_199,
      m_axil_rdata(25) => n_0_200,
      m_axil_rdata(24) => n_0_201,
      m_axil_rdata(23) => n_0_202,
      m_axil_rdata(22) => n_0_203,
      m_axil_rdata(21) => n_0_204,
      m_axil_rdata(20) => n_0_205,
      m_axil_rdata(19) => n_0_206,
      m_axil_rdata(18) => n_0_207,
      m_axil_rdata(17) => n_0_208,
      m_axil_rdata(16) => n_0_209,
      m_axil_rdata(15) => n_0_210,
      m_axil_rdata(14) => n_0_211,
      m_axil_rdata(13) => n_0_212,
      m_axil_rdata(12) => n_0_213,
      m_axil_rdata(11) => n_0_214,
      m_axil_rdata(10) => n_0_215,
      m_axil_rdata(9) => n_0_216,
      m_axil_rdata(8) => n_0_217,
      m_axil_rdata(7) => n_0_218,
      m_axil_rdata(6) => n_0_219,
      m_axil_rdata(5) => n_0_220,
      m_axil_rdata(4) => n_0_221,
      m_axil_rdata(3) => n_0_222,
      m_axil_rdata(2) => n_0_223,
      m_axil_rdata(1) => n_0_224,
      m_axil_rdata(0) => n_0_225,
      m_axil_rready => udma_wrapper_n_12717,
      m_axil_rresp(1) => n_0_226,
      m_axil_rresp(0) => n_0_227,
      m_axil_rvalid => n_0_228,
      m_axil_wdata(31) => udma_wrapper_n_12635,
      m_axil_wdata(30) => udma_wrapper_n_12636,
      m_axil_wdata(29) => udma_wrapper_n_12637,
      m_axil_wdata(28) => udma_wrapper_n_12638,
      m_axil_wdata(27) => udma_wrapper_n_12639,
      m_axil_wdata(26) => udma_wrapper_n_12640,
      m_axil_wdata(25) => udma_wrapper_n_12641,
      m_axil_wdata(24) => udma_wrapper_n_12642,
      m_axil_wdata(23) => udma_wrapper_n_12643,
      m_axil_wdata(22) => udma_wrapper_n_12644,
      m_axil_wdata(21) => udma_wrapper_n_12645,
      m_axil_wdata(20) => udma_wrapper_n_12646,
      m_axil_wdata(19) => udma_wrapper_n_12647,
      m_axil_wdata(18) => udma_wrapper_n_12648,
      m_axil_wdata(17) => udma_wrapper_n_12649,
      m_axil_wdata(16) => udma_wrapper_n_12650,
      m_axil_wdata(15) => udma_wrapper_n_12651,
      m_axil_wdata(14) => udma_wrapper_n_12652,
      m_axil_wdata(13) => udma_wrapper_n_12653,
      m_axil_wdata(12) => udma_wrapper_n_12654,
      m_axil_wdata(11) => udma_wrapper_n_12655,
      m_axil_wdata(10) => udma_wrapper_n_12656,
      m_axil_wdata(9) => udma_wrapper_n_12657,
      m_axil_wdata(8) => udma_wrapper_n_12658,
      m_axil_wdata(7) => udma_wrapper_n_12659,
      m_axil_wdata(6) => udma_wrapper_n_12660,
      m_axil_wdata(5) => udma_wrapper_n_12661,
      m_axil_wdata(4) => udma_wrapper_n_12662,
      m_axil_wdata(3) => udma_wrapper_n_12663,
      m_axil_wdata(2) => udma_wrapper_n_12664,
      m_axil_wdata(1) => udma_wrapper_n_12665,
      m_axil_wdata(0) => udma_wrapper_n_12666,
      m_axil_wready => n_0_189,
      m_axil_wstrb(3) => udma_wrapper_n_12667,
      m_axil_wstrb(2) => udma_wrapper_n_12668,
      m_axil_wstrb(1) => udma_wrapper_n_12669,
      m_axil_wstrb(0) => udma_wrapper_n_12670,
      m_axil_wvalid => udma_wrapper_n_12671,
      \m_axis_cc\\.tdata\(63) => udma_wrapper_n_10858,
      \m_axis_cc\\.tdata\(62) => udma_wrapper_n_10859,
      \m_axis_cc\\.tdata\(61) => udma_wrapper_n_10860,
      \m_axis_cc\\.tdata\(60) => udma_wrapper_n_10861,
      \m_axis_cc\\.tdata\(59) => udma_wrapper_n_10862,
      \m_axis_cc\\.tdata\(58) => udma_wrapper_n_10863,
      \m_axis_cc\\.tdata\(57) => udma_wrapper_n_10864,
      \m_axis_cc\\.tdata\(56) => udma_wrapper_n_10865,
      \m_axis_cc\\.tdata\(55) => udma_wrapper_n_10866,
      \m_axis_cc\\.tdata\(54) => udma_wrapper_n_10867,
      \m_axis_cc\\.tdata\(53) => udma_wrapper_n_10868,
      \m_axis_cc\\.tdata\(52) => udma_wrapper_n_10869,
      \m_axis_cc\\.tdata\(51) => udma_wrapper_n_10870,
      \m_axis_cc\\.tdata\(50) => udma_wrapper_n_10871,
      \m_axis_cc\\.tdata\(49) => udma_wrapper_n_10872,
      \m_axis_cc\\.tdata\(48) => udma_wrapper_n_10873,
      \m_axis_cc\\.tdata\(47) => udma_wrapper_n_10874,
      \m_axis_cc\\.tdata\(46) => udma_wrapper_n_10875,
      \m_axis_cc\\.tdata\(45) => udma_wrapper_n_10876,
      \m_axis_cc\\.tdata\(44) => udma_wrapper_n_10877,
      \m_axis_cc\\.tdata\(43) => udma_wrapper_n_10878,
      \m_axis_cc\\.tdata\(42) => udma_wrapper_n_10879,
      \m_axis_cc\\.tdata\(41) => udma_wrapper_n_10880,
      \m_axis_cc\\.tdata\(40) => udma_wrapper_n_10881,
      \m_axis_cc\\.tdata\(39) => udma_wrapper_n_10882,
      \m_axis_cc\\.tdata\(38) => udma_wrapper_n_10883,
      \m_axis_cc\\.tdata\(37) => udma_wrapper_n_10884,
      \m_axis_cc\\.tdata\(36) => udma_wrapper_n_10885,
      \m_axis_cc\\.tdata\(35) => udma_wrapper_n_10886,
      \m_axis_cc\\.tdata\(34) => udma_wrapper_n_10887,
      \m_axis_cc\\.tdata\(33) => udma_wrapper_n_10888,
      \m_axis_cc\\.tdata\(32) => udma_wrapper_n_10889,
      \m_axis_cc\\.tdata\(31) => udma_wrapper_n_10890,
      \m_axis_cc\\.tdata\(30) => udma_wrapper_n_10891,
      \m_axis_cc\\.tdata\(29) => udma_wrapper_n_10892,
      \m_axis_cc\\.tdata\(28) => udma_wrapper_n_10893,
      \m_axis_cc\\.tdata\(27) => udma_wrapper_n_10894,
      \m_axis_cc\\.tdata\(26) => udma_wrapper_n_10895,
      \m_axis_cc\\.tdata\(25) => udma_wrapper_n_10896,
      \m_axis_cc\\.tdata\(24) => udma_wrapper_n_10897,
      \m_axis_cc\\.tdata\(23) => udma_wrapper_n_10898,
      \m_axis_cc\\.tdata\(22) => udma_wrapper_n_10899,
      \m_axis_cc\\.tdata\(21) => udma_wrapper_n_10900,
      \m_axis_cc\\.tdata\(20) => udma_wrapper_n_10901,
      \m_axis_cc\\.tdata\(19) => udma_wrapper_n_10902,
      \m_axis_cc\\.tdata\(18) => udma_wrapper_n_10903,
      \m_axis_cc\\.tdata\(17) => udma_wrapper_n_10904,
      \m_axis_cc\\.tdata\(16) => udma_wrapper_n_10905,
      \m_axis_cc\\.tdata\(15) => udma_wrapper_n_10906,
      \m_axis_cc\\.tdata\(14) => udma_wrapper_n_10907,
      \m_axis_cc\\.tdata\(13) => udma_wrapper_n_10908,
      \m_axis_cc\\.tdata\(12) => udma_wrapper_n_10909,
      \m_axis_cc\\.tdata\(11) => udma_wrapper_n_10910,
      \m_axis_cc\\.tdata\(10) => udma_wrapper_n_10911,
      \m_axis_cc\\.tdata\(9) => udma_wrapper_n_10912,
      \m_axis_cc\\.tdata\(8) => udma_wrapper_n_10913,
      \m_axis_cc\\.tdata\(7) => udma_wrapper_n_10914,
      \m_axis_cc\\.tdata\(6) => udma_wrapper_n_10915,
      \m_axis_cc\\.tdata\(5) => udma_wrapper_n_10916,
      \m_axis_cc\\.tdata\(4) => udma_wrapper_n_10917,
      \m_axis_cc\\.tdata\(3) => udma_wrapper_n_10918,
      \m_axis_cc\\.tdata\(2) => udma_wrapper_n_10919,
      \m_axis_cc\\.tdata\(1) => udma_wrapper_n_10920,
      \m_axis_cc\\.tdata\(0) => udma_wrapper_n_10921,
      \m_axis_cc\\.tkeep\(1 downto 0) => \NLW_udma_wrapper_m_axis_cc\\.tkeep_UNCONNECTED\(1 downto 0),
      \m_axis_cc\\.tlast\ => udma_wrapper_n_10955,
      \m_axis_cc\\.tready\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_167,
      \m_axis_cc\\.tuser\(32 downto 0) => \NLW_udma_wrapper_m_axis_cc\\.tuser_UNCONNECTED\(32 downto 0),
      \m_axis_cc\\.tvalid\ => udma_wrapper_n_10958,
      m_axis_cq_tdata(63 downto 0) => NLW_udma_wrapper_m_axis_cq_tdata_UNCONNECTED(63 downto 0),
      m_axis_cq_tkeep(1 downto 0) => NLW_udma_wrapper_m_axis_cq_tkeep_UNCONNECTED(1 downto 0),
      m_axis_cq_tlast => NLW_udma_wrapper_m_axis_cq_tlast_UNCONNECTED,
      m_axis_cq_tready => '0',
      m_axis_cq_tuser(84 downto 0) => NLW_udma_wrapper_m_axis_cq_tuser_UNCONNECTED(84 downto 0),
      m_axis_cq_tvalid => NLW_udma_wrapper_m_axis_cq_tvalid_UNCONNECTED,
      m_axis_h2c_tdata(63 downto 0) => NLW_udma_wrapper_m_axis_h2c_tdata_UNCONNECTED(63 downto 0),
      m_axis_h2c_tkeep(7 downto 0) => NLW_udma_wrapper_m_axis_h2c_tkeep_UNCONNECTED(7 downto 0),
      m_axis_h2c_tlast(0) => NLW_udma_wrapper_m_axis_h2c_tlast_UNCONNECTED(0),
      m_axis_h2c_tparity(7 downto 0) => NLW_udma_wrapper_m_axis_h2c_tparity_UNCONNECTED(7 downto 0),
      m_axis_h2c_tready(0) => '0',
      m_axis_h2c_tuser(47 downto 0) => NLW_udma_wrapper_m_axis_h2c_tuser_UNCONNECTED(47 downto 0),
      m_axis_h2c_tvalid(0) => NLW_udma_wrapper_m_axis_h2c_tvalid_UNCONNECTED(0),
      \m_axis_rq\\.tdata\(63) => udma_wrapper_n_10730,
      \m_axis_rq\\.tdata\(62) => udma_wrapper_n_10731,
      \m_axis_rq\\.tdata\(61) => udma_wrapper_n_10732,
      \m_axis_rq\\.tdata\(60) => udma_wrapper_n_10733,
      \m_axis_rq\\.tdata\(59) => udma_wrapper_n_10734,
      \m_axis_rq\\.tdata\(58) => udma_wrapper_n_10735,
      \m_axis_rq\\.tdata\(57) => udma_wrapper_n_10736,
      \m_axis_rq\\.tdata\(56) => udma_wrapper_n_10737,
      \m_axis_rq\\.tdata\(55) => udma_wrapper_n_10738,
      \m_axis_rq\\.tdata\(54) => udma_wrapper_n_10739,
      \m_axis_rq\\.tdata\(53) => udma_wrapper_n_10740,
      \m_axis_rq\\.tdata\(52) => udma_wrapper_n_10741,
      \m_axis_rq\\.tdata\(51) => udma_wrapper_n_10742,
      \m_axis_rq\\.tdata\(50) => udma_wrapper_n_10743,
      \m_axis_rq\\.tdata\(49) => udma_wrapper_n_10744,
      \m_axis_rq\\.tdata\(48) => udma_wrapper_n_10745,
      \m_axis_rq\\.tdata\(47) => udma_wrapper_n_10746,
      \m_axis_rq\\.tdata\(46) => udma_wrapper_n_10747,
      \m_axis_rq\\.tdata\(45) => udma_wrapper_n_10748,
      \m_axis_rq\\.tdata\(44) => udma_wrapper_n_10749,
      \m_axis_rq\\.tdata\(43) => udma_wrapper_n_10750,
      \m_axis_rq\\.tdata\(42) => udma_wrapper_n_10751,
      \m_axis_rq\\.tdata\(41) => udma_wrapper_n_10752,
      \m_axis_rq\\.tdata\(40) => udma_wrapper_n_10753,
      \m_axis_rq\\.tdata\(39) => udma_wrapper_n_10754,
      \m_axis_rq\\.tdata\(38) => udma_wrapper_n_10755,
      \m_axis_rq\\.tdata\(37) => udma_wrapper_n_10756,
      \m_axis_rq\\.tdata\(36) => udma_wrapper_n_10757,
      \m_axis_rq\\.tdata\(35) => udma_wrapper_n_10758,
      \m_axis_rq\\.tdata\(34) => udma_wrapper_n_10759,
      \m_axis_rq\\.tdata\(33) => udma_wrapper_n_10760,
      \m_axis_rq\\.tdata\(32) => udma_wrapper_n_10761,
      \m_axis_rq\\.tdata\(31) => udma_wrapper_n_10762,
      \m_axis_rq\\.tdata\(30) => udma_wrapper_n_10763,
      \m_axis_rq\\.tdata\(29) => udma_wrapper_n_10764,
      \m_axis_rq\\.tdata\(28) => udma_wrapper_n_10765,
      \m_axis_rq\\.tdata\(27) => udma_wrapper_n_10766,
      \m_axis_rq\\.tdata\(26) => udma_wrapper_n_10767,
      \m_axis_rq\\.tdata\(25) => udma_wrapper_n_10768,
      \m_axis_rq\\.tdata\(24) => udma_wrapper_n_10769,
      \m_axis_rq\\.tdata\(23) => udma_wrapper_n_10770,
      \m_axis_rq\\.tdata\(22) => udma_wrapper_n_10771,
      \m_axis_rq\\.tdata\(21) => udma_wrapper_n_10772,
      \m_axis_rq\\.tdata\(20) => udma_wrapper_n_10773,
      \m_axis_rq\\.tdata\(19) => udma_wrapper_n_10774,
      \m_axis_rq\\.tdata\(18) => udma_wrapper_n_10775,
      \m_axis_rq\\.tdata\(17) => udma_wrapper_n_10776,
      \m_axis_rq\\.tdata\(16) => udma_wrapper_n_10777,
      \m_axis_rq\\.tdata\(15) => udma_wrapper_n_10778,
      \m_axis_rq\\.tdata\(14) => udma_wrapper_n_10779,
      \m_axis_rq\\.tdata\(13) => udma_wrapper_n_10780,
      \m_axis_rq\\.tdata\(12) => udma_wrapper_n_10781,
      \m_axis_rq\\.tdata\(11) => udma_wrapper_n_10782,
      \m_axis_rq\\.tdata\(10) => udma_wrapper_n_10783,
      \m_axis_rq\\.tdata\(9) => udma_wrapper_n_10784,
      \m_axis_rq\\.tdata\(8) => udma_wrapper_n_10785,
      \m_axis_rq\\.tdata\(7) => udma_wrapper_n_10786,
      \m_axis_rq\\.tdata\(6) => udma_wrapper_n_10787,
      \m_axis_rq\\.tdata\(5) => udma_wrapper_n_10788,
      \m_axis_rq\\.tdata\(4) => udma_wrapper_n_10789,
      \m_axis_rq\\.tdata\(3) => udma_wrapper_n_10790,
      \m_axis_rq\\.tdata\(2) => udma_wrapper_n_10791,
      \m_axis_rq\\.tdata\(1) => udma_wrapper_n_10792,
      \m_axis_rq\\.tdata\(0) => udma_wrapper_n_10793,
      \m_axis_rq\\.tkeep\(1 downto 0) => \NLW_udma_wrapper_m_axis_rq\\.tkeep_UNCONNECTED\(1 downto 0),
      \m_axis_rq\\.tlast\ => udma_wrapper_n_10794,
      \m_axis_rq\\.tready\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_168,
      \m_axis_rq\\.tuser\(59 downto 28) => \NLW_udma_wrapper_m_axis_rq\\.tuser_UNCONNECTED\(59 downto 28),
      \m_axis_rq\\.tuser\(27) => udma_wrapper_n_10827,
      \m_axis_rq\\.tuser\(26) => udma_wrapper_n_10828,
      \m_axis_rq\\.tuser\(25) => udma_wrapper_n_10829,
      \m_axis_rq\\.tuser\(24) => udma_wrapper_n_10830,
      \m_axis_rq\\.tuser\(23 downto 8) => \NLW_udma_wrapper_m_axis_rq\\.tuser_UNCONNECTED\(23 downto 8),
      \m_axis_rq\\.tuser\(7) => udma_wrapper_n_10847,
      \m_axis_rq\\.tuser\(6) => udma_wrapper_n_10848,
      \m_axis_rq\\.tuser\(5) => udma_wrapper_n_10849,
      \m_axis_rq\\.tuser\(4) => udma_wrapper_n_10850,
      \m_axis_rq\\.tuser\(3) => udma_wrapper_n_10851,
      \m_axis_rq\\.tuser\(2) => udma_wrapper_n_10852,
      \m_axis_rq\\.tuser\(1) => udma_wrapper_n_10853,
      \m_axis_rq\\.tuser\(0) => udma_wrapper_n_10854,
      \m_axis_rq\\.tvalid\ => udma_wrapper_n_10857,
      \mi_c2h0_dat\\.radr\(8 downto 0) => \mi_c2h0_dat\\.radr\(8 downto 0),
      \mi_c2h0_dat\\.rdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h0_dat\\.rdat\(63 downto 0) => \mi_c2h0_dat\\.rdat\(63 downto 0),
      \mi_c2h0_dat\\.rdbe\ => '0',
      \mi_c2h0_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h0_dat\\.ren_UNCONNECTED\,
      \mi_c2h0_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h0_dat\\.rsbe\ => '0',
      \mi_c2h0_dat\\.wadr\(8 downto 0) => \mi_c2h0_dat\\.wadr\(8 downto 0),
      \mi_c2h0_dat\\.wdat\(511 downto 64) => \NLW_udma_wrapper_mi_c2h0_dat\\.wdat_UNCONNECTED\(511 downto 64),
      \mi_c2h0_dat\\.wdat\(63 downto 0) => \mi_c2h0_dat\\.wdat\(63 downto 0),
      \mi_c2h0_dat\\.wen\(1) => \NLW_udma_wrapper_mi_c2h0_dat\\.wen_UNCONNECTED\(1),
      \mi_c2h0_dat\\.wen\(0) => \mi_c2h0_dat\\.wen\(0),
      \mi_c2h0_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h0_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h1_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h1_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_c2h1_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h1_dat\\.rdbe\ => '0',
      \mi_c2h1_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h1_dat\\.ren_UNCONNECTED\,
      \mi_c2h1_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h1_dat\\.rsbe\ => '0',
      \mi_c2h1_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h1_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_c2h1_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h1_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h1_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_c2h1_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_c2h1_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h1_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h2_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h2_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_c2h2_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h2_dat\\.rdbe\ => '0',
      \mi_c2h2_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h2_dat\\.ren_UNCONNECTED\,
      \mi_c2h2_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h2_dat\\.rsbe\ => '0',
      \mi_c2h2_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h2_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_c2h2_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h2_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h2_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_c2h2_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_c2h2_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h2_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h3_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h3_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_c2h3_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h3_dat\\.rdbe\ => '0',
      \mi_c2h3_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h3_dat\\.ren_UNCONNECTED\,
      \mi_c2h3_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h3_dat\\.rsbe\ => '0',
      \mi_c2h3_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h3_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_c2h3_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h3_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h3_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_c2h3_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_c2h3_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h3_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_axi_dsc_cpld\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.radr_UNCONNECTED\(9 downto 0),
      \mi_c2h_axi_dsc_cpld\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpld\\.rdbe\ => '0',
      \mi_c2h_axi_dsc_cpld\\.ren\ => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.ren_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpld\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpld\\.rsbe\ => '0',
      \mi_c2h_axi_dsc_cpld\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_c2h_axi_dsc_cpld\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_axi_dsc_cpld\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wen_UNCONNECTED\(7 downto 0),
      \mi_c2h_axi_dsc_cpld\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_axi_dsc_cpli\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.radr_UNCONNECTED\(9 downto 0),
      \mi_c2h_axi_dsc_cpli\\.rdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_axi_dsc_cpli\\.rdbe\ => '0',
      \mi_c2h_axi_dsc_cpli\\.ren\ => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.ren_UNCONNECTED\,
      \mi_c2h_axi_dsc_cpli\\.rpar\(3 downto 0) => B"0000",
      \mi_c2h_axi_dsc_cpli\\.rsbe\ => '0',
      \mi_c2h_axi_dsc_cpli\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_c2h_axi_dsc_cpli\\.wdat\(79 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wdat_UNCONNECTED\(79 downto 0),
      \mi_c2h_axi_dsc_cpli\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wen_UNCONNECTED\(7 downto 0),
      \mi_c2h_axi_dsc_cpli\\.wpar\(3 downto 0) => \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\\.wpar_UNCONNECTED\(3 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.radr\(9) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.radr_UNCONNECTED\(9),
      \mi_c2h_pcie_dsc_cpld\\.radr\(8 downto 0) => \mi_c2h_pcie_dsc_cpld\\.radr\(8 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.rdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpld\\.rdat\(63 downto 0) => \mi_c2h_pcie_dsc_cpld\\.rdat\(63 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.rdbe\ => '0',
      \mi_c2h_pcie_dsc_cpld\\.ren\ => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.ren_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpld\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpld\\.rsbe\ => '0',
      \mi_c2h_pcie_dsc_cpld\\.wadr\(9) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wadr_UNCONNECTED\(9),
      \mi_c2h_pcie_dsc_cpld\\.wadr\(8 downto 0) => \mi_c2h_pcie_dsc_cpld\\.wadr\(8 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.wdat\(511 downto 64) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wdat_UNCONNECTED\(511 downto 64),
      \mi_c2h_pcie_dsc_cpld\\.wdat\(63 downto 0) => \mi_c2h_pcie_dsc_cpld\\.wdat\(63 downto 0),
      \mi_c2h_pcie_dsc_cpld\\.wen\(7 downto 1) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wen_UNCONNECTED\(7 downto 1),
      \mi_c2h_pcie_dsc_cpld\\.wen\(0) => \mi_c2h_pcie_dsc_cpld\\.wen\(0),
      \mi_c2h_pcie_dsc_cpld\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.radr_UNCONNECTED\(9 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.rdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_pcie_dsc_cpli\\.rdbe\ => '0',
      \mi_c2h_pcie_dsc_cpli\\.ren\ => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.ren_UNCONNECTED\,
      \mi_c2h_pcie_dsc_cpli\\.rpar\(3 downto 0) => B"0000",
      \mi_c2h_pcie_dsc_cpli\\.rsbe\ => '0',
      \mi_c2h_pcie_dsc_cpli\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.wdat\(79 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wdat_UNCONNECTED\(79 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wen_UNCONNECTED\(7 downto 0),
      \mi_c2h_pcie_dsc_cpli\\.wpar\(3 downto 0) => \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\\.wpar_UNCONNECTED\(3 downto 0),
      \mi_c2h_rd_brg_dat\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.radr_UNCONNECTED\(9 downto 0),
      \mi_c2h_rd_brg_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_rd_brg_dat\\.rdbe\ => '0',
      \mi_c2h_rd_brg_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.ren_UNCONNECTED\,
      \mi_c2h_rd_brg_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_rd_brg_dat\\.rsbe\ => '0',
      \mi_c2h_rd_brg_dat\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_c2h_rd_brg_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_rd_brg_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_c2h_rd_brg_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h_rd_brg_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_c2h_wr_brg_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_c2h_wr_brg_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_wr_brg_dat\\.rdbe\ => '0',
      \mi_c2h_wr_brg_dat\\.ren\ => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.ren_UNCONNECTED\,
      \mi_c2h_wr_brg_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_c2h_wr_brg_dat\\.rsbe\ => '0',
      \mi_c2h_wr_brg_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_c2h_wr_brg_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_c2h_wr_brg_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_c2h_wr_brg_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_c2h_wr_brg_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_dsc_crd_rcv\\.radr\(11 downto 0) => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.radr_UNCONNECTED\(11 downto 0),
      \mi_dsc_crd_rcv\\.rdat\(15 downto 0) => B"0000000000000000",
      \mi_dsc_crd_rcv\\.rdbe\ => '0',
      \mi_dsc_crd_rcv\\.ren\ => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.ren_UNCONNECTED\,
      \mi_dsc_crd_rcv\\.rpar\(1 downto 0) => B"00",
      \mi_dsc_crd_rcv\\.rsbe\ => '0',
      \mi_dsc_crd_rcv\\.wadr\(11 downto 0) => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wadr_UNCONNECTED\(11 downto 0),
      \mi_dsc_crd_rcv\\.wdat\(15 downto 0) => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wdat_UNCONNECTED\(15 downto 0),
      \mi_dsc_crd_rcv\\.wen\ => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wen_UNCONNECTED\,
      \mi_dsc_crd_rcv\\.wpar\(1 downto 0) => \NLW_udma_wrapper_mi_dsc_crd_rcv\\.wpar_UNCONNECTED\(1 downto 0),
      \mi_h2c0_dat\\.radr\(8 downto 0) => \mi_h2c0_dat\\.radr\(8 downto 0),
      \mi_h2c0_dat\\.rdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c0_dat\\.rdat\(63 downto 0) => \mi_h2c0_dat\\.rdat\(63 downto 0),
      \mi_h2c0_dat\\.rdbe\ => '0',
      \mi_h2c0_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c0_dat\\.ren_UNCONNECTED\,
      \mi_h2c0_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c0_dat\\.rsbe\ => '0',
      \mi_h2c0_dat\\.wadr\(8 downto 0) => \mi_h2c0_dat\\.wadr\(8 downto 0),
      \mi_h2c0_dat\\.wdat\(511 downto 64) => \NLW_udma_wrapper_mi_h2c0_dat\\.wdat_UNCONNECTED\(511 downto 64),
      \mi_h2c0_dat\\.wdat\(63 downto 0) => \mi_h2c0_dat\\.wdat\(63 downto 0),
      \mi_h2c0_dat\\.wen\(1) => \NLW_udma_wrapper_mi_h2c0_dat\\.wen_UNCONNECTED\(1),
      \mi_h2c0_dat\\.wen\(0) => \mi_h2c0_dat\\.wen\(0),
      \mi_h2c0_dat\\.wpar\(63 downto 8) => \NLW_udma_wrapper_mi_h2c0_dat\\.wpar_UNCONNECTED\(63 downto 8),
      \mi_h2c0_dat\\.wpar\(7 downto 0) => \mi_h2c0_dat\\.wpar\(7 downto 0),
      \mi_h2c1_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c1_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_h2c1_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c1_dat\\.rdbe\ => '0',
      \mi_h2c1_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c1_dat\\.ren_UNCONNECTED\,
      \mi_h2c1_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c1_dat\\.rsbe\ => '0',
      \mi_h2c1_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c1_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_h2c1_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_h2c1_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_h2c1_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_h2c1_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_h2c1_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c1_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c2_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c2_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_h2c2_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c2_dat\\.rdbe\ => '0',
      \mi_h2c2_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c2_dat\\.ren_UNCONNECTED\,
      \mi_h2c2_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c2_dat\\.rsbe\ => '0',
      \mi_h2c2_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c2_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_h2c2_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_h2c2_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_h2c2_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_h2c2_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_h2c2_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c2_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c3_dat\\.radr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c3_dat\\.radr_UNCONNECTED\(8 downto 0),
      \mi_h2c3_dat\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c3_dat\\.rdbe\ => '0',
      \mi_h2c3_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c3_dat\\.ren_UNCONNECTED\,
      \mi_h2c3_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c3_dat\\.rsbe\ => '0',
      \mi_h2c3_dat\\.wadr\(8 downto 0) => \NLW_udma_wrapper_mi_h2c3_dat\\.wadr_UNCONNECTED\(8 downto 0),
      \mi_h2c3_dat\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_h2c3_dat\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_h2c3_dat\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_h2c3_dat\\.wen_UNCONNECTED\(1 downto 0),
      \mi_h2c3_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c3_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_axi_dsc_cpld\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.radr_UNCONNECTED\(9 downto 0),
      \mi_h2c_axi_dsc_cpld\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpld\\.rdbe\ => '0',
      \mi_h2c_axi_dsc_cpld\\.ren\ => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.ren_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpld\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpld\\.rsbe\ => '0',
      \mi_h2c_axi_dsc_cpld\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_h2c_axi_dsc_cpld\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_h2c_axi_dsc_cpld\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wen_UNCONNECTED\(7 downto 0),
      \mi_h2c_axi_dsc_cpld\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_axi_dsc_cpli\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.radr_UNCONNECTED\(9 downto 0),
      \mi_h2c_axi_dsc_cpli\\.rdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_axi_dsc_cpli\\.rdbe\ => '0',
      \mi_h2c_axi_dsc_cpli\\.ren\ => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.ren_UNCONNECTED\,
      \mi_h2c_axi_dsc_cpli\\.rpar\(3 downto 0) => B"0000",
      \mi_h2c_axi_dsc_cpli\\.rsbe\ => '0',
      \mi_h2c_axi_dsc_cpli\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_h2c_axi_dsc_cpli\\.wdat\(79 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wdat_UNCONNECTED\(79 downto 0),
      \mi_h2c_axi_dsc_cpli\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wen_UNCONNECTED\(7 downto 0),
      \mi_h2c_axi_dsc_cpli\\.wpar\(3 downto 0) => \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\\.wpar_UNCONNECTED\(3 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.radr_UNCONNECTED\(9 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.rdat\(511 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpld\\.rdbe\ => '0',
      \mi_h2c_pcie_dsc_cpld\\.ren\ => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.ren_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpld\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpld\\.rsbe\ => '0',
      \mi_h2c_pcie_dsc_cpld\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.wdat\(511 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wdat_UNCONNECTED\(511 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wen_UNCONNECTED\(7 downto 0),
      \mi_h2c_pcie_dsc_cpld\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.radr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.radr_UNCONNECTED\(9 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.rdat\(79 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_pcie_dsc_cpli\\.rdbe\ => '0',
      \mi_h2c_pcie_dsc_cpli\\.ren\ => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.ren_UNCONNECTED\,
      \mi_h2c_pcie_dsc_cpli\\.rpar\(3 downto 0) => B"0000",
      \mi_h2c_pcie_dsc_cpli\\.rsbe\ => '0',
      \mi_h2c_pcie_dsc_cpli\\.wadr\(9 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wadr_UNCONNECTED\(9 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.wdat\(79 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wdat_UNCONNECTED\(79 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.wen\(7 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wen_UNCONNECTED\(7 downto 0),
      \mi_h2c_pcie_dsc_cpli\\.wpar\(3 downto 0) => \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\\.wpar_UNCONNECTED\(3 downto 0),
      \mi_h2c_rd_brg_dat\\.radr\(8 downto 0) => \mi_h2c_rd_brg_dat\\.radr\(8 downto 0),
      \mi_h2c_rd_brg_dat\\.rdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_rd_brg_dat\\.rdat\(63 downto 0) => \mi_h2c_rd_brg_dat\\.rdat\(63 downto 0),
      \mi_h2c_rd_brg_dat\\.rdbe\ => '0',
      \mi_h2c_rd_brg_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.ren_UNCONNECTED\,
      \mi_h2c_rd_brg_dat\\.rpar\(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_rd_brg_dat\\.rsbe\ => '0',
      \mi_h2c_rd_brg_dat\\.wadr\(8 downto 0) => \mi_h2c_rd_brg_dat\\.wadr\(8 downto 0),
      \mi_h2c_rd_brg_dat\\.wdat\(511 downto 64) => \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wdat_UNCONNECTED\(511 downto 64),
      \mi_h2c_rd_brg_dat\\.wdat\(63 downto 0) => \mi_h2c_rd_brg_dat\\.wdat\(63 downto 0),
      \mi_h2c_rd_brg_dat\\.wen\(1) => \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wen_UNCONNECTED\(1),
      \mi_h2c_rd_brg_dat\\.wen\(0) => \mi_h2c_rd_brg_dat\\.wen\(0),
      \mi_h2c_rd_brg_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c_rd_brg_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_h2c_wr_brg_dat\\.radr\(10 downto 9) => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.radr_UNCONNECTED\(10 downto 9),
      \mi_h2c_wr_brg_dat\\.radr\(8 downto 0) => \mi_h2c_wr_brg_dat\\.radr\(8 downto 0),
      \mi_h2c_wr_brg_dat\\.rdat\(511 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_h2c_wr_brg_dat\\.rdat\(63 downto 0) => \mi_h2c_wr_brg_dat\\.rdat\(63 downto 0),
      \mi_h2c_wr_brg_dat\\.rdbe\ => '0',
      \mi_h2c_wr_brg_dat\\.ren\ => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.ren_UNCONNECTED\,
      \mi_h2c_wr_brg_dat\\.rpar\(63 downto 8) => B"00000000000000000000000000000000000000000000000000000000",
      \mi_h2c_wr_brg_dat\\.rpar\(7 downto 0) => \mi_h2c_wr_brg_dat\\.rpar\(7 downto 0),
      \mi_h2c_wr_brg_dat\\.rsbe\ => '0',
      \mi_h2c_wr_brg_dat\\.wadr\(10 downto 9) => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wadr_UNCONNECTED\(10 downto 9),
      \mi_h2c_wr_brg_dat\\.wadr\(8 downto 0) => \mi_h2c_wr_brg_dat\\.wadr\(8 downto 0),
      \mi_h2c_wr_brg_dat\\.wdat\(511 downto 64) => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wdat_UNCONNECTED\(511 downto 64),
      \mi_h2c_wr_brg_dat\\.wdat\(63 downto 0) => \mi_h2c_wr_brg_dat\\.wdat\(63 downto 0),
      \mi_h2c_wr_brg_dat\\.wen\(1) => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wen_UNCONNECTED\(1),
      \mi_h2c_wr_brg_dat\\.wen\(0) => \mi_h2c_wr_brg_dat\\.wen\(0),
      \mi_h2c_wr_brg_dat\\.wpar\(63 downto 0) => \NLW_udma_wrapper_mi_h2c_wr_brg_dat\\.wpar_UNCONNECTED\(63 downto 0),
      \mi_hw_ctxt\\.radr\(11 downto 0) => \NLW_udma_wrapper_mi_hw_ctxt\\.radr_UNCONNECTED\(11 downto 0),
      \mi_hw_ctxt\\.rdat\(31 downto 0) => B"00000000000000000000000000000000",
      \mi_hw_ctxt\\.rdbe\ => '0',
      \mi_hw_ctxt\\.ren\ => \NLW_udma_wrapper_mi_hw_ctxt\\.ren_UNCONNECTED\,
      \mi_hw_ctxt\\.rpar\(7 downto 0) => B"00000000",
      \mi_hw_ctxt\\.rsbe\ => '0',
      \mi_hw_ctxt\\.wadr\(11 downto 0) => \NLW_udma_wrapper_mi_hw_ctxt\\.wadr_UNCONNECTED\(11 downto 0),
      \mi_hw_ctxt\\.wdat\(31 downto 0) => \NLW_udma_wrapper_mi_hw_ctxt\\.wdat_UNCONNECTED\(31 downto 0),
      \mi_hw_ctxt\\.wen\ => \NLW_udma_wrapper_mi_hw_ctxt\\.wen_UNCONNECTED\,
      \mi_hw_ctxt\\.wpar\(7 downto 0) => \NLW_udma_wrapper_mi_hw_ctxt\\.wpar_UNCONNECTED\(7 downto 0),
      \mi_sw_ctxt\\.radr\(11 downto 0) => \NLW_udma_wrapper_mi_sw_ctxt\\.radr_UNCONNECTED\(11 downto 0),
      \mi_sw_ctxt\\.rdat\(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_sw_ctxt\\.rdbe\ => '0',
      \mi_sw_ctxt\\.ren\ => \NLW_udma_wrapper_mi_sw_ctxt\\.ren_UNCONNECTED\,
      \mi_sw_ctxt\\.rpar\(7 downto 0) => B"00000000",
      \mi_sw_ctxt\\.rsbe\ => '0',
      \mi_sw_ctxt\\.wadr\(11 downto 0) => \NLW_udma_wrapper_mi_sw_ctxt\\.wadr_UNCONNECTED\(11 downto 0),
      \mi_sw_ctxt\\.wdat\(127 downto 0) => \NLW_udma_wrapper_mi_sw_ctxt\\.wdat_UNCONNECTED\(127 downto 0),
      \mi_sw_ctxt\\.wen\(3 downto 0) => \NLW_udma_wrapper_mi_sw_ctxt\\.wen_UNCONNECTED\(3 downto 0),
      \mi_sw_ctxt\\.wpar\(7 downto 0) => \NLW_udma_wrapper_mi_sw_ctxt\\.wpar_UNCONNECTED\(7 downto 0),
      \mi_wb_base_ctxt\\.radr\(11 downto 0) => \NLW_udma_wrapper_mi_wb_base_ctxt\\.radr_UNCONNECTED\(11 downto 0),
      \mi_wb_base_ctxt\\.rdat\(127 downto 0) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \mi_wb_base_ctxt\\.rdbe\ => '0',
      \mi_wb_base_ctxt\\.ren\ => \NLW_udma_wrapper_mi_wb_base_ctxt\\.ren_UNCONNECTED\,
      \mi_wb_base_ctxt\\.rpar\(7 downto 0) => B"00000000",
      \mi_wb_base_ctxt\\.rsbe\ => '0',
      \mi_wb_base_ctxt\\.wadr\(11 downto 0) => \NLW_udma_wrapper_mi_wb_base_ctxt\\.wadr_UNCONNECTED\(11 downto 0),
      \mi_wb_base_ctxt\\.wdat\(63 downto 0) => \NLW_udma_wrapper_mi_wb_base_ctxt\\.wdat_UNCONNECTED\(63 downto 0),
      \mi_wb_base_ctxt\\.wen\(1 downto 0) => \NLW_udma_wrapper_mi_wb_base_ctxt\\.wen_UNCONNECTED\(1 downto 0),
      \mi_wb_base_ctxt\\.wpar\(7 downto 0) => \NLW_udma_wrapper_mi_wb_base_ctxt\\.wpar_UNCONNECTED\(7 downto 0),
      \pcie_dma_gic\\.interrupt\(6 downto 0) => \NLW_udma_wrapper_pcie_dma_gic\\.interrupt_UNCONNECTED\(6 downto 0),
      \pcie_dma_in\\.cfg_current_speed\(2 downto 0) => B"000",
      \pcie_dma_in\\.cfg_err_cor_out\ => '0',
      \pcie_dma_in\\.cfg_err_fatal_out\ => '0',
      \pcie_dma_in\\.cfg_err_nonfatal_out\ => '0',
      \pcie_dma_in\\.cfg_ext_function_number\(7 downto 0) => B"00000000",
      \pcie_dma_in\\.cfg_ext_read_received\ => '0',
      \pcie_dma_in\\.cfg_ext_register_number\(9 downto 0) => B"0000000000",
      \pcie_dma_in\\.cfg_ext_write_byte_enable\(3 downto 0) => B"0000",
      \pcie_dma_in\\.cfg_ext_write_data\(31 downto 0) => B"00000000000000000000000000000000",
      \pcie_dma_in\\.cfg_ext_write_received\ => '0',
      \pcie_dma_in\\.cfg_fc_nph\(7 downto 0) => \pcie_dma_in\\.cfg_fc_nph\(7 downto 0),
      \pcie_dma_in\\.cfg_flr_in_process\(3 downto 0) => B"0000",
      \pcie_dma_in\\.cfg_function_status\(15 downto 0) => B"0000000000000000",
      \pcie_dma_in\\.cfg_hot_reset_out\ => '0',
      \pcie_dma_in\\.cfg_interrupt_msi_enable\ => \^msi_enable\,
      \pcie_dma_in\\.cfg_interrupt_msi_fail\ => '0',
      \pcie_dma_in\\.cfg_interrupt_msi_mask_update\ => '0',
      \pcie_dma_in\\.cfg_interrupt_msi_sent\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_312,
      \pcie_dma_in\\.cfg_interrupt_msix_enable\(3 downto 0) => B"0000",
      \pcie_dma_in\\.cfg_interrupt_msix_fail\ => '0',
      \pcie_dma_in\\.cfg_interrupt_msix_mask\(3 downto 0) => B"0000",
      \pcie_dma_in\\.cfg_interrupt_msix_sent\ => '0',
      \pcie_dma_in\\.cfg_interrupt_msix_vf_enable\(5 downto 0) => B"000000",
      \pcie_dma_in\\.cfg_interrupt_msix_vf_mask\(5 downto 0) => B"000000",
      \pcie_dma_in\\.cfg_interrupt_sent\ => \pcie_dma_in\\.cfg_interrupt_sent\,
      \pcie_dma_in\\.cfg_local_error\ => '0',
      \pcie_dma_in\\.cfg_ltssm_state\(5 downto 0) => B"000000",
      \pcie_dma_in\\.cfg_max_payload\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_137,
      \pcie_dma_in\\.cfg_max_payload\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_138,
      \pcie_dma_in\\.cfg_max_payload\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_139,
      \pcie_dma_in\\.cfg_max_read_req\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_134,
      \pcie_dma_in\\.cfg_max_read_req\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_135,
      \pcie_dma_in\\.cfg_max_read_req\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_136,
      \pcie_dma_in\\.cfg_mgmt_read_data\(31 downto 0) => B"00000000000000000000000000000000",
      \pcie_dma_in\\.cfg_mgmt_read_write_done\ => '0',
      \pcie_dma_in\\.cfg_msg_received\ => '0',
      \pcie_dma_in\\.cfg_msg_received_data\(7 downto 0) => B"00000000",
      \pcie_dma_in\\.cfg_msg_received_type\(4 downto 0) => B"00000",
      \pcie_dma_in\\.cfg_msg_transmit_done\ => '0',
      \pcie_dma_in\\.cfg_negotiated_width\(3 downto 0) => B"0000",
      \pcie_dma_in\\.cfg_per_func_status_data\(15 downto 0) => B"0000000000000000",
      \pcie_dma_in\\.cfg_per_function_update_done\ => '0',
      \pcie_dma_in\\.cfg_phy_link_down\ => \pcie_dma_in\\.cfg_phy_link_down\,
      \pcie_dma_in\\.cfg_phy_link_status\(1 downto 0) => B"00",
      \pcie_dma_in\\.cfg_pl_status_change\ => '0',
      \pcie_dma_in\\.cfg_vf_flr_in_process\(251 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      \pcie_dma_in\\.pcie_cq_np_req_count\(5 downto 0) => B"000000",
      \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0) => pcie_rq_seq_num0(3 downto 0),
      \pcie_dma_in\\.pcie_rq_seq_num1\(3 downto 0) => B"0000",
      \pcie_dma_in\\.pcie_rq_seq_num_vld0\ => pcie_rq_seq_num_vld0,
      \pcie_dma_in\\.pcie_rq_seq_num_vld1\ => '0',
      \pcie_dma_in\\.pcie_tfc_nph_av\(3 downto 0) => B"0000",
      \pcie_dma_out\\.cfg_config_space_enable\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_config_space_enable_UNCONNECTED\,
      \pcie_dma_out\\.cfg_ds_bus_number\(7 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_bus_number_UNCONNECTED\(7 downto 0),
      \pcie_dma_out\\.cfg_ds_device_number\(4 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_device_number_UNCONNECTED\(4 downto 0),
      \pcie_dma_out\\.cfg_ds_function_number\(2 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_function_number_UNCONNECTED\(2 downto 0),
      \pcie_dma_out\\.cfg_ds_port_number\(7 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ds_port_number_UNCONNECTED\(7 downto 0),
      \pcie_dma_out\\.cfg_dsn\(63 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_dsn_UNCONNECTED\(63 downto 0),
      \pcie_dma_out\\.cfg_err_cor_in\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_err_cor_in_UNCONNECTED\,
      \pcie_dma_out\\.cfg_err_uncor_in\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_err_uncor_in_UNCONNECTED\,
      \pcie_dma_out\\.cfg_ext_read_data\(31 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ext_read_data_UNCONNECTED\(31 downto 0),
      \pcie_dma_out\\.cfg_ext_read_data_valid\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_ext_read_data_valid_UNCONNECTED\,
      \pcie_dma_out\\.cfg_fc_sel\(2 downto 1) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_fc_sel_UNCONNECTED\(2 downto 1),
      \pcie_dma_out\\.cfg_fc_sel\(0) => cfg_fc_sel(0),
      \pcie_dma_out\\.cfg_flr_done\(3 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_flr_done_UNCONNECTED\(3 downto 0),
      \pcie_dma_out\\.cfg_hot_reset_in\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_hot_reset_in_UNCONNECTED\,
      \pcie_dma_out\\.cfg_interrupt_int\(3 downto 1) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_int_UNCONNECTED\(3 downto 1),
      \pcie_dma_out\\.cfg_interrupt_int\(0) => cfg_interrupt_int(0),
      \pcie_dma_out\\.cfg_interrupt_msi_attr\(2 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_attr_UNCONNECTED\(2 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_function_number\(3 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_function_number_UNCONNECTED\(3 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_int\(31 downto 0) => cfg_interrupt_msi_int(31 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_pending_status\(31 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_UNCONNECTED\(31 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_pending_status_data_enable\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_data_enable_UNCONNECTED\,
      \pcie_dma_out\\.cfg_interrupt_msi_pending_status_function_num\(3 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_pending_status_function_num_UNCONNECTED\(3 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_tph_present\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_present_UNCONNECTED\,
      \pcie_dma_out\\.cfg_interrupt_msi_tph_st_tag\(8 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_st_tag_UNCONNECTED\(8 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msi_tph_type\(1 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msi_tph_type_UNCONNECTED\(1 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msix_address\(255 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_address_UNCONNECTED\(255 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msix_data\(31 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_data_UNCONNECTED\(31 downto 0),
      \pcie_dma_out\\.cfg_interrupt_msix_int\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_msix_int_UNCONNECTED\,
      \pcie_dma_out\\.cfg_interrupt_pending\(3 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_interrupt_pending_UNCONNECTED\(3 downto 0),
      \pcie_dma_out\\.cfg_link_training_enable\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_link_training_enable_UNCONNECTED\,
      \pcie_dma_out\\.cfg_mgmt_addr\(18 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_addr_UNCONNECTED\(18 downto 0),
      \pcie_dma_out\\.cfg_mgmt_byte_enable\(3 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_byte_enable_UNCONNECTED\(3 downto 0),
      \pcie_dma_out\\.cfg_mgmt_function_number\(7 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_function_number_UNCONNECTED\(7 downto 0),
      \pcie_dma_out\\.cfg_mgmt_read\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_read_UNCONNECTED\,
      \pcie_dma_out\\.cfg_mgmt_type1_cfg_reg_access\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_type1_cfg_reg_access_UNCONNECTED\,
      \pcie_dma_out\\.cfg_mgmt_write\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_write_UNCONNECTED\,
      \pcie_dma_out\\.cfg_mgmt_write_data\(31 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_mgmt_write_data_UNCONNECTED\(31 downto 0),
      \pcie_dma_out\\.cfg_msg_transmit\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_UNCONNECTED\,
      \pcie_dma_out\\.cfg_msg_transmit_data\(31 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_data_UNCONNECTED\(31 downto 0),
      \pcie_dma_out\\.cfg_msg_transmit_type\(2 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_msg_transmit_type_UNCONNECTED\(2 downto 0),
      \pcie_dma_out\\.cfg_per_func_status_control\(2 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_func_status_control_UNCONNECTED\(2 downto 0),
      \pcie_dma_out\\.cfg_per_function_logic_request\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_logic_request_UNCONNECTED\,
      \pcie_dma_out\\.cfg_per_function_number\(6 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_number_UNCONNECTED\(6 downto 0),
      \pcie_dma_out\\.cfg_per_function_output_request\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_per_function_output_request_UNCONNECTED\,
      \pcie_dma_out\\.cfg_vf_flr_done\ => \NLW_udma_wrapper_pcie_dma_out\\.cfg_vf_flr_done_UNCONNECTED\,
      \pcie_dma_out\\.cfg_vf_flr_func_num\(7 downto 0) => \NLW_udma_wrapper_pcie_dma_out\\.cfg_vf_flr_func_num_UNCONNECTED\(7 downto 0),
      \pcie_dma_out\\.pcie_cq_np_req\(1) => \NLW_udma_wrapper_pcie_dma_out\\.pcie_cq_np_req_UNCONNECTED\(1),
      \pcie_dma_out\\.pcie_cq_np_req\(0) => pcie_cq_np_req,
      pf1_lite_ext(5 downto 0) => B"000000",
      rbar_bar_size(5 downto 0) => B"000000",
      rbar_function_number(7 downto 0) => B"00000000",
      rbar_write_enable_bar0 => '0',
      rbar_write_enable_bar1 => '0',
      rbar_write_enable_bar2 => '0',
      rbar_write_enable_bar3 => '0',
      rbar_write_enable_bar4 => '0',
      rbar_write_enable_bar5 => '0',
      s_axi_araddr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_udma_wrapper_s_axi_arready_UNCONNECTED,
      s_axi_arregion(3 downto 0) => B"0000",
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_udma_wrapper_s_axi_awready_UNCONNECTED,
      s_axi_awregion(3 downto 0) => B"0000",
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_udma_wrapper_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_udma_wrapper_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_udma_wrapper_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(63 downto 0) => NLW_udma_wrapper_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rdataeccparity(7 downto 0) => NLW_udma_wrapper_s_axi_rdataeccparity_UNCONNECTED(7 downto 0),
      s_axi_rid(3 downto 0) => NLW_udma_wrapper_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_udma_wrapper_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_udma_wrapper_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_udma_wrapper_s_axi_rvalid_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wdataeccparity(7 downto 0) => B"00000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_udma_wrapper_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(7 downto 0) => B"00000000",
      s_axi_wvalid => '0',
      s_axil_araddr(31 downto 18) => B"00000000000000",
      s_axil_araddr(17) => n_0_314,
      s_axil_araddr(16) => n_0_315,
      s_axil_araddr(15) => n_0_316,
      s_axil_araddr(14) => n_0_317,
      s_axil_araddr(13) => n_0_318,
      s_axil_araddr(12) => n_0_319,
      s_axil_araddr(11) => n_0_320,
      s_axil_araddr(10) => n_0_321,
      s_axil_araddr(9) => n_0_322,
      s_axil_araddr(8) => n_0_323,
      s_axil_araddr(7) => n_0_324,
      s_axil_araddr(6) => n_0_325,
      s_axil_araddr(5) => n_0_326,
      s_axil_araddr(4) => n_0_327,
      s_axil_araddr(3) => n_0_328,
      s_axil_araddr(2) => n_0_329,
      s_axil_araddr(1) => n_0_330,
      s_axil_araddr(0) => n_0_331,
      s_axil_arprot(2 downto 0) => B"000",
      s_axil_arready => udma_wrapper_n_12723,
      s_axil_arvalid => n_0_332,
      s_axil_awaddr(31 downto 18) => B"00000000000000",
      s_axil_awaddr(17) => n_0_243,
      s_axil_awaddr(16) => n_0_244,
      s_axil_awaddr(15) => n_0_245,
      s_axil_awaddr(14) => n_0_246,
      s_axil_awaddr(13) => n_0_247,
      s_axil_awaddr(12) => n_0_248,
      s_axil_awaddr(11) => n_0_249,
      s_axil_awaddr(10) => n_0_250,
      s_axil_awaddr(9) => n_0_251,
      s_axil_awaddr(8) => n_0_252,
      s_axil_awaddr(7) => n_0_253,
      s_axil_awaddr(6) => n_0_254,
      s_axil_awaddr(5) => n_0_255,
      s_axil_awaddr(4) => n_0_256,
      s_axil_awaddr(3) => n_0_257,
      s_axil_awaddr(2) => n_0_258,
      s_axil_awaddr(1) => n_0_259,
      s_axil_awaddr(0) => n_0_260,
      s_axil_awprot(2 downto 0) => B"000",
      s_axil_awready => udma_wrapper_n_12718,
      s_axil_awvalid => n_0_261,
      s_axil_bready => n_0_299,
      s_axil_bresp(1 downto 0) => NLW_udma_wrapper_s_axil_bresp_UNCONNECTED(1 downto 0),
      s_axil_bvalid => udma_wrapper_n_12720,
      s_axil_rdata(31) => udma_wrapper_n_12724,
      s_axil_rdata(30) => udma_wrapper_n_12725,
      s_axil_rdata(29) => udma_wrapper_n_12726,
      s_axil_rdata(28) => udma_wrapper_n_12727,
      s_axil_rdata(27) => udma_wrapper_n_12728,
      s_axil_rdata(26) => udma_wrapper_n_12729,
      s_axil_rdata(25) => udma_wrapper_n_12730,
      s_axil_rdata(24) => udma_wrapper_n_12731,
      s_axil_rdata(23) => udma_wrapper_n_12732,
      s_axil_rdata(22) => udma_wrapper_n_12733,
      s_axil_rdata(21) => udma_wrapper_n_12734,
      s_axil_rdata(20) => udma_wrapper_n_12735,
      s_axil_rdata(19) => udma_wrapper_n_12736,
      s_axil_rdata(18) => udma_wrapper_n_12737,
      s_axil_rdata(17) => udma_wrapper_n_12738,
      s_axil_rdata(16) => udma_wrapper_n_12739,
      s_axil_rdata(15) => udma_wrapper_n_12740,
      s_axil_rdata(14) => udma_wrapper_n_12741,
      s_axil_rdata(13) => udma_wrapper_n_12742,
      s_axil_rdata(12) => udma_wrapper_n_12743,
      s_axil_rdata(11) => udma_wrapper_n_12744,
      s_axil_rdata(10) => udma_wrapper_n_12745,
      s_axil_rdata(9) => udma_wrapper_n_12746,
      s_axil_rdata(8) => udma_wrapper_n_12747,
      s_axil_rdata(7) => udma_wrapper_n_12748,
      s_axil_rdata(6) => udma_wrapper_n_12749,
      s_axil_rdata(5) => udma_wrapper_n_12750,
      s_axil_rdata(4) => udma_wrapper_n_12751,
      s_axil_rdata(3) => udma_wrapper_n_12752,
      s_axil_rdata(2) => udma_wrapper_n_12753,
      s_axil_rdata(1) => udma_wrapper_n_12754,
      s_axil_rdata(0) => udma_wrapper_n_12755,
      s_axil_rready => n_0_333,
      s_axil_rresp(1 downto 0) => NLW_udma_wrapper_s_axil_rresp_UNCONNECTED(1 downto 0),
      s_axil_rvalid => udma_wrapper_n_12758,
      s_axil_wdata(31) => n_0_262,
      s_axil_wdata(30) => n_0_263,
      s_axil_wdata(29) => n_0_264,
      s_axil_wdata(28) => n_0_265,
      s_axil_wdata(27) => n_0_266,
      s_axil_wdata(26) => n_0_267,
      s_axil_wdata(25) => n_0_268,
      s_axil_wdata(24) => n_0_269,
      s_axil_wdata(23) => n_0_270,
      s_axil_wdata(22) => n_0_271,
      s_axil_wdata(21) => n_0_272,
      s_axil_wdata(20) => n_0_273,
      s_axil_wdata(19) => n_0_274,
      s_axil_wdata(18) => n_0_275,
      s_axil_wdata(17) => n_0_276,
      s_axil_wdata(16) => n_0_277,
      s_axil_wdata(15) => n_0_278,
      s_axil_wdata(14) => n_0_279,
      s_axil_wdata(13) => n_0_280,
      s_axil_wdata(12) => n_0_281,
      s_axil_wdata(11) => n_0_282,
      s_axil_wdata(10) => n_0_283,
      s_axil_wdata(9) => n_0_284,
      s_axil_wdata(8) => n_0_285,
      s_axil_wdata(7) => n_0_286,
      s_axil_wdata(6) => n_0_287,
      s_axil_wdata(5) => n_0_288,
      s_axil_wdata(4) => n_0_289,
      s_axil_wdata(3) => n_0_290,
      s_axil_wdata(2) => n_0_291,
      s_axil_wdata(1) => n_0_292,
      s_axil_wdata(0) => n_0_293,
      s_axil_wready => udma_wrapper_n_12719,
      s_axil_wstrb(3) => n_0_294,
      s_axil_wstrb(2) => n_0_295,
      s_axil_wstrb(1) => n_0_296,
      s_axil_wstrb(0) => n_0_297,
      s_axil_wvalid => n_0_298,
      s_axis_c2h_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tkeep(7 downto 0) => B"00000000",
      s_axis_c2h_tlast(0) => '0',
      s_axis_c2h_tparity(7 downto 0) => B"00000000",
      s_axis_c2h_tready(0) => NLW_udma_wrapper_s_axis_c2h_tready_UNCONNECTED(0),
      s_axis_c2h_tuser(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tvalid(0) => '0',
      \s_axis_cq\\.tdata\(63) => xdma_0_pcie2_to_pcie3_wrapper_i_n_241,
      \s_axis_cq\\.tdata\(62) => xdma_0_pcie2_to_pcie3_wrapper_i_n_242,
      \s_axis_cq\\.tdata\(61) => xdma_0_pcie2_to_pcie3_wrapper_i_n_243,
      \s_axis_cq\\.tdata\(60) => xdma_0_pcie2_to_pcie3_wrapper_i_n_244,
      \s_axis_cq\\.tdata\(59) => xdma_0_pcie2_to_pcie3_wrapper_i_n_245,
      \s_axis_cq\\.tdata\(58) => xdma_0_pcie2_to_pcie3_wrapper_i_n_246,
      \s_axis_cq\\.tdata\(57) => xdma_0_pcie2_to_pcie3_wrapper_i_n_247,
      \s_axis_cq\\.tdata\(56) => xdma_0_pcie2_to_pcie3_wrapper_i_n_248,
      \s_axis_cq\\.tdata\(55) => xdma_0_pcie2_to_pcie3_wrapper_i_n_249,
      \s_axis_cq\\.tdata\(54) => xdma_0_pcie2_to_pcie3_wrapper_i_n_250,
      \s_axis_cq\\.tdata\(53) => xdma_0_pcie2_to_pcie3_wrapper_i_n_251,
      \s_axis_cq\\.tdata\(52) => xdma_0_pcie2_to_pcie3_wrapper_i_n_252,
      \s_axis_cq\\.tdata\(51) => xdma_0_pcie2_to_pcie3_wrapper_i_n_253,
      \s_axis_cq\\.tdata\(50) => xdma_0_pcie2_to_pcie3_wrapper_i_n_254,
      \s_axis_cq\\.tdata\(49) => xdma_0_pcie2_to_pcie3_wrapper_i_n_255,
      \s_axis_cq\\.tdata\(48) => xdma_0_pcie2_to_pcie3_wrapper_i_n_256,
      \s_axis_cq\\.tdata\(47) => xdma_0_pcie2_to_pcie3_wrapper_i_n_257,
      \s_axis_cq\\.tdata\(46) => xdma_0_pcie2_to_pcie3_wrapper_i_n_258,
      \s_axis_cq\\.tdata\(45) => xdma_0_pcie2_to_pcie3_wrapper_i_n_259,
      \s_axis_cq\\.tdata\(44) => xdma_0_pcie2_to_pcie3_wrapper_i_n_260,
      \s_axis_cq\\.tdata\(43) => xdma_0_pcie2_to_pcie3_wrapper_i_n_261,
      \s_axis_cq\\.tdata\(42) => xdma_0_pcie2_to_pcie3_wrapper_i_n_262,
      \s_axis_cq\\.tdata\(41) => xdma_0_pcie2_to_pcie3_wrapper_i_n_263,
      \s_axis_cq\\.tdata\(40) => xdma_0_pcie2_to_pcie3_wrapper_i_n_264,
      \s_axis_cq\\.tdata\(39) => xdma_0_pcie2_to_pcie3_wrapper_i_n_265,
      \s_axis_cq\\.tdata\(38) => xdma_0_pcie2_to_pcie3_wrapper_i_n_266,
      \s_axis_cq\\.tdata\(37) => xdma_0_pcie2_to_pcie3_wrapper_i_n_267,
      \s_axis_cq\\.tdata\(36) => xdma_0_pcie2_to_pcie3_wrapper_i_n_268,
      \s_axis_cq\\.tdata\(35) => xdma_0_pcie2_to_pcie3_wrapper_i_n_269,
      \s_axis_cq\\.tdata\(34) => xdma_0_pcie2_to_pcie3_wrapper_i_n_270,
      \s_axis_cq\\.tdata\(33) => xdma_0_pcie2_to_pcie3_wrapper_i_n_271,
      \s_axis_cq\\.tdata\(32) => xdma_0_pcie2_to_pcie3_wrapper_i_n_272,
      \s_axis_cq\\.tdata\(31) => xdma_0_pcie2_to_pcie3_wrapper_i_n_273,
      \s_axis_cq\\.tdata\(30) => xdma_0_pcie2_to_pcie3_wrapper_i_n_274,
      \s_axis_cq\\.tdata\(29) => xdma_0_pcie2_to_pcie3_wrapper_i_n_275,
      \s_axis_cq\\.tdata\(28) => xdma_0_pcie2_to_pcie3_wrapper_i_n_276,
      \s_axis_cq\\.tdata\(27) => xdma_0_pcie2_to_pcie3_wrapper_i_n_277,
      \s_axis_cq\\.tdata\(26) => xdma_0_pcie2_to_pcie3_wrapper_i_n_278,
      \s_axis_cq\\.tdata\(25) => xdma_0_pcie2_to_pcie3_wrapper_i_n_279,
      \s_axis_cq\\.tdata\(24) => xdma_0_pcie2_to_pcie3_wrapper_i_n_280,
      \s_axis_cq\\.tdata\(23) => xdma_0_pcie2_to_pcie3_wrapper_i_n_281,
      \s_axis_cq\\.tdata\(22) => xdma_0_pcie2_to_pcie3_wrapper_i_n_282,
      \s_axis_cq\\.tdata\(21) => xdma_0_pcie2_to_pcie3_wrapper_i_n_283,
      \s_axis_cq\\.tdata\(20) => xdma_0_pcie2_to_pcie3_wrapper_i_n_284,
      \s_axis_cq\\.tdata\(19) => xdma_0_pcie2_to_pcie3_wrapper_i_n_285,
      \s_axis_cq\\.tdata\(18) => xdma_0_pcie2_to_pcie3_wrapper_i_n_286,
      \s_axis_cq\\.tdata\(17) => xdma_0_pcie2_to_pcie3_wrapper_i_n_287,
      \s_axis_cq\\.tdata\(16) => xdma_0_pcie2_to_pcie3_wrapper_i_n_288,
      \s_axis_cq\\.tdata\(15) => xdma_0_pcie2_to_pcie3_wrapper_i_n_289,
      \s_axis_cq\\.tdata\(14) => xdma_0_pcie2_to_pcie3_wrapper_i_n_290,
      \s_axis_cq\\.tdata\(13) => xdma_0_pcie2_to_pcie3_wrapper_i_n_291,
      \s_axis_cq\\.tdata\(12) => xdma_0_pcie2_to_pcie3_wrapper_i_n_292,
      \s_axis_cq\\.tdata\(11) => xdma_0_pcie2_to_pcie3_wrapper_i_n_293,
      \s_axis_cq\\.tdata\(10) => xdma_0_pcie2_to_pcie3_wrapper_i_n_294,
      \s_axis_cq\\.tdata\(9) => xdma_0_pcie2_to_pcie3_wrapper_i_n_295,
      \s_axis_cq\\.tdata\(8) => xdma_0_pcie2_to_pcie3_wrapper_i_n_296,
      \s_axis_cq\\.tdata\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_297,
      \s_axis_cq\\.tdata\(6) => xdma_0_pcie2_to_pcie3_wrapper_i_n_298,
      \s_axis_cq\\.tdata\(5) => xdma_0_pcie2_to_pcie3_wrapper_i_n_299,
      \s_axis_cq\\.tdata\(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_300,
      \s_axis_cq\\.tdata\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_301,
      \s_axis_cq\\.tdata\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_302,
      \s_axis_cq\\.tdata\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_303,
      \s_axis_cq\\.tdata\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_304,
      \s_axis_cq\\.tkeep\(1 downto 0) => B"00",
      \s_axis_cq\\.tlast\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_240,
      \s_axis_cq\\.tready\(21 downto 1) => \NLW_udma_wrapper_s_axis_cq\\.tready_UNCONNECTED\(21 downto 1),
      \s_axis_cq\\.tready\(0) => udma_wrapper_n_11002,
      \s_axis_cq\\.tuser\(84 downto 8) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000",
      \s_axis_cq\\.tuser\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_305,
      \s_axis_cq\\.tuser\(6 downto 4) => B"000",
      \s_axis_cq\\.tuser\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_306,
      \s_axis_cq\\.tuser\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_307,
      \s_axis_cq\\.tuser\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_308,
      \s_axis_cq\\.tuser\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_309,
      \s_axis_cq\\.tvalid\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_310,
      \s_axis_rc\\.tdata\(63) => xdma_0_pcie2_to_pcie3_wrapper_i_n_176,
      \s_axis_rc\\.tdata\(62) => xdma_0_pcie2_to_pcie3_wrapper_i_n_177,
      \s_axis_rc\\.tdata\(61) => xdma_0_pcie2_to_pcie3_wrapper_i_n_178,
      \s_axis_rc\\.tdata\(60) => xdma_0_pcie2_to_pcie3_wrapper_i_n_179,
      \s_axis_rc\\.tdata\(59) => xdma_0_pcie2_to_pcie3_wrapper_i_n_180,
      \s_axis_rc\\.tdata\(58) => xdma_0_pcie2_to_pcie3_wrapper_i_n_181,
      \s_axis_rc\\.tdata\(57) => xdma_0_pcie2_to_pcie3_wrapper_i_n_182,
      \s_axis_rc\\.tdata\(56) => xdma_0_pcie2_to_pcie3_wrapper_i_n_183,
      \s_axis_rc\\.tdata\(55) => xdma_0_pcie2_to_pcie3_wrapper_i_n_184,
      \s_axis_rc\\.tdata\(54) => xdma_0_pcie2_to_pcie3_wrapper_i_n_185,
      \s_axis_rc\\.tdata\(53) => xdma_0_pcie2_to_pcie3_wrapper_i_n_186,
      \s_axis_rc\\.tdata\(52) => xdma_0_pcie2_to_pcie3_wrapper_i_n_187,
      \s_axis_rc\\.tdata\(51) => xdma_0_pcie2_to_pcie3_wrapper_i_n_188,
      \s_axis_rc\\.tdata\(50) => xdma_0_pcie2_to_pcie3_wrapper_i_n_189,
      \s_axis_rc\\.tdata\(49) => xdma_0_pcie2_to_pcie3_wrapper_i_n_190,
      \s_axis_rc\\.tdata\(48) => xdma_0_pcie2_to_pcie3_wrapper_i_n_191,
      \s_axis_rc\\.tdata\(47) => xdma_0_pcie2_to_pcie3_wrapper_i_n_192,
      \s_axis_rc\\.tdata\(46) => xdma_0_pcie2_to_pcie3_wrapper_i_n_193,
      \s_axis_rc\\.tdata\(45) => xdma_0_pcie2_to_pcie3_wrapper_i_n_194,
      \s_axis_rc\\.tdata\(44) => xdma_0_pcie2_to_pcie3_wrapper_i_n_195,
      \s_axis_rc\\.tdata\(43) => xdma_0_pcie2_to_pcie3_wrapper_i_n_196,
      \s_axis_rc\\.tdata\(42) => xdma_0_pcie2_to_pcie3_wrapper_i_n_197,
      \s_axis_rc\\.tdata\(41) => xdma_0_pcie2_to_pcie3_wrapper_i_n_198,
      \s_axis_rc\\.tdata\(40) => xdma_0_pcie2_to_pcie3_wrapper_i_n_199,
      \s_axis_rc\\.tdata\(39) => xdma_0_pcie2_to_pcie3_wrapper_i_n_200,
      \s_axis_rc\\.tdata\(38) => xdma_0_pcie2_to_pcie3_wrapper_i_n_201,
      \s_axis_rc\\.tdata\(37) => xdma_0_pcie2_to_pcie3_wrapper_i_n_202,
      \s_axis_rc\\.tdata\(36) => xdma_0_pcie2_to_pcie3_wrapper_i_n_203,
      \s_axis_rc\\.tdata\(35) => xdma_0_pcie2_to_pcie3_wrapper_i_n_204,
      \s_axis_rc\\.tdata\(34) => xdma_0_pcie2_to_pcie3_wrapper_i_n_205,
      \s_axis_rc\\.tdata\(33) => xdma_0_pcie2_to_pcie3_wrapper_i_n_206,
      \s_axis_rc\\.tdata\(32) => xdma_0_pcie2_to_pcie3_wrapper_i_n_207,
      \s_axis_rc\\.tdata\(31) => xdma_0_pcie2_to_pcie3_wrapper_i_n_208,
      \s_axis_rc\\.tdata\(30) => xdma_0_pcie2_to_pcie3_wrapper_i_n_209,
      \s_axis_rc\\.tdata\(29) => xdma_0_pcie2_to_pcie3_wrapper_i_n_210,
      \s_axis_rc\\.tdata\(28) => xdma_0_pcie2_to_pcie3_wrapper_i_n_211,
      \s_axis_rc\\.tdata\(27) => xdma_0_pcie2_to_pcie3_wrapper_i_n_212,
      \s_axis_rc\\.tdata\(26) => xdma_0_pcie2_to_pcie3_wrapper_i_n_213,
      \s_axis_rc\\.tdata\(25) => xdma_0_pcie2_to_pcie3_wrapper_i_n_214,
      \s_axis_rc\\.tdata\(24) => xdma_0_pcie2_to_pcie3_wrapper_i_n_215,
      \s_axis_rc\\.tdata\(23) => xdma_0_pcie2_to_pcie3_wrapper_i_n_216,
      \s_axis_rc\\.tdata\(22) => xdma_0_pcie2_to_pcie3_wrapper_i_n_217,
      \s_axis_rc\\.tdata\(21) => xdma_0_pcie2_to_pcie3_wrapper_i_n_218,
      \s_axis_rc\\.tdata\(20) => xdma_0_pcie2_to_pcie3_wrapper_i_n_219,
      \s_axis_rc\\.tdata\(19) => xdma_0_pcie2_to_pcie3_wrapper_i_n_220,
      \s_axis_rc\\.tdata\(18) => xdma_0_pcie2_to_pcie3_wrapper_i_n_221,
      \s_axis_rc\\.tdata\(17) => xdma_0_pcie2_to_pcie3_wrapper_i_n_222,
      \s_axis_rc\\.tdata\(16) => xdma_0_pcie2_to_pcie3_wrapper_i_n_223,
      \s_axis_rc\\.tdata\(15) => xdma_0_pcie2_to_pcie3_wrapper_i_n_224,
      \s_axis_rc\\.tdata\(14) => xdma_0_pcie2_to_pcie3_wrapper_i_n_225,
      \s_axis_rc\\.tdata\(13) => xdma_0_pcie2_to_pcie3_wrapper_i_n_226,
      \s_axis_rc\\.tdata\(12) => xdma_0_pcie2_to_pcie3_wrapper_i_n_227,
      \s_axis_rc\\.tdata\(11) => xdma_0_pcie2_to_pcie3_wrapper_i_n_228,
      \s_axis_rc\\.tdata\(10) => xdma_0_pcie2_to_pcie3_wrapper_i_n_229,
      \s_axis_rc\\.tdata\(9) => xdma_0_pcie2_to_pcie3_wrapper_i_n_230,
      \s_axis_rc\\.tdata\(8) => xdma_0_pcie2_to_pcie3_wrapper_i_n_231,
      \s_axis_rc\\.tdata\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_232,
      \s_axis_rc\\.tdata\(6) => xdma_0_pcie2_to_pcie3_wrapper_i_n_233,
      \s_axis_rc\\.tdata\(5) => xdma_0_pcie2_to_pcie3_wrapper_i_n_234,
      \s_axis_rc\\.tdata\(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_235,
      \s_axis_rc\\.tdata\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_236,
      \s_axis_rc\\.tdata\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_237,
      \s_axis_rc\\.tdata\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_238,
      \s_axis_rc\\.tdata\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_239,
      \s_axis_rc\\.tkeep\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_173,
      \s_axis_rc\\.tkeep\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_174,
      \s_axis_rc\\.tlast\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_175,
      \s_axis_rc\\.tready\(21 downto 1) => \NLW_udma_wrapper_s_axis_rc\\.tready_UNCONNECTED\(21 downto 1),
      \s_axis_rc\\.tready\(0) => \axis_rc\\.tready\,
      \s_axis_rc\\.tuser\(74 downto 35) => B"0000000000000000000000000000000000000000",
      \s_axis_rc\\.tuser\(34) => xdma_0_pcie2_to_pcie3_wrapper_i_n_169,
      \s_axis_rc\\.tuser\(33) => '0',
      \s_axis_rc\\.tuser\(32) => xdma_0_pcie2_to_pcie3_wrapper_i_n_170,
      \s_axis_rc\\.tuser\(31 downto 8) => B"000000000000000000000000",
      \s_axis_rc\\.tuser\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_171,
      \s_axis_rc\\.tuser\(6 downto 4) => B"000",
      \s_axis_rc\\.tuser\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_172,
      \s_axis_rc\\.tuser\(2 downto 0) => B"000",
      \s_axis_rc\\.tvalid\ => '0',
      s_axis_rq_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_rq_tkeep(1 downto 0) => B"00",
      s_axis_rq_tlast => '0',
      s_axis_rq_tready => NLW_udma_wrapper_s_axis_rq_tready_UNCONNECTED,
      s_axis_rq_tuser(59 downto 0) => B"000000000000000000000000000000000000000000000000000000000000",
      s_axis_rq_tvalid => '0',
      sys_reset => \^integrated_bloc_reset_o\,
      user_cfg_ext_function_number_o(7 downto 0) => NLW_udma_wrapper_user_cfg_ext_function_number_o_UNCONNECTED(7 downto 0),
      user_cfg_ext_read_data_i(31 downto 0) => B"00000000000000000000000000000000",
      user_cfg_ext_read_data_valid_i => '0',
      user_cfg_ext_read_received_o => NLW_udma_wrapper_user_cfg_ext_read_received_o_UNCONNECTED,
      user_cfg_ext_register_number_o(9 downto 0) => NLW_udma_wrapper_user_cfg_ext_register_number_o_UNCONNECTED(9 downto 0),
      user_cfg_ext_write_byte_enable_o(3 downto 0) => NLW_udma_wrapper_user_cfg_ext_write_byte_enable_o_UNCONNECTED(3 downto 0),
      user_cfg_ext_write_data_o(31 downto 0) => NLW_udma_wrapper_user_cfg_ext_write_data_o_UNCONNECTED(31 downto 0),
      user_cfg_ext_write_received_o => NLW_udma_wrapper_user_cfg_ext_write_received_o_UNCONNECTED,
      user_clk => \^axi_aclk\,
      usr_flr_clr => NLW_udma_wrapper_usr_flr_clr_UNCONNECTED,
      usr_flr_done_fnc(7 downto 0) => B"00000000",
      usr_flr_done_vld => '0',
      usr_flr_fnc(7 downto 0) => NLW_udma_wrapper_usr_flr_fnc_UNCONNECTED(7 downto 0),
      usr_flr_set => NLW_udma_wrapper_usr_flr_set_UNCONNECTED,
      usr_irq_ack(0) => usr_irq_ack(0),
      usr_irq_fail => NLW_udma_wrapper_usr_irq_fail_UNCONNECTED,
      usr_irq_function_number(1) => n_0_334,
      usr_irq_function_number(0) => n_0_335,
      usr_irq_req(0) => usr_irq_req(0)
    );
xdma_0_pcie2_to_pcie3_wrapper_i: entity work.xdma_0_xdma_0_pcie2_to_pcie3_wrapper
     port map (
      Integrated_bloc_reset_o => \^integrated_bloc_reset_o\,
      cfg_bus_number_o(7 downto 0) => cfg_bus_number_o(7 downto 0),
      cfg_dcommand(5) => xdma_0_pcie2_to_pcie3_wrapper_i_n_134,
      cfg_dcommand(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_135,
      cfg_dcommand(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_136,
      cfg_dcommand(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_137,
      cfg_dcommand(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_138,
      cfg_dcommand(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_139,
      cfg_device_number_o(4 downto 0) => cfg_device_number_o(4 downto 0),
      cfg_function_number_o(2 downto 0) => cfg_function_number_o(2 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => msi_vector_width(2 downto 0),
      cfg_interrupt_msienable => \^msi_enable\,
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_read_data(31 downto 0),
      cfg_mgmt_rd_wr_done => cfg_mgmt_read_write_done,
      cfg_to_turnoff_o => cfg_to_turnoff_o,
      clk_msien_reg(31 downto 0) => cfg_mgmt_write_data(31 downto 0),
      clk_msien_reg_0(3 downto 0) => cfg_mgmt_byte_enable(3 downto 0),
      clk_msien_reg_1(9 downto 0) => cfg_mgmt_addr(9 downto 0),
      clk_msien_reg_2 => cfg_mgmt_write,
      clk_msien_reg_3 => cfg_mgmt_read,
      clk_msien_reg_4 => cfg_mgmt_type1_cfg_reg_access,
      fc_nph(7 downto 0) => \pcie_dma_in\\.cfg_fc_nph\(7 downto 0),
      in0 => \xdma_0_axi_stream_intf_i/xdma_0_dma_cpl_i/p_0_in\,
      \m_axis_cc\\.tdata\(63) => udma_wrapper_n_10858,
      \m_axis_cc\\.tdata\(62) => udma_wrapper_n_10859,
      \m_axis_cc\\.tdata\(61) => udma_wrapper_n_10860,
      \m_axis_cc\\.tdata\(60) => udma_wrapper_n_10861,
      \m_axis_cc\\.tdata\(59) => udma_wrapper_n_10862,
      \m_axis_cc\\.tdata\(58) => udma_wrapper_n_10863,
      \m_axis_cc\\.tdata\(57) => udma_wrapper_n_10864,
      \m_axis_cc\\.tdata\(56) => udma_wrapper_n_10865,
      \m_axis_cc\\.tdata\(55) => udma_wrapper_n_10866,
      \m_axis_cc\\.tdata\(54) => udma_wrapper_n_10867,
      \m_axis_cc\\.tdata\(53) => udma_wrapper_n_10868,
      \m_axis_cc\\.tdata\(52) => udma_wrapper_n_10869,
      \m_axis_cc\\.tdata\(51) => udma_wrapper_n_10870,
      \m_axis_cc\\.tdata\(50) => udma_wrapper_n_10871,
      \m_axis_cc\\.tdata\(49) => udma_wrapper_n_10872,
      \m_axis_cc\\.tdata\(48) => udma_wrapper_n_10873,
      \m_axis_cc\\.tdata\(47) => udma_wrapper_n_10874,
      \m_axis_cc\\.tdata\(46) => udma_wrapper_n_10875,
      \m_axis_cc\\.tdata\(45) => udma_wrapper_n_10876,
      \m_axis_cc\\.tdata\(44) => udma_wrapper_n_10877,
      \m_axis_cc\\.tdata\(43) => udma_wrapper_n_10878,
      \m_axis_cc\\.tdata\(42) => udma_wrapper_n_10879,
      \m_axis_cc\\.tdata\(41) => udma_wrapper_n_10880,
      \m_axis_cc\\.tdata\(40) => udma_wrapper_n_10881,
      \m_axis_cc\\.tdata\(39) => udma_wrapper_n_10882,
      \m_axis_cc\\.tdata\(38) => udma_wrapper_n_10883,
      \m_axis_cc\\.tdata\(37) => udma_wrapper_n_10884,
      \m_axis_cc\\.tdata\(36) => udma_wrapper_n_10885,
      \m_axis_cc\\.tdata\(35) => udma_wrapper_n_10886,
      \m_axis_cc\\.tdata\(34) => udma_wrapper_n_10887,
      \m_axis_cc\\.tdata\(33) => udma_wrapper_n_10888,
      \m_axis_cc\\.tdata\(32) => udma_wrapper_n_10889,
      \m_axis_cc\\.tdata\(31) => udma_wrapper_n_10890,
      \m_axis_cc\\.tdata\(30) => udma_wrapper_n_10891,
      \m_axis_cc\\.tdata\(29) => udma_wrapper_n_10892,
      \m_axis_cc\\.tdata\(28) => udma_wrapper_n_10893,
      \m_axis_cc\\.tdata\(27) => udma_wrapper_n_10894,
      \m_axis_cc\\.tdata\(26) => udma_wrapper_n_10895,
      \m_axis_cc\\.tdata\(25) => udma_wrapper_n_10896,
      \m_axis_cc\\.tdata\(24) => udma_wrapper_n_10897,
      \m_axis_cc\\.tdata\(23) => udma_wrapper_n_10898,
      \m_axis_cc\\.tdata\(22) => udma_wrapper_n_10899,
      \m_axis_cc\\.tdata\(21) => udma_wrapper_n_10900,
      \m_axis_cc\\.tdata\(20) => udma_wrapper_n_10901,
      \m_axis_cc\\.tdata\(19) => udma_wrapper_n_10902,
      \m_axis_cc\\.tdata\(18) => udma_wrapper_n_10903,
      \m_axis_cc\\.tdata\(17) => udma_wrapper_n_10904,
      \m_axis_cc\\.tdata\(16) => udma_wrapper_n_10905,
      \m_axis_cc\\.tdata\(15) => udma_wrapper_n_10906,
      \m_axis_cc\\.tdata\(14) => udma_wrapper_n_10907,
      \m_axis_cc\\.tdata\(13) => udma_wrapper_n_10908,
      \m_axis_cc\\.tdata\(12) => udma_wrapper_n_10909,
      \m_axis_cc\\.tdata\(11) => udma_wrapper_n_10910,
      \m_axis_cc\\.tdata\(10) => udma_wrapper_n_10911,
      \m_axis_cc\\.tdata\(9) => udma_wrapper_n_10912,
      \m_axis_cc\\.tdata\(8) => udma_wrapper_n_10913,
      \m_axis_cc\\.tdata\(7) => udma_wrapper_n_10914,
      \m_axis_cc\\.tdata\(6) => udma_wrapper_n_10915,
      \m_axis_cc\\.tdata\(5) => udma_wrapper_n_10916,
      \m_axis_cc\\.tdata\(4) => udma_wrapper_n_10917,
      \m_axis_cc\\.tdata\(3) => udma_wrapper_n_10918,
      \m_axis_cc\\.tdata\(2) => udma_wrapper_n_10919,
      \m_axis_cc\\.tdata\(1) => udma_wrapper_n_10920,
      \m_axis_cc\\.tdata\(0) => udma_wrapper_n_10921,
      \m_axis_cc\\.tlast\ => udma_wrapper_n_10955,
      \m_axis_cc\\.tready\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_167,
      \m_axis_cc\\.tvalid\ => udma_wrapper_n_10958,
      \m_axis_rq\\.tdata\(63) => udma_wrapper_n_10730,
      \m_axis_rq\\.tdata\(62) => udma_wrapper_n_10731,
      \m_axis_rq\\.tdata\(61) => udma_wrapper_n_10732,
      \m_axis_rq\\.tdata\(60) => udma_wrapper_n_10733,
      \m_axis_rq\\.tdata\(59) => udma_wrapper_n_10734,
      \m_axis_rq\\.tdata\(58) => udma_wrapper_n_10735,
      \m_axis_rq\\.tdata\(57) => udma_wrapper_n_10736,
      \m_axis_rq\\.tdata\(56) => udma_wrapper_n_10737,
      \m_axis_rq\\.tdata\(55) => udma_wrapper_n_10738,
      \m_axis_rq\\.tdata\(54) => udma_wrapper_n_10739,
      \m_axis_rq\\.tdata\(53) => udma_wrapper_n_10740,
      \m_axis_rq\\.tdata\(52) => udma_wrapper_n_10741,
      \m_axis_rq\\.tdata\(51) => udma_wrapper_n_10742,
      \m_axis_rq\\.tdata\(50) => udma_wrapper_n_10743,
      \m_axis_rq\\.tdata\(49) => udma_wrapper_n_10744,
      \m_axis_rq\\.tdata\(48) => udma_wrapper_n_10745,
      \m_axis_rq\\.tdata\(47) => udma_wrapper_n_10746,
      \m_axis_rq\\.tdata\(46) => udma_wrapper_n_10747,
      \m_axis_rq\\.tdata\(45) => udma_wrapper_n_10748,
      \m_axis_rq\\.tdata\(44) => udma_wrapper_n_10749,
      \m_axis_rq\\.tdata\(43) => udma_wrapper_n_10750,
      \m_axis_rq\\.tdata\(42) => udma_wrapper_n_10751,
      \m_axis_rq\\.tdata\(41) => udma_wrapper_n_10752,
      \m_axis_rq\\.tdata\(40) => udma_wrapper_n_10753,
      \m_axis_rq\\.tdata\(39) => udma_wrapper_n_10754,
      \m_axis_rq\\.tdata\(38) => udma_wrapper_n_10755,
      \m_axis_rq\\.tdata\(37) => udma_wrapper_n_10756,
      \m_axis_rq\\.tdata\(36) => udma_wrapper_n_10757,
      \m_axis_rq\\.tdata\(35) => udma_wrapper_n_10758,
      \m_axis_rq\\.tdata\(34) => udma_wrapper_n_10759,
      \m_axis_rq\\.tdata\(33) => udma_wrapper_n_10760,
      \m_axis_rq\\.tdata\(32) => udma_wrapper_n_10761,
      \m_axis_rq\\.tdata\(31) => udma_wrapper_n_10762,
      \m_axis_rq\\.tdata\(30) => udma_wrapper_n_10763,
      \m_axis_rq\\.tdata\(29) => udma_wrapper_n_10764,
      \m_axis_rq\\.tdata\(28) => udma_wrapper_n_10765,
      \m_axis_rq\\.tdata\(27) => udma_wrapper_n_10766,
      \m_axis_rq\\.tdata\(26) => udma_wrapper_n_10767,
      \m_axis_rq\\.tdata\(25) => udma_wrapper_n_10768,
      \m_axis_rq\\.tdata\(24) => udma_wrapper_n_10769,
      \m_axis_rq\\.tdata\(23) => udma_wrapper_n_10770,
      \m_axis_rq\\.tdata\(22) => udma_wrapper_n_10771,
      \m_axis_rq\\.tdata\(21) => udma_wrapper_n_10772,
      \m_axis_rq\\.tdata\(20) => udma_wrapper_n_10773,
      \m_axis_rq\\.tdata\(19) => udma_wrapper_n_10774,
      \m_axis_rq\\.tdata\(18) => udma_wrapper_n_10775,
      \m_axis_rq\\.tdata\(17) => udma_wrapper_n_10776,
      \m_axis_rq\\.tdata\(16) => udma_wrapper_n_10777,
      \m_axis_rq\\.tdata\(15) => udma_wrapper_n_10778,
      \m_axis_rq\\.tdata\(14) => udma_wrapper_n_10779,
      \m_axis_rq\\.tdata\(13) => udma_wrapper_n_10780,
      \m_axis_rq\\.tdata\(12) => udma_wrapper_n_10781,
      \m_axis_rq\\.tdata\(11) => udma_wrapper_n_10782,
      \m_axis_rq\\.tdata\(10) => udma_wrapper_n_10783,
      \m_axis_rq\\.tdata\(9) => udma_wrapper_n_10784,
      \m_axis_rq\\.tdata\(8) => udma_wrapper_n_10785,
      \m_axis_rq\\.tdata\(7) => udma_wrapper_n_10786,
      \m_axis_rq\\.tdata\(6) => udma_wrapper_n_10787,
      \m_axis_rq\\.tdata\(5) => udma_wrapper_n_10788,
      \m_axis_rq\\.tdata\(4) => udma_wrapper_n_10789,
      \m_axis_rq\\.tdata\(3) => udma_wrapper_n_10790,
      \m_axis_rq\\.tdata\(2) => udma_wrapper_n_10791,
      \m_axis_rq\\.tdata\(1) => udma_wrapper_n_10792,
      \m_axis_rq\\.tdata\(0) => udma_wrapper_n_10793,
      \m_axis_rq\\.tlast\ => udma_wrapper_n_10794,
      \m_axis_rq\\.tready\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_168,
      \m_axis_rq\\.tuser\(11) => udma_wrapper_n_10827,
      \m_axis_rq\\.tuser\(10) => udma_wrapper_n_10828,
      \m_axis_rq\\.tuser\(9) => udma_wrapper_n_10829,
      \m_axis_rq\\.tuser\(8) => udma_wrapper_n_10830,
      \m_axis_rq\\.tuser\(7) => udma_wrapper_n_10847,
      \m_axis_rq\\.tuser\(6) => udma_wrapper_n_10848,
      \m_axis_rq\\.tuser\(5) => udma_wrapper_n_10849,
      \m_axis_rq\\.tuser\(4) => udma_wrapper_n_10850,
      \m_axis_rq\\.tuser\(3) => udma_wrapper_n_10851,
      \m_axis_rq\\.tuser\(2) => udma_wrapper_n_10852,
      \m_axis_rq\\.tuser\(1) => udma_wrapper_n_10853,
      \m_axis_rq\\.tuser\(0) => udma_wrapper_n_10854,
      \m_axis_rq\\.tvalid\ => udma_wrapper_n_10857,
      m_axis_rx_tdata_o(63 downto 0) => m_axis_rx_tdata_o(63 downto 0),
      m_axis_rx_tkeep_o(3 downto 0) => \^m_axis_rx_tkeep_o\(7 downto 4),
      m_axis_rx_tlast_o => m_axis_rx_tlast_o,
      m_axis_rx_tuser_o(13) => \^m_axis_rx_tuser_o\(21),
      m_axis_rx_tuser_o(12 downto 10) => \^m_axis_rx_tuser_o\(19 downto 17),
      m_axis_rx_tuser_o(9) => \^m_axis_rx_tuser_o\(14),
      m_axis_rx_tuser_o(8 downto 0) => \^m_axis_rx_tuser_o\(8 downto 0),
      m_axis_rx_tvalid_o => m_axis_rx_tvalid_o,
      \out\(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      \pcie_dma_in\\.cfg_interrupt_msi_sent\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_312,
      \pcie_dma_in\\.cfg_interrupt_sent\ => \pcie_dma_in\\.cfg_interrupt_sent\,
      \pcie_dma_in\\.cfg_phy_link_down\ => \pcie_dma_in\\.cfg_phy_link_down\,
      \pcie_dma_in\\.pcie_rq_seq_num0\(3 downto 0) => pcie_rq_seq_num0(3 downto 0),
      \pcie_dma_in\\.pcie_rq_seq_num_vld0\ => pcie_rq_seq_num_vld0,
      \pcie_dma_out\\.cfg_fc_sel\(0) => cfg_fc_sel(0),
      \pcie_dma_out\\.cfg_interrupt_int\(0) => cfg_interrupt_int(0),
      \pcie_dma_out\\.cfg_interrupt_msi_int\(31 downto 0) => cfg_interrupt_msi_int(31 downto 0),
      \pcie_dma_out\\.pcie_cq_np_req\(0) => pcie_cq_np_req,
      rdy_reg1_reg(1 downto 0) => pci_exp_rxn(1 downto 0),
      rdy_reg1_reg_0 => sys_clk,
      reset_n_reg2_reg => sys_rst_n,
      \s_axis_cq\\.tdata\(63) => xdma_0_pcie2_to_pcie3_wrapper_i_n_241,
      \s_axis_cq\\.tdata\(62) => xdma_0_pcie2_to_pcie3_wrapper_i_n_242,
      \s_axis_cq\\.tdata\(61) => xdma_0_pcie2_to_pcie3_wrapper_i_n_243,
      \s_axis_cq\\.tdata\(60) => xdma_0_pcie2_to_pcie3_wrapper_i_n_244,
      \s_axis_cq\\.tdata\(59) => xdma_0_pcie2_to_pcie3_wrapper_i_n_245,
      \s_axis_cq\\.tdata\(58) => xdma_0_pcie2_to_pcie3_wrapper_i_n_246,
      \s_axis_cq\\.tdata\(57) => xdma_0_pcie2_to_pcie3_wrapper_i_n_247,
      \s_axis_cq\\.tdata\(56) => xdma_0_pcie2_to_pcie3_wrapper_i_n_248,
      \s_axis_cq\\.tdata\(55) => xdma_0_pcie2_to_pcie3_wrapper_i_n_249,
      \s_axis_cq\\.tdata\(54) => xdma_0_pcie2_to_pcie3_wrapper_i_n_250,
      \s_axis_cq\\.tdata\(53) => xdma_0_pcie2_to_pcie3_wrapper_i_n_251,
      \s_axis_cq\\.tdata\(52) => xdma_0_pcie2_to_pcie3_wrapper_i_n_252,
      \s_axis_cq\\.tdata\(51) => xdma_0_pcie2_to_pcie3_wrapper_i_n_253,
      \s_axis_cq\\.tdata\(50) => xdma_0_pcie2_to_pcie3_wrapper_i_n_254,
      \s_axis_cq\\.tdata\(49) => xdma_0_pcie2_to_pcie3_wrapper_i_n_255,
      \s_axis_cq\\.tdata\(48) => xdma_0_pcie2_to_pcie3_wrapper_i_n_256,
      \s_axis_cq\\.tdata\(47) => xdma_0_pcie2_to_pcie3_wrapper_i_n_257,
      \s_axis_cq\\.tdata\(46) => xdma_0_pcie2_to_pcie3_wrapper_i_n_258,
      \s_axis_cq\\.tdata\(45) => xdma_0_pcie2_to_pcie3_wrapper_i_n_259,
      \s_axis_cq\\.tdata\(44) => xdma_0_pcie2_to_pcie3_wrapper_i_n_260,
      \s_axis_cq\\.tdata\(43) => xdma_0_pcie2_to_pcie3_wrapper_i_n_261,
      \s_axis_cq\\.tdata\(42) => xdma_0_pcie2_to_pcie3_wrapper_i_n_262,
      \s_axis_cq\\.tdata\(41) => xdma_0_pcie2_to_pcie3_wrapper_i_n_263,
      \s_axis_cq\\.tdata\(40) => xdma_0_pcie2_to_pcie3_wrapper_i_n_264,
      \s_axis_cq\\.tdata\(39) => xdma_0_pcie2_to_pcie3_wrapper_i_n_265,
      \s_axis_cq\\.tdata\(38) => xdma_0_pcie2_to_pcie3_wrapper_i_n_266,
      \s_axis_cq\\.tdata\(37) => xdma_0_pcie2_to_pcie3_wrapper_i_n_267,
      \s_axis_cq\\.tdata\(36) => xdma_0_pcie2_to_pcie3_wrapper_i_n_268,
      \s_axis_cq\\.tdata\(35) => xdma_0_pcie2_to_pcie3_wrapper_i_n_269,
      \s_axis_cq\\.tdata\(34) => xdma_0_pcie2_to_pcie3_wrapper_i_n_270,
      \s_axis_cq\\.tdata\(33) => xdma_0_pcie2_to_pcie3_wrapper_i_n_271,
      \s_axis_cq\\.tdata\(32) => xdma_0_pcie2_to_pcie3_wrapper_i_n_272,
      \s_axis_cq\\.tdata\(31) => xdma_0_pcie2_to_pcie3_wrapper_i_n_273,
      \s_axis_cq\\.tdata\(30) => xdma_0_pcie2_to_pcie3_wrapper_i_n_274,
      \s_axis_cq\\.tdata\(29) => xdma_0_pcie2_to_pcie3_wrapper_i_n_275,
      \s_axis_cq\\.tdata\(28) => xdma_0_pcie2_to_pcie3_wrapper_i_n_276,
      \s_axis_cq\\.tdata\(27) => xdma_0_pcie2_to_pcie3_wrapper_i_n_277,
      \s_axis_cq\\.tdata\(26) => xdma_0_pcie2_to_pcie3_wrapper_i_n_278,
      \s_axis_cq\\.tdata\(25) => xdma_0_pcie2_to_pcie3_wrapper_i_n_279,
      \s_axis_cq\\.tdata\(24) => xdma_0_pcie2_to_pcie3_wrapper_i_n_280,
      \s_axis_cq\\.tdata\(23) => xdma_0_pcie2_to_pcie3_wrapper_i_n_281,
      \s_axis_cq\\.tdata\(22) => xdma_0_pcie2_to_pcie3_wrapper_i_n_282,
      \s_axis_cq\\.tdata\(21) => xdma_0_pcie2_to_pcie3_wrapper_i_n_283,
      \s_axis_cq\\.tdata\(20) => xdma_0_pcie2_to_pcie3_wrapper_i_n_284,
      \s_axis_cq\\.tdata\(19) => xdma_0_pcie2_to_pcie3_wrapper_i_n_285,
      \s_axis_cq\\.tdata\(18) => xdma_0_pcie2_to_pcie3_wrapper_i_n_286,
      \s_axis_cq\\.tdata\(17) => xdma_0_pcie2_to_pcie3_wrapper_i_n_287,
      \s_axis_cq\\.tdata\(16) => xdma_0_pcie2_to_pcie3_wrapper_i_n_288,
      \s_axis_cq\\.tdata\(15) => xdma_0_pcie2_to_pcie3_wrapper_i_n_289,
      \s_axis_cq\\.tdata\(14) => xdma_0_pcie2_to_pcie3_wrapper_i_n_290,
      \s_axis_cq\\.tdata\(13) => xdma_0_pcie2_to_pcie3_wrapper_i_n_291,
      \s_axis_cq\\.tdata\(12) => xdma_0_pcie2_to_pcie3_wrapper_i_n_292,
      \s_axis_cq\\.tdata\(11) => xdma_0_pcie2_to_pcie3_wrapper_i_n_293,
      \s_axis_cq\\.tdata\(10) => xdma_0_pcie2_to_pcie3_wrapper_i_n_294,
      \s_axis_cq\\.tdata\(9) => xdma_0_pcie2_to_pcie3_wrapper_i_n_295,
      \s_axis_cq\\.tdata\(8) => xdma_0_pcie2_to_pcie3_wrapper_i_n_296,
      \s_axis_cq\\.tdata\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_297,
      \s_axis_cq\\.tdata\(6) => xdma_0_pcie2_to_pcie3_wrapper_i_n_298,
      \s_axis_cq\\.tdata\(5) => xdma_0_pcie2_to_pcie3_wrapper_i_n_299,
      \s_axis_cq\\.tdata\(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_300,
      \s_axis_cq\\.tdata\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_301,
      \s_axis_cq\\.tdata\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_302,
      \s_axis_cq\\.tdata\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_303,
      \s_axis_cq\\.tdata\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_304,
      \s_axis_cq\\.tlast\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_240,
      \s_axis_cq\\.tready\(0) => udma_wrapper_n_11002,
      \s_axis_cq\\.tuser\(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_305,
      \s_axis_cq\\.tuser\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_306,
      \s_axis_cq\\.tuser\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_307,
      \s_axis_cq\\.tuser\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_308,
      \s_axis_cq\\.tuser\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_309,
      \s_axis_cq\\.tvalid\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_310,
      \s_axis_rc\\.tdata\(63) => xdma_0_pcie2_to_pcie3_wrapper_i_n_176,
      \s_axis_rc\\.tdata\(62) => xdma_0_pcie2_to_pcie3_wrapper_i_n_177,
      \s_axis_rc\\.tdata\(61) => xdma_0_pcie2_to_pcie3_wrapper_i_n_178,
      \s_axis_rc\\.tdata\(60) => xdma_0_pcie2_to_pcie3_wrapper_i_n_179,
      \s_axis_rc\\.tdata\(59) => xdma_0_pcie2_to_pcie3_wrapper_i_n_180,
      \s_axis_rc\\.tdata\(58) => xdma_0_pcie2_to_pcie3_wrapper_i_n_181,
      \s_axis_rc\\.tdata\(57) => xdma_0_pcie2_to_pcie3_wrapper_i_n_182,
      \s_axis_rc\\.tdata\(56) => xdma_0_pcie2_to_pcie3_wrapper_i_n_183,
      \s_axis_rc\\.tdata\(55) => xdma_0_pcie2_to_pcie3_wrapper_i_n_184,
      \s_axis_rc\\.tdata\(54) => xdma_0_pcie2_to_pcie3_wrapper_i_n_185,
      \s_axis_rc\\.tdata\(53) => xdma_0_pcie2_to_pcie3_wrapper_i_n_186,
      \s_axis_rc\\.tdata\(52) => xdma_0_pcie2_to_pcie3_wrapper_i_n_187,
      \s_axis_rc\\.tdata\(51) => xdma_0_pcie2_to_pcie3_wrapper_i_n_188,
      \s_axis_rc\\.tdata\(50) => xdma_0_pcie2_to_pcie3_wrapper_i_n_189,
      \s_axis_rc\\.tdata\(49) => xdma_0_pcie2_to_pcie3_wrapper_i_n_190,
      \s_axis_rc\\.tdata\(48) => xdma_0_pcie2_to_pcie3_wrapper_i_n_191,
      \s_axis_rc\\.tdata\(47) => xdma_0_pcie2_to_pcie3_wrapper_i_n_192,
      \s_axis_rc\\.tdata\(46) => xdma_0_pcie2_to_pcie3_wrapper_i_n_193,
      \s_axis_rc\\.tdata\(45) => xdma_0_pcie2_to_pcie3_wrapper_i_n_194,
      \s_axis_rc\\.tdata\(44) => xdma_0_pcie2_to_pcie3_wrapper_i_n_195,
      \s_axis_rc\\.tdata\(43) => xdma_0_pcie2_to_pcie3_wrapper_i_n_196,
      \s_axis_rc\\.tdata\(42) => xdma_0_pcie2_to_pcie3_wrapper_i_n_197,
      \s_axis_rc\\.tdata\(41) => xdma_0_pcie2_to_pcie3_wrapper_i_n_198,
      \s_axis_rc\\.tdata\(40) => xdma_0_pcie2_to_pcie3_wrapper_i_n_199,
      \s_axis_rc\\.tdata\(39) => xdma_0_pcie2_to_pcie3_wrapper_i_n_200,
      \s_axis_rc\\.tdata\(38) => xdma_0_pcie2_to_pcie3_wrapper_i_n_201,
      \s_axis_rc\\.tdata\(37) => xdma_0_pcie2_to_pcie3_wrapper_i_n_202,
      \s_axis_rc\\.tdata\(36) => xdma_0_pcie2_to_pcie3_wrapper_i_n_203,
      \s_axis_rc\\.tdata\(35) => xdma_0_pcie2_to_pcie3_wrapper_i_n_204,
      \s_axis_rc\\.tdata\(34) => xdma_0_pcie2_to_pcie3_wrapper_i_n_205,
      \s_axis_rc\\.tdata\(33) => xdma_0_pcie2_to_pcie3_wrapper_i_n_206,
      \s_axis_rc\\.tdata\(32) => xdma_0_pcie2_to_pcie3_wrapper_i_n_207,
      \s_axis_rc\\.tdata\(31) => xdma_0_pcie2_to_pcie3_wrapper_i_n_208,
      \s_axis_rc\\.tdata\(30) => xdma_0_pcie2_to_pcie3_wrapper_i_n_209,
      \s_axis_rc\\.tdata\(29) => xdma_0_pcie2_to_pcie3_wrapper_i_n_210,
      \s_axis_rc\\.tdata\(28) => xdma_0_pcie2_to_pcie3_wrapper_i_n_211,
      \s_axis_rc\\.tdata\(27) => xdma_0_pcie2_to_pcie3_wrapper_i_n_212,
      \s_axis_rc\\.tdata\(26) => xdma_0_pcie2_to_pcie3_wrapper_i_n_213,
      \s_axis_rc\\.tdata\(25) => xdma_0_pcie2_to_pcie3_wrapper_i_n_214,
      \s_axis_rc\\.tdata\(24) => xdma_0_pcie2_to_pcie3_wrapper_i_n_215,
      \s_axis_rc\\.tdata\(23) => xdma_0_pcie2_to_pcie3_wrapper_i_n_216,
      \s_axis_rc\\.tdata\(22) => xdma_0_pcie2_to_pcie3_wrapper_i_n_217,
      \s_axis_rc\\.tdata\(21) => xdma_0_pcie2_to_pcie3_wrapper_i_n_218,
      \s_axis_rc\\.tdata\(20) => xdma_0_pcie2_to_pcie3_wrapper_i_n_219,
      \s_axis_rc\\.tdata\(19) => xdma_0_pcie2_to_pcie3_wrapper_i_n_220,
      \s_axis_rc\\.tdata\(18) => xdma_0_pcie2_to_pcie3_wrapper_i_n_221,
      \s_axis_rc\\.tdata\(17) => xdma_0_pcie2_to_pcie3_wrapper_i_n_222,
      \s_axis_rc\\.tdata\(16) => xdma_0_pcie2_to_pcie3_wrapper_i_n_223,
      \s_axis_rc\\.tdata\(15) => xdma_0_pcie2_to_pcie3_wrapper_i_n_224,
      \s_axis_rc\\.tdata\(14) => xdma_0_pcie2_to_pcie3_wrapper_i_n_225,
      \s_axis_rc\\.tdata\(13) => xdma_0_pcie2_to_pcie3_wrapper_i_n_226,
      \s_axis_rc\\.tdata\(12) => xdma_0_pcie2_to_pcie3_wrapper_i_n_227,
      \s_axis_rc\\.tdata\(11) => xdma_0_pcie2_to_pcie3_wrapper_i_n_228,
      \s_axis_rc\\.tdata\(10) => xdma_0_pcie2_to_pcie3_wrapper_i_n_229,
      \s_axis_rc\\.tdata\(9) => xdma_0_pcie2_to_pcie3_wrapper_i_n_230,
      \s_axis_rc\\.tdata\(8) => xdma_0_pcie2_to_pcie3_wrapper_i_n_231,
      \s_axis_rc\\.tdata\(7) => xdma_0_pcie2_to_pcie3_wrapper_i_n_232,
      \s_axis_rc\\.tdata\(6) => xdma_0_pcie2_to_pcie3_wrapper_i_n_233,
      \s_axis_rc\\.tdata\(5) => xdma_0_pcie2_to_pcie3_wrapper_i_n_234,
      \s_axis_rc\\.tdata\(4) => xdma_0_pcie2_to_pcie3_wrapper_i_n_235,
      \s_axis_rc\\.tdata\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_236,
      \s_axis_rc\\.tdata\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_237,
      \s_axis_rc\\.tdata\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_238,
      \s_axis_rc\\.tdata\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_239,
      \s_axis_rc\\.tkeep\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_173,
      \s_axis_rc\\.tkeep\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_174,
      \s_axis_rc\\.tlast\ => xdma_0_pcie2_to_pcie3_wrapper_i_n_175,
      \s_axis_rc\\.tready\(0) => \axis_rc\\.tready\,
      \s_axis_rc\\.tuser\(3) => xdma_0_pcie2_to_pcie3_wrapper_i_n_169,
      \s_axis_rc\\.tuser\(2) => xdma_0_pcie2_to_pcie3_wrapper_i_n_170,
      \s_axis_rc\\.tuser\(1) => xdma_0_pcie2_to_pcie3_wrapper_i_n_171,
      \s_axis_rc\\.tuser\(0) => xdma_0_pcie2_to_pcie3_wrapper_i_n_172,
      s_axis_tx_tready_o => s_axis_tx_tready_o,
      user_clk_out => \^axi_aclk\,
      user_lnk_up => \^user_lnk_up\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xdma_0 is
  port (
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    axi_aclk : out STD_LOGIC;
    axi_aresetn : out STD_LOGIC;
    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
    msi_enable : out STD_LOGIC;
    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC;
    m_axi_wready : in STD_LOGIC;
    m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bvalid : in STD_LOGIC;
    m_axi_arready : in STD_LOGIC;
    m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rlast : in STD_LOGIC;
    m_axi_rvalid : in STD_LOGIC;
    m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_awlock : out STD_LOGIC;
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_arlock : out STD_LOGIC;
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rready : out STD_LOGIC;
    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
    cfg_mgmt_write : in STD_LOGIC;
    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_read : in STD_LOGIC;
    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_read_write_done : out STD_LOGIC;
    cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC;
    m_axib_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awvalid : out STD_LOGIC;
    m_axib_awready : in STD_LOGIC;
    m_axib_awlock : out STD_LOGIC;
    m_axib_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_wlast : out STD_LOGIC;
    m_axib_wvalid : out STD_LOGIC;
    m_axib_wready : in STD_LOGIC;
    m_axib_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_bvalid : in STD_LOGIC;
    m_axib_bready : out STD_LOGIC;
    m_axib_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arvalid : out STD_LOGIC;
    m_axib_arready : in STD_LOGIC;
    m_axib_arlock : out STD_LOGIC;
    m_axib_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_rlast : in STD_LOGIC;
    m_axib_rvalid : in STD_LOGIC;
    cfg_bus_number_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_to_turnoff_o : out STD_LOGIC;
    m_axis_rx_tdata_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast_o : out STD_LOGIC;
    m_axis_rx_tuser_o : out STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_rx_tvalid_o : out STD_LOGIC;
    Integrated_bloc_reset_o : out STD_LOGIC;
    s_axis_tx_tready_o : out STD_LOGIC;
    m_axib_rready : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of xdma_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of xdma_0 : entity is "xdma_0,xdma_0_core_top,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of xdma_0 : entity is "yes";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xdma_0 : entity is "xdma_0_core_top,Vivado 2020.2";
end xdma_0;

architecture STRUCTURE of xdma_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^m_axis_rx_tkeep_o\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \^m_axis_rx_tuser_o\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal NLW_inst_ats_pri_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_atspri_m_axis_cq_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_atspri_m_axis_cq_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_atspri_s_axis_rq_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_axi_ctl_aresetn_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_c2h_dsc_byp_ready_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_c2h_dsc_byp_ready_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_c2h_dsc_byp_ready_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_c2h_dsc_byp_ready_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cap_req_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_cor_in_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_cor_o_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_fatal_o_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_nonfatal_o_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_err_uncor_in_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_ext_read_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_ext_write_received_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msi_fail_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msi_pending_status_data_enable_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msi_sent_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msi_tph_present_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msix_fail_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msix_int_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_interrupt_msix_sent_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_link_training_enable_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_local_error_valid_o_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_mgmt_read_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_mgmt_type1_cfg_reg_access_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_mgmt_write_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_msg_transmit_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_status_ats_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_status_pr_en_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_status_pr_rf_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_status_pr_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cfg_status_pr_uprgi_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_core_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_active_ack_tx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_active_req_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_cntl_chk_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_crdgnt_chk_tx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_crdgnt_tx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_crdrtn_chk_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_crdrtn_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_deact_hint_tx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_valid_chk_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_cxs0_valid_rx_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_drp_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_drpclk_usp_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_ch_gt_drpclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_bufg_gt_ce_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_bufg_gt_reset_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_bufgtcemask_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_gt_bufgtrstmask_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_phy_clk_txoutclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_ext_usp_qpllxrcalenb_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gt_drp_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_reset_rx_done_us_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_reset_rx_done_usp_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_reset_tx_done_us_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_reset_tx_done_usp_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_userclk_rx_active_us_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_userclk_rx_active_usp_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_userclk_tx_active_us_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_userclk_tx_active_usp_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_gtwiz_userclk_tx_reset_us_in_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_h2c_dsc_byp_ready_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_h2c_dsc_byp_ready_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_h2c_dsc_byp_ready_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_h2c_dsc_byp_ready_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_dclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_oobclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_pclk_out_slave_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_userclk1_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_int_userclk2_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msi_vec0to31_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msi_vec32to63_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msix_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msix_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msix_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_interrupt_out_msix_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axib_arlock_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axib_awlock_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axil_arvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axil_awvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axil_bready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axil_rready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axil_wvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_cc_tlast_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_cc_tvalid_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_cq_tready_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tlast_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tlast_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tlast_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tlast_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tvalid_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tvalid_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tvalid_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_h2c_tvalid_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_rc_tready_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_rq_tlast_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_m_axis_rq_tvalid_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_mcap_design_switch_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_msix_enable_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_active_ack_rx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_active_req_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_cntl_chk_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_crdgnt_chk_rx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_crdgnt_rx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_crdrtn_chk_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_crdrtn_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_deact_hint_rx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_valid_chk_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pcie4_cxs0_valid_tx_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_phy_prst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_phy_rrst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_phy_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_gen3_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_qrst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_rate_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_tx0_rcvr_det_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_pipe_txoutclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_gen3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_ovrd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_rst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_drp_start_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_qpll_qplld_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_rd_interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axib_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axil_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axil_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axil_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axil_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axil_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_c2h_tready_0_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_c2h_tready_1_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_c2h_tready_2_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_c2h_tready_3_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_cc_tlast_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_cc_tvalid_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_cq_tlast_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_cq_tready_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_cq_tvalid_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_rc_tlast_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_rc_tready_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_rc_tvalid_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_rq_tlast_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_s_axis_rq_tvalid_sd_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_m_axis_cq_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_m_axis_cq_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_m_axis_rc_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_m_axis_rc_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_s_axis_cc_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc0_ats_s_axis_rq_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_m_axis_cq_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_m_axis_cq_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_m_axis_rc_tlast_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_m_axis_rc_tvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_s_axis_cc_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sc1_ats_s_axis_rq_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_cfgclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_cfgmclk_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_eos_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_startup_preq_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sys_clk_bufg_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_sys_clk_ce_out_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_usr_flr_clr_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_usr_flr_set_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_wr_interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_inst_atspri_m_axis_cq_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_atspri_m_axis_cq_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_atspri_m_axis_cq_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 84 downto 0 );
  signal NLW_inst_c2h_sts_0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_c2h_sts_1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_c2h_sts_2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_c2h_sts_3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_current_speed_o_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_ds_bus_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_ds_device_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_cfg_ds_function_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_ds_port_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_dsn_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_cfg_ext_function_number_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_ext_register_number_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_cfg_ext_write_byte_enable_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_ext_write_data_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_fc_sel_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_flr_done_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_flr_in_process_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_function_status_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_interrupt_int_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_attr_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_enable_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_function_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_int_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_pending_status_function_num_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_pending_status_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_tph_st_tag_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_cfg_interrupt_msi_tph_type_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cfg_interrupt_msix_address_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_cfg_interrupt_msix_data_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_interrupt_msix_enable_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cfg_interrupt_msix_mask_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cfg_interrupt_msix_vec_pending_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cfg_interrupt_pending_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_local_error_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_cfg_ltssm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_cfg_ltssm_state_o_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_cfg_max_payload_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_max_read_req_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_mgmt_addr_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_cfg_mgmt_byte_enable_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_mgmt_function_number_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_cfg_mgmt_write_data_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_msg_transmit_data_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_msg_transmit_type_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_cfg_negotiated_width_o_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_cfg_status_ats_stu_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_cfg_status_ost_pr_alloc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cfg_vf_flr_in_process_UNCONNECTED : STD_LOGIC_VECTOR ( 251 downto 0 );
  signal NLW_inst_common_commands_out_UNCONNECTED : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal NLW_inst_cpllfreqlock_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cpllpd_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cpllpd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cpllreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cpllreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_cxs0_cntl_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_cxs0_data_chk_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_cxs0_data_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal NLW_inst_dmonfiforeset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_dmonfiforeset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_dmonitorclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_dmonitorclk_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drp_do_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_drpaddr_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal NLW_inst_drpaddr_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal NLW_inst_drpclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drpdi_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_drpdi_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_drpen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drpen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drprst_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drpwe_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_drpwe_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_ext_ch_gt_drpdo_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_ext_ch_gt_drprdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_ext_phy_clk_bufgtdiv_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_ext_qpll1pd_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_qpll1rate_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_ext_qpll1refclk_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_qpll1reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_usp_qpll0pd_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_usp_qpll0reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_usp_qpll1pd_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_usp_qpll1reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_ext_usp_qpllxrate_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_ext_usp_qpllxrefclk_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_eyescanreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_eyescanreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_bufgtdiv_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_inst_gt_ch_drp_rdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_cplllock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 33 downto 0 );
  signal NLW_inst_gt_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_gen34_eios_det_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_gtpowergood_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_pcierateidle_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_pcieuserratestart_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_phystatus_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_qpll0lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_gt_qpll1lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_gt_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_gt_rxcdrlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxoutclk_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxoutclkfabric_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxoutclkpcs_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxprbslocked_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxrecclkout_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_gt_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_rxvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txelecidle_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txoutclk_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txoutclkfabric_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txoutclkpcs_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txprogdivresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gt_txsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gthrxn_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gthrxp_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gtrefclk00_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_gtrefclk01_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_gtrefclk01_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_gtrefclk0_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gtrefclk0_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gtrxreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gtrxreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gttxreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_gttxreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_h2c_sts_0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_h2c_sts_1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_h2c_sts_2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_h2c_sts_3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_int_qpll1lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_qpll1outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_qpll1outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_qplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_qplloutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_qplloutrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_int_usp_qpll0lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_usp_qpll0outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_usp_qpll0outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_usp_qpll1lock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_usp_qpll1outclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_int_usp_qpll1outrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_loopback_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_loopback_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axib_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axib_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axib_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axil_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axil_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axil_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_inst_m_axil_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axil_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_m_axil_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal NLW_inst_m_axil_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_m_axil_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axis_cc_tdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_cc_tkeep_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axis_cc_tready_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axis_cc_tuser_out_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal NLW_inst_m_axis_h2c_tdata_0_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_h2c_tdata_1_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_h2c_tdata_2_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_h2c_tdata_3_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_h2c_tkeep_0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tkeep_1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tkeep_2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tkeep_3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tuser_0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tuser_1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tuser_2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_h2c_tuser_3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_m_axis_rq_tdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_m_axis_rq_tkeep_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_m_axis_rq_tready_out_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axis_rq_tuser_out_UNCONNECTED : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal NLW_inst_m_axis_rx_tkeep_o_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_m_axis_rx_tuser_o_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 9 );
  signal NLW_inst_pcie4_cxs0_cntl_tx_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_pcie4_cxs0_data_chk_tx_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_pcie4_cxs0_data_tx_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal NLW_inst_pcie_cq_np_req_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcieeqrxeqadaptdone_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcieeqrxeqadaptdone_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcierateqpll0_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_pcierateqpll1_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_inst_pcierstidle_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcierstidle_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pciersttxsyncstart_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pciersttxsyncstart_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcieuserratedone_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcieuserratedone_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pcsrsvdin_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_phy_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_phy_rxeq_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_phy_txeq_ctrl_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_phy_txeq_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_phy_txeq_preset_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_pipe_cpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_pipe_debug_0_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_1_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_2_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_3_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_4_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_5_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_6_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_7_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_8_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_9_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_128_0_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_128_1_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_128_2_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_128_3_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_ext_16_0_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_ext_16_1_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_ext_16_2_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_debug_debug_out_ext_16_3_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_debug_inject_rx_status_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_pipe_debug_inject_tx_status_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_pipe_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_inst_pipe_drp_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_pipe_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_pclk_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_qpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_pipe_qrst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_pipe_rate_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_pipe_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_pipe_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_pipe_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxdisperr_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxnotintable_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_pipe_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_pipe_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_sync_fsm_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_pipe_sync_fsm_tx_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_inst_pipe_tx0_powerdown_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_tx_0_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_10_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_11_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_12_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_13_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_14_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_15_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_1_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_2_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_3_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_4_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_5_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_6_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_7_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_8_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_tx_9_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 83 downto 0 );
  signal NLW_inst_pipe_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_pipe_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll0clk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll0freqlock_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll0pd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll0refclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll0reset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll1clk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll1freqlock_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll1pd_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll1pd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll1refclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpll1reset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll1reset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_qpll_qpllreset_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_qpllrsvd2_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_qpllrsvd3_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_inst_rcalenb_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_inst_resetovrd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rx8b10ben_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rx8b10ben_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxbufreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxbufreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcdrfreqreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcdrhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcdrhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcdrreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcommadeten_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxcommadeten_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfeagchold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfeagchold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfecfokhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfecfokhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfekhhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfekhhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfelfhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfelfhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfelpmreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap10hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap10hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap11hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap11hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap12hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap12hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap13hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap13hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap14hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap14hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap15hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap15hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap2hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap2hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap3hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap3hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap4hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap4hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap5hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap5hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap6hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap6hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap7hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap7hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap8hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap8hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap9hold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfetap9hold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfeuthold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfeuthold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfevphold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxdfevphold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmgchold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmgchold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmhfhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmhfhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmlfhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmlfhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmoshold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxlpmoshold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxmcommaalignen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxmcommaalignen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxoshold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxoshold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpcommaalignen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpcommaalignen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpcsreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpd_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_rxpd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_rxpmareset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpolarity_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxpolarity_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxprbscntreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxprbscntreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxprbssel_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_rxprbssel_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_rxprogdivreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxprogdivreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxrate_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_rxrate_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_rxratemode_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxratemode_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxslide_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxslide_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxtermination_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxuserrdy_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxuserrdy_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxusrclk2_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxusrclk2_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxusrclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_rxusrclk_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axib_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_s_axib_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axib_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_s_axib_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_s_axib_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axib_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_s_axil_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axil_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_s_axil_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axis_cc_tdata_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_s_axis_cc_tkeep_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axis_cc_tuser_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 );
  signal NLW_inst_s_axis_cq_tdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_s_axis_cq_tkeep_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axis_cq_tuser_out_UNCONNECTED : STD_LOGIC_VECTOR ( 84 downto 0 );
  signal NLW_inst_s_axis_rc_tdata_out_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_s_axis_rc_tkeep_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axis_rc_tuser_out_UNCONNECTED : STD_LOGIC_VECTOR ( 74 downto 0 );
  signal NLW_inst_s_axis_rq_tdata_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_s_axis_rq_tkeep_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_s_axis_rq_tuser_sd_UNCONNECTED : STD_LOGIC_VECTOR ( 59 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_cq_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_cq_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_cq_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 84 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_rc_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_rc_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_sc0_ats_m_axis_rc_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 74 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_cq_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_cq_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_cq_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 84 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_rc_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_rc_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_sc1_ats_m_axis_rc_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 74 downto 0 );
  signal NLW_inst_startup_di_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_tx8b10ben_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_tx8b10ben_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txctrl0_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_txctrl0_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_txctrl1_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_txctrl1_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_inst_txctrl2_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_txctrl2_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_inst_txdata_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal NLW_inst_txdata_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal NLW_inst_txdeemph_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdeemph_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_txdetectrx_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdetectrx_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdiffctrl_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_txdiffctrl_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_txdlybypass_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlybypass_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyhold_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyhold_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyovrden_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyovrden_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlysreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlysreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyupdown_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txdlyupdown_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txelecidle_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txelecidle_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txinhibit_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txmaincursor_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_txmaincursor_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_inst_txmargin_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txmargin_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txoutclksel_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txoutclksel_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txpcsreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txpd_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_txpd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_inst_txpdelecidlemode_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphalign_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphalign_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphalignen_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphalignen_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlypd_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlypd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlyreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlyreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlytstclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphdlytstclk_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphinit_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphinit_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphovrden_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txphovrden_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txpisopd_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txpmareset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txpostcursor_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_txpostcursor_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_txprbsforceerr_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txprbsforceerr_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txprbssel_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_txprbssel_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_inst_txprecursor_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_txprecursor_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_inst_txprogdivreset_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txprogdivreset_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txrate_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txrate_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_inst_txswing_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txswing_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncallin_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncallin_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncin_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncin_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncmode_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txsyncmode_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txuserrdy_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txuserrdy_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txusrclk2_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txusrclk2_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txusrclk_us_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_txusrclk_usp_in_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_inst_usr_flr_fnc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute ACS_EXT_CAP_ENABLE : string;
  attribute ACS_EXT_CAP_ENABLE of inst : label is "FALSE";
  attribute AXI4MM_ULTRA : integer;
  attribute AXI4MM_ULTRA of inst : label is 0;
  attribute AXILITE_MASTER_APERTURE_SIZE : string;
  attribute AXILITE_MASTER_APERTURE_SIZE of inst : label is "8'b00001101";
  attribute AXILITE_MASTER_CONTROL : string;
  attribute AXILITE_MASTER_CONTROL of inst : label is "3'b000";
  attribute AXISTEN_IF_ENABLE_MSG_ROUTE : string;
  attribute AXISTEN_IF_ENABLE_MSG_ROUTE of inst : label is "18'b000000000000000000";
  attribute AXIST_BYPASS_APERTURE_SIZE : string;
  attribute AXIST_BYPASS_APERTURE_SIZE of inst : label is "8'b00001101";
  attribute AXIST_BYPASS_CONTROL : string;
  attribute AXIST_BYPASS_CONTROL of inst : label is "3'b100";
  attribute AXIS_CCIX_RX_TDATA_WIDTH : integer;
  attribute AXIS_CCIX_RX_TDATA_WIDTH of inst : label is 256;
  attribute AXIS_CCIX_RX_TUSER_WIDTH : integer;
  attribute AXIS_CCIX_RX_TUSER_WIDTH of inst : label is 47;
  attribute AXIS_CCIX_TX_TDATA_WIDTH : integer;
  attribute AXIS_CCIX_TX_TDATA_WIDTH of inst : label is 256;
  attribute AXIS_CCIX_TX_TUSER_WIDTH : integer;
  attribute AXIS_CCIX_TX_TUSER_WIDTH of inst : label is 47;
  attribute AXIS_PIPE_LINE_STAGE : integer;
  attribute AXIS_PIPE_LINE_STAGE of inst : label is 0;
  attribute AXI_ACLK_LOOPBACK : string;
  attribute AXI_ACLK_LOOPBACK of inst : label is "FALSE";
  attribute AXI_ADDR_WIDTH : integer;
  attribute AXI_ADDR_WIDTH of inst : label is 64;
  attribute AXI_DATA_WIDTH : integer;
  attribute AXI_DATA_WIDTH of inst : label is 64;
  attribute AXI_VIP_IN_EXDES : string;
  attribute AXI_VIP_IN_EXDES of inst : label is "FALSE";
  attribute AXSIZE_BYTE_ACCESS_EN : string;
  attribute AXSIZE_BYTE_ACCESS_EN of inst : label is "FALSE";
  attribute BACKPRESSURE : integer;
  attribute BACKPRESSURE of inst : label is 0;
  attribute BARLITE0 : integer;
  attribute BARLITE0 of inst : label is 7;
  attribute BARLITE1 : integer;
  attribute BARLITE1 of inst : label is 0;
  attribute BARLITE2 : integer;
  attribute BARLITE2 of inst : label is 7;
  attribute BARLITE_EXT_PF0 : string;
  attribute BARLITE_EXT_PF0 of inst : label is "6'b000000";
  attribute BARLITE_EXT_PF1 : string;
  attribute BARLITE_EXT_PF1 of inst : label is "6'b000000";
  attribute BARLITE_EXT_PF2 : string;
  attribute BARLITE_EXT_PF2 of inst : label is "6'b000000";
  attribute BARLITE_EXT_PF3 : string;
  attribute BARLITE_EXT_PF3 of inst : label is "6'b000000";
  attribute BARLITE_INT_PF0 : string;
  attribute BARLITE_INT_PF0 of inst : label is "6'b000001";
  attribute BARLITE_INT_PF1 : string;
  attribute BARLITE_INT_PF1 of inst : label is "6'b000000";
  attribute BARLITE_INT_PF2 : string;
  attribute BARLITE_INT_PF2 of inst : label is "6'b000000";
  attribute BARLITE_INT_PF3 : string;
  attribute BARLITE_INT_PF3 of inst : label is "6'b000000";
  attribute C2H_XDMA_CHNL : string;
  attribute C2H_XDMA_CHNL of inst : label is "8'b00001111";
  attribute CCIX_DVSEC : string;
  attribute CCIX_DVSEC of inst : label is "FALSE";
  attribute CCIX_ENABLE : string;
  attribute CCIX_ENABLE of inst : label is "FALSE";
  attribute CDC_WB_EN : integer;
  attribute CDC_WB_EN of inst : label is 1;
  attribute CFG_EXT_IF : string;
  attribute CFG_EXT_IF of inst : label is "FALSE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of inst : label is "TRUE";
  attribute COMPONENT_NAME : string;
  attribute COMPONENT_NAME of inst : label is "xdma_0";
  attribute CORE_CLK_FREQ : integer;
  attribute CORE_CLK_FREQ of inst : label is 2;
  attribute C_ADDR_ALGN : integer;
  attribute C_ADDR_ALGN of inst : label is 1;
  attribute C_ADDR_BITS : integer;
  attribute C_ADDR_BITS of inst : label is 64;
  attribute C_ATS_CAP_NEXTPTR : string;
  attribute C_ATS_CAP_NEXTPTR of inst : label is "12'b000000000000";
  attribute C_ATS_CC_TUSER_WIDTH : integer;
  attribute C_ATS_CC_TUSER_WIDTH of inst : label is 33;
  attribute C_ATS_CQ_TUSER_WIDTH : integer;
  attribute C_ATS_CQ_TUSER_WIDTH of inst : label is 85;
  attribute C_ATS_DATA_WIDTH : integer;
  attribute C_ATS_DATA_WIDTH of inst : label is 64;
  attribute C_ATS_ENABLE : string;
  attribute C_ATS_ENABLE of inst : label is "FALSE";
  attribute C_ATS_OFFSET : string;
  attribute C_ATS_OFFSET of inst : label is "30'b000000000000000000000100100000";
  attribute C_ATS_RC_TUSER_WIDTH : integer;
  attribute C_ATS_RC_TUSER_WIDTH of inst : label is 75;
  attribute C_ATS_RQ_TUSER_WIDTH : integer;
  attribute C_ATS_RQ_TUSER_WIDTH of inst : label is 60;
  attribute C_ATS_SWITCH_UNIQUE_BDF : integer;
  attribute C_ATS_SWITCH_UNIQUE_BDF of inst : label is 1;
  attribute C_AXIBAR2PCIEATTR_0 : string;
  attribute C_AXIBAR2PCIEATTR_0 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_1 : string;
  attribute C_AXIBAR2PCIEATTR_1 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_2 : string;
  attribute C_AXIBAR2PCIEATTR_2 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_3 : string;
  attribute C_AXIBAR2PCIEATTR_3 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_4 : string;
  attribute C_AXIBAR2PCIEATTR_4 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEATTR_5 : string;
  attribute C_AXIBAR2PCIEATTR_5 of inst : label is "3'b000";
  attribute C_AXIBAR2PCIEBAR_0 : string;
  attribute C_AXIBAR2PCIEBAR_0 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_1 : string;
  attribute C_AXIBAR2PCIEBAR_1 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_2 : string;
  attribute C_AXIBAR2PCIEBAR_2 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_3 : string;
  attribute C_AXIBAR2PCIEBAR_3 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_4 : string;
  attribute C_AXIBAR2PCIEBAR_4 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR2PCIEBAR_5 : string;
  attribute C_AXIBAR2PCIEBAR_5 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_0 : string;
  attribute C_AXIBAR_0 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_1 : string;
  attribute C_AXIBAR_1 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_2 : string;
  attribute C_AXIBAR_2 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_3 : string;
  attribute C_AXIBAR_3 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_4 : string;
  attribute C_AXIBAR_4 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_5 : string;
  attribute C_AXIBAR_5 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_AS_0 : integer;
  attribute C_AXIBAR_AS_0 of inst : label is 1;
  attribute C_AXIBAR_AS_1 : integer;
  attribute C_AXIBAR_AS_1 of inst : label is 1;
  attribute C_AXIBAR_AS_2 : integer;
  attribute C_AXIBAR_AS_2 of inst : label is 1;
  attribute C_AXIBAR_AS_3 : integer;
  attribute C_AXIBAR_AS_3 of inst : label is 1;
  attribute C_AXIBAR_AS_4 : integer;
  attribute C_AXIBAR_AS_4 of inst : label is 1;
  attribute C_AXIBAR_AS_5 : integer;
  attribute C_AXIBAR_AS_5 of inst : label is 1;
  attribute C_AXIBAR_HIGHADDR_0 : string;
  attribute C_AXIBAR_HIGHADDR_0 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_1 : string;
  attribute C_AXIBAR_HIGHADDR_1 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_2 : string;
  attribute C_AXIBAR_HIGHADDR_2 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_3 : string;
  attribute C_AXIBAR_HIGHADDR_3 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_4 : string;
  attribute C_AXIBAR_HIGHADDR_4 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_HIGHADDR_5 : string;
  attribute C_AXIBAR_HIGHADDR_5 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_AXIBAR_NOXLATE : integer;
  attribute C_AXIBAR_NOXLATE of inst : label is 0;
  attribute C_AXIBAR_NUM : integer;
  attribute C_AXIBAR_NUM of inst : label is 1;
  attribute C_AXIBAR_REGIONEN : integer;
  attribute C_AXIBAR_REGIONEN of inst : label is 0;
  attribute C_BASEADDR : integer;
  attribute C_BASEADDR of inst : label is 4096;
  attribute C_C2H_NUM_CHNL : integer;
  attribute C_C2H_NUM_CHNL of inst : label is 1;
  attribute C_C2H_NUM_RIDS : integer;
  attribute C_C2H_NUM_RIDS of inst : label is 16;
  attribute C_C2H_TUSER_WIDTH : integer;
  attribute C_C2H_TUSER_WIDTH of inst : label is 64;
  attribute C_COMP_TIMEOUT : integer;
  attribute C_COMP_TIMEOUT of inst : label is 1;
  attribute C_DEVICE_NUMBER : integer;
  attribute C_DEVICE_NUMBER of inst : label is 0;
  attribute C_DSC_MAGIC_EN : integer;
  attribute C_DSC_MAGIC_EN of inst : label is 1;
  attribute C_ECC_ENABLE : integer;
  attribute C_ECC_ENABLE of inst : label is 0;
  attribute C_ENABLE_RESOURCE_REDUCTION : string;
  attribute C_ENABLE_RESOURCE_REDUCTION of inst : label is "FALSE";
  attribute C_FAMILY : string;
  attribute C_FAMILY of inst : label is "artix7";
  attribute C_FF_ON_INT_IF : string;
  attribute C_FF_ON_INT_IF of inst : label is "FALSE";
  attribute C_GEN2_DEVICES : string;
  attribute C_GEN2_DEVICES of inst : label is "1'b1";
  attribute C_H2C_NUM_CHNL : integer;
  attribute C_H2C_NUM_CHNL of inst : label is 1;
  attribute C_H2C_NUM_RIDS : integer;
  attribute C_H2C_NUM_RIDS of inst : label is 32;
  attribute C_H2C_TUSER_WIDTH : integer;
  attribute C_H2C_TUSER_WIDTH of inst : label is 48;
  attribute C_HIGHADDR : integer;
  attribute C_HIGHADDR of inst : label is 8191;
  attribute C_IGNORE_SIZE_AXI_SLAVE : integer;
  attribute C_IGNORE_SIZE_AXI_SLAVE of inst : label is 1;
  attribute C_INCLUDE_BAROFFSET_REG : integer;
  attribute C_INCLUDE_BAROFFSET_REG of inst : label is 1;
  attribute C_INCLUDE_RC : integer;
  attribute C_INCLUDE_RC of inst : label is 0;
  attribute C_INTX_RX_PIN_EN : integer;
  attribute C_INTX_RX_PIN_EN of inst : label is 1;
  attribute C_INV_QUEUE_DEPTH : string;
  attribute C_INV_QUEUE_DEPTH of inst : label is "5'b00000";
  attribute C_KEEP_WIDTH : integer;
  attribute C_KEEP_WIDTH of inst : label is 8;
  attribute C_LAST_CORE_CAP_ADDR : string;
  attribute C_LAST_CORE_CAP_ADDR of inst : label is "12'b000100000000";
  attribute C_LEGACY_INT_EN : string;
  attribute C_LEGACY_INT_EN of inst : label is "TRUE";
  attribute C_METERING_ON : integer;
  attribute C_METERING_ON of inst : label is 1;
  attribute C_MSIX_INT_TABLE_EN : integer;
  attribute C_MSIX_INT_TABLE_EN of inst : label is 0;
  attribute C_MSIX_RX_PIN_EN : integer;
  attribute C_MSIX_RX_PIN_EN of inst : label is 1;
  attribute C_MSI_ENABLED : string;
  attribute C_MSI_ENABLED of inst : label is "TRUE";
  attribute C_MSI_RX_PIN_EN : integer;
  attribute C_MSI_RX_PIN_EN of inst : label is 0;
  attribute C_M_AXIL_ARUSER_WIDTH : integer;
  attribute C_M_AXIL_ARUSER_WIDTH of inst : label is 11;
  attribute C_M_AXIL_AWUSER_WIDTH : integer;
  attribute C_M_AXIL_AWUSER_WIDTH of inst : label is 11;
  attribute C_M_AXIS_DATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_WIDTH of inst : label is 64;
  attribute C_M_AXIS_RC_USER_WIDTH : integer;
  attribute C_M_AXIS_RC_USER_WIDTH of inst : label is 75;
  attribute C_M_AXIS_RQ_USER_WIDTH : integer;
  attribute C_M_AXIS_RQ_USER_WIDTH of inst : label is 60;
  attribute C_M_AXIS_USER_WIDTH : integer;
  attribute C_M_AXIS_USER_WIDTH of inst : label is 64;
  attribute C_M_AXI_ADDR_WIDTH : integer;
  attribute C_M_AXI_ADDR_WIDTH of inst : label is 64;
  attribute C_M_AXI_ARUSER_WIDTH : integer;
  attribute C_M_AXI_ARUSER_WIDTH of inst : label is 8;
  attribute C_M_AXI_AWUSER_WIDTH : integer;
  attribute C_M_AXI_AWUSER_WIDTH of inst : label is 8;
  attribute C_M_AXI_BUSER_WIDTH : integer;
  attribute C_M_AXI_BUSER_WIDTH of inst : label is 1;
  attribute C_M_AXI_DATA_WIDTH : integer;
  attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
  attribute C_M_AXI_ID_WIDTH : integer;
  attribute C_M_AXI_ID_WIDTH of inst : label is 4;
  attribute C_M_AXI_NUM_READ : integer;
  attribute C_M_AXI_NUM_READ of inst : label is 8;
  attribute C_M_AXI_NUM_READQ : integer;
  attribute C_M_AXI_NUM_READQ of inst : label is 2;
  attribute C_M_AXI_NUM_WRITE : integer;
  attribute C_M_AXI_NUM_WRITE of inst : label is 4;
  attribute C_M_AXI_NUM_WRITE_SCALE : integer;
  attribute C_M_AXI_NUM_WRITE_SCALE of inst : label is 1;
  attribute C_M_AXI_RUSER_WIDTH : integer;
  attribute C_M_AXI_RUSER_WIDTH of inst : label is 8;
  attribute C_M_AXI_WUSER_WIDTH : integer;
  attribute C_M_AXI_WUSER_WIDTH of inst : label is 8;
  attribute C_M_KEEP_WIDTH : integer;
  attribute C_M_KEEP_WIDTH of inst : label is 2;
  attribute C_NUMQ_PER_CHNL : integer;
  attribute C_NUMQ_PER_CHNL of inst : label is 256;
  attribute C_NUM_AXI_DSC_CPL_DID : integer;
  attribute C_NUM_AXI_DSC_CPL_DID of inst : label is 64;
  attribute C_NUM_DSC_PCIE_RID : integer;
  attribute C_NUM_DSC_PCIE_RID of inst : label is 32;
  attribute C_NUM_MSIX_VECTORS : integer;
  attribute C_NUM_MSIX_VECTORS of inst : label is 32;
  attribute C_NUM_OF_SC : integer;
  attribute C_NUM_OF_SC of inst : label is 1;
  attribute C_NUM_PCIE_DSC_CPL_DID : integer;
  attribute C_NUM_PCIE_DSC_CPL_DID of inst : label is 256;
  attribute C_NUM_USER_INTR : integer;
  attribute C_NUM_USER_INTR of inst : label is 9;
  attribute C_NUM_USER_NEW_INTR : integer;
  attribute C_NUM_USER_NEW_INTR of inst : label is 6;
  attribute C_NUM_USR_IRQ : integer;
  attribute C_NUM_USR_IRQ of inst : label is 1;
  attribute C_OLD_BRIDGE_TIMEOUT : integer;
  attribute C_OLD_BRIDGE_TIMEOUT of inst : label is 0;
  attribute C_OST_PR_CAP : integer;
  attribute C_OST_PR_CAP of inst : label is 0;
  attribute C_PARITY_CHECK : integer;
  attribute C_PARITY_CHECK of inst : label is 0;
  attribute C_PARITY_GEN : integer;
  attribute C_PARITY_GEN of inst : label is 0;
  attribute C_PARITY_PROP : integer;
  attribute C_PARITY_PROP of inst : label is 0;
  attribute C_PCIEBAR2AXIBAR_0 : string;
  attribute C_PCIEBAR2AXIBAR_0 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_0_TMP : string;
  attribute C_PCIEBAR2AXIBAR_0_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_1 : string;
  attribute C_PCIEBAR2AXIBAR_1 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_1_TMP : string;
  attribute C_PCIEBAR2AXIBAR_1_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_2 : string;
  attribute C_PCIEBAR2AXIBAR_2 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_2_TMP : string;
  attribute C_PCIEBAR2AXIBAR_2_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_3 : string;
  attribute C_PCIEBAR2AXIBAR_3 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_3_TMP : string;
  attribute C_PCIEBAR2AXIBAR_3_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_4 : string;
  attribute C_PCIEBAR2AXIBAR_4 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_4_TMP : string;
  attribute C_PCIEBAR2AXIBAR_4_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_5 : string;
  attribute C_PCIEBAR2AXIBAR_5 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_5_TMP : string;
  attribute C_PCIEBAR2AXIBAR_5_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_6 : string;
  attribute C_PCIEBAR2AXIBAR_6 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR2AXIBAR_6_TMP : string;
  attribute C_PCIEBAR2AXIBAR_6_TMP of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_PCIEBAR_AS : integer;
  attribute C_PCIEBAR_AS of inst : label is 1;
  attribute C_PCIEBAR_LEN_0 : integer;
  attribute C_PCIEBAR_LEN_0 of inst : label is 16;
  attribute C_PCIEBAR_LEN_1 : integer;
  attribute C_PCIEBAR_LEN_1 of inst : label is 20;
  attribute C_PCIEBAR_LEN_2 : integer;
  attribute C_PCIEBAR_LEN_2 of inst : label is 64;
  attribute C_PCIEBAR_LEN_3 : integer;
  attribute C_PCIEBAR_LEN_3 of inst : label is 64;
  attribute C_PCIEBAR_LEN_4 : integer;
  attribute C_PCIEBAR_LEN_4 of inst : label is 64;
  attribute C_PCIEBAR_LEN_5 : integer;
  attribute C_PCIEBAR_LEN_5 of inst : label is 64;
  attribute C_PCIEBAR_LEN_6 : integer;
  attribute C_PCIEBAR_LEN_6 of inst : label is 7;
  attribute C_PCIEBAR_NUM : integer;
  attribute C_PCIEBAR_NUM of inst : label is 6;
  attribute C_PCIE_PFS_SUPPORTED : integer;
  attribute C_PCIE_PFS_SUPPORTED of inst : label is 0;
  attribute C_PRI_ENABLE : string;
  attribute C_PRI_ENABLE of inst : label is "FALSE";
  attribute C_PR_CAP_NEXTPTR : string;
  attribute C_PR_CAP_NEXTPTR of inst : label is "12'b000000000000";
  attribute C_PR_OFFSET : string;
  attribute C_PR_OFFSET of inst : label is "30'b000000000000000000000100100100";
  attribute C_RD_BUFFER_ADDR_SIZE : integer;
  attribute C_RD_BUFFER_ADDR_SIZE of inst : label is 9;
  attribute C_RD_BUFFER_SIZE_BITS : integer;
  attribute C_RD_BUFFER_SIZE_BITS of inst : label is 5;
  attribute C_SLAVE_READ_64OS_EN : integer;
  attribute C_SLAVE_READ_64OS_EN of inst : label is 0;
  attribute C_SMMU_EN : integer;
  attribute C_SMMU_EN of inst : label is 0;
  attribute C_SRIOV_EN : integer;
  attribute C_SRIOV_EN of inst : label is 0;
  attribute C_S_AXIS_CC_USER_WIDTH : integer;
  attribute C_S_AXIS_CC_USER_WIDTH of inst : label is 33;
  attribute C_S_AXIS_CQP_USER_WIDTH : integer;
  attribute C_S_AXIS_CQP_USER_WIDTH of inst : label is 85;
  attribute C_S_AXIS_CQ_USER_WIDTH : integer;
  attribute C_S_AXIS_CQ_USER_WIDTH of inst : label is 85;
  attribute C_S_AXIS_DATA_WIDTH : integer;
  attribute C_S_AXIS_DATA_WIDTH of inst : label is 64;
  attribute C_S_AXIS_USER_WIDTH : integer;
  attribute C_S_AXIS_USER_WIDTH of inst : label is 64;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of inst : label is 64;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of inst : label is 64;
  attribute C_S_AXI_ID_WIDTH : integer;
  attribute C_S_AXI_ID_WIDTH of inst : label is 4;
  attribute C_S_AXI_NUM_READ : integer;
  attribute C_S_AXI_NUM_READ of inst : label is 8;
  attribute C_S_AXI_NUM_WRITE : integer;
  attribute C_S_AXI_NUM_WRITE of inst : label is 8;
  attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
  attribute C_S_AXI_SUPPORTS_NARROW_BURST of inst : label is 0;
  attribute C_S_KEEP_WIDTH : integer;
  attribute C_S_KEEP_WIDTH of inst : label is 2;
  attribute C_TIMEOUT0_SEL : string;
  attribute C_TIMEOUT0_SEL of inst : label is "4'b1110";
  attribute C_TIMEOUT1_SEL : string;
  attribute C_TIMEOUT1_SEL of inst : label is "4'b1111";
  attribute C_TIMEOUT_MULT : string;
  attribute C_TIMEOUT_MULT of inst : label is "3'b011";
  attribute C_USER_PTR : string;
  attribute C_USER_PTR of inst : label is "16'b0000000011011000";
  attribute C_VSEC_CAP_ADDR : string;
  attribute C_VSEC_CAP_ADDR of inst : label is "12'b000100101000";
  attribute C_VSEC_CAP_LAST : string;
  attribute C_VSEC_CAP_LAST of inst : label is "FALSE";
  attribute C_VSEC_ID : string;
  attribute C_VSEC_ID of inst : label is "16'b0000000000000000";
  attribute DAT_WIDTH : integer;
  attribute DAT_WIDTH of inst : label is 64;
  attribute DEDICATE_PERST : string;
  attribute DEDICATE_PERST of inst : label is "true";
  attribute DEV_PORT_TYPE : integer;
  attribute DEV_PORT_TYPE of inst : label is 0;
  attribute DIFF_AXI_ADDR_WIDTH : integer;
  attribute DIFF_AXI_ADDR_WIDTH of inst : label is 0;
  attribute DISABLE_BRAM_PIPELINE : string;
  attribute DISABLE_BRAM_PIPELINE of inst : label is "FALSE";
  attribute DISABLE_EQ_SYNCHRONIZER : string;
  attribute DISABLE_EQ_SYNCHRONIZER of inst : label is "FALSE";
  attribute DMA_2RP : string;
  attribute DMA_2RP of inst : label is "FALSE";
  attribute DMA_EN : integer;
  attribute DMA_EN of inst : label is 1;
  attribute DMA_MM : integer;
  attribute DMA_MM of inst : label is 1;
  attribute DMA_RESET_SOURCE_SEL : integer;
  attribute DMA_RESET_SOURCE_SEL of inst : label is 0;
  attribute DMA_SP : integer;
  attribute DMA_SP of inst : label is 0;
  attribute DMA_ST : integer;
  attribute DMA_ST of inst : label is 0;
  attribute DRP_CLK_SEL : integer;
  attribute DRP_CLK_SEL of inst : label is 0;
  attribute DSC_BYPASS_RD : integer;
  attribute DSC_BYPASS_RD of inst : label is 0;
  attribute DSC_BYPASS_WR : integer;
  attribute DSC_BYPASS_WR of inst : label is 0;
  attribute ENABLE_ATS_SWITCH : string;
  attribute ENABLE_ATS_SWITCH of inst : label is "FALSE";
  attribute ENABLE_IBERT : string;
  attribute ENABLE_IBERT of inst : label is "false";
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of inst : label is "FALSE";
  attribute ENABLE_LTSSM_DBG : string;
  attribute ENABLE_LTSSM_DBG of inst : label is "FALSE";
  attribute ENABLE_MORE : string;
  attribute ENABLE_MORE of inst : label is "FALSE";
  attribute EN_AXI_MASTER_IF : string;
  attribute EN_AXI_MASTER_IF of inst : label is "TRUE";
  attribute EN_AXI_SLAVE_IF : string;
  attribute EN_AXI_SLAVE_IF of inst : label is "TRUE";
  attribute EN_DEBUG_PORTS : string;
  attribute EN_DEBUG_PORTS of inst : label is "FALSE";
  attribute EN_GT_SELECTION : string;
  attribute EN_GT_SELECTION of inst : label is "FALSE";
  attribute EN_PCIE_DEBUG_PORTS : string;
  attribute EN_PCIE_DEBUG_PORTS of inst : label is "FALSE";
  attribute EN_RCHNL_0 : string;
  attribute EN_RCHNL_0 of inst : label is "TRUE";
  attribute EN_RCHNL_1 : string;
  attribute EN_RCHNL_1 of inst : label is "FALSE";
  attribute EN_RCHNL_2 : string;
  attribute EN_RCHNL_2 of inst : label is "FALSE";
  attribute EN_RCHNL_3 : string;
  attribute EN_RCHNL_3 of inst : label is "FALSE";
  attribute EN_RCHNL_4 : string;
  attribute EN_RCHNL_4 of inst : label is "FALSE";
  attribute EN_RCHNL_5 : string;
  attribute EN_RCHNL_5 of inst : label is "FALSE";
  attribute EN_RCHNL_6 : string;
  attribute EN_RCHNL_6 of inst : label is "FALSE";
  attribute EN_RCHNL_7 : string;
  attribute EN_RCHNL_7 of inst : label is "FALSE";
  attribute EN_TRANSCEIVER_STATUS_PORTS : string;
  attribute EN_TRANSCEIVER_STATUS_PORTS of inst : label is "false";
  attribute EN_WCHNL_0 : string;
  attribute EN_WCHNL_0 of inst : label is "TRUE";
  attribute EN_WCHNL_1 : string;
  attribute EN_WCHNL_1 of inst : label is "FALSE";
  attribute EN_WCHNL_2 : string;
  attribute EN_WCHNL_2 of inst : label is "FALSE";
  attribute EN_WCHNL_3 : string;
  attribute EN_WCHNL_3 of inst : label is "FALSE";
  attribute EN_WCHNL_4 : string;
  attribute EN_WCHNL_4 of inst : label is "FALSE";
  attribute EN_WCHNL_5 : string;
  attribute EN_WCHNL_5 of inst : label is "FALSE";
  attribute EN_WCHNL_6 : string;
  attribute EN_WCHNL_6 of inst : label is "FALSE";
  attribute EN_WCHNL_7 : string;
  attribute EN_WCHNL_7 of inst : label is "FALSE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of inst : label is "false";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of inst : label is "false";
  attribute EXT_SYS_CLK_BUFG : string;
  attribute EXT_SYS_CLK_BUFG of inst : label is "FALSE";
  attribute EXT_XVC_VSEC_ENABLE : string;
  attribute EXT_XVC_VSEC_ENABLE of inst : label is "FALSE";
  attribute FIRSTVF_OFFSET_PF0 : integer;
  attribute FIRSTVF_OFFSET_PF0 of inst : label is 0;
  attribute FIRSTVF_OFFSET_PF1 : integer;
  attribute FIRSTVF_OFFSET_PF1 of inst : label is 0;
  attribute FIRSTVF_OFFSET_PF2 : integer;
  attribute FIRSTVF_OFFSET_PF2 of inst : label is 0;
  attribute FIRSTVF_OFFSET_PF3 : integer;
  attribute FIRSTVF_OFFSET_PF3 of inst : label is 0;
  attribute FLR_ENABLE : string;
  attribute FLR_ENABLE of inst : label is "FALSE";
  attribute FREE_RUN_FREQ : integer;
  attribute FREE_RUN_FREQ of inst : label is 0;
  attribute FUNC_MODE : integer;
  attribute FUNC_MODE of inst : label is 1;
  attribute GEN4_EIEOS_0S7 : string;
  attribute GEN4_EIEOS_0S7 of inst : label is "TRUE";
  attribute GTCOM_IN_CORE : integer;
  attribute GTCOM_IN_CORE of inst : label is 2;
  attribute GTWIZ_IN_CORE : integer;
  attribute GTWIZ_IN_CORE of inst : label is 1;
  attribute H2C_XDMA_CHNL : string;
  attribute H2C_XDMA_CHNL of inst : label is "8'b00001111";
  attribute IMPL_TARGET : string;
  attribute IMPL_TARGET of inst : label is "SOFT";
  attribute INS_LOSS_PROFILE : string;
  attribute INS_LOSS_PROFILE of inst : label is "Add-in_Card";
  attribute INTERRUPT_OUT_WIDTH : integer;
  attribute INTERRUPT_OUT_WIDTH of inst : label is 1;
  attribute IS_BOARD_PROJECT : integer;
  attribute IS_BOARD_PROJECT of inst : label is 0;
  attribute LEGACY_CFG_EXT_IF : string;
  attribute LEGACY_CFG_EXT_IF of inst : label is "FALSE";
  attribute MCAP_ENABLEMENT : string;
  attribute MCAP_ENABLEMENT of inst : label is "NONE";
  attribute MCAP_FPGA_BITSTREAM_VERSION : integer;
  attribute MCAP_FPGA_BITSTREAM_VERSION of inst : label is 0;
  attribute MM_SLAVE_EN : integer;
  attribute MM_SLAVE_EN of inst : label is 0;
  attribute MSIX_ENABLED : string;
  attribute MSIX_ENABLED of inst : label is "FALSE";
  attribute MSIX_IMPL_EXT : string;
  attribute MSIX_IMPL_EXT of inst : label is "FALSE";
  attribute MSIX_PCIE_INTERNAL : integer;
  attribute MSIX_PCIE_INTERNAL of inst : label is 0;
  attribute MSIX_RX_DECODE_EN : string;
  attribute MSIX_RX_DECODE_EN of inst : label is "FALSE";
  attribute MSIX_VEC_NUM : integer;
  attribute MSIX_VEC_NUM of inst : label is 1024;
  attribute MSI_ENABLED : string;
  attribute MSI_ENABLED of inst : label is "TRUE";
  attribute MULTQ_CHNL : string;
  attribute MULTQ_CHNL of inst : label is "8'b00000000";
  attribute MULTQ_EN : integer;
  attribute MULTQ_EN of inst : label is 0;
  attribute MULT_PF_DES : string;
  attribute MULT_PF_DES of inst : label is "FALSE";
  attribute MULT_PF_DESIGN : integer;
  attribute MULT_PF_DESIGN of inst : label is 0;
  attribute NUM_PFS : integer;
  attribute NUM_PFS of inst : label is 1;
  attribute NUM_VFS_PF0 : integer;
  attribute NUM_VFS_PF0 of inst : label is 0;
  attribute NUM_VFS_PF1 : integer;
  attribute NUM_VFS_PF1 of inst : label is 0;
  attribute NUM_VFS_PF2 : integer;
  attribute NUM_VFS_PF2 of inst : label is 0;
  attribute NUM_VFS_PF3 : integer;
  attribute NUM_VFS_PF3 of inst : label is 0;
  attribute PCIE3_DRP : string;
  attribute PCIE3_DRP of inst : label is "false";
  attribute PCIEBAR_NUM : integer;
  attribute PCIEBAR_NUM of inst : label is 6;
  attribute PCIE_BLK_LOCN : integer;
  attribute PCIE_BLK_LOCN of inst : label is 0;
  attribute PCIE_BLK_TYPE : integer;
  attribute PCIE_BLK_TYPE of inst : label is 0;
  attribute PCIE_ID_IF : string;
  attribute PCIE_ID_IF of inst : label is "FALSE";
  attribute PF0_BAR0_APERTURE_SIZE : string;
  attribute PF0_BAR0_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF0_BAR0_CONTROL : string;
  attribute PF0_BAR0_CONTROL of inst : label is "3'b100";
  attribute PF0_BAR1_APERTURE_SIZE : string;
  attribute PF0_BAR1_APERTURE_SIZE of inst : label is "8'b00000101";
  attribute PF0_BAR1_CONTROL : string;
  attribute PF0_BAR1_CONTROL of inst : label is "3'b000";
  attribute PF0_BAR2_APERTURE_SIZE : string;
  attribute PF0_BAR2_APERTURE_SIZE of inst : label is "8'b00000101";
  attribute PF0_BAR2_CONTROL : string;
  attribute PF0_BAR2_CONTROL of inst : label is "3'b000";
  attribute PF0_BAR3_APERTURE_SIZE : string;
  attribute PF0_BAR3_APERTURE_SIZE of inst : label is "8'b00000101";
  attribute PF0_BAR3_CONTROL : string;
  attribute PF0_BAR3_CONTROL of inst : label is "3'b000";
  attribute PF0_BAR4_APERTURE_SIZE : string;
  attribute PF0_BAR4_APERTURE_SIZE of inst : label is "8'b00000101";
  attribute PF0_BAR4_CONTROL : string;
  attribute PF0_BAR4_CONTROL of inst : label is "3'b000";
  attribute PF0_BAR5_APERTURE_SIZE : string;
  attribute PF0_BAR5_APERTURE_SIZE of inst : label is "8'b00000101";
  attribute PF0_BAR5_CONTROL : string;
  attribute PF0_BAR5_CONTROL of inst : label is "3'b000";
  attribute PF0_CLASS_CODE : string;
  attribute PF0_CLASS_CODE of inst : label is "24'b000001110000000000000001";
  attribute PF0_DEVICE_ID : string;
  attribute PF0_DEVICE_ID of inst : label is "16'b0111000000100010";
  attribute PF0_EXPANSION_ROM_APERTURE_SIZE : string;
  attribute PF0_EXPANSION_ROM_APERTURE_SIZE of inst : label is "5'b00000";
  attribute PF0_EXPANSION_ROM_ENABLE : string;
  attribute PF0_EXPANSION_ROM_ENABLE of inst : label is "FALSE";
  attribute PF0_INTERRUPT_PIN : string;
  attribute PF0_INTERRUPT_PIN of inst : label is "3'b001";
  attribute PF0_MSIX_TAR_ID : string;
  attribute PF0_MSIX_TAR_ID of inst : label is "6'b001000";
  attribute PF0_MSI_CAP_MULTIMSGCAP : integer;
  attribute PF0_MSI_CAP_MULTIMSGCAP of inst : label is 0;
  attribute PF0_REVISION_ID : string;
  attribute PF0_REVISION_ID of inst : label is "8'b00000000";
  attribute PF0_SUBSYSTEM_ID : string;
  attribute PF0_SUBSYSTEM_ID of inst : label is "16'b0000000000000111";
  attribute PF0_SUBSYSTEM_VENDOR_ID : string;
  attribute PF0_SUBSYSTEM_VENDOR_ID of inst : label is "16'b0001000011101110";
  attribute PF0_VENDOR_ID : string;
  attribute PF0_VENDOR_ID of inst : label is "16'b0001000011101110";
  attribute PF1_BAR0_APERTURE_SIZE : string;
  attribute PF1_BAR0_APERTURE_SIZE of inst : label is "8'b00010010";
  attribute PF1_BAR0_CONTROL : string;
  attribute PF1_BAR0_CONTROL of inst : label is "3'b100";
  attribute PF1_BAR1_APERTURE_SIZE : string;
  attribute PF1_BAR1_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF1_BAR1_CONTROL : string;
  attribute PF1_BAR1_CONTROL of inst : label is "3'b000";
  attribute PF1_BAR2_APERTURE_SIZE : string;
  attribute PF1_BAR2_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF1_BAR2_CONTROL : string;
  attribute PF1_BAR2_CONTROL of inst : label is "3'b110";
  attribute PF1_BAR3_APERTURE_SIZE : string;
  attribute PF1_BAR3_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF1_BAR3_CONTROL : string;
  attribute PF1_BAR3_CONTROL of inst : label is "3'b000";
  attribute PF1_BAR4_APERTURE_SIZE : string;
  attribute PF1_BAR4_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF1_BAR4_CONTROL : string;
  attribute PF1_BAR4_CONTROL of inst : label is "3'b110";
  attribute PF1_BAR5_APERTURE_SIZE : string;
  attribute PF1_BAR5_APERTURE_SIZE of inst : label is "8'b00001010";
  attribute PF1_BAR5_CONTROL : string;
  attribute PF1_BAR5_CONTROL of inst : label is "3'b000";
  attribute PF1_CLASS_CODE : string;
  attribute PF1_CLASS_CODE of inst : label is "24'b000001110000000000000001";
  attribute PF1_DEVICE_ID : string;
  attribute PF1_DEVICE_ID of inst : label is "16'b1001000100010001";
  attribute PF1_ENABLED : integer;
  attribute PF1_ENABLED of inst : label is 0;
  attribute PF1_EXPANSION_ROM_APERTURE_SIZE : string;
  attribute PF1_EXPANSION_ROM_APERTURE_SIZE of inst : label is "5'b00000";
  attribute PF1_EXPANSION_ROM_ENABLE : string;
  attribute PF1_EXPANSION_ROM_ENABLE of inst : label is "FALSE";
  attribute PF1_MSIX_TAR_ID : string;
  attribute PF1_MSIX_TAR_ID of inst : label is "6'b001001";
  attribute PF1_PCIEBAR2AXIBAR_0 : string;
  attribute PF1_PCIEBAR2AXIBAR_0 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_1 : string;
  attribute PF1_PCIEBAR2AXIBAR_1 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_2 : string;
  attribute PF1_PCIEBAR2AXIBAR_2 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_3 : string;
  attribute PF1_PCIEBAR2AXIBAR_3 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_4 : string;
  attribute PF1_PCIEBAR2AXIBAR_4 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_5 : string;
  attribute PF1_PCIEBAR2AXIBAR_5 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_PCIEBAR2AXIBAR_6 : string;
  attribute PF1_PCIEBAR2AXIBAR_6 of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute PF1_REVISION_ID : string;
  attribute PF1_REVISION_ID of inst : label is "8'b00000000";
  attribute PF1_SUBSYSTEM_ID : string;
  attribute PF1_SUBSYSTEM_ID of inst : label is "16'b0000000000000111";
  attribute PF1_SUBSYSTEM_VENDOR_ID : string;
  attribute PF1_SUBSYSTEM_VENDOR_ID of inst : label is "16'b0001000011101110";
  attribute PF1_VENDOR_ID : string;
  attribute PF1_VENDOR_ID of inst : label is "16'b0001000011101110";
  attribute PF2_DEVICE_ID : string;
  attribute PF2_DEVICE_ID of inst : label is "16'b1001001000010001";
  attribute PF2_ENABLED : integer;
  attribute PF2_ENABLED of inst : label is 0;
  attribute PF2_REVISION_ID : string;
  attribute PF2_REVISION_ID of inst : label is "8'b00000000";
  attribute PF2_SUBSYSTEM_ID : string;
  attribute PF2_SUBSYSTEM_ID of inst : label is "16'b0000000000000111";
  attribute PF3_DEVICE_ID : string;
  attribute PF3_DEVICE_ID of inst : label is "16'b1001001100010001";
  attribute PF3_ENABLED : integer;
  attribute PF3_ENABLED of inst : label is 0;
  attribute PF3_REVISION_ID : string;
  attribute PF3_REVISION_ID of inst : label is "8'b00000000";
  attribute PF3_SUBSYSTEM_ID : string;
  attribute PF3_SUBSYSTEM_ID of inst : label is "16'b0000000000000111";
  attribute PF_SWAP : string;
  attribute PF_SWAP of inst : label is "FALSE";
  attribute PIPE_DEBUG_EN : string;
  attribute PIPE_DEBUG_EN of inst : label is "FALSE";
  attribute PIPE_LINE_STAGE : integer;
  attribute PIPE_LINE_STAGE of inst : label is 2;
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of inst : label is "false";
  attribute PLL_TYPE : integer;
  attribute PLL_TYPE of inst : label is 2;
  attribute PL_DISABLE_UPCONFIG_CAPABLE : string;
  attribute PL_DISABLE_UPCONFIG_CAPABLE of inst : label is "FALSE";
  attribute PL_LINK_CAP_MAX_LINK_SPEED : integer;
  attribute PL_LINK_CAP_MAX_LINK_SPEED of inst : label is 2;
  attribute PL_LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute PL_LINK_CAP_MAX_LINK_WIDTH of inst : label is 2;
  attribute PL_UPSTREAM_FACING : string;
  attribute PL_UPSTREAM_FACING of inst : label is "true";
  attribute PMON_EN : integer;
  attribute PMON_EN of inst : label is 1;
  attribute PROG_USR_IRQ_VEC_MAP : integer;
  attribute PROG_USR_IRQ_VEC_MAP of inst : label is 0;
  attribute RBAR_ENABLE : string;
  attribute RBAR_ENABLE of inst : label is "FALSE";
  attribute RD_CH0_ENABLED : string;
  attribute RD_CH0_ENABLED of inst : label is "FALSE";
  attribute RD_CH1_ENABLED : string;
  attribute RD_CH1_ENABLED of inst : label is "FALSE";
  attribute RD_CH2_ENABLED : string;
  attribute RD_CH2_ENABLED of inst : label is "FALSE";
  attribute RD_CH3_ENABLED : string;
  attribute RD_CH3_ENABLED of inst : label is "FALSE";
  attribute REF_CLK_FREQ : integer;
  attribute REF_CLK_FREQ of inst : label is 0;
  attribute RQ_SEQ_NUM_IGNORE : integer;
  attribute RQ_SEQ_NUM_IGNORE of inst : label is 0;
  attribute RUNBIT_FIX : string;
  attribute RUNBIT_FIX of inst : label is "FALSE";
  attribute RUN_BIT_FIX : integer;
  attribute RUN_BIT_FIX of inst : label is 0;
  attribute RX_DETECT : integer;
  attribute RX_DETECT of inst : label is 0;
  attribute SELECT_QUAD : string;
  attribute SELECT_QUAD of inst : label is "GTH_Quad_128";
  attribute SHARED_LOGIC : integer;
  attribute SHARED_LOGIC of inst : label is 0;
  attribute SHARED_LOGIC_BOTH : string;
  attribute SHARED_LOGIC_BOTH of inst : label is "false";
  attribute SHARED_LOGIC_BOTH_7XG2 : string;
  attribute SHARED_LOGIC_BOTH_7XG2 of inst : label is "false";
  attribute SHARED_LOGIC_CLK : string;
  attribute SHARED_LOGIC_CLK of inst : label is "false";
  attribute SHARED_LOGIC_CLK_7XG2 : string;
  attribute SHARED_LOGIC_CLK_7XG2 of inst : label is "false";
  attribute SHARED_LOGIC_GTC : string;
  attribute SHARED_LOGIC_GTC of inst : label is "false";
  attribute SHARED_LOGIC_GTC_7XG2 : string;
  attribute SHARED_LOGIC_GTC_7XG2 of inst : label is "false";
  attribute SHELL_BRIDGE : integer;
  attribute SHELL_BRIDGE of inst : label is 0;
  attribute SILICON_REV : string;
  attribute SILICON_REV of inst : label is "Pre-Production";
  attribute SOFT_RESET_EN : string;
  attribute SOFT_RESET_EN of inst : label is "FALSE";
  attribute SPLIT_DMA : string;
  attribute SPLIT_DMA of inst : label is "FALSE";
  attribute SPLIT_DMA_SINGLE_PF : string;
  attribute SPLIT_DMA_SINGLE_PF of inst : label is "FALSE";
  attribute SRIOV_ACTIVE_VFS : integer;
  attribute SRIOV_ACTIVE_VFS of inst : label is 252;
  attribute SRIOV_EN : integer;
  attribute SRIOV_EN of inst : label is 0;
  attribute STS_WIDTH : integer;
  attribute STS_WIDTH of inst : label is 8;
  attribute SYS_RESET_POLARITY : integer;
  attribute SYS_RESET_POLARITY of inst : label is 0;
  attribute TCQ : integer;
  attribute TCQ of inst : label is 1;
  attribute TL_LEGACY_MODE_ENABLE : string;
  attribute TL_LEGACY_MODE_ENABLE of inst : label is "false";
  attribute TL_PF_ENABLE_REG : string;
  attribute TL_PF_ENABLE_REG of inst : label is "2'b00";
  attribute ULTRASCALE : string;
  attribute ULTRASCALE of inst : label is "FALSE";
  attribute ULTRASCALE_PLUS : string;
  attribute ULTRASCALE_PLUS of inst : label is "FALSE";
  attribute USER_CLK_FREQ : integer;
  attribute USER_CLK_FREQ of inst : label is 1;
  attribute USE_ATTR : integer;
  attribute USE_ATTR of inst : label is 0;
  attribute USE_STANDARD_INTERFACES : string;
  attribute USE_STANDARD_INTERFACES of inst : label is "FALSE";
  attribute USRINT_EXPN : string;
  attribute USRINT_EXPN of inst : label is "FALSE";
  attribute USR_INT_EXPN : integer;
  attribute USR_INT_EXPN of inst : label is 0;
  attribute USR_IRQ_EXDES : string;
  attribute USR_IRQ_EXDES of inst : label is "FALSE";
  attribute USR_MPL_SIZE : integer;
  attribute USR_MPL_SIZE of inst : label is 4096;
  attribute USR_MRS_SIZE : integer;
  attribute USR_MRS_SIZE of inst : label is 4096;
  attribute V7_GEN3 : string;
  attribute V7_GEN3 of inst : label is "FALSE";
  attribute VCU118_BOARD : string;
  attribute VCU118_BOARD of inst : label is "FALSE";
  attribute VCU1262 : string;
  attribute VCU1262 of inst : label is "FALSE";
  attribute VERSION : integer;
  attribute VERSION of inst : label is 6;
  attribute VF_BARLITE_EXT_PF0 : string;
  attribute VF_BARLITE_EXT_PF0 of inst : label is "6'b000000";
  attribute VF_BARLITE_EXT_PF1 : string;
  attribute VF_BARLITE_EXT_PF1 of inst : label is "6'b000000";
  attribute VF_BARLITE_EXT_PF2 : string;
  attribute VF_BARLITE_EXT_PF2 of inst : label is "6'b000000";
  attribute VF_BARLITE_EXT_PF3 : string;
  attribute VF_BARLITE_EXT_PF3 of inst : label is "6'b000000";
  attribute VF_BARLITE_INT_PF0 : string;
  attribute VF_BARLITE_INT_PF0 of inst : label is "6'b000001";
  attribute VF_BARLITE_INT_PF1 : string;
  attribute VF_BARLITE_INT_PF1 of inst : label is "6'b000001";
  attribute VF_BARLITE_INT_PF2 : string;
  attribute VF_BARLITE_INT_PF2 of inst : label is "6'b000001";
  attribute VF_BARLITE_INT_PF3 : string;
  attribute VF_BARLITE_INT_PF3 of inst : label is "6'b000001";
  attribute VU9P_BOARD : string;
  attribute VU9P_BOARD of inst : label is "FALSE";
  attribute VU9P_TUL_EX : string;
  attribute VU9P_TUL_EX of inst : label is "FALSE";
  attribute WR_CH0_ENABLED : string;
  attribute WR_CH0_ENABLED of inst : label is "FALSE";
  attribute WR_CH1_ENABLED : string;
  attribute WR_CH1_ENABLED of inst : label is "FALSE";
  attribute WR_CH2_ENABLED : string;
  attribute WR_CH2_ENABLED of inst : label is "FALSE";
  attribute WR_CH3_ENABLED : string;
  attribute WR_CH3_ENABLED of inst : label is "FALSE";
  attribute XDMA_APERTURE_SIZE : string;
  attribute XDMA_APERTURE_SIZE of inst : label is "8'b00001001";
  attribute XDMA_AXILITE_MASTER : string;
  attribute XDMA_AXILITE_MASTER of inst : label is "FALSE";
  attribute XDMA_AXILITE_SLAVE : string;
  attribute XDMA_AXILITE_SLAVE of inst : label is "FALSE";
  attribute XDMA_AXIST_BYPASS : string;
  attribute XDMA_AXIST_BYPASS of inst : label is "TRUE";
  attribute XDMA_AXI_INTF_MM : integer;
  attribute XDMA_AXI_INTF_MM of inst : label is 1;
  attribute XDMA_CONTROL : string;
  attribute XDMA_CONTROL of inst : label is "3'b100";
  attribute XDMA_DSC_BYPASS : string;
  attribute XDMA_DSC_BYPASS of inst : label is "FALSE";
  attribute XDMA_DSC_ENG : integer;
  attribute XDMA_DSC_ENG of inst : label is 1;
  attribute XDMA_NON_INCREMENTAL_EXDES : string;
  attribute XDMA_NON_INCREMENTAL_EXDES of inst : label is "FALSE";
  attribute XDMA_NUM_PCIE_TAG : integer;
  attribute XDMA_NUM_PCIE_TAG of inst : label is 64;
  attribute XDMA_NUM_USR_IRQ : integer;
  attribute XDMA_NUM_USR_IRQ of inst : label is 1;
  attribute XDMA_PCIE_64BIT_EN : string;
  attribute XDMA_PCIE_64BIT_EN of inst : label is "xdma_pcie_64bit_en";
  attribute XDMA_RNUM_CHNL : integer;
  attribute XDMA_RNUM_CHNL of inst : label is 1;
  attribute XDMA_RNUM_RIDS : integer;
  attribute XDMA_RNUM_RIDS of inst : label is 32;
  attribute XDMA_STS_PORTS : string;
  attribute XDMA_STS_PORTS of inst : label is "FALSE";
  attribute XDMA_ST_INFINITE_DESC_EXDES : string;
  attribute XDMA_ST_INFINITE_DESC_EXDES of inst : label is "FALSE";
  attribute XDMA_WNUM_CHNL : integer;
  attribute XDMA_WNUM_CHNL of inst : label is 1;
  attribute XDMA_WNUM_RIDS : integer;
  attribute XDMA_WNUM_RIDS of inst : label is 16;
  attribute xlnx_ref_board : string;
  attribute xlnx_ref_board of inst : label is "None";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of axi_aclk : signal is "xilinx.com:signal:clock:1.0 CLK.axi_aclk CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of axi_aclk : signal is "XIL_INTERFACENAME CLK.axi_aclk, ASSOCIATED_BUSIF M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx, ASSOCIATED_RESET axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of axi_aresetn : signal is "xilinx.com:signal:reset:1.0 RST.axi_aresetn RST";
  attribute X_INTERFACE_PARAMETER of axi_aresetn : signal is "XIL_INTERFACENAME RST.axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of cfg_mgmt_read : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN";
  attribute X_INTERFACE_INFO of cfg_mgmt_read_write_done : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE";
  attribute X_INTERFACE_INFO of cfg_mgmt_type1_cfg_reg_access : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS";
  attribute X_INTERFACE_INFO of cfg_mgmt_write : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN";
  attribute X_INTERFACE_INFO of m_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK";
  attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
  attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
  attribute X_INTERFACE_INFO of m_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK";
  attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
  attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
  attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
  attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
  attribute X_INTERFACE_INFO of m_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
  attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
  attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, SUPPORTS_NARROW_BURST 0, HAS_BURST 0, HAS_BURST.VALUE_SRC CONSTANT, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
  attribute X_INTERFACE_INFO of m_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
  attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
  attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
  attribute X_INTERFACE_INFO of m_axib_arlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARLOCK";
  attribute X_INTERFACE_INFO of m_axib_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARREADY";
  attribute X_INTERFACE_INFO of m_axib_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARVALID";
  attribute X_INTERFACE_INFO of m_axib_awlock : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWLOCK";
  attribute X_INTERFACE_INFO of m_axib_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWREADY";
  attribute X_INTERFACE_INFO of m_axib_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWVALID";
  attribute X_INTERFACE_INFO of m_axib_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BREADY";
  attribute X_INTERFACE_INFO of m_axib_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BVALID";
  attribute X_INTERFACE_INFO of m_axib_rlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RLAST";
  attribute X_INTERFACE_INFO of m_axib_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RREADY";
  attribute X_INTERFACE_PARAMETER of m_axib_rready : signal is "XIL_INTERFACENAME M_AXI_BYPASS, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, HAS_BURST 0, SUPPORTS_NARROW_BURST 0, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 256, PHASE 0.000, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of m_axib_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RVALID";
  attribute X_INTERFACE_INFO of m_axib_wlast : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WLAST";
  attribute X_INTERFACE_INFO of m_axib_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WREADY";
  attribute X_INTERFACE_INFO of m_axib_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WVALID";
  attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
  attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of sys_rst_n : signal is "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST";
  attribute X_INTERFACE_PARAMETER of sys_rst_n : signal is "XIL_INTERFACENAME RST.sys_rst_n, BOARD.ASSOCIATED_PARAM SYS_RST_N_BOARD_INTERFACE, TYPE PCIE_PERST, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of cfg_mgmt_addr : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR";
  attribute X_INTERFACE_INFO of cfg_mgmt_byte_enable : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN";
  attribute X_INTERFACE_INFO of cfg_mgmt_read_data : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA";
  attribute X_INTERFACE_INFO of cfg_mgmt_write_data : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA";
  attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
  attribute X_INTERFACE_INFO of m_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
  attribute X_INTERFACE_INFO of m_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
  attribute X_INTERFACE_INFO of m_axi_arid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARID";
  attribute X_INTERFACE_INFO of m_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
  attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
  attribute X_INTERFACE_INFO of m_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
  attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
  attribute X_INTERFACE_INFO of m_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
  attribute X_INTERFACE_INFO of m_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
  attribute X_INTERFACE_INFO of m_axi_awid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWID";
  attribute X_INTERFACE_INFO of m_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
  attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
  attribute X_INTERFACE_INFO of m_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
  attribute X_INTERFACE_INFO of m_axi_bid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BID";
  attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
  attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
  attribute X_INTERFACE_INFO of m_axi_rid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RID";
  attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
  attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
  attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
  attribute X_INTERFACE_INFO of m_axib_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARADDR";
  attribute X_INTERFACE_INFO of m_axib_arburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARBURST";
  attribute X_INTERFACE_INFO of m_axib_arcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARCACHE";
  attribute X_INTERFACE_INFO of m_axib_arid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARID";
  attribute X_INTERFACE_INFO of m_axib_arlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARLEN";
  attribute X_INTERFACE_INFO of m_axib_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARPROT";
  attribute X_INTERFACE_INFO of m_axib_arsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARSIZE";
  attribute X_INTERFACE_INFO of m_axib_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWADDR";
  attribute X_INTERFACE_INFO of m_axib_awburst : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWBURST";
  attribute X_INTERFACE_INFO of m_axib_awcache : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWCACHE";
  attribute X_INTERFACE_INFO of m_axib_awid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWID";
  attribute X_INTERFACE_INFO of m_axib_awlen : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWLEN";
  attribute X_INTERFACE_INFO of m_axib_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWPROT";
  attribute X_INTERFACE_INFO of m_axib_awsize : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWSIZE";
  attribute X_INTERFACE_INFO of m_axib_bid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BID";
  attribute X_INTERFACE_INFO of m_axib_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BRESP";
  attribute X_INTERFACE_INFO of m_axib_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RDATA";
  attribute X_INTERFACE_INFO of m_axib_rid : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RID";
  attribute X_INTERFACE_INFO of m_axib_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RRESP";
  attribute X_INTERFACE_INFO of m_axib_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WDATA";
  attribute X_INTERFACE_INFO of m_axib_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WSTRB";
  attribute X_INTERFACE_INFO of pci_exp_rxn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt rxn";
  attribute X_INTERFACE_PARAMETER of pci_exp_rxn : signal is "XIL_INTERFACENAME pcie_mgt, BOARD.ASSOCIATED_PARAM PCIE_BOARD_INTERFACE";
  attribute X_INTERFACE_INFO of pci_exp_rxp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt rxp";
  attribute X_INTERFACE_INFO of pci_exp_txn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt txn";
  attribute X_INTERFACE_INFO of pci_exp_txp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt txp";
begin
  m_axib_arlock <= \<const0>\;
  m_axib_awlock <= \<const0>\;
  m_axis_rx_tkeep_o(7 downto 4) <= \^m_axis_rx_tkeep_o\(7 downto 4);
  m_axis_rx_tkeep_o(3) <= \<const1>\;
  m_axis_rx_tkeep_o(2) <= \<const1>\;
  m_axis_rx_tkeep_o(1) <= \<const1>\;
  m_axis_rx_tkeep_o(0) <= \<const1>\;
  m_axis_rx_tuser_o(21) <= \^m_axis_rx_tuser_o\(21);
  m_axis_rx_tuser_o(20) <= \<const0>\;
  m_axis_rx_tuser_o(19 downto 17) <= \^m_axis_rx_tuser_o\(19 downto 17);
  m_axis_rx_tuser_o(16) <= \<const0>\;
  m_axis_rx_tuser_o(15) <= \<const0>\;
  m_axis_rx_tuser_o(14) <= \^m_axis_rx_tuser_o\(14);
  m_axis_rx_tuser_o(13) <= \<const0>\;
  m_axis_rx_tuser_o(12) <= \<const0>\;
  m_axis_rx_tuser_o(11) <= \<const0>\;
  m_axis_rx_tuser_o(10) <= \<const0>\;
  m_axis_rx_tuser_o(9) <= \<const0>\;
  m_axis_rx_tuser_o(8 downto 0) <= \^m_axis_rx_tuser_o\(8 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
inst: entity work.xdma_0_xdma_0_core_top
     port map (
      Integrated_bloc_reset_o => Integrated_bloc_reset_o,
      ats_pri_en => NLW_inst_ats_pri_en_UNCONNECTED,
      atspri_m_axis_cq_tdata(63 downto 0) => NLW_inst_atspri_m_axis_cq_tdata_UNCONNECTED(63 downto 0),
      atspri_m_axis_cq_tkeep(1 downto 0) => NLW_inst_atspri_m_axis_cq_tkeep_UNCONNECTED(1 downto 0),
      atspri_m_axis_cq_tlast => NLW_inst_atspri_m_axis_cq_tlast_UNCONNECTED,
      atspri_m_axis_cq_tready => '0',
      atspri_m_axis_cq_tuser(84 downto 0) => NLW_inst_atspri_m_axis_cq_tuser_UNCONNECTED(84 downto 0),
      atspri_m_axis_cq_tvalid => NLW_inst_atspri_m_axis_cq_tvalid_UNCONNECTED,
      atspri_s_axis_rq_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      atspri_s_axis_rq_tkeep(1 downto 0) => B"00",
      atspri_s_axis_rq_tlast => '0',
      atspri_s_axis_rq_tready => NLW_inst_atspri_s_axis_rq_tready_UNCONNECTED,
      atspri_s_axis_rq_tuser(59 downto 0) => B"000000000000000000000000000000000000000000000000000000000000",
      atspri_s_axis_rq_tvalid => '0',
      axi_aclk => axi_aclk,
      axi_aresetn => axi_aresetn,
      axi_ctl_aclk => '0',
      axi_ctl_aresetn => NLW_inst_axi_ctl_aresetn_UNCONNECTED,
      bufgtce_us_out(5 downto 0) => B"000000",
      bufgtce_usp_out(1 downto 0) => B"00",
      bufgtcemask_us_out(5 downto 0) => B"000000",
      bufgtcemask_usp_out(5 downto 0) => B"000000",
      bufgtdiv_us_out(17 downto 0) => B"000000000000000000",
      bufgtdiv_usp_out(17 downto 0) => B"000000000000000000",
      bufgtreset_us_out(5 downto 0) => B"000000",
      bufgtreset_usp_out(1 downto 0) => B"00",
      bufgtrstmask_us_out(5 downto 0) => B"000000",
      bufgtrstmask_usp_out(5 downto 0) => B"000000",
      c2h_dsc_byp_ctl_0(15 downto 0) => B"0000000000000000",
      c2h_dsc_byp_ctl_1(15 downto 0) => B"0000000000000000",
      c2h_dsc_byp_ctl_2(15 downto 0) => B"0000000000000000",
      c2h_dsc_byp_ctl_3(15 downto 0) => B"0000000000000000",
      c2h_dsc_byp_dst_addr_0(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_dst_addr_1(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_dst_addr_2(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_dst_addr_3(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_len_0(27 downto 0) => B"0000000000000000000000000000",
      c2h_dsc_byp_len_1(27 downto 0) => B"0000000000000000000000000000",
      c2h_dsc_byp_len_2(27 downto 0) => B"0000000000000000000000000000",
      c2h_dsc_byp_len_3(27 downto 0) => B"0000000000000000000000000000",
      c2h_dsc_byp_load_0 => '0',
      c2h_dsc_byp_load_1 => '0',
      c2h_dsc_byp_load_2 => '0',
      c2h_dsc_byp_load_3 => '0',
      c2h_dsc_byp_ready_0 => NLW_inst_c2h_dsc_byp_ready_0_UNCONNECTED,
      c2h_dsc_byp_ready_1 => NLW_inst_c2h_dsc_byp_ready_1_UNCONNECTED,
      c2h_dsc_byp_ready_2 => NLW_inst_c2h_dsc_byp_ready_2_UNCONNECTED,
      c2h_dsc_byp_ready_3 => NLW_inst_c2h_dsc_byp_ready_3_UNCONNECTED,
      c2h_dsc_byp_src_addr_0(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_src_addr_1(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_src_addr_2(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_dsc_byp_src_addr_3(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      c2h_sts_0(7 downto 0) => NLW_inst_c2h_sts_0_UNCONNECTED(7 downto 0),
      c2h_sts_1(7 downto 0) => NLW_inst_c2h_sts_1_UNCONNECTED(7 downto 0),
      c2h_sts_2(7 downto 0) => NLW_inst_c2h_sts_2_UNCONNECTED(7 downto 0),
      c2h_sts_3(7 downto 0) => NLW_inst_c2h_sts_3_UNCONNECTED(7 downto 0),
      cap_gnt => '1',
      cap_rel => '0',
      cap_req => NLW_inst_cap_req_UNCONNECTED,
      ccix_optimized_tlp_tx_and_rx_enable_in => '0',
      cfg_bus_number_o(7 downto 0) => cfg_bus_number_o(7 downto 0),
      cfg_current_speed_o(2 downto 0) => NLW_inst_cfg_current_speed_o_UNCONNECTED(2 downto 0),
      cfg_current_speed_sd(1 downto 0) => B"00",
      cfg_dev_id_pf0(15 downto 0) => B"0111000000100010",
      cfg_dev_id_pf1(15 downto 0) => B"1001000100010001",
      cfg_dev_id_pf2(15 downto 0) => B"1001001000010001",
      cfg_dev_id_pf3(15 downto 0) => B"1001001100010001",
      cfg_device_number_o(4 downto 0) => cfg_device_number_o(4 downto 0),
      cfg_ds_bus_number_sd(7 downto 0) => NLW_inst_cfg_ds_bus_number_sd_UNCONNECTED(7 downto 0),
      cfg_ds_device_number_sd(4 downto 0) => NLW_inst_cfg_ds_device_number_sd_UNCONNECTED(4 downto 0),
      cfg_ds_function_number_sd(2 downto 0) => NLW_inst_cfg_ds_function_number_sd_UNCONNECTED(2 downto 0),
      cfg_ds_port_number_sd(7 downto 0) => NLW_inst_cfg_ds_port_number_sd_UNCONNECTED(7 downto 0),
      cfg_dsn_sd(63 downto 0) => NLW_inst_cfg_dsn_sd_UNCONNECTED(63 downto 0),
      cfg_err_cor_in_sd => NLW_inst_cfg_err_cor_in_sd_UNCONNECTED,
      cfg_err_cor_o => NLW_inst_cfg_err_cor_o_UNCONNECTED,
      cfg_err_cor_out_sd => '0',
      cfg_err_fatal_o => NLW_inst_cfg_err_fatal_o_UNCONNECTED,
      cfg_err_fatal_out_sd => '0',
      cfg_err_nonfatal_o => NLW_inst_cfg_err_nonfatal_o_UNCONNECTED,
      cfg_err_nonfatal_out_sd => '0',
      cfg_err_uncor_in_sd => NLW_inst_cfg_err_uncor_in_sd_UNCONNECTED,
      cfg_ext_function_number(7 downto 0) => NLW_inst_cfg_ext_function_number_UNCONNECTED(7 downto 0),
      cfg_ext_read_data(31 downto 0) => B"00000000000000000000000000000000",
      cfg_ext_read_data_valid => '0',
      cfg_ext_read_received => NLW_inst_cfg_ext_read_received_UNCONNECTED,
      cfg_ext_register_number(9 downto 0) => NLW_inst_cfg_ext_register_number_UNCONNECTED(9 downto 0),
      cfg_ext_write_byte_enable(3 downto 0) => NLW_inst_cfg_ext_write_byte_enable_UNCONNECTED(3 downto 0),
      cfg_ext_write_data(31 downto 0) => NLW_inst_cfg_ext_write_data_UNCONNECTED(31 downto 0),
      cfg_ext_write_received => NLW_inst_cfg_ext_write_received_UNCONNECTED,
      cfg_fc_nph_sd(7 downto 0) => B"00000000",
      cfg_fc_sel_sd(2 downto 0) => NLW_inst_cfg_fc_sel_sd_UNCONNECTED(2 downto 0),
      cfg_fc_vc_sel => '0',
      cfg_flr_done(3 downto 0) => B"0000",
      cfg_flr_done_sd(3 downto 0) => NLW_inst_cfg_flr_done_sd_UNCONNECTED(3 downto 0),
      cfg_flr_in_process(3 downto 0) => NLW_inst_cfg_flr_in_process_UNCONNECTED(3 downto 0),
      cfg_flr_in_process_sd(3 downto 0) => B"0000",
      cfg_function_number_o(2 downto 0) => cfg_function_number_o(2 downto 0),
      cfg_function_status(7 downto 0) => NLW_inst_cfg_function_status_UNCONNECTED(7 downto 0),
      cfg_function_status_sd(15 downto 0) => B"0000000000000000",
      cfg_hot_reset_out_sd => '0',
      cfg_interrupt_int_sd(3 downto 0) => NLW_inst_cfg_interrupt_int_sd_UNCONNECTED(3 downto 0),
      cfg_interrupt_msi_attr_sd(2 downto 0) => NLW_inst_cfg_interrupt_msi_attr_sd_UNCONNECTED(2 downto 0),
      cfg_interrupt_msi_data_sd(31 downto 0) => B"00000000000000000000000000000000",
      cfg_interrupt_msi_enable(3 downto 0) => NLW_inst_cfg_interrupt_msi_enable_UNCONNECTED(3 downto 0),
      cfg_interrupt_msi_enable_sd(3 downto 0) => B"0000",
      cfg_interrupt_msi_fail => NLW_inst_cfg_interrupt_msi_fail_UNCONNECTED,
      cfg_interrupt_msi_fail_sd => '0',
      cfg_interrupt_msi_function_number_sd(7 downto 0) => NLW_inst_cfg_interrupt_msi_function_number_sd_UNCONNECTED(7 downto 0),
      cfg_interrupt_msi_int_sd(31 downto 0) => NLW_inst_cfg_interrupt_msi_int_sd_UNCONNECTED(31 downto 0),
      cfg_interrupt_msi_mask_update_sd => '0',
      cfg_interrupt_msi_pending_status_data_enable_sd => NLW_inst_cfg_interrupt_msi_pending_status_data_enable_sd_UNCONNECTED,
      cfg_interrupt_msi_pending_status_function_num_sd(3 downto 0) => NLW_inst_cfg_interrupt_msi_pending_status_function_num_sd_UNCONNECTED(3 downto 0),
      cfg_interrupt_msi_pending_status_sd(31 downto 0) => NLW_inst_cfg_interrupt_msi_pending_status_sd_UNCONNECTED(31 downto 0),
      cfg_interrupt_msi_sent => NLW_inst_cfg_interrupt_msi_sent_UNCONNECTED,
      cfg_interrupt_msi_sent_sd => '0',
      cfg_interrupt_msi_tph_present_sd => NLW_inst_cfg_interrupt_msi_tph_present_sd_UNCONNECTED,
      cfg_interrupt_msi_tph_st_tag_sd(8 downto 0) => NLW_inst_cfg_interrupt_msi_tph_st_tag_sd_UNCONNECTED(8 downto 0),
      cfg_interrupt_msi_tph_type_sd(1 downto 0) => NLW_inst_cfg_interrupt_msi_tph_type_sd_UNCONNECTED(1 downto 0),
      cfg_interrupt_msix_address(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      cfg_interrupt_msix_address_sd(63 downto 0) => NLW_inst_cfg_interrupt_msix_address_sd_UNCONNECTED(63 downto 0),
      cfg_interrupt_msix_data(31 downto 0) => B"00000000000000000000000000000000",
      cfg_interrupt_msix_data_sd(31 downto 0) => NLW_inst_cfg_interrupt_msix_data_sd_UNCONNECTED(31 downto 0),
      cfg_interrupt_msix_enable(1 downto 0) => NLW_inst_cfg_interrupt_msix_enable_UNCONNECTED(1 downto 0),
      cfg_interrupt_msix_enable_sd(3 downto 0) => B"0000",
      cfg_interrupt_msix_fail => NLW_inst_cfg_interrupt_msix_fail_UNCONNECTED,
      cfg_interrupt_msix_int => '0',
      cfg_interrupt_msix_int_sd => NLW_inst_cfg_interrupt_msix_int_sd_UNCONNECTED,
      cfg_interrupt_msix_mask(1 downto 0) => NLW_inst_cfg_interrupt_msix_mask_UNCONNECTED(1 downto 0),
      cfg_interrupt_msix_mask_sd(3 downto 0) => B"0000",
      cfg_interrupt_msix_sent => NLW_inst_cfg_interrupt_msix_sent_UNCONNECTED,
      cfg_interrupt_msix_vec_pending_sd(1 downto 0) => NLW_inst_cfg_interrupt_msix_vec_pending_sd_UNCONNECTED(1 downto 0),
      cfg_interrupt_msix_vec_pending_status_sd => '0',
      cfg_interrupt_msix_vf_enable_sd(251 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      cfg_interrupt_msix_vf_mask_sd(251 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      cfg_interrupt_pending_sd(3 downto 0) => NLW_inst_cfg_interrupt_pending_sd_UNCONNECTED(3 downto 0),
      cfg_interrupt_sent_sd => '0',
      cfg_link_training_enable_sd => NLW_inst_cfg_link_training_enable_sd_UNCONNECTED,
      cfg_local_error_o(4 downto 0) => NLW_inst_cfg_local_error_o_UNCONNECTED(4 downto 0),
      cfg_local_error_out_sd(4 downto 0) => B"00000",
      cfg_local_error_valid_o => NLW_inst_cfg_local_error_valid_o_UNCONNECTED,
      cfg_ltssm_state(5 downto 0) => NLW_inst_cfg_ltssm_state_UNCONNECTED(5 downto 0),
      cfg_ltssm_state_o(5 downto 0) => NLW_inst_cfg_ltssm_state_o_UNCONNECTED(5 downto 0),
      cfg_ltssm_state_sd(5 downto 0) => B"000000",
      cfg_max_payload(2 downto 0) => NLW_inst_cfg_max_payload_UNCONNECTED(2 downto 0),
      cfg_max_payload_sd(1 downto 0) => B"00",
      cfg_max_read_req(2 downto 0) => NLW_inst_cfg_max_read_req_UNCONNECTED(2 downto 0),
      cfg_max_read_req_sd(2 downto 0) => B"000",
      cfg_mgmt_addr(18 downto 0) => cfg_mgmt_addr(18 downto 0),
      cfg_mgmt_addr_sd(9 downto 0) => NLW_inst_cfg_mgmt_addr_sd_UNCONNECTED(9 downto 0),
      cfg_mgmt_byte_enable(3 downto 0) => cfg_mgmt_byte_enable(3 downto 0),
      cfg_mgmt_byte_enable_sd(3 downto 0) => NLW_inst_cfg_mgmt_byte_enable_sd_UNCONNECTED(3 downto 0),
      cfg_mgmt_function_number_sd(7 downto 0) => NLW_inst_cfg_mgmt_function_number_sd_UNCONNECTED(7 downto 0),
      cfg_mgmt_read => cfg_mgmt_read,
      cfg_mgmt_read_data(31 downto 0) => cfg_mgmt_read_data(31 downto 0),
      cfg_mgmt_read_data_sd(31 downto 0) => B"00000000000000000000000000000000",
      cfg_mgmt_read_sd => NLW_inst_cfg_mgmt_read_sd_UNCONNECTED,
      cfg_mgmt_read_write_done => cfg_mgmt_read_write_done,
      cfg_mgmt_read_write_done_sd => '0',
      cfg_mgmt_type1_cfg_reg_access => cfg_mgmt_type1_cfg_reg_access,
      cfg_mgmt_type1_cfg_reg_access_sd => NLW_inst_cfg_mgmt_type1_cfg_reg_access_sd_UNCONNECTED,
      cfg_mgmt_write => cfg_mgmt_write,
      cfg_mgmt_write_data(31 downto 0) => cfg_mgmt_write_data(31 downto 0),
      cfg_mgmt_write_data_sd(31 downto 0) => NLW_inst_cfg_mgmt_write_data_sd_UNCONNECTED(31 downto 0),
      cfg_mgmt_write_sd => NLW_inst_cfg_mgmt_write_sd_UNCONNECTED,
      cfg_msg_received_data_sd(7 downto 0) => B"00000000",
      cfg_msg_received_sd => '0',
      cfg_msg_received_type_sd(4 downto 0) => B"00000",
      cfg_msg_transmit_data_sd(31 downto 0) => NLW_inst_cfg_msg_transmit_data_sd_UNCONNECTED(31 downto 0),
      cfg_msg_transmit_done_sd => '0',
      cfg_msg_transmit_sd => NLW_inst_cfg_msg_transmit_sd_UNCONNECTED,
      cfg_msg_transmit_type_sd(2 downto 0) => NLW_inst_cfg_msg_transmit_type_sd_UNCONNECTED(2 downto 0),
      cfg_negotiated_width_o(3 downto 0) => NLW_inst_cfg_negotiated_width_o_UNCONNECTED(3 downto 0),
      cfg_negotiated_width_sd(2 downto 0) => B"000",
      cfg_phy_link_down_sd => '0',
      cfg_phy_link_status_sd(1 downto 0) => B"00",
      cfg_pl_status_change_sd => '0',
      cfg_rev_id_pf0(7 downto 0) => B"00000000",
      cfg_rev_id_pf1(7 downto 0) => B"00000000",
      cfg_rev_id_pf2(7 downto 0) => B"00000000",
      cfg_rev_id_pf3(7 downto 0) => B"00000000",
      cfg_status_ats_en => NLW_inst_cfg_status_ats_en_UNCONNECTED,
      cfg_status_ats_stu(4 downto 0) => NLW_inst_cfg_status_ats_stu_UNCONNECTED(4 downto 0),
      cfg_status_clr_s => '0',
      cfg_status_ost_pr_alloc(31 downto 0) => NLW_inst_cfg_status_ost_pr_alloc_UNCONNECTED(31 downto 0),
      cfg_status_pr_en => NLW_inst_cfg_status_pr_en_UNCONNECTED,
      cfg_status_pr_rf => NLW_inst_cfg_status_pr_rf_UNCONNECTED,
      cfg_status_pr_rst => NLW_inst_cfg_status_pr_rst_UNCONNECTED,
      cfg_status_pr_uprgi => NLW_inst_cfg_status_pr_uprgi_UNCONNECTED,
      cfg_status_set_rf => '0',
      cfg_status_set_s => '0',
      cfg_status_set_uprgi => '0',
      cfg_subsys_id_pf0(15 downto 0) => B"0000000000000111",
      cfg_subsys_id_pf1(15 downto 0) => B"0000000000000111",
      cfg_subsys_id_pf2(15 downto 0) => B"0000000000000111",
      cfg_subsys_id_pf3(15 downto 0) => B"0000000000000111",
      cfg_subsys_vend_id(15 downto 0) => B"0001000011101110",
      cfg_to_turnoff_o => cfg_to_turnoff_o,
      cfg_vend_id(15 downto 0) => B"0001000011101110",
      cfg_vf_flr_done => '0',
      cfg_vf_flr_func_num(7 downto 0) => B"00000000",
      cfg_vf_flr_in_process(251 downto 0) => NLW_inst_cfg_vf_flr_in_process_UNCONNECTED(251 downto 0),
      cfg_vf_flr_in_process_sd(251 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      common_commands_in(25 downto 0) => B"00000000000000000000000000",
      common_commands_out(25 downto 0) => NLW_inst_common_commands_out_UNCONNECTED(25 downto 0),
      core_clk => NLW_inst_core_clk_UNCONNECTED,
      cpllfreqlock_usp_in(1 downto 0) => NLW_inst_cpllfreqlock_usp_in_UNCONNECTED(1 downto 0),
      cplllock_us_out(1 downto 0) => B"00",
      cplllock_usp_out(1 downto 0) => B"00",
      cpllpd_us_in(1 downto 0) => NLW_inst_cpllpd_us_in_UNCONNECTED(1 downto 0),
      cpllpd_usp_in(1 downto 0) => NLW_inst_cpllpd_usp_in_UNCONNECTED(1 downto 0),
      cpllreset_us_in(1 downto 0) => NLW_inst_cpllreset_us_in_UNCONNECTED(1 downto 0),
      cpllreset_usp_in(1 downto 0) => NLW_inst_cpllreset_usp_in_UNCONNECTED(1 downto 0),
      cxs0_active_ack_rx => '0',
      cxs0_active_ack_tx => NLW_inst_cxs0_active_ack_tx_UNCONNECTED,
      cxs0_active_req_rx => NLW_inst_cxs0_active_req_rx_UNCONNECTED,
      cxs0_active_req_tx => '0',
      cxs0_cntl_chk_rx => NLW_inst_cxs0_cntl_chk_rx_UNCONNECTED,
      cxs0_cntl_chk_tx => '0',
      cxs0_cntl_rx(13 downto 0) => NLW_inst_cxs0_cntl_rx_UNCONNECTED(13 downto 0),
      cxs0_cntl_tx(13 downto 0) => B"00000000000000",
      cxs0_crdgnt_chk_rx => '0',
      cxs0_crdgnt_chk_tx => NLW_inst_cxs0_crdgnt_chk_tx_UNCONNECTED,
      cxs0_crdgnt_rx => '0',
      cxs0_crdgnt_tx => NLW_inst_cxs0_crdgnt_tx_UNCONNECTED,
      cxs0_crdrtn_chk_rx => NLW_inst_cxs0_crdrtn_chk_rx_UNCONNECTED,
      cxs0_crdrtn_chk_tx => '0',
      cxs0_crdrtn_rx => NLW_inst_cxs0_crdrtn_rx_UNCONNECTED,
      cxs0_crdrtn_tx => '0',
      cxs0_data_chk_rx(31 downto 0) => NLW_inst_cxs0_data_chk_rx_UNCONNECTED(31 downto 0),
      cxs0_data_chk_tx(31 downto 0) => B"00000000000000000000000000000000",
      cxs0_data_rx(255 downto 0) => NLW_inst_cxs0_data_rx_UNCONNECTED(255 downto 0),
      cxs0_data_tx(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      cxs0_deact_hint_rx => '0',
      cxs0_deact_hint_tx => NLW_inst_cxs0_deact_hint_tx_UNCONNECTED,
      cxs0_valid_chk_rx => NLW_inst_cxs0_valid_chk_rx_UNCONNECTED,
      cxs0_valid_chk_tx => '0',
      cxs0_valid_rx => NLW_inst_cxs0_valid_rx_UNCONNECTED,
      cxs0_valid_tx => '0',
      dma_bridge_resetn => '1',
      dmonfiforeset_us_in(1 downto 0) => NLW_inst_dmonfiforeset_us_in_UNCONNECTED(1 downto 0),
      dmonfiforeset_usp_in(1 downto 0) => NLW_inst_dmonfiforeset_usp_in_UNCONNECTED(1 downto 0),
      dmonitorclk_us_in(1 downto 0) => NLW_inst_dmonitorclk_us_in_UNCONNECTED(1 downto 0),
      dmonitorclk_usp_in(1 downto 0) => NLW_inst_dmonitorclk_usp_in_UNCONNECTED(1 downto 0),
      dmonitorout_us_out(33 downto 0) => B"0000000000000000000000000000000000",
      dmonitorout_usp_out(31 downto 0) => B"00000000000000000000000000000000",
      drp_addr(10 downto 0) => B"00000000000",
      drp_clk => '0',
      drp_di(15 downto 0) => B"0000000000000000",
      drp_do(15 downto 0) => NLW_inst_drp_do_UNCONNECTED(15 downto 0),
      drp_en => '0',
      drp_rdy => NLW_inst_drp_rdy_UNCONNECTED,
      drp_we => '0',
      drpaddr_us_in(17 downto 0) => NLW_inst_drpaddr_us_in_UNCONNECTED(17 downto 0),
      drpaddr_usp_in(19 downto 0) => NLW_inst_drpaddr_usp_in_UNCONNECTED(19 downto 0),
      drpclk_us_in(1 downto 0) => NLW_inst_drpclk_us_in_UNCONNECTED(1 downto 0),
      drpclk_usp_in => NLW_inst_drpclk_usp_in_UNCONNECTED,
      drpdi_us_in(31 downto 0) => NLW_inst_drpdi_us_in_UNCONNECTED(31 downto 0),
      drpdi_usp_in(31 downto 0) => NLW_inst_drpdi_usp_in_UNCONNECTED(31 downto 0),
      drpdo_us_out(31 downto 0) => B"00000000000000000000000000000000",
      drpdo_usp_out(31 downto 0) => B"00000000000000000000000000000000",
      drpen_us_in(1 downto 0) => NLW_inst_drpen_us_in_UNCONNECTED(1 downto 0),
      drpen_usp_in(1 downto 0) => NLW_inst_drpen_usp_in_UNCONNECTED(1 downto 0),
      drprdy_us_out(1 downto 0) => B"00",
      drprdy_usp_out(1 downto 0) => B"00",
      drprst_usp_in(1 downto 0) => NLW_inst_drprst_usp_in_UNCONNECTED(1 downto 0),
      drpwe_us_in(1 downto 0) => NLW_inst_drpwe_us_in_UNCONNECTED(1 downto 0),
      drpwe_usp_in(1 downto 0) => NLW_inst_drpwe_usp_in_UNCONNECTED(1 downto 0),
      ext_ch_gt_drpaddr(17 downto 0) => B"000000000000000000",
      ext_ch_gt_drpclk => NLW_inst_ext_ch_gt_drpclk_UNCONNECTED,
      ext_ch_gt_drpdi(31 downto 0) => B"00000000000000000000000000000000",
      ext_ch_gt_drpdo(31 downto 0) => NLW_inst_ext_ch_gt_drpdo_UNCONNECTED(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => B"00",
      ext_ch_gt_drprdy(1 downto 0) => NLW_inst_ext_ch_gt_drprdy_UNCONNECTED(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => B"00",
      ext_phy_clk_bufg_gt_ce => NLW_inst_ext_phy_clk_bufg_gt_ce_UNCONNECTED,
      ext_phy_clk_bufg_gt_reset => NLW_inst_ext_phy_clk_bufg_gt_reset_UNCONNECTED,
      ext_phy_clk_bufgtcemask => NLW_inst_ext_phy_clk_bufgtcemask_UNCONNECTED,
      ext_phy_clk_bufgtdiv(8 downto 0) => NLW_inst_ext_phy_clk_bufgtdiv_UNCONNECTED(8 downto 0),
      ext_phy_clk_gt_bufgtrstmask => NLW_inst_ext_phy_clk_gt_bufgtrstmask_UNCONNECTED,
      ext_phy_clk_int_clock => '0',
      ext_phy_clk_pclk => '0',
      ext_phy_clk_pclk2_gt => '0',
      ext_phy_clk_phy_coreclk => '0',
      ext_phy_clk_phy_mcapclk => '0',
      ext_phy_clk_phy_pclk2 => '0',
      ext_phy_clk_phy_userclk => '0',
      ext_phy_clk_rst_idle => NLW_inst_ext_phy_clk_rst_idle_UNCONNECTED,
      ext_phy_clk_txoutclk => NLW_inst_ext_phy_clk_txoutclk_UNCONNECTED,
      ext_qpll1lock_out(0) => '0',
      ext_qpll1outclk_out(0) => '0',
      ext_qpll1outrefclk_out(0) => '0',
      ext_qpll1pd(0) => NLW_inst_ext_qpll1pd_UNCONNECTED(0),
      ext_qpll1rate(2 downto 0) => NLW_inst_ext_qpll1rate_UNCONNECTED(2 downto 0),
      ext_qpll1refclk(0) => NLW_inst_ext_qpll1refclk_UNCONNECTED(0),
      ext_qpll1reset(0) => NLW_inst_ext_qpll1reset_UNCONNECTED(0),
      ext_usp_qpll0lock_out(0) => '0',
      ext_usp_qpll0outclk_out(0) => '0',
      ext_usp_qpll0outrefclk_out(0) => '0',
      ext_usp_qpll0pd(0) => NLW_inst_ext_usp_qpll0pd_UNCONNECTED(0),
      ext_usp_qpll0reset(0) => NLW_inst_ext_usp_qpll0reset_UNCONNECTED(0),
      ext_usp_qpll1lock_out(0) => '0',
      ext_usp_qpll1outclk_out(0) => '0',
      ext_usp_qpll1outrefclk_out(0) => '0',
      ext_usp_qpll1pd(0) => NLW_inst_ext_usp_qpll1pd_UNCONNECTED(0),
      ext_usp_qpll1reset(0) => NLW_inst_ext_usp_qpll1reset_UNCONNECTED(0),
      ext_usp_qpllxrate(2 downto 0) => NLW_inst_ext_usp_qpllxrate_UNCONNECTED(2 downto 0),
      ext_usp_qpllxrcalenb => NLW_inst_ext_usp_qpllxrcalenb_UNCONNECTED,
      ext_usp_qpllxrefclk(0) => NLW_inst_ext_usp_qpllxrefclk_UNCONNECTED(0),
      eyescandataerror_us_out(1 downto 0) => B"00",
      eyescanreset_us_in(1 downto 0) => NLW_inst_eyescanreset_us_in_UNCONNECTED(1 downto 0),
      eyescanreset_usp_in(1 downto 0) => NLW_inst_eyescanreset_usp_in_UNCONNECTED(1 downto 0),
      free_run_clock => '0',
      gt_bufgtdiv(8 downto 0) => NLW_inst_gt_bufgtdiv_UNCONNECTED(8 downto 0),
      gt_ch_drp_rdy(1 downto 0) => NLW_inst_gt_ch_drp_rdy_UNCONNECTED(1 downto 0),
      gt_cplllock(1 downto 0) => NLW_inst_gt_cplllock_UNCONNECTED(1 downto 0),
      gt_dmonfiforeset(1 downto 0) => B"00",
      gt_dmonitorclk(1 downto 0) => B"00",
      gt_dmonitorout(33 downto 0) => NLW_inst_gt_dmonitorout_UNCONNECTED(33 downto 0),
      gt_drp_clk => NLW_inst_gt_drp_clk_UNCONNECTED,
      gt_eyescandataerror(1 downto 0) => NLW_inst_gt_eyescandataerror_UNCONNECTED(1 downto 0),
      gt_gen34_eios_det(1 downto 0) => NLW_inst_gt_gen34_eios_det_UNCONNECTED(1 downto 0),
      gt_gtpowergood(1 downto 0) => NLW_inst_gt_gtpowergood_UNCONNECTED(1 downto 0),
      gt_loopback(5 downto 0) => B"000000",
      gt_pcierateidle(1 downto 0) => NLW_inst_gt_pcierateidle_UNCONNECTED(1 downto 0),
      gt_pcieuserratedone(1 downto 0) => B"00",
      gt_pcieuserratestart(1 downto 0) => NLW_inst_gt_pcieuserratestart_UNCONNECTED(1 downto 0),
      gt_phystatus(1 downto 0) => NLW_inst_gt_phystatus_UNCONNECTED(1 downto 0),
      gt_qpll0lock(0) => NLW_inst_gt_qpll0lock_UNCONNECTED(0),
      gt_qpll1lock(0) => NLW_inst_gt_qpll1lock_UNCONNECTED(0),
      gt_rxbufreset(1 downto 0) => B"00",
      gt_rxbufstatus(5 downto 0) => NLW_inst_gt_rxbufstatus_UNCONNECTED(5 downto 0),
      gt_rxcdrlock(1 downto 0) => NLW_inst_gt_rxcdrlock_UNCONNECTED(1 downto 0),
      gt_rxcdrreset(1 downto 0) => B"00",
      gt_rxcommadet(1 downto 0) => NLW_inst_gt_rxcommadet_UNCONNECTED(1 downto 0),
      gt_rxdfelpmreset(1 downto 0) => B"00",
      gt_rxdlysresetdone(1 downto 0) => NLW_inst_gt_rxdlysresetdone_UNCONNECTED(1 downto 0),
      gt_rxoutclk(1 downto 0) => NLW_inst_gt_rxoutclk_UNCONNECTED(1 downto 0),
      gt_rxoutclkfabric(1 downto 0) => NLW_inst_gt_rxoutclkfabric_UNCONNECTED(1 downto 0),
      gt_rxoutclkpcs(1 downto 0) => NLW_inst_gt_rxoutclkpcs_UNCONNECTED(1 downto 0),
      gt_rxpcsreset(1 downto 0) => B"00",
      gt_rxphaligndone(1 downto 0) => NLW_inst_gt_rxphaligndone_UNCONNECTED(1 downto 0),
      gt_rxpmareset(1 downto 0) => B"00",
      gt_rxpmaresetdone(1 downto 0) => NLW_inst_gt_rxpmaresetdone_UNCONNECTED(1 downto 0),
      gt_rxprbscntreset(1 downto 0) => B"00",
      gt_rxprbserr(1 downto 0) => NLW_inst_gt_rxprbserr_UNCONNECTED(1 downto 0),
      gt_rxprbslocked(1 downto 0) => NLW_inst_gt_rxprbslocked_UNCONNECTED(1 downto 0),
      gt_rxprbssel(7 downto 0) => B"00000000",
      gt_rxrecclkout(1 downto 0) => NLW_inst_gt_rxrecclkout_UNCONNECTED(1 downto 0),
      gt_rxresetdone(1 downto 0) => NLW_inst_gt_rxresetdone_UNCONNECTED(1 downto 0),
      gt_rxstatus(5 downto 0) => NLW_inst_gt_rxstatus_UNCONNECTED(5 downto 0),
      gt_rxsyncdone(1 downto 0) => NLW_inst_gt_rxsyncdone_UNCONNECTED(1 downto 0),
      gt_rxvalid(1 downto 0) => NLW_inst_gt_rxvalid_UNCONNECTED(1 downto 0),
      gt_txdlysresetdone(1 downto 0) => NLW_inst_gt_txdlysresetdone_UNCONNECTED(1 downto 0),
      gt_txelecidle(1 downto 0) => NLW_inst_gt_txelecidle_UNCONNECTED(1 downto 0),
      gt_txinhibit(1 downto 0) => B"00",
      gt_txoutclk(1 downto 0) => NLW_inst_gt_txoutclk_UNCONNECTED(1 downto 0),
      gt_txoutclkfabric(1 downto 0) => NLW_inst_gt_txoutclkfabric_UNCONNECTED(1 downto 0),
      gt_txoutclkpcs(1 downto 0) => NLW_inst_gt_txoutclkpcs_UNCONNECTED(1 downto 0),
      gt_txpcsreset(1 downto 0) => B"00",
      gt_txphaligndone(1 downto 0) => NLW_inst_gt_txphaligndone_UNCONNECTED(1 downto 0),
      gt_txphinitdone(1 downto 0) => NLW_inst_gt_txphinitdone_UNCONNECTED(1 downto 0),
      gt_txpmareset(1 downto 0) => B"00",
      gt_txpmaresetdone(1 downto 0) => NLW_inst_gt_txpmaresetdone_UNCONNECTED(1 downto 0),
      gt_txprbsforceerr(1 downto 0) => B"00",
      gt_txprbssel(7 downto 0) => B"00000000",
      gt_txprogdivresetdone(1 downto 0) => NLW_inst_gt_txprogdivresetdone_UNCONNECTED(1 downto 0),
      gt_txresetdone(1 downto 0) => NLW_inst_gt_txresetdone_UNCONNECTED(1 downto 0),
      gt_txsyncdone(1 downto 0) => NLW_inst_gt_txsyncdone_UNCONNECTED(1 downto 0),
      gthrxn_us_in(1 downto 0) => NLW_inst_gthrxn_us_in_UNCONNECTED(1 downto 0),
      gthrxp_us_in(1 downto 0) => NLW_inst_gthrxp_us_in_UNCONNECTED(1 downto 0),
      gthtxn_us_out(1 downto 0) => B"00",
      gthtxp_us_out(1 downto 0) => B"00",
      gtpowergood_us_out(1 downto 0) => B"00",
      gtpowergood_usp_out(1 downto 0) => B"00",
      gtrefclk00_usp_in(0) => NLW_inst_gtrefclk00_usp_in_UNCONNECTED(0),
      gtrefclk01_us_in(0) => NLW_inst_gtrefclk01_us_in_UNCONNECTED(0),
      gtrefclk01_usp_in(0) => NLW_inst_gtrefclk01_usp_in_UNCONNECTED(0),
      gtrefclk0_us_in(1 downto 0) => NLW_inst_gtrefclk0_us_in_UNCONNECTED(1 downto 0),
      gtrefclk0_usp_in(1 downto 0) => NLW_inst_gtrefclk0_usp_in_UNCONNECTED(1 downto 0),
      gtrxreset_us_in(1 downto 0) => NLW_inst_gtrxreset_us_in_UNCONNECTED(1 downto 0),
      gtrxreset_usp_in(1 downto 0) => NLW_inst_gtrxreset_usp_in_UNCONNECTED(1 downto 0),
      gttxreset_us_in(1 downto 0) => NLW_inst_gttxreset_us_in_UNCONNECTED(1 downto 0),
      gttxreset_usp_in(1 downto 0) => NLW_inst_gttxreset_usp_in_UNCONNECTED(1 downto 0),
      gtwiz_reset_rx_done_us_in => NLW_inst_gtwiz_reset_rx_done_us_in_UNCONNECTED,
      gtwiz_reset_rx_done_usp_in => NLW_inst_gtwiz_reset_rx_done_usp_in_UNCONNECTED,
      gtwiz_reset_tx_done_us_in => NLW_inst_gtwiz_reset_tx_done_us_in_UNCONNECTED,
      gtwiz_reset_tx_done_usp_in => NLW_inst_gtwiz_reset_tx_done_usp_in_UNCONNECTED,
      gtwiz_userclk_rx_active_us_in => NLW_inst_gtwiz_userclk_rx_active_us_in_UNCONNECTED,
      gtwiz_userclk_rx_active_usp_in => NLW_inst_gtwiz_userclk_rx_active_usp_in_UNCONNECTED,
      gtwiz_userclk_tx_active_us_in => NLW_inst_gtwiz_userclk_tx_active_us_in_UNCONNECTED,
      gtwiz_userclk_tx_active_usp_in => NLW_inst_gtwiz_userclk_tx_active_usp_in_UNCONNECTED,
      gtwiz_userclk_tx_reset_us_in => NLW_inst_gtwiz_userclk_tx_reset_us_in_UNCONNECTED,
      h2c_dsc_byp_ctl_0(15 downto 0) => B"0000000000000000",
      h2c_dsc_byp_ctl_1(15 downto 0) => B"0000000000000000",
      h2c_dsc_byp_ctl_2(15 downto 0) => B"0000000000000000",
      h2c_dsc_byp_ctl_3(15 downto 0) => B"0000000000000000",
      h2c_dsc_byp_dst_addr_0(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_dst_addr_1(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_dst_addr_2(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_dst_addr_3(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_len_0(27 downto 0) => B"0000000000000000000000000000",
      h2c_dsc_byp_len_1(27 downto 0) => B"0000000000000000000000000000",
      h2c_dsc_byp_len_2(27 downto 0) => B"0000000000000000000000000000",
      h2c_dsc_byp_len_3(27 downto 0) => B"0000000000000000000000000000",
      h2c_dsc_byp_load_0 => '0',
      h2c_dsc_byp_load_1 => '0',
      h2c_dsc_byp_load_2 => '0',
      h2c_dsc_byp_load_3 => '0',
      h2c_dsc_byp_ready_0 => NLW_inst_h2c_dsc_byp_ready_0_UNCONNECTED,
      h2c_dsc_byp_ready_1 => NLW_inst_h2c_dsc_byp_ready_1_UNCONNECTED,
      h2c_dsc_byp_ready_2 => NLW_inst_h2c_dsc_byp_ready_2_UNCONNECTED,
      h2c_dsc_byp_ready_3 => NLW_inst_h2c_dsc_byp_ready_3_UNCONNECTED,
      h2c_dsc_byp_src_addr_0(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_src_addr_1(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_src_addr_2(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_dsc_byp_src_addr_3(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      h2c_sts_0(7 downto 0) => NLW_inst_h2c_sts_0_UNCONNECTED(7 downto 0),
      h2c_sts_1(7 downto 0) => NLW_inst_h2c_sts_1_UNCONNECTED(7 downto 0),
      h2c_sts_2(7 downto 0) => NLW_inst_h2c_sts_2_UNCONNECTED(7 downto 0),
      h2c_sts_3(7 downto 0) => NLW_inst_h2c_sts_3_UNCONNECTED(7 downto 0),
      int_dclk_out => NLW_inst_int_dclk_out_UNCONNECTED,
      int_oobclk_out => NLW_inst_int_oobclk_out_UNCONNECTED,
      int_pclk_out_slave => NLW_inst_int_pclk_out_slave_UNCONNECTED,
      int_pclk_sel_slave(1 downto 0) => B"00",
      int_pipe_rxusrclk_out => NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED,
      int_qpll1lock_out(0) => NLW_inst_int_qpll1lock_out_UNCONNECTED(0),
      int_qpll1outclk_out(0) => NLW_inst_int_qpll1outclk_out_UNCONNECTED(0),
      int_qpll1outrefclk_out(0) => NLW_inst_int_qpll1outrefclk_out_UNCONNECTED(0),
      int_qplllock_out(1 downto 0) => NLW_inst_int_qplllock_out_UNCONNECTED(1 downto 0),
      int_qplloutclk_out(1 downto 0) => NLW_inst_int_qplloutclk_out_UNCONNECTED(1 downto 0),
      int_qplloutrefclk_out(1 downto 0) => NLW_inst_int_qplloutrefclk_out_UNCONNECTED(1 downto 0),
      int_rxoutclk_out(1 downto 0) => NLW_inst_int_rxoutclk_out_UNCONNECTED(1 downto 0),
      int_userclk1_out => NLW_inst_int_userclk1_out_UNCONNECTED,
      int_userclk2_out => NLW_inst_int_userclk2_out_UNCONNECTED,
      int_usp_qpll0lock_out(0) => NLW_inst_int_usp_qpll0lock_out_UNCONNECTED(0),
      int_usp_qpll0outclk_out(0) => NLW_inst_int_usp_qpll0outclk_out_UNCONNECTED(0),
      int_usp_qpll0outrefclk_out(0) => NLW_inst_int_usp_qpll0outrefclk_out_UNCONNECTED(0),
      int_usp_qpll1lock_out(0) => NLW_inst_int_usp_qpll1lock_out_UNCONNECTED(0),
      int_usp_qpll1outclk_out(0) => NLW_inst_int_usp_qpll1outclk_out_UNCONNECTED(0),
      int_usp_qpll1outrefclk_out(0) => NLW_inst_int_usp_qpll1outrefclk_out_UNCONNECTED(0),
      interrupt_out => NLW_inst_interrupt_out_UNCONNECTED,
      interrupt_out_msi_vec0to31 => NLW_inst_interrupt_out_msi_vec0to31_UNCONNECTED,
      interrupt_out_msi_vec32to63 => NLW_inst_interrupt_out_msi_vec32to63_UNCONNECTED,
      interrupt_out_msix_0 => NLW_inst_interrupt_out_msix_0_UNCONNECTED,
      interrupt_out_msix_1 => NLW_inst_interrupt_out_msix_1_UNCONNECTED,
      interrupt_out_msix_2 => NLW_inst_interrupt_out_msix_2_UNCONNECTED,
      interrupt_out_msix_3 => NLW_inst_interrupt_out_msix_3_UNCONNECTED,
      loopback_us_in(5 downto 0) => NLW_inst_loopback_us_in_UNCONNECTED(5 downto 0),
      loopback_usp_in(5 downto 0) => NLW_inst_loopback_usp_in_UNCONNECTED(5 downto 0),
      m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0),
      m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
      m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
      m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
      m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
      m_axi_arlock => m_axi_arlock,
      m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
      m_axi_arready => m_axi_arready,
      m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
      m_axi_arvalid => m_axi_arvalid,
      m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0),
      m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
      m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
      m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
      m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
      m_axi_awlock => m_axi_awlock,
      m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
      m_axi_awready => m_axi_awready,
      m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
      m_axi_awvalid => m_axi_awvalid,
      m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
      m_axi_bready => m_axi_bready,
      m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
      m_axi_bvalid => m_axi_bvalid,
      m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
      m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
      m_axi_rlast => m_axi_rlast,
      m_axi_rready => m_axi_rready,
      m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
      m_axi_ruser(7 downto 0) => B"00000000",
      m_axi_rvalid => m_axi_rvalid,
      m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
      m_axi_wlast => m_axi_wlast,
      m_axi_wready => m_axi_wready,
      m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
      m_axi_wuser(7 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(7 downto 0),
      m_axi_wvalid => m_axi_wvalid,
      m_axib_araddr(63 downto 0) => m_axib_araddr(63 downto 0),
      m_axib_arburst(1 downto 0) => m_axib_arburst(1 downto 0),
      m_axib_arcache(3 downto 0) => m_axib_arcache(3 downto 0),
      m_axib_arid(3 downto 0) => m_axib_arid(3 downto 0),
      m_axib_arlen(7 downto 0) => m_axib_arlen(7 downto 0),
      m_axib_arlock => NLW_inst_m_axib_arlock_UNCONNECTED,
      m_axib_arprot(2 downto 0) => m_axib_arprot(2 downto 0),
      m_axib_arready => m_axib_arready,
      m_axib_arsize(2 downto 0) => m_axib_arsize(2 downto 0),
      m_axib_aruser(7 downto 0) => NLW_inst_m_axib_aruser_UNCONNECTED(7 downto 0),
      m_axib_arvalid => m_axib_arvalid,
      m_axib_awaddr(63 downto 0) => m_axib_awaddr(63 downto 0),
      m_axib_awburst(1 downto 0) => m_axib_awburst(1 downto 0),
      m_axib_awcache(3 downto 0) => m_axib_awcache(3 downto 0),
      m_axib_awid(3 downto 0) => m_axib_awid(3 downto 0),
      m_axib_awlen(7 downto 0) => m_axib_awlen(7 downto 0),
      m_axib_awlock => NLW_inst_m_axib_awlock_UNCONNECTED,
      m_axib_awprot(2 downto 0) => m_axib_awprot(2 downto 0),
      m_axib_awready => m_axib_awready,
      m_axib_awsize(2 downto 0) => m_axib_awsize(2 downto 0),
      m_axib_awuser(7 downto 0) => NLW_inst_m_axib_awuser_UNCONNECTED(7 downto 0),
      m_axib_awvalid => m_axib_awvalid,
      m_axib_bid(3 downto 0) => m_axib_bid(3 downto 0),
      m_axib_bready => m_axib_bready,
      m_axib_bresp(1 downto 0) => m_axib_bresp(1 downto 0),
      m_axib_bvalid => m_axib_bvalid,
      m_axib_rdata(63 downto 0) => m_axib_rdata(63 downto 0),
      m_axib_rid(3 downto 0) => m_axib_rid(3 downto 0),
      m_axib_rlast => m_axib_rlast,
      m_axib_rready => m_axib_rready,
      m_axib_rresp(1 downto 0) => m_axib_rresp(1 downto 0),
      m_axib_ruser(7 downto 0) => B"00000000",
      m_axib_rvalid => m_axib_rvalid,
      m_axib_wdata(63 downto 0) => m_axib_wdata(63 downto 0),
      m_axib_wlast => m_axib_wlast,
      m_axib_wready => m_axib_wready,
      m_axib_wstrb(7 downto 0) => m_axib_wstrb(7 downto 0),
      m_axib_wuser(7 downto 0) => NLW_inst_m_axib_wuser_UNCONNECTED(7 downto 0),
      m_axib_wvalid => m_axib_wvalid,
      m_axil_araddr(31 downto 0) => NLW_inst_m_axil_araddr_UNCONNECTED(31 downto 0),
      m_axil_arprot(2 downto 0) => NLW_inst_m_axil_arprot_UNCONNECTED(2 downto 0),
      m_axil_arready => '0',
      m_axil_aruser(10 downto 0) => NLW_inst_m_axil_aruser_UNCONNECTED(10 downto 0),
      m_axil_arvalid => NLW_inst_m_axil_arvalid_UNCONNECTED,
      m_axil_awaddr(31 downto 0) => NLW_inst_m_axil_awaddr_UNCONNECTED(31 downto 0),
      m_axil_awprot(2 downto 0) => NLW_inst_m_axil_awprot_UNCONNECTED(2 downto 0),
      m_axil_awready => '0',
      m_axil_awuser(10 downto 0) => NLW_inst_m_axil_awuser_UNCONNECTED(10 downto 0),
      m_axil_awvalid => NLW_inst_m_axil_awvalid_UNCONNECTED,
      m_axil_bready => NLW_inst_m_axil_bready_UNCONNECTED,
      m_axil_bresp(1 downto 0) => B"00",
      m_axil_bvalid => '0',
      m_axil_rdata(31 downto 0) => B"00000000000000000000000000000000",
      m_axil_rready => NLW_inst_m_axil_rready_UNCONNECTED,
      m_axil_rresp(1 downto 0) => B"00",
      m_axil_rvalid => '0',
      m_axil_wdata(31 downto 0) => NLW_inst_m_axil_wdata_UNCONNECTED(31 downto 0),
      m_axil_wready => '0',
      m_axil_wstrb(3 downto 0) => NLW_inst_m_axil_wstrb_UNCONNECTED(3 downto 0),
      m_axil_wvalid => NLW_inst_m_axil_wvalid_UNCONNECTED,
      m_axis_cc_tdata_out(63 downto 0) => NLW_inst_m_axis_cc_tdata_out_UNCONNECTED(63 downto 0),
      m_axis_cc_tkeep_out(1 downto 0) => NLW_inst_m_axis_cc_tkeep_out_UNCONNECTED(1 downto 0),
      m_axis_cc_tlast_out => NLW_inst_m_axis_cc_tlast_out_UNCONNECTED,
      m_axis_cc_tready_out(3 downto 0) => NLW_inst_m_axis_cc_tready_out_UNCONNECTED(3 downto 0),
      m_axis_cc_tuser_out(32 downto 0) => NLW_inst_m_axis_cc_tuser_out_UNCONNECTED(32 downto 0),
      m_axis_cc_tvalid_out => NLW_inst_m_axis_cc_tvalid_out_UNCONNECTED,
      m_axis_cq_tdata_sd(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      m_axis_cq_tkeep_sd(1 downto 0) => B"00",
      m_axis_cq_tlast_sd => '0',
      m_axis_cq_tready_sd => NLW_inst_m_axis_cq_tready_sd_UNCONNECTED,
      m_axis_cq_tuser_sd(84 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axis_cq_tvalid_sd => '0',
      m_axis_h2c_tdata_0(63 downto 0) => NLW_inst_m_axis_h2c_tdata_0_UNCONNECTED(63 downto 0),
      m_axis_h2c_tdata_1(63 downto 0) => NLW_inst_m_axis_h2c_tdata_1_UNCONNECTED(63 downto 0),
      m_axis_h2c_tdata_2(63 downto 0) => NLW_inst_m_axis_h2c_tdata_2_UNCONNECTED(63 downto 0),
      m_axis_h2c_tdata_3(63 downto 0) => NLW_inst_m_axis_h2c_tdata_3_UNCONNECTED(63 downto 0),
      m_axis_h2c_tkeep_0(7 downto 0) => NLW_inst_m_axis_h2c_tkeep_0_UNCONNECTED(7 downto 0),
      m_axis_h2c_tkeep_1(7 downto 0) => NLW_inst_m_axis_h2c_tkeep_1_UNCONNECTED(7 downto 0),
      m_axis_h2c_tkeep_2(7 downto 0) => NLW_inst_m_axis_h2c_tkeep_2_UNCONNECTED(7 downto 0),
      m_axis_h2c_tkeep_3(7 downto 0) => NLW_inst_m_axis_h2c_tkeep_3_UNCONNECTED(7 downto 0),
      m_axis_h2c_tlast_0 => NLW_inst_m_axis_h2c_tlast_0_UNCONNECTED,
      m_axis_h2c_tlast_1 => NLW_inst_m_axis_h2c_tlast_1_UNCONNECTED,
      m_axis_h2c_tlast_2 => NLW_inst_m_axis_h2c_tlast_2_UNCONNECTED,
      m_axis_h2c_tlast_3 => NLW_inst_m_axis_h2c_tlast_3_UNCONNECTED,
      m_axis_h2c_tready_0 => '0',
      m_axis_h2c_tready_1 => '0',
      m_axis_h2c_tready_2 => '0',
      m_axis_h2c_tready_3 => '0',
      m_axis_h2c_tuser_0(7 downto 0) => NLW_inst_m_axis_h2c_tuser_0_UNCONNECTED(7 downto 0),
      m_axis_h2c_tuser_1(7 downto 0) => NLW_inst_m_axis_h2c_tuser_1_UNCONNECTED(7 downto 0),
      m_axis_h2c_tuser_2(7 downto 0) => NLW_inst_m_axis_h2c_tuser_2_UNCONNECTED(7 downto 0),
      m_axis_h2c_tuser_3(7 downto 0) => NLW_inst_m_axis_h2c_tuser_3_UNCONNECTED(7 downto 0),
      m_axis_h2c_tvalid_0 => NLW_inst_m_axis_h2c_tvalid_0_UNCONNECTED,
      m_axis_h2c_tvalid_1 => NLW_inst_m_axis_h2c_tvalid_1_UNCONNECTED,
      m_axis_h2c_tvalid_2 => NLW_inst_m_axis_h2c_tvalid_2_UNCONNECTED,
      m_axis_h2c_tvalid_3 => NLW_inst_m_axis_h2c_tvalid_3_UNCONNECTED,
      m_axis_rc_tdata_sd(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      m_axis_rc_tkeep_sd(1 downto 0) => B"00",
      m_axis_rc_tlast_sd => '0',
      m_axis_rc_tready_sd => NLW_inst_m_axis_rc_tready_sd_UNCONNECTED,
      m_axis_rc_tuser_sd(74 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000",
      m_axis_rc_tvalid_sd => '0',
      m_axis_rq_tdata_out(63 downto 0) => NLW_inst_m_axis_rq_tdata_out_UNCONNECTED(63 downto 0),
      m_axis_rq_tkeep_out(1 downto 0) => NLW_inst_m_axis_rq_tkeep_out_UNCONNECTED(1 downto 0),
      m_axis_rq_tlast_out => NLW_inst_m_axis_rq_tlast_out_UNCONNECTED,
      m_axis_rq_tready_out(3 downto 0) => NLW_inst_m_axis_rq_tready_out_UNCONNECTED(3 downto 0),
      m_axis_rq_tuser_out(59 downto 0) => NLW_inst_m_axis_rq_tuser_out_UNCONNECTED(59 downto 0),
      m_axis_rq_tvalid_out => NLW_inst_m_axis_rq_tvalid_out_UNCONNECTED,
      m_axis_rx_tdata_o(63 downto 0) => m_axis_rx_tdata_o(63 downto 0),
      m_axis_rx_tkeep_o(7 downto 4) => \^m_axis_rx_tkeep_o\(7 downto 4),
      m_axis_rx_tkeep_o(3 downto 0) => NLW_inst_m_axis_rx_tkeep_o_UNCONNECTED(3 downto 0),
      m_axis_rx_tlast_o => m_axis_rx_tlast_o,
      m_axis_rx_tuser_o(21) => \^m_axis_rx_tuser_o\(21),
      m_axis_rx_tuser_o(20) => NLW_inst_m_axis_rx_tuser_o_UNCONNECTED(20),
      m_axis_rx_tuser_o(19 downto 17) => \^m_axis_rx_tuser_o\(19 downto 17),
      m_axis_rx_tuser_o(16 downto 15) => NLW_inst_m_axis_rx_tuser_o_UNCONNECTED(16 downto 15),
      m_axis_rx_tuser_o(14) => \^m_axis_rx_tuser_o\(14),
      m_axis_rx_tuser_o(13 downto 9) => NLW_inst_m_axis_rx_tuser_o_UNCONNECTED(13 downto 9),
      m_axis_rx_tuser_o(8 downto 0) => \^m_axis_rx_tuser_o\(8 downto 0),
      m_axis_rx_tvalid_o => m_axis_rx_tvalid_o,
      mcap_design_switch => NLW_inst_mcap_design_switch_UNCONNECTED,
      mcap_eos_in => '0',
      msi_enable => msi_enable,
      msi_vector_width(2 downto 0) => msi_vector_width(2 downto 0),
      msix_enable => NLW_inst_msix_enable_UNCONNECTED,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pcie4_cxs0_active_ack_rx_sd => NLW_inst_pcie4_cxs0_active_ack_rx_sd_UNCONNECTED,
      pcie4_cxs0_active_ack_tx_sd => '0',
      pcie4_cxs0_active_req_rx_sd => '0',
      pcie4_cxs0_active_req_tx_sd => NLW_inst_pcie4_cxs0_active_req_tx_sd_UNCONNECTED,
      pcie4_cxs0_cntl_chk_rx_sd => '0',
      pcie4_cxs0_cntl_chk_tx_sd => NLW_inst_pcie4_cxs0_cntl_chk_tx_sd_UNCONNECTED,
      pcie4_cxs0_cntl_rx_sd(13 downto 0) => B"00000000000000",
      pcie4_cxs0_cntl_tx_sd(13 downto 0) => NLW_inst_pcie4_cxs0_cntl_tx_sd_UNCONNECTED(13 downto 0),
      pcie4_cxs0_crdgnt_chk_rx_sd => NLW_inst_pcie4_cxs0_crdgnt_chk_rx_sd_UNCONNECTED,
      pcie4_cxs0_crdgnt_chk_tx_sd => '0',
      pcie4_cxs0_crdgnt_rx_sd => NLW_inst_pcie4_cxs0_crdgnt_rx_sd_UNCONNECTED,
      pcie4_cxs0_crdgnt_tx_sd => '0',
      pcie4_cxs0_crdrtn_chk_rx_sd => '0',
      pcie4_cxs0_crdrtn_chk_tx_sd => NLW_inst_pcie4_cxs0_crdrtn_chk_tx_sd_UNCONNECTED,
      pcie4_cxs0_crdrtn_rx_sd => '0',
      pcie4_cxs0_crdrtn_tx_sd => NLW_inst_pcie4_cxs0_crdrtn_tx_sd_UNCONNECTED,
      pcie4_cxs0_data_chk_rx_sd(31 downto 0) => B"00000000000000000000000000000000",
      pcie4_cxs0_data_chk_tx_sd(31 downto 0) => NLW_inst_pcie4_cxs0_data_chk_tx_sd_UNCONNECTED(31 downto 0),
      pcie4_cxs0_data_rx_sd(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pcie4_cxs0_data_tx_sd(255 downto 0) => NLW_inst_pcie4_cxs0_data_tx_sd_UNCONNECTED(255 downto 0),
      pcie4_cxs0_deact_hint_rx_sd => NLW_inst_pcie4_cxs0_deact_hint_rx_sd_UNCONNECTED,
      pcie4_cxs0_deact_hint_tx_sd => '0',
      pcie4_cxs0_valid_chk_rx_sd => '0',
      pcie4_cxs0_valid_chk_tx_sd => NLW_inst_pcie4_cxs0_valid_chk_tx_sd_UNCONNECTED,
      pcie4_cxs0_valid_rx_sd => '0',
      pcie4_cxs0_valid_tx_sd => NLW_inst_pcie4_cxs0_valid_tx_sd_UNCONNECTED,
      pcie_cq_np_req_count_sd(5 downto 0) => B"000000",
      pcie_cq_np_req_sd(1 downto 0) => NLW_inst_pcie_cq_np_req_sd_UNCONNECTED(1 downto 0),
      pcie_rq_seq_num0_sd(5 downto 0) => B"000000",
      pcie_rq_seq_num1_sd(5 downto 0) => B"000000",
      pcie_rq_seq_num_vld0_sd => '0',
      pcie_rq_seq_num_vld1_sd => '0',
      pcie_tfc_npd_av_sd(3 downto 0) => B"0000",
      pcie_tfc_nph_av_sd(3 downto 0) => B"0000",
      pcieeqrxeqadaptdone_us_in(1 downto 0) => NLW_inst_pcieeqrxeqadaptdone_us_in_UNCONNECTED(1 downto 0),
      pcieeqrxeqadaptdone_usp_in(1 downto 0) => NLW_inst_pcieeqrxeqadaptdone_usp_in_UNCONNECTED(1 downto 0),
      pcierategen3_us_out(1 downto 0) => B"00",
      pcierategen3_usp_out(1 downto 0) => B"00",
      pcierateidle_us_out(1 downto 0) => B"00",
      pcierateidle_usp_out(1 downto 0) => B"00",
      pcierateqpll0_usp_in(2 downto 0) => NLW_inst_pcierateqpll0_usp_in_UNCONNECTED(2 downto 0),
      pcierateqpll1_usp_in(2 downto 0) => NLW_inst_pcierateqpll1_usp_in_UNCONNECTED(2 downto 0),
      pcierateqpllpd_us_out(3 downto 0) => B"0000",
      pcierateqpllpd_usp_out(3 downto 0) => B"0000",
      pcierateqpllreset_us_out(3 downto 0) => B"0000",
      pcierateqpllreset_usp_out(3 downto 0) => B"0000",
      pcierstidle_us_in(1 downto 0) => NLW_inst_pcierstidle_us_in_UNCONNECTED(1 downto 0),
      pcierstidle_usp_in(1 downto 0) => NLW_inst_pcierstidle_usp_in_UNCONNECTED(1 downto 0),
      pciersttxsyncstart_us_in(1 downto 0) => NLW_inst_pciersttxsyncstart_us_in_UNCONNECTED(1 downto 0),
      pciersttxsyncstart_usp_in(1 downto 0) => NLW_inst_pciersttxsyncstart_usp_in_UNCONNECTED(1 downto 0),
      pciesynctxsyncdone_us_out(1 downto 0) => B"00",
      pciesynctxsyncdone_usp_out(1 downto 0) => B"00",
      pcieusergen3rdy_us_out(1 downto 0) => B"00",
      pcieusergen3rdy_usp_out(1 downto 0) => B"00",
      pcieuserphystatusrst_us_out(1 downto 0) => B"00",
      pcieuserphystatusrst_usp_out(1 downto 0) => B"00",
      pcieuserratedone_us_in(1 downto 0) => NLW_inst_pcieuserratedone_us_in_UNCONNECTED(1 downto 0),
      pcieuserratedone_usp_in(1 downto 0) => NLW_inst_pcieuserratedone_usp_in_UNCONNECTED(1 downto 0),
      pcieuserratestart_us_out(1 downto 0) => B"00",
      pcieuserratestart_usp_out(1 downto 0) => B"00",
      pcsrsvdin_us_in(31 downto 0) => NLW_inst_pcsrsvdin_us_in_UNCONNECTED(31 downto 0),
      pcsrsvdout_us_out(23 downto 0) => B"000000000000000000000000",
      phy_prst_n => NLW_inst_phy_prst_n_UNCONNECTED,
      phy_rdy_out_sd => '0',
      phy_rrst_n => NLW_inst_phy_rrst_n_UNCONNECTED,
      phy_rst_fsm(3 downto 0) => NLW_inst_phy_rst_fsm_UNCONNECTED(3 downto 0),
      phy_rst_idle => NLW_inst_phy_rst_idle_UNCONNECTED,
      phy_rxeq_fsm(5 downto 0) => NLW_inst_phy_rxeq_fsm_UNCONNECTED(5 downto 0),
      phy_txeq_ctrl(3 downto 0) => NLW_inst_phy_txeq_ctrl_UNCONNECTED(3 downto 0),
      phy_txeq_fsm(5 downto 0) => NLW_inst_phy_txeq_fsm_UNCONNECTED(5 downto 0),
      phy_txeq_preset(7 downto 0) => NLW_inst_phy_txeq_preset_UNCONNECTED(7 downto 0),
      phystatus_us_out(1 downto 0) => B"00",
      phystatus_usp_out(1 downto 0) => B"00",
      pipe_clk => NLW_inst_pipe_clk_UNCONNECTED,
      pipe_cpll_lock(1 downto 0) => NLW_inst_pipe_cpll_lock_UNCONNECTED(1 downto 0),
      pipe_dclk_in => '0',
      pipe_debug(31 downto 0) => NLW_inst_pipe_debug_UNCONNECTED(31 downto 0),
      pipe_debug_0(1 downto 0) => NLW_inst_pipe_debug_0_UNCONNECTED(1 downto 0),
      pipe_debug_1(1 downto 0) => NLW_inst_pipe_debug_1_UNCONNECTED(1 downto 0),
      pipe_debug_2(1 downto 0) => NLW_inst_pipe_debug_2_UNCONNECTED(1 downto 0),
      pipe_debug_3(1 downto 0) => NLW_inst_pipe_debug_3_UNCONNECTED(1 downto 0),
      pipe_debug_4(1 downto 0) => NLW_inst_pipe_debug_4_UNCONNECTED(1 downto 0),
      pipe_debug_5(1 downto 0) => NLW_inst_pipe_debug_5_UNCONNECTED(1 downto 0),
      pipe_debug_6(1 downto 0) => NLW_inst_pipe_debug_6_UNCONNECTED(1 downto 0),
      pipe_debug_7(1 downto 0) => NLW_inst_pipe_debug_7_UNCONNECTED(1 downto 0),
      pipe_debug_8(1 downto 0) => NLW_inst_pipe_debug_8_UNCONNECTED(1 downto 0),
      pipe_debug_9(1 downto 0) => NLW_inst_pipe_debug_9_UNCONNECTED(1 downto 0),
      pipe_debug_ctl_in_rx0(31 downto 0) => B"00000000000000000000000000000000",
      pipe_debug_ctl_in_rx1(31 downto 0) => B"00000000000000000000000000000000",
      pipe_debug_ctl_in_tx0(31 downto 0) => B"00000000000000000000000000000000",
      pipe_debug_ctl_in_tx1(31 downto 0) => B"00000000000000000000000000000000",
      pipe_debug_ctl_vec4(3 downto 0) => B"0000",
      pipe_debug_debug_out_128_0(127 downto 0) => NLW_inst_pipe_debug_debug_out_128_0_UNCONNECTED(127 downto 0),
      pipe_debug_debug_out_128_1(127 downto 0) => NLW_inst_pipe_debug_debug_out_128_1_UNCONNECTED(127 downto 0),
      pipe_debug_debug_out_128_2(127 downto 0) => NLW_inst_pipe_debug_debug_out_128_2_UNCONNECTED(127 downto 0),
      pipe_debug_debug_out_128_3(127 downto 0) => NLW_inst_pipe_debug_debug_out_128_3_UNCONNECTED(127 downto 0),
      pipe_debug_debug_out_ext_16_0(15 downto 0) => NLW_inst_pipe_debug_debug_out_ext_16_0_UNCONNECTED(15 downto 0),
      pipe_debug_debug_out_ext_16_1(15 downto 0) => NLW_inst_pipe_debug_debug_out_ext_16_1_UNCONNECTED(15 downto 0),
      pipe_debug_debug_out_ext_16_2(15 downto 0) => NLW_inst_pipe_debug_debug_out_ext_16_2_UNCONNECTED(15 downto 0),
      pipe_debug_debug_out_ext_16_3(15 downto 0) => NLW_inst_pipe_debug_debug_out_ext_16_3_UNCONNECTED(15 downto 0),
      pipe_debug_inject_rx_status(7 downto 0) => NLW_inst_pipe_debug_inject_rx_status_UNCONNECTED(7 downto 0),
      pipe_debug_inject_tx_status(7 downto 0) => NLW_inst_pipe_debug_inject_tx_status_UNCONNECTED(7 downto 0),
      pipe_debug_ltssm_pol_act => '0',
      pipe_debug_ltssm_rec_spd_1 => '0',
      pipe_debug_mux_ctl(31 downto 0) => B"00000000000000000000000000000000",
      pipe_dmonitorout(29 downto 0) => NLW_inst_pipe_dmonitorout_UNCONNECTED(29 downto 0),
      pipe_drp_fsm(13 downto 0) => NLW_inst_pipe_drp_fsm_UNCONNECTED(13 downto 0),
      pipe_eyescandataerror(1 downto 0) => NLW_inst_pipe_eyescandataerror_UNCONNECTED(1 downto 0),
      pipe_gen3_out => NLW_inst_pipe_gen3_out_UNCONNECTED,
      pipe_loopback(2 downto 0) => B"000",
      pipe_mmcm_lock_in => '1',
      pipe_mmcm_rst_n => '1',
      pipe_oobclk_in => '0',
      pipe_pclk_in => '0',
      pipe_pclk_sel_out(1 downto 0) => NLW_inst_pipe_pclk_sel_out_UNCONNECTED(1 downto 0),
      pipe_qpll_lock(0) => NLW_inst_pipe_qpll_lock_UNCONNECTED(0),
      pipe_qrst_fsm(11 downto 0) => NLW_inst_pipe_qrst_fsm_UNCONNECTED(11 downto 0),
      pipe_qrst_idle => NLW_inst_pipe_qrst_idle_UNCONNECTED,
      pipe_rate_fsm(9 downto 0) => NLW_inst_pipe_rate_fsm_UNCONNECTED(9 downto 0),
      pipe_rate_idle => NLW_inst_pipe_rate_idle_UNCONNECTED,
      pipe_rst_fsm(4 downto 0) => NLW_inst_pipe_rst_fsm_UNCONNECTED(4 downto 0),
      pipe_rst_idle => NLW_inst_pipe_rst_idle_UNCONNECTED,
      pipe_rx_0_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_10_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_11_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_12_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_13_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_14_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_15_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_1_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_2_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_3_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_4_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_5_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_6_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_7_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_8_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rx_9_sigs(83 downto 0) => B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      pipe_rxbufstatus(5 downto 0) => NLW_inst_pipe_rxbufstatus_UNCONNECTED(5 downto 0),
      pipe_rxcommadet(1 downto 0) => NLW_inst_pipe_rxcommadet_UNCONNECTED(1 downto 0),
      pipe_rxdisperr(15 downto 0) => NLW_inst_pipe_rxdisperr_UNCONNECTED(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => NLW_inst_pipe_rxdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_rxnotintable(15 downto 0) => NLW_inst_pipe_rxnotintable_UNCONNECTED(15 downto 0),
      pipe_rxoutclk_in(1 downto 0) => B"00",
      pipe_rxoutclk_out(1 downto 0) => NLW_inst_pipe_rxoutclk_out_UNCONNECTED(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => NLW_inst_pipe_rxphaligndone_UNCONNECTED(1 downto 0),
      pipe_rxpmaresetdone(1 downto 0) => NLW_inst_pipe_rxpmaresetdone_UNCONNECTED(1 downto 0),
      pipe_rxprbscntreset => '0',
      pipe_rxprbserr(1 downto 0) => NLW_inst_pipe_rxprbserr_UNCONNECTED(1 downto 0),
      pipe_rxprbssel(2 downto 0) => B"000",
      pipe_rxstatus(5 downto 0) => NLW_inst_pipe_rxstatus_UNCONNECTED(5 downto 0),
      pipe_rxsyncdone(1 downto 0) => NLW_inst_pipe_rxsyncdone_UNCONNECTED(1 downto 0),
      pipe_rxusrclk_in => '0',
      pipe_sync_fsm_rx(13 downto 0) => NLW_inst_pipe_sync_fsm_rx_UNCONNECTED(13 downto 0),
      pipe_sync_fsm_tx(11 downto 0) => NLW_inst_pipe_sync_fsm_tx_UNCONNECTED(11 downto 0),
      pipe_tx0_powerdown(1 downto 0) => NLW_inst_pipe_tx0_powerdown_UNCONNECTED(1 downto 0),
      pipe_tx0_rcvr_det => NLW_inst_pipe_tx0_rcvr_det_UNCONNECTED,
      pipe_tx_0_sigs(83 downto 0) => NLW_inst_pipe_tx_0_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_10_sigs(83 downto 0) => NLW_inst_pipe_tx_10_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_11_sigs(83 downto 0) => NLW_inst_pipe_tx_11_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_12_sigs(83 downto 0) => NLW_inst_pipe_tx_12_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_13_sigs(83 downto 0) => NLW_inst_pipe_tx_13_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_14_sigs(83 downto 0) => NLW_inst_pipe_tx_14_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_15_sigs(83 downto 0) => NLW_inst_pipe_tx_15_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_1_sigs(83 downto 0) => NLW_inst_pipe_tx_1_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_2_sigs(83 downto 0) => NLW_inst_pipe_tx_2_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_3_sigs(83 downto 0) => NLW_inst_pipe_tx_3_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_4_sigs(83 downto 0) => NLW_inst_pipe_tx_4_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_5_sigs(83 downto 0) => NLW_inst_pipe_tx_5_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_6_sigs(83 downto 0) => NLW_inst_pipe_tx_6_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_7_sigs(83 downto 0) => NLW_inst_pipe_tx_7_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_8_sigs(83 downto 0) => NLW_inst_pipe_tx_8_sigs_UNCONNECTED(83 downto 0),
      pipe_tx_9_sigs(83 downto 0) => NLW_inst_pipe_tx_9_sigs_UNCONNECTED(83 downto 0),
      pipe_txdlysresetdone(1 downto 0) => NLW_inst_pipe_txdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_txinhibit(1 downto 0) => B"00",
      pipe_txoutclk_out => NLW_inst_pipe_txoutclk_out_UNCONNECTED,
      pipe_txphaligndone(1 downto 0) => NLW_inst_pipe_txphaligndone_UNCONNECTED(1 downto 0),
      pipe_txphinitdone(1 downto 0) => NLW_inst_pipe_txphinitdone_UNCONNECTED(1 downto 0),
      pipe_txprbsforceerr => '0',
      pipe_txprbssel(2 downto 0) => B"000",
      pipe_userclk1_in => '0',
      pipe_userclk2_in => '0',
      qpll0clk_us_in(1 downto 0) => NLW_inst_qpll0clk_us_in_UNCONNECTED(1 downto 0),
      qpll0freqlock_usp_in(1 downto 0) => NLW_inst_qpll0freqlock_usp_in_UNCONNECTED(1 downto 0),
      qpll0lock_usp_out(0) => '0',
      qpll0outclk_usp_out(0) => '0',
      qpll0outrefclk_usp_out(0) => '0',
      qpll0pd_usp_in(0) => NLW_inst_qpll0pd_usp_in_UNCONNECTED(0),
      qpll0refclk_us_in(1 downto 0) => NLW_inst_qpll0refclk_us_in_UNCONNECTED(1 downto 0),
      qpll0reset_usp_in(0) => NLW_inst_qpll0reset_usp_in_UNCONNECTED(0),
      qpll1clk_us_in(1 downto 0) => NLW_inst_qpll1clk_us_in_UNCONNECTED(1 downto 0),
      qpll1freqlock_usp_in(1 downto 0) => NLW_inst_qpll1freqlock_usp_in_UNCONNECTED(1 downto 0),
      qpll1lock_us_out(0) => '0',
      qpll1lock_usp_out(0) => '0',
      qpll1outclk_us_out(0) => '0',
      qpll1outclk_usp_out(0) => '0',
      qpll1outrefclk_us_out(0) => '0',
      qpll1outrefclk_usp_out(0) => '0',
      qpll1pd_us_in(0) => NLW_inst_qpll1pd_us_in_UNCONNECTED(0),
      qpll1pd_usp_in(0) => NLW_inst_qpll1pd_usp_in_UNCONNECTED(0),
      qpll1refclk_us_in(1 downto 0) => NLW_inst_qpll1refclk_us_in_UNCONNECTED(1 downto 0),
      qpll1reset_us_in(0) => NLW_inst_qpll1reset_us_in_UNCONNECTED(0),
      qpll1reset_usp_in(0) => NLW_inst_qpll1reset_usp_in_UNCONNECTED(0),
      qpll_drp_clk => NLW_inst_qpll_drp_clk_UNCONNECTED,
      qpll_drp_crscode(11 downto 0) => B"000000000000",
      qpll_drp_done(1 downto 0) => B"00",
      qpll_drp_fsm(17 downto 0) => B"000000000000000000",
      qpll_drp_gen3 => NLW_inst_qpll_drp_gen3_UNCONNECTED,
      qpll_drp_ovrd => NLW_inst_qpll_drp_ovrd_UNCONNECTED,
      qpll_drp_reset(1 downto 0) => B"00",
      qpll_drp_rst_n => NLW_inst_qpll_drp_rst_n_UNCONNECTED,
      qpll_drp_start => NLW_inst_qpll_drp_start_UNCONNECTED,
      qpll_qplld => NLW_inst_qpll_qplld_UNCONNECTED,
      qpll_qplllock(1 downto 0) => B"00",
      qpll_qplloutclk(1 downto 0) => B"00",
      qpll_qplloutrefclk(1 downto 0) => B"00",
      qpll_qpllreset(1 downto 0) => NLW_inst_qpll_qpllreset_UNCONNECTED(1 downto 0),
      qpllrsvd2_us_in(4 downto 0) => NLW_inst_qpllrsvd2_us_in_UNCONNECTED(4 downto 0),
      qpllrsvd3_us_in(4 downto 0) => NLW_inst_qpllrsvd3_us_in_UNCONNECTED(4 downto 0),
      rbar_bar_size_sd(5 downto 0) => B"000000",
      rbar_function_number_sd(7 downto 0) => B"00000000",
      rbar_write_enable_bar0_sd => '0',
      rbar_write_enable_bar1_sd => '0',
      rbar_write_enable_bar2_sd => '0',
      rbar_write_enable_bar3_sd => '0',
      rbar_write_enable_bar4_sd => '0',
      rbar_write_enable_bar5_sd => '0',
      rcalenb_usp_in(0) => NLW_inst_rcalenb_usp_in_UNCONNECTED(0),
      rd_interrupt => NLW_inst_rd_interrupt_UNCONNECTED,
      resetovrd_usp_in(1 downto 0) => NLW_inst_resetovrd_usp_in_UNCONNECTED(1 downto 0),
      rx8b10ben_us_in(1 downto 0) => NLW_inst_rx8b10ben_us_in_UNCONNECTED(1 downto 0),
      rx8b10ben_usp_in(1 downto 0) => NLW_inst_rx8b10ben_usp_in_UNCONNECTED(1 downto 0),
      rxbufreset_us_in(1 downto 0) => NLW_inst_rxbufreset_us_in_UNCONNECTED(1 downto 0),
      rxbufreset_usp_in(1 downto 0) => NLW_inst_rxbufreset_usp_in_UNCONNECTED(1 downto 0),
      rxbufstatus_us_out(5 downto 0) => B"000000",
      rxbufstatus_usp_out(5 downto 0) => B"000000",
      rxbyteisaligned_us_out(1 downto 0) => B"00",
      rxbyteisaligned_usp_out(1 downto 0) => B"00",
      rxbyterealign_us_out(1 downto 0) => B"00",
      rxbyterealign_usp_out(1 downto 0) => B"00",
      rxcdrfreqreset_usp_in(1 downto 0) => NLW_inst_rxcdrfreqreset_usp_in_UNCONNECTED(1 downto 0),
      rxcdrhold_us_in(1 downto 0) => NLW_inst_rxcdrhold_us_in_UNCONNECTED(1 downto 0),
      rxcdrhold_usp_in(1 downto 0) => NLW_inst_rxcdrhold_usp_in_UNCONNECTED(1 downto 0),
      rxcdrlock_us_out(1 downto 0) => B"00",
      rxcdrlock_usp_out(1 downto 0) => B"00",
      rxcdrreset_usp_in(1 downto 0) => NLW_inst_rxcdrreset_usp_in_UNCONNECTED(1 downto 0),
      rxclkcorcnt_us_out(3 downto 0) => B"0000",
      rxclkcorcnt_usp_out(3 downto 0) => B"0000",
      rxcommadet_us_out(1 downto 0) => B"00",
      rxcommadet_usp_out(1 downto 0) => B"00",
      rxcommadeten_us_in(1 downto 0) => NLW_inst_rxcommadeten_us_in_UNCONNECTED(1 downto 0),
      rxcommadeten_usp_in(1 downto 0) => NLW_inst_rxcommadeten_usp_in_UNCONNECTED(1 downto 0),
      rxctrl0_us_out(31 downto 0) => B"00000000000000000000000000000000",
      rxctrl0_usp_out(31 downto 0) => B"00000000000000000000000000000000",
      rxctrl1_us_out(31 downto 0) => B"00000000000000000000000000000000",
      rxctrl1_usp_out(31 downto 0) => B"00000000000000000000000000000000",
      rxctrl2_us_out(15 downto 0) => B"0000000000000000",
      rxctrl2_usp_out(15 downto 0) => B"0000000000000000",
      rxctrl3_us_out(15 downto 0) => B"0000000000000000",
      rxctrl3_usp_out(15 downto 0) => B"0000000000000000",
      rxdata_us_out(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      rxdata_usp_out(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      rxdfeagchold_us_in(1 downto 0) => NLW_inst_rxdfeagchold_us_in_UNCONNECTED(1 downto 0),
      rxdfeagchold_usp_in(1 downto 0) => NLW_inst_rxdfeagchold_usp_in_UNCONNECTED(1 downto 0),
      rxdfecfokhold_us_in(1 downto 0) => NLW_inst_rxdfecfokhold_us_in_UNCONNECTED(1 downto 0),
      rxdfecfokhold_usp_in(1 downto 0) => NLW_inst_rxdfecfokhold_usp_in_UNCONNECTED(1 downto 0),
      rxdfekhhold_us_in(1 downto 0) => NLW_inst_rxdfekhhold_us_in_UNCONNECTED(1 downto 0),
      rxdfekhhold_usp_in(1 downto 0) => NLW_inst_rxdfekhhold_usp_in_UNCONNECTED(1 downto 0),
      rxdfelfhold_us_in(1 downto 0) => NLW_inst_rxdfelfhold_us_in_UNCONNECTED(1 downto 0),
      rxdfelfhold_usp_in(1 downto 0) => NLW_inst_rxdfelfhold_usp_in_UNCONNECTED(1 downto 0),
      rxdfelpmreset_usp_in(1 downto 0) => NLW_inst_rxdfelpmreset_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap10hold_us_in(1 downto 0) => NLW_inst_rxdfetap10hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap10hold_usp_in(1 downto 0) => NLW_inst_rxdfetap10hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap11hold_us_in(1 downto 0) => NLW_inst_rxdfetap11hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap11hold_usp_in(1 downto 0) => NLW_inst_rxdfetap11hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap12hold_us_in(1 downto 0) => NLW_inst_rxdfetap12hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap12hold_usp_in(1 downto 0) => NLW_inst_rxdfetap12hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap13hold_us_in(1 downto 0) => NLW_inst_rxdfetap13hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap13hold_usp_in(1 downto 0) => NLW_inst_rxdfetap13hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap14hold_us_in(1 downto 0) => NLW_inst_rxdfetap14hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap14hold_usp_in(1 downto 0) => NLW_inst_rxdfetap14hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap15hold_us_in(1 downto 0) => NLW_inst_rxdfetap15hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap15hold_usp_in(1 downto 0) => NLW_inst_rxdfetap15hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap2hold_us_in(1 downto 0) => NLW_inst_rxdfetap2hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap2hold_usp_in(1 downto 0) => NLW_inst_rxdfetap2hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap3hold_us_in(1 downto 0) => NLW_inst_rxdfetap3hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap3hold_usp_in(1 downto 0) => NLW_inst_rxdfetap3hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap4hold_us_in(1 downto 0) => NLW_inst_rxdfetap4hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap4hold_usp_in(1 downto 0) => NLW_inst_rxdfetap4hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap5hold_us_in(1 downto 0) => NLW_inst_rxdfetap5hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap5hold_usp_in(1 downto 0) => NLW_inst_rxdfetap5hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap6hold_us_in(1 downto 0) => NLW_inst_rxdfetap6hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap6hold_usp_in(1 downto 0) => NLW_inst_rxdfetap6hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap7hold_us_in(1 downto 0) => NLW_inst_rxdfetap7hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap7hold_usp_in(1 downto 0) => NLW_inst_rxdfetap7hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap8hold_us_in(1 downto 0) => NLW_inst_rxdfetap8hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap8hold_usp_in(1 downto 0) => NLW_inst_rxdfetap8hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfetap9hold_us_in(1 downto 0) => NLW_inst_rxdfetap9hold_us_in_UNCONNECTED(1 downto 0),
      rxdfetap9hold_usp_in(1 downto 0) => NLW_inst_rxdfetap9hold_usp_in_UNCONNECTED(1 downto 0),
      rxdfeuthold_us_in(1 downto 0) => NLW_inst_rxdfeuthold_us_in_UNCONNECTED(1 downto 0),
      rxdfeuthold_usp_in(1 downto 0) => NLW_inst_rxdfeuthold_usp_in_UNCONNECTED(1 downto 0),
      rxdfevphold_us_in(1 downto 0) => NLW_inst_rxdfevphold_us_in_UNCONNECTED(1 downto 0),
      rxdfevphold_usp_in(1 downto 0) => NLW_inst_rxdfevphold_usp_in_UNCONNECTED(1 downto 0),
      rxdlysresetdone_us_out(1 downto 0) => B"00",
      rxdlysresetdone_usp_out(1 downto 0) => B"00",
      rxelecidle_us_out(1 downto 0) => B"00",
      rxelecidle_usp_out(1 downto 0) => B"00",
      rxlpmen_us_in(1 downto 0) => NLW_inst_rxlpmen_us_in_UNCONNECTED(1 downto 0),
      rxlpmen_usp_in(1 downto 0) => NLW_inst_rxlpmen_usp_in_UNCONNECTED(1 downto 0),
      rxlpmgchold_us_in(1 downto 0) => NLW_inst_rxlpmgchold_us_in_UNCONNECTED(1 downto 0),
      rxlpmgchold_usp_in(1 downto 0) => NLW_inst_rxlpmgchold_usp_in_UNCONNECTED(1 downto 0),
      rxlpmhfhold_us_in(1 downto 0) => NLW_inst_rxlpmhfhold_us_in_UNCONNECTED(1 downto 0),
      rxlpmhfhold_usp_in(1 downto 0) => NLW_inst_rxlpmhfhold_usp_in_UNCONNECTED(1 downto 0),
      rxlpmlfhold_us_in(1 downto 0) => NLW_inst_rxlpmlfhold_us_in_UNCONNECTED(1 downto 0),
      rxlpmlfhold_usp_in(1 downto 0) => NLW_inst_rxlpmlfhold_usp_in_UNCONNECTED(1 downto 0),
      rxlpmoshold_us_in(1 downto 0) => NLW_inst_rxlpmoshold_us_in_UNCONNECTED(1 downto 0),
      rxlpmoshold_usp_in(1 downto 0) => NLW_inst_rxlpmoshold_usp_in_UNCONNECTED(1 downto 0),
      rxmcommaalignen_us_in(1 downto 0) => NLW_inst_rxmcommaalignen_us_in_UNCONNECTED(1 downto 0),
      rxmcommaalignen_usp_in(1 downto 0) => NLW_inst_rxmcommaalignen_usp_in_UNCONNECTED(1 downto 0),
      rxoshold_us_in(1 downto 0) => NLW_inst_rxoshold_us_in_UNCONNECTED(1 downto 0),
      rxoshold_usp_in(1 downto 0) => NLW_inst_rxoshold_usp_in_UNCONNECTED(1 downto 0),
      rxoutclk_us_out(1 downto 0) => B"00",
      rxoutclk_usp_out(1 downto 0) => B"00",
      rxoutclkfabric_usp_out(1 downto 0) => B"00",
      rxoutclkpcs_usp_out(1 downto 0) => B"00",
      rxpcommaalignen_us_in(1 downto 0) => NLW_inst_rxpcommaalignen_us_in_UNCONNECTED(1 downto 0),
      rxpcommaalignen_usp_in(1 downto 0) => NLW_inst_rxpcommaalignen_usp_in_UNCONNECTED(1 downto 0),
      rxpcsreset_usp_in(1 downto 0) => NLW_inst_rxpcsreset_usp_in_UNCONNECTED(1 downto 0),
      rxpd_us_in(3 downto 0) => NLW_inst_rxpd_us_in_UNCONNECTED(3 downto 0),
      rxpd_usp_in(3 downto 0) => NLW_inst_rxpd_usp_in_UNCONNECTED(3 downto 0),
      rxphaligndone_us_out(1 downto 0) => B"00",
      rxphaligndone_usp_out(1 downto 0) => B"00",
      rxpmareset_usp_in(1 downto 0) => NLW_inst_rxpmareset_usp_in_UNCONNECTED(1 downto 0),
      rxpmaresetdone_us_out(1 downto 0) => B"00",
      rxpmaresetdone_usp_out(1 downto 0) => B"00",
      rxpolarity_us_in(1 downto 0) => NLW_inst_rxpolarity_us_in_UNCONNECTED(1 downto 0),
      rxpolarity_usp_in(1 downto 0) => NLW_inst_rxpolarity_usp_in_UNCONNECTED(1 downto 0),
      rxprbscntreset_us_in(1 downto 0) => NLW_inst_rxprbscntreset_us_in_UNCONNECTED(1 downto 0),
      rxprbscntreset_usp_in(1 downto 0) => NLW_inst_rxprbscntreset_usp_in_UNCONNECTED(1 downto 0),
      rxprbserr_us_out(1 downto 0) => B"00",
      rxprbserr_usp_out(1 downto 0) => B"00",
      rxprbslocked_us_out(1 downto 0) => B"00",
      rxprbslocked_usp_out(1 downto 0) => B"00",
      rxprbssel_us_in(7 downto 0) => NLW_inst_rxprbssel_us_in_UNCONNECTED(7 downto 0),
      rxprbssel_usp_in(7 downto 0) => NLW_inst_rxprbssel_usp_in_UNCONNECTED(7 downto 0),
      rxprgdivresetdone_us_out(1 downto 0) => B"00",
      rxprogdivreset_us_in(1 downto 0) => NLW_inst_rxprogdivreset_us_in_UNCONNECTED(1 downto 0),
      rxprogdivreset_usp_in(1 downto 0) => NLW_inst_rxprogdivreset_usp_in_UNCONNECTED(1 downto 0),
      rxrate_us_in(5 downto 0) => NLW_inst_rxrate_us_in_UNCONNECTED(5 downto 0),
      rxrate_usp_in(5 downto 0) => NLW_inst_rxrate_usp_in_UNCONNECTED(5 downto 0),
      rxratedone_us_out(1 downto 0) => B"00",
      rxratedone_usp_out(1 downto 0) => B"00",
      rxratemode_us_in(1 downto 0) => NLW_inst_rxratemode_us_in_UNCONNECTED(1 downto 0),
      rxratemode_usp_in(1 downto 0) => NLW_inst_rxratemode_usp_in_UNCONNECTED(1 downto 0),
      rxrecclkout_usp_out(1 downto 0) => B"00",
      rxresetdone_us_out(1 downto 0) => B"00",
      rxresetdone_usp_out(1 downto 0) => B"00",
      rxslide_us_in(1 downto 0) => NLW_inst_rxslide_us_in_UNCONNECTED(1 downto 0),
      rxslide_usp_in(1 downto 0) => NLW_inst_rxslide_usp_in_UNCONNECTED(1 downto 0),
      rxstatus_us_out(5 downto 0) => B"000000",
      rxstatus_usp_out(5 downto 0) => B"000000",
      rxsyncdone_us_out(1 downto 0) => B"00",
      rxsyncdone_usp_out(1 downto 0) => B"00",
      rxtermination_usp_in(1 downto 0) => NLW_inst_rxtermination_usp_in_UNCONNECTED(1 downto 0),
      rxuserrdy_us_in(1 downto 0) => NLW_inst_rxuserrdy_us_in_UNCONNECTED(1 downto 0),
      rxuserrdy_usp_in(1 downto 0) => NLW_inst_rxuserrdy_usp_in_UNCONNECTED(1 downto 0),
      rxusrclk2_us_in(1 downto 0) => NLW_inst_rxusrclk2_us_in_UNCONNECTED(1 downto 0),
      rxusrclk2_usp_in(1 downto 0) => NLW_inst_rxusrclk2_usp_in_UNCONNECTED(1 downto 0),
      rxusrclk_us_in(1 downto 0) => NLW_inst_rxusrclk_us_in_UNCONNECTED(1 downto 0),
      rxusrclk_usp_in(1 downto 0) => NLW_inst_rxusrclk_usp_in_UNCONNECTED(1 downto 0),
      rxvalid_us_out(1 downto 0) => B"00",
      rxvalid_usp_out(1 downto 0) => B"00",
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(13 downto 0) => B"00000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arcache(3 downto 0) => B"0000",
      s_axi_arid(15 downto 0) => B"0000000000000000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arlock(0) => '0',
      s_axi_arprot(2 downto 0) => B"000",
      s_axi_arqos(3 downto 0) => B"0000",
      s_axi_arready => NLW_inst_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_aruser(15 downto 0) => B"0000000000000000",
      s_axi_arvalid => '0',
      s_axi_awaddr(13 downto 0) => B"00000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awcache(3 downto 0) => B"0000",
      s_axi_awid(15 downto 0) => B"0000000000000000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awlock(0) => '0',
      s_axi_awprot(2 downto 0) => B"000",
      s_axi_awqos(3 downto 0) => B"0000",
      s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awuser(15 downto 0) => B"0000000000000000",
      s_axi_awvalid => '0',
      s_axi_bid(15 downto 0) => NLW_inst_s_axi_bid_UNCONNECTED(15 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
      s_axi_rdata(31 downto 0) => NLW_inst_s_axi_rdata_UNCONNECTED(31 downto 0),
      s_axi_rid(15 downto 0) => NLW_inst_s_axi_rid_UNCONNECTED(15 downto 0),
      s_axi_rlast => NLW_inst_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_inst_s_axi_rvalid_UNCONNECTED,
      s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(3 downto 0) => B"0000",
      s_axi_wvalid => '0',
      s_axib_araddr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axib_arburst(1 downto 0) => B"00",
      s_axib_arid(3 downto 0) => B"0000",
      s_axib_arlen(7 downto 0) => B"00000000",
      s_axib_arready => NLW_inst_s_axib_arready_UNCONNECTED,
      s_axib_arregion(3 downto 0) => B"0000",
      s_axib_arsize(2 downto 0) => B"000",
      s_axib_arvalid => '0',
      s_axib_awaddr(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axib_awburst(1 downto 0) => B"00",
      s_axib_awid(3 downto 0) => B"0000",
      s_axib_awlen(7 downto 0) => B"00000000",
      s_axib_awready => NLW_inst_s_axib_awready_UNCONNECTED,
      s_axib_awregion(3 downto 0) => B"0000",
      s_axib_awsize(2 downto 0) => B"000",
      s_axib_awvalid => '0',
      s_axib_bid(3 downto 0) => NLW_inst_s_axib_bid_UNCONNECTED(3 downto 0),
      s_axib_bready => '0',
      s_axib_bresp(1 downto 0) => NLW_inst_s_axib_bresp_UNCONNECTED(1 downto 0),
      s_axib_bvalid => NLW_inst_s_axib_bvalid_UNCONNECTED,
      s_axib_rdata(63 downto 0) => NLW_inst_s_axib_rdata_UNCONNECTED(63 downto 0),
      s_axib_rid(3 downto 0) => NLW_inst_s_axib_rid_UNCONNECTED(3 downto 0),
      s_axib_rlast => NLW_inst_s_axib_rlast_UNCONNECTED,
      s_axib_rready => '0',
      s_axib_rresp(1 downto 0) => NLW_inst_s_axib_rresp_UNCONNECTED(1 downto 0),
      s_axib_ruser(7 downto 0) => NLW_inst_s_axib_ruser_UNCONNECTED(7 downto 0),
      s_axib_rvalid => NLW_inst_s_axib_rvalid_UNCONNECTED,
      s_axib_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axib_wlast => '0',
      s_axib_wready => NLW_inst_s_axib_wready_UNCONNECTED,
      s_axib_wstrb(7 downto 0) => B"00000000",
      s_axib_wuser(7 downto 0) => B"00000000",
      s_axib_wvalid => '0',
      s_axil_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axil_arprot(2 downto 0) => B"000",
      s_axil_arready => NLW_inst_s_axil_arready_UNCONNECTED,
      s_axil_arvalid => '0',
      s_axil_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axil_awprot(2 downto 0) => B"000",
      s_axil_awready => NLW_inst_s_axil_awready_UNCONNECTED,
      s_axil_awvalid => '0',
      s_axil_bready => '0',
      s_axil_bresp(1 downto 0) => NLW_inst_s_axil_bresp_UNCONNECTED(1 downto 0),
      s_axil_bvalid => NLW_inst_s_axil_bvalid_UNCONNECTED,
      s_axil_rdata(31 downto 0) => NLW_inst_s_axil_rdata_UNCONNECTED(31 downto 0),
      s_axil_rready => '0',
      s_axil_rresp(1 downto 0) => NLW_inst_s_axil_rresp_UNCONNECTED(1 downto 0),
      s_axil_rvalid => NLW_inst_s_axil_rvalid_UNCONNECTED,
      s_axil_wdata(31 downto 0) => B"00000000000000000000000000000000",
      s_axil_wready => NLW_inst_s_axil_wready_UNCONNECTED,
      s_axil_wstrb(3 downto 0) => B"0000",
      s_axil_wvalid => '0',
      s_axis_c2h_tdata_0(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tdata_1(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tdata_2(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tdata_3(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axis_c2h_tkeep_0(7 downto 0) => B"00000000",
      s_axis_c2h_tkeep_1(7 downto 0) => B"00000000",
      s_axis_c2h_tkeep_2(7 downto 0) => B"00000000",
      s_axis_c2h_tkeep_3(7 downto 0) => B"00000000",
      s_axis_c2h_tlast_0 => '0',
      s_axis_c2h_tlast_1 => '0',
      s_axis_c2h_tlast_2 => '0',
      s_axis_c2h_tlast_3 => '0',
      s_axis_c2h_tready_0 => NLW_inst_s_axis_c2h_tready_0_UNCONNECTED,
      s_axis_c2h_tready_1 => NLW_inst_s_axis_c2h_tready_1_UNCONNECTED,
      s_axis_c2h_tready_2 => NLW_inst_s_axis_c2h_tready_2_UNCONNECTED,
      s_axis_c2h_tready_3 => NLW_inst_s_axis_c2h_tready_3_UNCONNECTED,
      s_axis_c2h_tuser_0(7 downto 0) => B"00000000",
      s_axis_c2h_tuser_1(7 downto 0) => B"00000000",
      s_axis_c2h_tuser_2(7 downto 0) => B"00000000",
      s_axis_c2h_tuser_3(7 downto 0) => B"00000000",
      s_axis_c2h_tvalid_0 => '0',
      s_axis_c2h_tvalid_1 => '0',
      s_axis_c2h_tvalid_2 => '0',
      s_axis_c2h_tvalid_3 => '0',
      s_axis_cc_tdata_sd(63 downto 0) => NLW_inst_s_axis_cc_tdata_sd_UNCONNECTED(63 downto 0),
      s_axis_cc_tkeep_sd(1 downto 0) => NLW_inst_s_axis_cc_tkeep_sd_UNCONNECTED(1 downto 0),
      s_axis_cc_tlast_sd => NLW_inst_s_axis_cc_tlast_sd_UNCONNECTED,
      s_axis_cc_tready_sd(3 downto 0) => B"0000",
      s_axis_cc_tuser_sd(32 downto 0) => NLW_inst_s_axis_cc_tuser_sd_UNCONNECTED(32 downto 0),
      s_axis_cc_tvalid_sd => NLW_inst_s_axis_cc_tvalid_sd_UNCONNECTED,
      s_axis_cq_tdata_out(63 downto 0) => NLW_inst_s_axis_cq_tdata_out_UNCONNECTED(63 downto 0),
      s_axis_cq_tkeep_out(1 downto 0) => NLW_inst_s_axis_cq_tkeep_out_UNCONNECTED(1 downto 0),
      s_axis_cq_tlast_out => NLW_inst_s_axis_cq_tlast_out_UNCONNECTED,
      s_axis_cq_tready_out => NLW_inst_s_axis_cq_tready_out_UNCONNECTED,
      s_axis_cq_tuser_out(84 downto 0) => NLW_inst_s_axis_cq_tuser_out_UNCONNECTED(84 downto 0),
      s_axis_cq_tvalid_out => NLW_inst_s_axis_cq_tvalid_out_UNCONNECTED,
      s_axis_rc_tdata_out(63 downto 0) => NLW_inst_s_axis_rc_tdata_out_UNCONNECTED(63 downto 0),
      s_axis_rc_tkeep_out(1 downto 0) => NLW_inst_s_axis_rc_tkeep_out_UNCONNECTED(1 downto 0),
      s_axis_rc_tlast_out => NLW_inst_s_axis_rc_tlast_out_UNCONNECTED,
      s_axis_rc_tready_out => NLW_inst_s_axis_rc_tready_out_UNCONNECTED,
      s_axis_rc_tuser_out(74 downto 0) => NLW_inst_s_axis_rc_tuser_out_UNCONNECTED(74 downto 0),
      s_axis_rc_tvalid_out => NLW_inst_s_axis_rc_tvalid_out_UNCONNECTED,
      s_axis_rq_tdata_sd(63 downto 0) => NLW_inst_s_axis_rq_tdata_sd_UNCONNECTED(63 downto 0),
      s_axis_rq_tkeep_sd(1 downto 0) => NLW_inst_s_axis_rq_tkeep_sd_UNCONNECTED(1 downto 0),
      s_axis_rq_tlast_sd => NLW_inst_s_axis_rq_tlast_sd_UNCONNECTED,
      s_axis_rq_tready_sd(3 downto 0) => B"0000",
      s_axis_rq_tuser_sd(59 downto 0) => NLW_inst_s_axis_rq_tuser_sd_UNCONNECTED(59 downto 0),
      s_axis_rq_tvalid_sd => NLW_inst_s_axis_rq_tvalid_sd_UNCONNECTED,
      s_axis_tx_tready_o => s_axis_tx_tready_o,
      sc0_ats_m_axis_cq_tdata(63 downto 0) => NLW_inst_sc0_ats_m_axis_cq_tdata_UNCONNECTED(63 downto 0),
      sc0_ats_m_axis_cq_tkeep(7 downto 0) => NLW_inst_sc0_ats_m_axis_cq_tkeep_UNCONNECTED(7 downto 0),
      sc0_ats_m_axis_cq_tlast => NLW_inst_sc0_ats_m_axis_cq_tlast_UNCONNECTED,
      sc0_ats_m_axis_cq_tready => '0',
      sc0_ats_m_axis_cq_tuser(84 downto 0) => NLW_inst_sc0_ats_m_axis_cq_tuser_UNCONNECTED(84 downto 0),
      sc0_ats_m_axis_cq_tvalid => NLW_inst_sc0_ats_m_axis_cq_tvalid_UNCONNECTED,
      sc0_ats_m_axis_rc_tdata(63 downto 0) => NLW_inst_sc0_ats_m_axis_rc_tdata_UNCONNECTED(63 downto 0),
      sc0_ats_m_axis_rc_tkeep(7 downto 0) => NLW_inst_sc0_ats_m_axis_rc_tkeep_UNCONNECTED(7 downto 0),
      sc0_ats_m_axis_rc_tlast => NLW_inst_sc0_ats_m_axis_rc_tlast_UNCONNECTED,
      sc0_ats_m_axis_rc_tready => '0',
      sc0_ats_m_axis_rc_tuser(74 downto 0) => NLW_inst_sc0_ats_m_axis_rc_tuser_UNCONNECTED(74 downto 0),
      sc0_ats_m_axis_rc_tvalid => NLW_inst_sc0_ats_m_axis_rc_tvalid_UNCONNECTED,
      sc0_ats_s_axis_cc_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      sc0_ats_s_axis_cc_tkeep(7 downto 0) => B"00000000",
      sc0_ats_s_axis_cc_tlast => '0',
      sc0_ats_s_axis_cc_tready => NLW_inst_sc0_ats_s_axis_cc_tready_UNCONNECTED,
      sc0_ats_s_axis_cc_tuser(32 downto 0) => B"000000000000000000000000000000000",
      sc0_ats_s_axis_cc_tvalid => '0',
      sc0_ats_s_axis_rq_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      sc0_ats_s_axis_rq_tkeep(7 downto 0) => B"00000000",
      sc0_ats_s_axis_rq_tlast => '0',
      sc0_ats_s_axis_rq_tready => NLW_inst_sc0_ats_s_axis_rq_tready_UNCONNECTED,
      sc0_ats_s_axis_rq_tuser(59 downto 0) => B"000000000000000000000000000000000000000000000000000000000000",
      sc0_ats_s_axis_rq_tvalid => '0',
      sc1_ats_m_axis_cq_tdata(63 downto 0) => NLW_inst_sc1_ats_m_axis_cq_tdata_UNCONNECTED(63 downto 0),
      sc1_ats_m_axis_cq_tkeep(7 downto 0) => NLW_inst_sc1_ats_m_axis_cq_tkeep_UNCONNECTED(7 downto 0),
      sc1_ats_m_axis_cq_tlast => NLW_inst_sc1_ats_m_axis_cq_tlast_UNCONNECTED,
      sc1_ats_m_axis_cq_tready => '0',
      sc1_ats_m_axis_cq_tuser(84 downto 0) => NLW_inst_sc1_ats_m_axis_cq_tuser_UNCONNECTED(84 downto 0),
      sc1_ats_m_axis_cq_tvalid => NLW_inst_sc1_ats_m_axis_cq_tvalid_UNCONNECTED,
      sc1_ats_m_axis_rc_tdata(63 downto 0) => NLW_inst_sc1_ats_m_axis_rc_tdata_UNCONNECTED(63 downto 0),
      sc1_ats_m_axis_rc_tkeep(7 downto 0) => NLW_inst_sc1_ats_m_axis_rc_tkeep_UNCONNECTED(7 downto 0),
      sc1_ats_m_axis_rc_tlast => NLW_inst_sc1_ats_m_axis_rc_tlast_UNCONNECTED,
      sc1_ats_m_axis_rc_tready => '0',
      sc1_ats_m_axis_rc_tuser(74 downto 0) => NLW_inst_sc1_ats_m_axis_rc_tuser_UNCONNECTED(74 downto 0),
      sc1_ats_m_axis_rc_tvalid => NLW_inst_sc1_ats_m_axis_rc_tvalid_UNCONNECTED,
      sc1_ats_s_axis_cc_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      sc1_ats_s_axis_cc_tkeep(7 downto 0) => B"00000000",
      sc1_ats_s_axis_cc_tlast => '0',
      sc1_ats_s_axis_cc_tready => NLW_inst_sc1_ats_s_axis_cc_tready_UNCONNECTED,
      sc1_ats_s_axis_cc_tuser(32 downto 0) => B"000000000000000000000000000000000",
      sc1_ats_s_axis_cc_tvalid => '0',
      sc1_ats_s_axis_rq_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      sc1_ats_s_axis_rq_tkeep(7 downto 0) => B"00000000",
      sc1_ats_s_axis_rq_tlast => '0',
      sc1_ats_s_axis_rq_tready => NLW_inst_sc1_ats_s_axis_rq_tready_UNCONNECTED,
      sc1_ats_s_axis_rq_tuser(59 downto 0) => B"000000000000000000000000000000000000000000000000000000000000",
      sc1_ats_s_axis_rq_tvalid => '0',
      startup_cfgclk => NLW_inst_startup_cfgclk_UNCONNECTED,
      startup_cfgmclk => NLW_inst_startup_cfgmclk_UNCONNECTED,
      startup_di(3 downto 0) => NLW_inst_startup_di_UNCONNECTED(3 downto 0),
      startup_do(3 downto 0) => B"0000",
      startup_dts(3 downto 0) => B"0000",
      startup_eos => NLW_inst_startup_eos_UNCONNECTED,
      startup_fcsbo => '0',
      startup_fcsbts => '0',
      startup_gsr => '0',
      startup_gts => '0',
      startup_keyclearb => '1',
      startup_pack => '0',
      startup_preq => NLW_inst_startup_preq_UNCONNECTED,
      startup_usrcclko => '0',
      startup_usrcclkts => '1',
      startup_usrdoneo => '0',
      startup_usrdonets => '1',
      sys_clk => sys_clk,
      sys_clk_bufg => NLW_inst_sys_clk_bufg_UNCONNECTED,
      sys_clk_ce_out => NLW_inst_sys_clk_ce_out_UNCONNECTED,
      sys_clk_gt => '0',
      sys_rst_n => sys_rst_n,
      tx8b10ben_us_in(1 downto 0) => NLW_inst_tx8b10ben_us_in_UNCONNECTED(1 downto 0),
      tx8b10ben_usp_in(1 downto 0) => NLW_inst_tx8b10ben_usp_in_UNCONNECTED(1 downto 0),
      txctrl0_us_in(31 downto 0) => NLW_inst_txctrl0_us_in_UNCONNECTED(31 downto 0),
      txctrl0_usp_in(31 downto 0) => NLW_inst_txctrl0_usp_in_UNCONNECTED(31 downto 0),
      txctrl1_us_in(31 downto 0) => NLW_inst_txctrl1_us_in_UNCONNECTED(31 downto 0),
      txctrl1_usp_in(31 downto 0) => NLW_inst_txctrl1_usp_in_UNCONNECTED(31 downto 0),
      txctrl2_us_in(15 downto 0) => NLW_inst_txctrl2_us_in_UNCONNECTED(15 downto 0),
      txctrl2_usp_in(15 downto 0) => NLW_inst_txctrl2_usp_in_UNCONNECTED(15 downto 0),
      txdata_us_in(255 downto 0) => NLW_inst_txdata_us_in_UNCONNECTED(255 downto 0),
      txdata_usp_in(255 downto 0) => NLW_inst_txdata_usp_in_UNCONNECTED(255 downto 0),
      txdeemph_us_in(1 downto 0) => NLW_inst_txdeemph_us_in_UNCONNECTED(1 downto 0),
      txdeemph_usp_in(3 downto 0) => NLW_inst_txdeemph_usp_in_UNCONNECTED(3 downto 0),
      txdetectrx_us_in(1 downto 0) => NLW_inst_txdetectrx_us_in_UNCONNECTED(1 downto 0),
      txdetectrx_usp_in(1 downto 0) => NLW_inst_txdetectrx_usp_in_UNCONNECTED(1 downto 0),
      txdiffctrl_us_in(7 downto 0) => NLW_inst_txdiffctrl_us_in_UNCONNECTED(7 downto 0),
      txdiffctrl_usp_in(9 downto 0) => NLW_inst_txdiffctrl_usp_in_UNCONNECTED(9 downto 0),
      txdlybypass_us_in(1 downto 0) => NLW_inst_txdlybypass_us_in_UNCONNECTED(1 downto 0),
      txdlybypass_usp_in(1 downto 0) => NLW_inst_txdlybypass_usp_in_UNCONNECTED(1 downto 0),
      txdlyen_us_in(1 downto 0) => NLW_inst_txdlyen_us_in_UNCONNECTED(1 downto 0),
      txdlyen_usp_in(1 downto 0) => NLW_inst_txdlyen_usp_in_UNCONNECTED(1 downto 0),
      txdlyhold_us_in(1 downto 0) => NLW_inst_txdlyhold_us_in_UNCONNECTED(1 downto 0),
      txdlyhold_usp_in(1 downto 0) => NLW_inst_txdlyhold_usp_in_UNCONNECTED(1 downto 0),
      txdlyovrden_us_in(1 downto 0) => NLW_inst_txdlyovrden_us_in_UNCONNECTED(1 downto 0),
      txdlyovrden_usp_in(1 downto 0) => NLW_inst_txdlyovrden_usp_in_UNCONNECTED(1 downto 0),
      txdlysreset_us_in(1 downto 0) => NLW_inst_txdlysreset_us_in_UNCONNECTED(1 downto 0),
      txdlysreset_usp_in(1 downto 0) => NLW_inst_txdlysreset_usp_in_UNCONNECTED(1 downto 0),
      txdlysresetdone_us_out(1 downto 0) => B"00",
      txdlysresetdone_usp_out(1 downto 0) => B"00",
      txdlyupdown_us_in(1 downto 0) => NLW_inst_txdlyupdown_us_in_UNCONNECTED(1 downto 0),
      txdlyupdown_usp_in(1 downto 0) => NLW_inst_txdlyupdown_usp_in_UNCONNECTED(1 downto 0),
      txelecidle_us_in(1 downto 0) => NLW_inst_txelecidle_us_in_UNCONNECTED(1 downto 0),
      txelecidle_usp_in(1 downto 0) => NLW_inst_txelecidle_usp_in_UNCONNECTED(1 downto 0),
      txinhibit_us_in(1 downto 0) => NLW_inst_txinhibit_us_in_UNCONNECTED(1 downto 0),
      txmaincursor_us_in(13 downto 0) => NLW_inst_txmaincursor_us_in_UNCONNECTED(13 downto 0),
      txmaincursor_usp_in(13 downto 0) => NLW_inst_txmaincursor_usp_in_UNCONNECTED(13 downto 0),
      txmargin_us_in(5 downto 0) => NLW_inst_txmargin_us_in_UNCONNECTED(5 downto 0),
      txmargin_usp_in(5 downto 0) => NLW_inst_txmargin_usp_in_UNCONNECTED(5 downto 0),
      txoutclk_us_out(1 downto 0) => B"00",
      txoutclk_usp_out(1 downto 0) => B"00",
      txoutclkfabric_usp_out(1 downto 0) => B"00",
      txoutclkpcs_usp_out(1 downto 0) => B"00",
      txoutclksel_us_in(5 downto 0) => NLW_inst_txoutclksel_us_in_UNCONNECTED(5 downto 0),
      txoutclksel_usp_in(5 downto 0) => NLW_inst_txoutclksel_usp_in_UNCONNECTED(5 downto 0),
      txpcsreset_usp_in(1 downto 0) => NLW_inst_txpcsreset_usp_in_UNCONNECTED(1 downto 0),
      txpd_us_in(3 downto 0) => NLW_inst_txpd_us_in_UNCONNECTED(3 downto 0),
      txpd_usp_in(3 downto 0) => NLW_inst_txpd_usp_in_UNCONNECTED(3 downto 0),
      txpdelecidlemode_usp_in(1 downto 0) => NLW_inst_txpdelecidlemode_usp_in_UNCONNECTED(1 downto 0),
      txphalign_us_in(1 downto 0) => NLW_inst_txphalign_us_in_UNCONNECTED(1 downto 0),
      txphalign_usp_in(1 downto 0) => NLW_inst_txphalign_usp_in_UNCONNECTED(1 downto 0),
      txphaligndone_us_out(1 downto 0) => B"00",
      txphaligndone_usp_out(1 downto 0) => B"00",
      txphalignen_us_in(1 downto 0) => NLW_inst_txphalignen_us_in_UNCONNECTED(1 downto 0),
      txphalignen_usp_in(1 downto 0) => NLW_inst_txphalignen_usp_in_UNCONNECTED(1 downto 0),
      txphdlypd_us_in(1 downto 0) => NLW_inst_txphdlypd_us_in_UNCONNECTED(1 downto 0),
      txphdlypd_usp_in(1 downto 0) => NLW_inst_txphdlypd_usp_in_UNCONNECTED(1 downto 0),
      txphdlyreset_us_in(1 downto 0) => NLW_inst_txphdlyreset_us_in_UNCONNECTED(1 downto 0),
      txphdlyreset_usp_in(1 downto 0) => NLW_inst_txphdlyreset_usp_in_UNCONNECTED(1 downto 0),
      txphdlytstclk_us_in(1 downto 0) => NLW_inst_txphdlytstclk_us_in_UNCONNECTED(1 downto 0),
      txphdlytstclk_usp_in(1 downto 0) => NLW_inst_txphdlytstclk_usp_in_UNCONNECTED(1 downto 0),
      txphinit_us_in(1 downto 0) => NLW_inst_txphinit_us_in_UNCONNECTED(1 downto 0),
      txphinit_usp_in(1 downto 0) => NLW_inst_txphinit_usp_in_UNCONNECTED(1 downto 0),
      txphinitdone_us_out(1 downto 0) => B"00",
      txphinitdone_usp_out(1 downto 0) => B"00",
      txphovrden_us_in(1 downto 0) => NLW_inst_txphovrden_us_in_UNCONNECTED(1 downto 0),
      txphovrden_usp_in(1 downto 0) => NLW_inst_txphovrden_usp_in_UNCONNECTED(1 downto 0),
      txpisopd_usp_in(1 downto 0) => NLW_inst_txpisopd_usp_in_UNCONNECTED(1 downto 0),
      txpmareset_usp_in(1 downto 0) => NLW_inst_txpmareset_usp_in_UNCONNECTED(1 downto 0),
      txpmaresetdone_us_out(1 downto 0) => B"00",
      txpmaresetdone_usp_out(1 downto 0) => B"00",
      txpostcursor_us_in(9 downto 0) => NLW_inst_txpostcursor_us_in_UNCONNECTED(9 downto 0),
      txpostcursor_usp_in(9 downto 0) => NLW_inst_txpostcursor_usp_in_UNCONNECTED(9 downto 0),
      txprbsforceerr_us_in(1 downto 0) => NLW_inst_txprbsforceerr_us_in_UNCONNECTED(1 downto 0),
      txprbsforceerr_usp_in(1 downto 0) => NLW_inst_txprbsforceerr_usp_in_UNCONNECTED(1 downto 0),
      txprbssel_us_in(7 downto 0) => NLW_inst_txprbssel_us_in_UNCONNECTED(7 downto 0),
      txprbssel_usp_in(7 downto 0) => NLW_inst_txprbssel_usp_in_UNCONNECTED(7 downto 0),
      txprecursor_us_in(9 downto 0) => NLW_inst_txprecursor_us_in_UNCONNECTED(9 downto 0),
      txprecursor_usp_in(9 downto 0) => NLW_inst_txprecursor_usp_in_UNCONNECTED(9 downto 0),
      txprgdivresetdone_us_out(1 downto 0) => B"00",
      txprgdivresetdone_usp_out(1 downto 0) => B"00",
      txprogdivreset_us_in(1 downto 0) => NLW_inst_txprogdivreset_us_in_UNCONNECTED(1 downto 0),
      txprogdivreset_usp_in(1 downto 0) => NLW_inst_txprogdivreset_usp_in_UNCONNECTED(1 downto 0),
      txrate_us_in(5 downto 0) => NLW_inst_txrate_us_in_UNCONNECTED(5 downto 0),
      txrate_usp_in(5 downto 0) => NLW_inst_txrate_usp_in_UNCONNECTED(5 downto 0),
      txresetdone_us_out(1 downto 0) => B"00",
      txresetdone_usp_out(1 downto 0) => B"00",
      txswing_us_in(1 downto 0) => NLW_inst_txswing_us_in_UNCONNECTED(1 downto 0),
      txswing_usp_in(1 downto 0) => NLW_inst_txswing_usp_in_UNCONNECTED(1 downto 0),
      txsyncallin_us_in(1 downto 0) => NLW_inst_txsyncallin_us_in_UNCONNECTED(1 downto 0),
      txsyncallin_usp_in(1 downto 0) => NLW_inst_txsyncallin_usp_in_UNCONNECTED(1 downto 0),
      txsyncdone_us_out(1 downto 0) => B"00",
      txsyncdone_usp_out(1 downto 0) => B"00",
      txsyncin_us_in(1 downto 0) => NLW_inst_txsyncin_us_in_UNCONNECTED(1 downto 0),
      txsyncin_usp_in(1 downto 0) => NLW_inst_txsyncin_usp_in_UNCONNECTED(1 downto 0),
      txsyncmode_us_in(1 downto 0) => NLW_inst_txsyncmode_us_in_UNCONNECTED(1 downto 0),
      txsyncmode_usp_in(1 downto 0) => NLW_inst_txsyncmode_usp_in_UNCONNECTED(1 downto 0),
      txsyncout_us_out(1 downto 0) => B"00",
      txsyncout_usp_out(1 downto 0) => B"00",
      txuserrdy_us_in(1 downto 0) => NLW_inst_txuserrdy_us_in_UNCONNECTED(1 downto 0),
      txuserrdy_usp_in(1 downto 0) => NLW_inst_txuserrdy_usp_in_UNCONNECTED(1 downto 0),
      txusrclk2_us_in(1 downto 0) => NLW_inst_txusrclk2_us_in_UNCONNECTED(1 downto 0),
      txusrclk2_usp_in(1 downto 0) => NLW_inst_txusrclk2_usp_in_UNCONNECTED(1 downto 0),
      txusrclk_us_in(1 downto 0) => NLW_inst_txusrclk_us_in_UNCONNECTED(1 downto 0),
      txusrclk_usp_in(1 downto 0) => NLW_inst_txusrclk_usp_in_UNCONNECTED(1 downto 0),
      user_clk_sd => '0',
      user_lnk_up => user_lnk_up,
      user_lnk_up_sd => '0',
      user_reset_sd => '0',
      usr_flr_clr => NLW_inst_usr_flr_clr_UNCONNECTED,
      usr_flr_done_fnc(7 downto 0) => B"00000000",
      usr_flr_done_vld => '0',
      usr_flr_fnc(7 downto 0) => NLW_inst_usr_flr_fnc_UNCONNECTED(7 downto 0),
      usr_flr_set => NLW_inst_usr_flr_set_UNCONNECTED,
      usr_irq_ack(0) => usr_irq_ack(0),
      usr_irq_function_number(1 downto 0) => B"00",
      usr_irq_req(0) => usr_irq_req(0),
      wr_interrupt => NLW_inst_wr_interrupt_UNCONNECTED
    );
end STRUCTURE;
