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##-----------------------------------------------------------------------------
##
## Project    : The Xilinx PCI Express DMA
## File       : xilinx_xdma_pcie_x0y0.xdc
## Version    : 4.1
##-----------------------------------------------------------------------------
###############################################################################
# User Configuration
# Link Width   - x2
# Link Speed   - gen2
# Family       - artix7
# Part         - xc7a100t
# Package      - fgg484
# Speed grade  - -2
# PCIe Block   - X0Y0
###############################################################################
#
#########################################################################################################################
# User Constraints
#########################################################################################################################

###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################

###############################################################################
# User Physical Constraints
###############################################################################

#########################################################################################################################
# End User Constraints
#########################################################################################################################
#
#
#
#########################################################################################################################
# PCIE Core Constraints
#########################################################################################################################


###############################################################################
# Pinout and Related I/O Constraints
###############################################################################
#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
# Some 7 series devices do not have 3.3 V I/Os available.
# Therefore the appropriate level shift is required to operate
# with these devices that contain only 1.8 V banks.
#

set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]
set_property PULLTYPE PULLUP [get_ports sys_rst_n]

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

#
#
# SYS clock 0 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#
set_property LOC IBUFDS_GTE2_X0Y3 [get_cells refclk_ibuf]

###############################################################################
# Timing Constraints
###############################################################################

create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]

###############################################################################
# Physical Constraints
###############################################################################

set_false_path -from [get_ports sys_rst_n]

#########################################################################################################################
# End PCIe Core Constraints
#########################################################################################################################

set_property PACKAGE_PIN J20 [get_ports sys_rst_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN A8 [get_ports {pci_exp_rxn[1]}]
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN C11 [get_ports {pci_exp_rxn[0]}]

connect_debug_port u_ila_0/probe0 [get_nets [list {xdma_app_i/s_axi_wdata[0]} {xdma_app_i/s_axi_wdata[1]} {xdma_app_i/s_axi_wdata[2]} {xdma_app_i/s_axi_wdata[3]} {xdma_app_i/s_axi_wdata[4]} {xdma_app_i/s_axi_wdata[5]} {xdma_app_i/s_axi_wdata[6]} {xdma_app_i/s_axi_wdata[7]} {xdma_app_i/s_axi_wdata[8]} {xdma_app_i/s_axi_wdata[9]} {xdma_app_i/s_axi_wdata[10]} {xdma_app_i/s_axi_wdata[11]} {xdma_app_i/s_axi_wdata[12]} {xdma_app_i/s_axi_wdata[13]} {xdma_app_i/s_axi_wdata[14]} {xdma_app_i/s_axi_wdata[15]} {xdma_app_i/s_axi_wdata[16]} {xdma_app_i/s_axi_wdata[17]} {xdma_app_i/s_axi_wdata[18]} {xdma_app_i/s_axi_wdata[19]} {xdma_app_i/s_axi_wdata[20]} {xdma_app_i/s_axi_wdata[21]} {xdma_app_i/s_axi_wdata[22]} {xdma_app_i/s_axi_wdata[23]} {xdma_app_i/s_axi_wdata[24]} {xdma_app_i/s_axi_wdata[25]} {xdma_app_i/s_axi_wdata[26]} {xdma_app_i/s_axi_wdata[27]} {xdma_app_i/s_axi_wdata[28]} {xdma_app_i/s_axi_wdata[29]} {xdma_app_i/s_axi_wdata[30]} {xdma_app_i/s_axi_wdata[31]} {xdma_app_i/s_axi_wdata[32]} {xdma_app_i/s_axi_wdata[33]} {xdma_app_i/s_axi_wdata[34]} {xdma_app_i/s_axi_wdata[35]} {xdma_app_i/s_axi_wdata[36]} {xdma_app_i/s_axi_wdata[37]} {xdma_app_i/s_axi_wdata[38]} {xdma_app_i/s_axi_wdata[39]} {xdma_app_i/s_axi_wdata[40]} {xdma_app_i/s_axi_wdata[41]} {xdma_app_i/s_axi_wdata[42]} {xdma_app_i/s_axi_wdata[43]} {xdma_app_i/s_axi_wdata[44]} {xdma_app_i/s_axi_wdata[45]} {xdma_app_i/s_axi_wdata[46]} {xdma_app_i/s_axi_wdata[47]} {xdma_app_i/s_axi_wdata[48]} {xdma_app_i/s_axi_wdata[49]} {xdma_app_i/s_axi_wdata[50]} {xdma_app_i/s_axi_wdata[51]} {xdma_app_i/s_axi_wdata[52]} {xdma_app_i/s_axi_wdata[53]} {xdma_app_i/s_axi_wdata[54]} {xdma_app_i/s_axi_wdata[55]} {xdma_app_i/s_axi_wdata[56]} {xdma_app_i/s_axi_wdata[57]} {xdma_app_i/s_axi_wdata[58]} {xdma_app_i/s_axi_wdata[59]} {xdma_app_i/s_axi_wdata[60]} {xdma_app_i/s_axi_wdata[61]} {xdma_app_i/s_axi_wdata[62]} {xdma_app_i/s_axi_wdata[63]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {xdma_app_i/s_axib_wdata[0]} {xdma_app_i/s_axib_wdata[1]} {xdma_app_i/s_axib_wdata[2]} {xdma_app_i/s_axib_wdata[3]} {xdma_app_i/s_axib_wdata[4]} {xdma_app_i/s_axib_wdata[5]} {xdma_app_i/s_axib_wdata[6]} {xdma_app_i/s_axib_wdata[7]} {xdma_app_i/s_axib_wdata[8]} {xdma_app_i/s_axib_wdata[9]} {xdma_app_i/s_axib_wdata[10]} {xdma_app_i/s_axib_wdata[11]} {xdma_app_i/s_axib_wdata[12]} {xdma_app_i/s_axib_wdata[13]} {xdma_app_i/s_axib_wdata[14]} {xdma_app_i/s_axib_wdata[15]} {xdma_app_i/s_axib_wdata[16]} {xdma_app_i/s_axib_wdata[17]} {xdma_app_i/s_axib_wdata[18]} {xdma_app_i/s_axib_wdata[19]} {xdma_app_i/s_axib_wdata[20]} {xdma_app_i/s_axib_wdata[21]} {xdma_app_i/s_axib_wdata[22]} {xdma_app_i/s_axib_wdata[23]} {xdma_app_i/s_axib_wdata[24]} {xdma_app_i/s_axib_wdata[25]} {xdma_app_i/s_axib_wdata[26]} {xdma_app_i/s_axib_wdata[27]} {xdma_app_i/s_axib_wdata[28]} {xdma_app_i/s_axib_wdata[29]} {xdma_app_i/s_axib_wdata[30]} {xdma_app_i/s_axib_wdata[31]} {xdma_app_i/s_axib_wdata[32]} {xdma_app_i/s_axib_wdata[33]} {xdma_app_i/s_axib_wdata[34]} {xdma_app_i/s_axib_wdata[35]} {xdma_app_i/s_axib_wdata[36]} {xdma_app_i/s_axib_wdata[37]} {xdma_app_i/s_axib_wdata[38]} {xdma_app_i/s_axib_wdata[39]} {xdma_app_i/s_axib_wdata[40]} {xdma_app_i/s_axib_wdata[41]} {xdma_app_i/s_axib_wdata[42]} {xdma_app_i/s_axib_wdata[43]} {xdma_app_i/s_axib_wdata[44]} {xdma_app_i/s_axib_wdata[45]} {xdma_app_i/s_axib_wdata[46]} {xdma_app_i/s_axib_wdata[47]} {xdma_app_i/s_axib_wdata[48]} {xdma_app_i/s_axib_wdata[49]} {xdma_app_i/s_axib_wdata[50]} {xdma_app_i/s_axib_wdata[51]} {xdma_app_i/s_axib_wdata[52]} {xdma_app_i/s_axib_wdata[53]} {xdma_app_i/s_axib_wdata[54]} {xdma_app_i/s_axib_wdata[55]} {xdma_app_i/s_axib_wdata[56]} {xdma_app_i/s_axib_wdata[57]} {xdma_app_i/s_axib_wdata[58]} {xdma_app_i/s_axib_wdata[59]} {xdma_app_i/s_axib_wdata[60]} {xdma_app_i/s_axib_wdata[61]} {xdma_app_i/s_axib_wdata[62]} {xdma_app_i/s_axib_wdata[63]}]]
connect_debug_port u_ila_0/probe3 [get_nets [list {xdma_app_i/s_axib_rdata[0]} {xdma_app_i/s_axib_rdata[1]} {xdma_app_i/s_axib_rdata[2]} {xdma_app_i/s_axib_rdata[3]} {xdma_app_i/s_axib_rdata[4]} {xdma_app_i/s_axib_rdata[5]} {xdma_app_i/s_axib_rdata[6]} {xdma_app_i/s_axib_rdata[7]} {xdma_app_i/s_axib_rdata[8]} {xdma_app_i/s_axib_rdata[9]} {xdma_app_i/s_axib_rdata[10]} {xdma_app_i/s_axib_rdata[11]} {xdma_app_i/s_axib_rdata[12]} {xdma_app_i/s_axib_rdata[13]} {xdma_app_i/s_axib_rdata[14]} {xdma_app_i/s_axib_rdata[15]} {xdma_app_i/s_axib_rdata[16]} {xdma_app_i/s_axib_rdata[17]} {xdma_app_i/s_axib_rdata[18]} {xdma_app_i/s_axib_rdata[19]} {xdma_app_i/s_axib_rdata[20]} {xdma_app_i/s_axib_rdata[21]} {xdma_app_i/s_axib_rdata[22]} {xdma_app_i/s_axib_rdata[23]} {xdma_app_i/s_axib_rdata[24]} {xdma_app_i/s_axib_rdata[25]} {xdma_app_i/s_axib_rdata[26]} {xdma_app_i/s_axib_rdata[27]} {xdma_app_i/s_axib_rdata[28]} {xdma_app_i/s_axib_rdata[29]} {xdma_app_i/s_axib_rdata[30]} {xdma_app_i/s_axib_rdata[31]} {xdma_app_i/s_axib_rdata[32]} {xdma_app_i/s_axib_rdata[33]} {xdma_app_i/s_axib_rdata[34]} {xdma_app_i/s_axib_rdata[35]} {xdma_app_i/s_axib_rdata[36]} {xdma_app_i/s_axib_rdata[37]} {xdma_app_i/s_axib_rdata[38]} {xdma_app_i/s_axib_rdata[39]} {xdma_app_i/s_axib_rdata[40]} {xdma_app_i/s_axib_rdata[41]} {xdma_app_i/s_axib_rdata[42]} {xdma_app_i/s_axib_rdata[43]} {xdma_app_i/s_axib_rdata[44]} {xdma_app_i/s_axib_rdata[45]} {xdma_app_i/s_axib_rdata[46]} {xdma_app_i/s_axib_rdata[47]} {xdma_app_i/s_axib_rdata[48]} {xdma_app_i/s_axib_rdata[49]} {xdma_app_i/s_axib_rdata[50]} {xdma_app_i/s_axib_rdata[51]} {xdma_app_i/s_axib_rdata[52]} {xdma_app_i/s_axib_rdata[53]} {xdma_app_i/s_axib_rdata[54]} {xdma_app_i/s_axib_rdata[55]} {xdma_app_i/s_axib_rdata[56]} {xdma_app_i/s_axib_rdata[57]} {xdma_app_i/s_axib_rdata[58]} {xdma_app_i/s_axib_rdata[59]} {xdma_app_i/s_axib_rdata[60]} {xdma_app_i/s_axib_rdata[61]} {xdma_app_i/s_axib_rdata[62]} {xdma_app_i/s_axib_rdata[63]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[0]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[1]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[2]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[3]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[4]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[5]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[6]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[7]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[8]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[9]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[10]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[11]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[12]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[13]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[14]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[15]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[16]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[17]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[18]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[19]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[20]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[21]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[22]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[23]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[24]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[25]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[26]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[27]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[28]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[29]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[30]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[31]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[32]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[33]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[34]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[35]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[36]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[37]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[38]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[39]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[40]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[41]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[42]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[43]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[44]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[45]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[46]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[47]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[48]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[49]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[50]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[51]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[52]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[53]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[54]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[55]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[56]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[57]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[58]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[59]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[60]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[61]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[62]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/m_axis_rx_tdata[63]}]]
connect_debug_port u_ila_0/probe7 [get_nets [list xdma_app_i/s_axi_rready]]
connect_debug_port u_ila_0/probe10 [get_nets [list xdma_app_i/s_axi_wvalid]]

set_property PACKAGE_PIN Y18 [get_ports LmkAClkSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports LmkAClkSpiM_o]
set_property PACKAGE_PIN U22 [get_ports LmkACsSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports LmkACsSpiM_o]
set_property PACKAGE_PIN P14 [get_ports LmkAMosiSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports LmkAMosiSpiM_o]
set_property PACKAGE_PIN AA16 [get_ports RstForFpga_o]
set_property IOSTANDARD LVCMOS33 [get_ports RstForFpga_o]
set_property PACKAGE_PIN W11 [get_ports TmsgClkSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgClkSpiM_o]
set_property PACKAGE_PIN AB15 [get_ports TmsgCsSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgCsSpiM_o]
set_property PACKAGE_PIN AB17 [get_ports TmsgMosiSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgMosiSpiM_o]

set_property PACKAGE_PIN V22 [get_ports LmkBCsSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports LmkBCsSpiM_o]









create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i_0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[0]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[1]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[2]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[3]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[4]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[5]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[6]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[7]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[8]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[9]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[10]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[11]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[12]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[13]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[14]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[15]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[16]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[17]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[18]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[19]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[20]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[21]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[22]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[23]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[24]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[25]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[26]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[27]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[28]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[29]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[30]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[31]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[32]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[33]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[34]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[35]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[36]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[37]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[38]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[39]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[40]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[41]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[42]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[43]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[44]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[45]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[46]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[47]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[48]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[49]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[50]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[51]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[52]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[53]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[54]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[55]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[56]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[57]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[58]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[59]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[60]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[61]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[62]} {xdma_0_i/inst/xdma_0_pcie2_to_pcie3_wrapper_i/s_axis_tx_tdata[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 64 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {xdma_app_i/s_axi_rdata[0]} {xdma_app_i/s_axi_rdata[1]} {xdma_app_i/s_axi_rdata[2]} {xdma_app_i/s_axi_rdata[3]} {xdma_app_i/s_axi_rdata[4]} {xdma_app_i/s_axi_rdata[5]} {xdma_app_i/s_axi_rdata[6]} {xdma_app_i/s_axi_rdata[7]} {xdma_app_i/s_axi_rdata[8]} {xdma_app_i/s_axi_rdata[9]} {xdma_app_i/s_axi_rdata[10]} {xdma_app_i/s_axi_rdata[11]} {xdma_app_i/s_axi_rdata[12]} {xdma_app_i/s_axi_rdata[13]} {xdma_app_i/s_axi_rdata[14]} {xdma_app_i/s_axi_rdata[15]} {xdma_app_i/s_axi_rdata[16]} {xdma_app_i/s_axi_rdata[17]} {xdma_app_i/s_axi_rdata[18]} {xdma_app_i/s_axi_rdata[19]} {xdma_app_i/s_axi_rdata[20]} {xdma_app_i/s_axi_rdata[21]} {xdma_app_i/s_axi_rdata[22]} {xdma_app_i/s_axi_rdata[23]} {xdma_app_i/s_axi_rdata[24]} {xdma_app_i/s_axi_rdata[25]} {xdma_app_i/s_axi_rdata[26]} {xdma_app_i/s_axi_rdata[27]} {xdma_app_i/s_axi_rdata[28]} {xdma_app_i/s_axi_rdata[29]} {xdma_app_i/s_axi_rdata[30]} {xdma_app_i/s_axi_rdata[31]} {xdma_app_i/s_axi_rdata[32]} {xdma_app_i/s_axi_rdata[33]} {xdma_app_i/s_axi_rdata[34]} {xdma_app_i/s_axi_rdata[35]} {xdma_app_i/s_axi_rdata[36]} {xdma_app_i/s_axi_rdata[37]} {xdma_app_i/s_axi_rdata[38]} {xdma_app_i/s_axi_rdata[39]} {xdma_app_i/s_axi_rdata[40]} {xdma_app_i/s_axi_rdata[41]} {xdma_app_i/s_axi_rdata[42]} {xdma_app_i/s_axi_rdata[43]} {xdma_app_i/s_axi_rdata[44]} {xdma_app_i/s_axi_rdata[45]} {xdma_app_i/s_axi_rdata[46]} {xdma_app_i/s_axi_rdata[47]} {xdma_app_i/s_axi_rdata[48]} {xdma_app_i/s_axi_rdata[49]} {xdma_app_i/s_axi_rdata[50]} {xdma_app_i/s_axi_rdata[51]} {xdma_app_i/s_axi_rdata[52]} {xdma_app_i/s_axi_rdata[53]} {xdma_app_i/s_axi_rdata[54]} {xdma_app_i/s_axi_rdata[55]} {xdma_app_i/s_axi_rdata[56]} {xdma_app_i/s_axi_rdata[57]} {xdma_app_i/s_axi_rdata[58]} {xdma_app_i/s_axi_rdata[59]} {xdma_app_i/s_axi_rdata[60]} {xdma_app_i/s_axi_rdata[61]} {xdma_app_i/s_axi_rdata[62]} {xdma_app_i/s_axi_rdata[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
set_property port_width 2 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {app/PIO/m_axis_rx_tuser[0]} {app/PIO/m_axis_rx_tuser[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 64 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]} {m_axis_rx_tdata[8]} {m_axis_rx_tdata[9]} {m_axis_rx_tdata[10]} {m_axis_rx_tdata[11]} {m_axis_rx_tdata[12]} {m_axis_rx_tdata[13]} {m_axis_rx_tdata[14]} {m_axis_rx_tdata[15]} {m_axis_rx_tdata[16]} {m_axis_rx_tdata[17]} {m_axis_rx_tdata[18]} {m_axis_rx_tdata[19]} {m_axis_rx_tdata[20]} {m_axis_rx_tdata[21]} {m_axis_rx_tdata[22]} {m_axis_rx_tdata[23]} {m_axis_rx_tdata[24]} {m_axis_rx_tdata[25]} {m_axis_rx_tdata[26]} {m_axis_rx_tdata[27]} {m_axis_rx_tdata[28]} {m_axis_rx_tdata[29]} {m_axis_rx_tdata[30]} {m_axis_rx_tdata[31]} {m_axis_rx_tdata[32]} {m_axis_rx_tdata[33]} {m_axis_rx_tdata[34]} {m_axis_rx_tdata[35]} {m_axis_rx_tdata[36]} {m_axis_rx_tdata[37]} {m_axis_rx_tdata[38]} {m_axis_rx_tdata[39]} {m_axis_rx_tdata[40]} {m_axis_rx_tdata[41]} {m_axis_rx_tdata[42]} {m_axis_rx_tdata[43]} {m_axis_rx_tdata[44]} {m_axis_rx_tdata[45]} {m_axis_rx_tdata[46]} {m_axis_rx_tdata[47]} {m_axis_rx_tdata[48]} {m_axis_rx_tdata[49]} {m_axis_rx_tdata[50]} {m_axis_rx_tdata[51]} {m_axis_rx_tdata[52]} {m_axis_rx_tdata[53]} {m_axis_rx_tdata[54]} {m_axis_rx_tdata[55]} {m_axis_rx_tdata[56]} {m_axis_rx_tdata[57]} {m_axis_rx_tdata[58]} {m_axis_rx_tdata[59]} {m_axis_rx_tdata[60]} {m_axis_rx_tdata[61]} {m_axis_rx_tdata[62]} {m_axis_rx_tdata[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 64 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 22 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {m_axis_rx_tuser[0]} {m_axis_rx_tuser[1]} {m_axis_rx_tuser[2]} {m_axis_rx_tuser[3]} {m_axis_rx_tuser[4]} {m_axis_rx_tuser[5]} {m_axis_rx_tuser[6]} {m_axis_rx_tuser[7]} {m_axis_rx_tuser[8]} {m_axis_rx_tuser[9]} {m_axis_rx_tuser[10]} {m_axis_rx_tuser[11]} {m_axis_rx_tuser[12]} {m_axis_rx_tuser[13]} {m_axis_rx_tuser[14]} {m_axis_rx_tuser[15]} {m_axis_rx_tuser[16]} {m_axis_rx_tuser[17]} {m_axis_rx_tuser[18]} {m_axis_rx_tuser[19]} {m_axis_rx_tuser[20]} {m_axis_rx_tuser[21]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list LmkACsSpiM_o_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list TmsgCsSpiM_o_OBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list app/PIO/PIO_EP_inst/valDataToTxFifo]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list app/PIO/PIO_EP_inst/valDataToFifoLmkA]]
set_property PACKAGE_PIN W16 [get_ports LrGpio_o]
set_property IOSTANDARD LVCMOS33 [get_ports LrGpio_o]
set_property PACKAGE_PIN J15 [get_ports Mod_o]
set_property IOSTANDARD LVCMOS33 [get_ports Mod_o]
set_property PACKAGE_PIN R17 [get_ports Pe1CsSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports Pe1CsSpiM_o]
set_property PACKAGE_PIN P15 [get_ports Pe1MosiSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports Pe1MosiSpiM_o]
set_property PACKAGE_PIN R16 [get_ports Pe2CsSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports Pe2CsSpiM_o]
set_property PACKAGE_PIN N17 [get_ports Pe2MosiSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports Pe2MosiSpiM_o]
set_property PACKAGE_PIN P16 [get_ports PeClkSpiM_o]
set_property IOSTANDARD LVCMOS33 [get_ports PeClkSpiM_o]
set_property PACKAGE_PIN Y16 [get_ports RfLd_i]
set_property IOSTANDARD LVCMOS33 [get_ports RfLd_i]
set_property PACKAGE_PIN AA15 [get_ports TmsgCsFlash_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgCsFlash_o]
set_property PACKAGE_PIN Y14 [get_ports TmsgMosi1_io]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgMosi1_io]
set_property PACKAGE_PIN AB16 [get_ports TmsgMosi2_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgMosi2_o]
set_property PACKAGE_PIN W14 [get_ports TmsgMosi3_o]
set_property IOSTANDARD LVCMOS33 [get_ports TmsgMosi3_o]
set_property PACKAGE_PIN W15 [get_ports HrGpio_o]
set_property IOSTANDARD LVCMOS33 [get_ports HrGpio_o]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets user_clk]
